Display device and method of manufacturing same

Abstract

The display device of the present invention includes a substrate and a pixel including a light-emitting region and a non-light-emitting region on the substrate, in which the pixel includes: a light-emitting element including a first end portion and a second end portion in the light-emitting region; a first pixel electrode electrically connected to a first end portion of the light emitting element; a second pixel electrode electrically connected to a second end portion of the light emitting element; an organic transmissive layer covering the first and second end portions of the light emitting element, the organic transmissive layer including light diffusing particles; and a color conversion layer on the organic transmission layer, the color conversion layer being capable of including color conversion particles for converting light of the first color emitted by the light emitting element into light of a second color.

Description

Technical Field

[0001] The present invention relates to a display device and a method of manufacturing the display device. Background Art

[0002] Recently, as interest in information display increases, research and development of display devices have been ongoing. Summary of the invention

[0003] Technical issues

[0004] An object of the disclosure is to provide a display device with improved reliability and a method of manufacturing the display device.

[0005] Furthermore, the disclosure is to provide a display device and a method of manufacturing the same, which can be manufactured through a relatively simple manufacturing process using a reduced number of masks, so that the production cost can be reduced.

[0006] However, aspects and features of the embodiments of the present disclosure are not limited to the above-mentioned aspects and features, and various modifications may be made without departing from the spirit and scope of the present disclosure.

[0007] Technical Solution

[0008] One or more embodiments of the present disclosure may provide a display device, the display device comprising: a substrate; and a pixel on the substrate and including an emission region and a non-emission region. The pixel may include: a light-emitting element, in the emission region, the light-emitting element including a first end and a second end; a first pixel electrode electrically connected to the first end of the light-emitting element; a second pixel electrode electrically connected to the second end of the light-emitting element; an organic transmission layer covering the first end and the second end of the light-emitting element, the organic transmission layer including light-diffusing particles; and a color conversion layer, on the organic transmission layer, the color conversion layer including color conversion particles that convert light of a first color emitted from the light-emitting element into light of a second color.

[0009] In one or more embodiments, the thickness of the organic transmission layer may be based on the wavelength of light emitted from the light emitting element.

[0010] In one or more embodiments, the light diffusion particles of the organic transmission layer may include a light scatterer having dispersibility in an organic solvent.

[0011] In one or more embodiments, the light scatterer may include titanium oxide (TiO 2 )、ZrO 2 ), aluminum oxide (Al 2 O 3 ), indium oxide (In 2 O 3), zinc oxide (ZnO) or tin oxide (SnO 2 ) at least one of.

[0012] In one or more embodiments, the display device may further include a coating layer between the organic transmission layer and the color conversion layer.

[0013] In one or more embodiments, the display device may further include: a pixel circuit layer including a transistor electrically connected to the light emitting element and a power line; a first bank pattern and a second bank pattern located on the pixel circuit layer in the emission region and spaced apart from each other; a first alignment electrode on the first bank pattern and electrically connected to the transistor; a second alignment electrode on the second bank pattern and electrically connected to the power line; and an insulating layer on the first alignment electrode and the second alignment electrode. The light emitting element may be on the insulating layer and may be between the first alignment electrode and the second alignment electrode in a plan view.

[0014] In one or more embodiments, the display device may further include a first insulating pattern between the insulating layer and the light emitting element.

[0015] In one or more embodiments, the display device may further include a second insulating pattern on the light emitting element, wherein the first end and the second end of the light emitting element are exposed from the second insulating pattern.

[0016] In one or more embodiments, the pixel may include a first pixel configured to emit red light and a second pixel configured to emit green light.

[0017] In one or more embodiments, the organic transmission layer may include: a first organic transmission layer in the first pixel; and a second organic transmission layer in the second pixel. A thickness of the first organic transmission layer may be smaller than a thickness of the second organic transmission layer.

[0018] In one or more embodiments, the color conversion layer may include: a first color conversion layer, which is in a first pixel and includes red color conversion particles that convert light emitted from a light-emitting element of the first pixel into red light; and a second color conversion layer, which is in a second pixel and includes green color conversion particles that convert light emitted from a light-emitting element of the second pixel into green light.

[0019] In one or more embodiments, the thickness of the organic transmission layer is 1.5 μm or more and less than 2.5 μm.

[0020] One or more embodiments of the present disclosure may provide a display device, the display device comprising: a substrate; a pixel on the substrate and including an emission region and a non-emission region. The pixel may include: a pixel circuit layer including a transistor and a power line on the substrate; a via layer on the transistor and the power line; a first alignment electrode and a second alignment electrode on the via layer and spaced apart from each other; a first dam pattern on the first alignment electrode; a second dam pattern on the second alignment electrode; an insulating layer on the first dam pattern and the second dam pattern; a light-emitting element on the insulating layer and located between the first alignment electrode and the second alignment electrode and including a first end and a second end in a longitudinal direction; a first pixel electrode electrically connected to a first end of the light-emitting element; a second pixel electrode electrically connected to a second end of the light-emitting element; an organic transmission layer covering the first end and the second end of the light-emitting element, the organic transmission layer including light-diffusing particles; and a color conversion layer on the organic transmission layer, the color conversion layer including color conversion particles that convert light of a first color emitted from the light-emitting element into light of a second color.

[0021] One or more embodiments of the present disclosure may provide a method for manufacturing a display device, the method comprising: forming a pixel including an emission region and a non-emission region on a substrate. The step of forming the pixel may include: forming a first alignment electrode and a second alignment electrode spaced apart from each other on the substrate; forming an insulating layer on the substrate, the first alignment electrode and the second alignment electrode; forming a first dam defining an emission region and a non-emission region on the insulating layer; using an electric field formed between the first alignment electrode and the second alignment electrode, aligning a light-emitting element on the insulating layer between the first alignment electrode and the second alignment electrode; forming a conductive layer on the light-emitting element and the insulating layer; forming an organic transmission layer including light-diffusing particles on the conductive layer; forming a coating layer on the organic transmission layer; removing a portion of the organic transmission layer and the coating layer using a first mask to expose a portion of the conductive layer; removing the exposed portion of the conductive layer, and forming a first pixel electrode electrically connected to a first end of the light-emitting element and a second pixel electrode electrically connected to a second end of the light-emitting element; and forming a color conversion layer on the organic transmission layer, the color conversion layer including color conversion particles that convert light of a first color emitted from the light-emitting element into light of a second color.

[0022] In one or more embodiments, the step of forming the organic transmission layer may include spraying an organic solvent including light diffusing particles in the emission area.

[0023] In one or more embodiments, the step of forming the organic transmission layer may include patterning the organic transmission layer so that the organic transmission layer overlaps the emission region except the non-emission region.

[0024] In one or more embodiments, forming the organic transmission layer may include applying an organic solvent including light diffusing particles to the emission region and the non-emission region and performing a front exposure operation. The organic transmission layer may be located on the first bank in the emission region.

[0025] In one or more embodiments, the step of forming the organic transmission layer may include forming a second bank on the first bank after forming the organic light emitting layer.

[0026] In one or more embodiments, the thickness of the organic transmission layer may be based on the wavelength of light emitted from the light emitting element.

[0027] In one or more embodiments, the light diffusion particles of the organic transmission layer may include a light scatterer having dispersibility in an organic solvent.

[0028] Beneficial Effects

[0029] According to the embodiments of the present invention, degradation occurring at both ends of a light emitting device may be prevented by providing an organic transmission layer including light diffusing particles on the light emitting device.

[0030] In addition, when an inkjet method or a whole surface exposure method is used in a process of providing an organic transmission layer between a light emitting element and a color conversion layer, a separate mask is not required, thereby simplifying the process and reducing costs.

[0031] However, the effects, aspects, and features of the present disclosure are not limited to the above-mentioned effects, aspects, and features, and various modifications may be made without departing from the spirit and scope of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a perspective view schematically showing a light emitting element according to one or more embodiments of the present disclosure.

[0033] Figure 2 It is shown Figure 1 A cross-sectional view of a light-emitting element.

[0034] Figure 3 is a plan view schematically illustrating a display device according to one or more embodiments of the present disclosure.

[0035] Figure 4 It is shown that the Figure 3 A circuit diagram showing the electrical connection relationship of components in a pixel.

[0036] Figure 5 It is schematically shown Figure 3 A plan view of each pixel shown in .

[0037] Figure 6aAccording to one or more embodiments, Figure 5 A cross-sectional view taken along line II-II'.

[0038] Figure 6b to Figure 6d According to one or more embodiments, Figure 5 A cross-sectional view taken along line II-II'.

[0039] Figure 7a A graph representing the penetration depth of light through an organic layer is shown.

[0040] Figure 7b Shown is a representation of passing through Figure 5 Graph of the penetration depth of light through the organic transmission layer shown in FIG.

[0041] Figure 8a Shown is the representation according to Figure 5 Graph showing the brightness maintenance rate of the organic transmission layer set as shown in FIG.

[0042] Figure 8b Shown is the representation according to Figure 5 Graph showing the color conversion retention rate of the color conversion layer with the arrangement of the organic transmission layer shown in FIG.

[0043] Figures 9 to 19 is a cross-sectional view for schematically describing a method of manufacturing a display element layer of a pixel according to one or more embodiments.

[0044] Figure 20 to Figure 25 is a cross-sectional view for schematically describing a method of manufacturing a display element layer of a pixel according to one or more embodiments.

[0045] Fig.26a and Figure 26b is a diagram showing the formation of a Figure 6a A cross-sectional view of the method of forming an organic transmission layer is shown in FIG.

[0046] Figures 27a to 27d is a diagram showing the formation of a Figure 6a A cross-sectional view of the method of forming an organic transmission layer is shown in FIG.

[0047] Fig.28a and Fig.28b is a diagram showing the formation of a Figure 6a A cross-sectional view of the method of forming an organic transmission layer is shown in FIG. DETAILED DESCRIPTION

[0048] Various embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals are used throughout the different drawings to denote the same components, and repeated descriptions of the same components will be omitted.

[0049] Figure 1 is a perspective view schematically showing a light emitting element LD according to one or more embodiments. Figure 2 It is shown Figure 1 A cross-sectional view of a light emitting element LD.

[0050] In one or more embodiments, the type and / or shape of the light emitting element LD is not limited to Figure 1 and Figure 2 The embodiment shown in FIG.

[0051] Reference Figure 1 and Figure 2 , the light emitting element LD may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 disposed between the first semiconductor layer 11 and the second semiconductor layer 13. For example, the light emitting element LD may be implemented as an emission stack (or referred to as a "stacked pattern") formed by sequentially stacking the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

[0052] The light emitting element LD may be formed in a shape extending in one direction. If the direction along which the light emitting element LD extends is defined as a longitudinal direction, the light emitting element LD may have a first end EP1 and a second end EP2 relative to the longitudinal direction. One of the first semiconductor layer 11 and the second semiconductor layer 13 may be disposed on the first end EP1 of the light emitting element LD, and the other of the first semiconductor layer 11 and the second semiconductor layer 13 may be disposed on the second end EP2 of the light emitting element LD. For example, the second semiconductor layer 13 may be disposed at the first end EP1 of the light emitting element LD, and the first semiconductor layer 11 may be disposed at the second end EP2 of the light emitting element LD.

[0053] The light emitting element LD can be arranged in various shapes. Figure 1 As shown in , the light emitting element LD may have a rod-like shape, a strip-like shape, or a column-like shape that is long relative to the longitudinal direction (i.e., has an aspect ratio greater than 1). Alternatively, the light emitting element LD may have a rod-like shape, a strip-like shape, or a column-like shape that is short relative to the longitudinal direction (or has an aspect ratio less than 1). As a further alternative, the light emitting element LD may have a rod-like shape, a strip-like shape, or a column-like shape having an aspect ratio of 1.

[0054] The light emitting element LD may include a light emitting diode (LED) manufactured to have an ultra-small size, for example, having a diameter D and / or a length L corresponding to a range from nanometer level (or nanometer level) to micrometer level (or micrometer level).

[0055] In the case where the light emitting element LD is long relative to the longitudinal direction (i.e., has an aspect ratio greater than 1), the diameter D of the light emitting element LD may be approximately in the range of 0.5 μm to 6 μm, and the length L of the light emitting element LD may be approximately in the range of 1 μm to 10 μm. However, the diameter D and the length L of the light emitting element LD are not limited thereto. The size of the light emitting element LD may be changed to meet the requirements (or design conditions) of the lighting device or the self-luminous display device to which the light emitting element LD is applied.

[0056] The first semiconductor layer 11 may include, for example, at least one n-type semiconductor layer. For example, the first semiconductor layer 11 may include an n-type semiconductor layer containing any one semiconductor material among InAlGaN, GaN, AlGaN, InGaN, AlN and InN and doped with a first conductive dopant (or n-type dopant) such as Si, Ge or Sn. However, the constituent material of the first semiconductor layer 11 is not limited thereto, and various other materials may be used to form the first semiconductor layer 11. Relative to the longitudinal direction of the light emitting element LD, the first semiconductor layer 11 may include an upper surface in contact with the active layer 12 and a lower surface exposed to the outside. The lower surface of the first semiconductor layer 11 may correspond to one end (or lower end) of the light emitting element LD.

[0057] The active layer 12 may be disposed on the first semiconductor layer 11 and have a single quantum well structure or a multi-quantum well structure. For example, in the case where the active layer 12 has a multi-quantum well structure, the active layer 12 may be formed by periodically and repeatedly stacking a barrier layer, a strain enhancement layer, and a well layer disposed as a unit. The strain enhancement layer may have a lattice constant smaller than that of the barrier layer, so that resistance to strain (e.g., compressive strain) applied to the well layer may be further enhanced. However, the structure of the active layer 12 is not limited to that of the aforementioned embodiment.

[0058] The active layer 12 may emit light having a wavelength approximately in the range of 400 nm to 900 nm and have a double heterostructure. In one or more embodiments, a cladding layer doped with a conductive dopant may be formed above and / or below the active layer 12 relative to the longitudinal direction of the light emitting element LD. For example, the cladding layer may be formed of an AlGaN layer or an InAlGaN layer. In one or more embodiments, materials such as AlGaN or InAlGaN may be used to form the active layer 12, and various other materials may be used to form the active layer 12. The active layer 12 may include a first surface in contact with the first semiconductor layer 11 and a second surface in contact with the second semiconductor layer 13.

[0059] If an electric field having a specific voltage or more is applied between opposite ends of the light emitting element LD, the light emitting element LD can emit light by combining electron-hole pairs in the active layer 12. Since the light emission of the light emitting element LD can be controlled based on the aforementioned principle, the light emitting element LD can be used as a light source (e.g., a light emitting source) of a pixel of a display device as well as various light emitting devices.

[0060] The second semiconductor layer 13 may be disposed on the second surface of the active layer 12 and include a semiconductor layer of a type different from that of the first semiconductor layer 11. For example, the second semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second semiconductor layer 13 may include a p-type semiconductor layer containing any one semiconductor material among InAlGaN, GaN, AlGaN, InGaN, AlN, and InN and doped with a second conductive dopant (or p-type dopant) such as Mg, Zn, Ca, Sr, or Ba. However, the material for forming the second semiconductor layer 13 is not limited thereto, and various other materials may be used to form the second semiconductor layer 13. Relative to the longitudinal direction of the light emitting element LD, the second semiconductor layer 13 may include a lower surface in contact with the second surface of the active layer 12, and an upper surface exposed to the outside. Here, the upper surface of the second semiconductor layer 13 may correspond to the remaining end (or upper end) of the light emitting element LD.

[0061] In one or more embodiments, the first semiconductor layer 11 and the second semiconductor layer 13 may have different thicknesses relative to the longitudinal direction of the light emitting element LD. For example, relative to the longitudinal direction of the light emitting element LD, the first semiconductor layer 11 may have a thickness greater than that of the second semiconductor layer 13. Therefore, the active layer 12 of the light emitting element LD may be disposed at a position closer to the upper surface of the second semiconductor layer 13 than to the lower surface of the first semiconductor layer 11.

[0062] Although the first semiconductor layer 11 and the second semiconductor layer 13 are both formed of a single layer, the present disclosure is not limited thereto. In one or more embodiments, depending on the material of the active layer 12, the first semiconductor layer 11 and the second semiconductor layer 13 may also each include one or more layers, for example, a cladding layer and / or a tensile strain barrier reduction (TSBR) layer. The TSBR layer may be a strain relief layer, which is disposed between semiconductor layers having different lattice structures and may therefore be used as a buffer layer to reduce the difference in lattice constants. Although the TSBR layer may be formed of a p-type semiconductor layer such as p-GaInP, p-AlInP or p-AlGaInP, the present disclosure is not limited thereto.

[0063] In one or more embodiments, the light emitting element LD may further include a contact electrode (hereinafter referred to as a "first contact electrode") disposed on the second semiconductor layer 13 in addition to the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13. In addition, in one or more embodiments, the light emitting element LD may further include another contact electrode (hereinafter referred to as a "second contact electrode") disposed on one end of the first semiconductor layer 11.

[0064] Each of the first contact electrode and the second contact electrode may be an ohmic contact electrode, but the present disclosure is not limited thereto. In one or more embodiments, each of the first contact electrode and the second contact electrode may be a Schottky contact electrode. The first contact electrode and the second contact electrode may include a conductive material. For example, the first contact electrode and the second contact electrode may include an opaque metal such as chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), and their oxides or alloys, used alone or in combination, but the present disclosure is not limited thereto. In one or more embodiments, the first contact electrode and the second contact electrode may also include materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x ), indium gallium zinc oxide (IGZO) and indium tin zinc oxide (ITZO). Here, zinc oxide (ZnO x ) can be zinc oxide (ZnO) and / or zinc peroxide (ZnO 2 ).

[0065] The materials included in the first contact electrode and the second contact electrode may be the same or different from each other. The first contact electrode and the second contact electrode may be substantially transparent or translucent. Therefore, the light generated from the light emitting element LD may pass through each of the first contact electrode and the second contact electrode, and then may be emitted from the light emitting element LD. In some embodiments, in the case where the light generated from the light emitting element LD is emitted from the light emitting element LD through an area other than the opposite ends of the light emitting element LD rather than through the first contact electrode and the second contact electrode, the first contact electrode and the second contact electrode may include an opaque metal.

[0066] In one or more embodiments, the light emitting element LD may further include an insulating layer 14 (or referred to as an "insulating film"). However, in some embodiments, the insulating layer 14 may be omitted, or may be provided to cover only some of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

[0067] The insulating layer 14 can prevent the active layer 12 from being short-circuited due to contact with a conductive material other than the first semiconductor layer 11 and the second semiconductor layer 13. In addition, the insulating layer 14 can reduce or minimize surface defects of the light-emitting element LD, thereby enhancing the life and emission efficiency of the light-emitting element LD. In the case where a plurality of light-emitting elements LD are arranged in close contact with each other, the insulating layer 14 can prevent an undesired short circuit from occurring between the light-emitting elements LD. The presence or absence of the insulating layer 14 is not limited as long as the active layer 12 can be prevented from being short-circuited with an external conductive material.

[0068] The insulating layer 14 may be provided to surround the entire outer surface (eg, outer peripheral surface or outer circumferential surface) of the emission stack including the first semiconductor layer 11 , the active layer 12 , and the second semiconductor layer 13 .

[0069] Although in the foregoing embodiments, the insulating layer 14 has been described as surrounding the entire corresponding outer surfaces (e.g., corresponding outer peripheral surfaces or peripheral surfaces) of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13, the present disclosure is not limited thereto. In one or more embodiments, in the case where the light emitting element LD includes a first contact electrode, the insulating layer 14 may surround the entire corresponding outer surfaces (e.g., corresponding outer peripheral surfaces or peripheral surfaces) of the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and the first contact electrode. In one or more embodiments, the insulating layer 14 may not surround the entire outer surface (e.g., outer peripheral surface or peripheral surface) of the first contact electrode, or may surround only a portion of the outer surface (e.g., outer peripheral surface or peripheral surface) of the first contact electrode, without surrounding other portions of the outer surface (e.g., outer peripheral surface or peripheral surface) of the first contact electrode. In addition, in one or more embodiments, in the case where the first contact electrode is disposed on one end (or upper end) of the light emitting element LD and the second contact electrode is disposed on the remaining end (or lower end) of the light emitting element LD, the insulating layer 14 may allow at least one region of each of the first contact electrode and the second contact electrode to be exposed.

[0070] The insulating layer 14 may include a transparent insulating material. For example, the insulating layer 14 may include a silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ), titanium oxide (TiO x ), hafnium oxide (HfO x ), strontium titanium oxide (SrTiO x ), cobalt oxide (Co x O y )、MgO、ZnO x), ruthenium oxide (RuO x ), nickel oxide (NiO), tungsten oxide (WO x ), tantalum oxide (TaO x ), Gadolinium oxide (GdO x )、ZrO x ), gallium oxide (GaO x ), vanadium oxide (V x O y )、ZnO:Al、ZnO:B、In x O y :H, niobium oxide (Nb x O y ), magnesium fluoride (MgF x ), aluminum fluoride (AlF x ), aluminum-based organic-inorganic composite polymer film (alucone polymer film), titanium nitride (TiN), tantalum nitride (TaN), aluminum nitride (AlN x ), gallium nitride (GaN), tungsten nitride (WN), hafnium nitride (HfN), niobium nitride (NbN), gadolinium nitride (GdN), zirconium nitride (ZrN) and vanadium nitride (VN) One or more insulating materials selected from the group consisting of. However, the present disclosure is not limited thereto, and various materials having insulating properties may be used as the material of the insulating layer 14.

[0071] The insulating layer 14 may have a single-layer structure or a multi-layer structure including a double-layer structure. For example, in the case where the insulating layer 14 is formed by a double-layer structure including a first insulating layer and a second insulating layer stacked continuously, the first insulating layer and the second insulating layer may be made of different materials (or different substances) and may be formed by different processes. In one or more embodiments, the first insulating layer and the second insulating layer may include the same material and may be formed by a continuous process.

[0072] In one or more embodiments, the light emitting element LD may be implemented as a light emitting pattern having a core-shell structure. In this case, the first semiconductor layer 11 may be disposed in the core of the light emitting element LD (i.e., the central portion of the light emitting element LD). The active layer 12 may be disposed and / or formed to surround the outer surface (e.g., the outer peripheral surface or the peripheral surface) of the first semiconductor layer 11. The second semiconductor layer 13 may be disposed and / or formed to surround the active layer 12. In addition, the light emitting element LD may further include a contact electrode formed to surround at least one side of the second semiconductor layer 13. In one or more embodiments, the light emitting element LD may further include an insulating layer 14, which is disposed on the outer surface (e.g., the outer peripheral surface or the peripheral surface) of the light emitting pattern having a core-shell structure and has a transparent insulating material. The light emitting element LD implemented as a light emitting pattern having a core-shell structure may be manufactured in a growth manner.

[0073] The light emitting element LD can be used as a light source (or light source) for various display devices. The light emitting element LD can be manufactured by a surface treatment process. For example, the light emitting element LD can be surface treated so that when a plurality of light emitting elements LD are mixed with a fluid solution (or solvent) and then supplied to each pixel area (e.g., the emission area of ​​each pixel or the emission area of ​​each sub-pixel), the light emitting element LD can be evenly distributed instead of unevenly agglomerated in the solution.

[0074] The light-emitting unit (or light-emitting device) including the above-mentioned light-emitting element LD can be used not only in a display device, but also in various types of electronic devices, each of which requires a light source. For example, in the case where a plurality of light-emitting elements LD are arranged in a pixel region of each pixel of a display panel, the light-emitting element LD can be used as a light source for the pixel. However, the application field of the light-emitting element LD is not limited to the above-mentioned example. For example, the light-emitting element LD can also be used in other types of electronic devices such as lighting devices that require a light source.

[0075] Figure 3 is a plan view schematically illustrating a display device according to one or more embodiments of the present disclosure.

[0076] For ease of description, Figure 3 The structure of the display device is schematically shown focusing on a display area DA on which an image is displayed.

[0077] Reference Figures 1 to 3 The display device may include a substrate SUB, a plurality of pixels PXL disposed on the substrate SUB and each including at least one light emitting element LD, a driver disposed on the substrate SUB and configured to drive the pixels PXL, and a line component disposed to connect the pixels PXL to the driver.

[0078] According to the method of driving the light emitting element LD, the display device can be classified into a passive matrix type display device and an active matrix type display device. For example, in the case where the display device is implemented as an active matrix type, each of the pixels PXL may include a driving transistor configured to control the amount of current to be supplied to the light emitting element LD, and a switching transistor configured to transmit a data signal to the driving transistor.

[0079] The display device can be arranged in various forms, for example, in the form of a rectangular plate having two pairs of parallel sides, but the present disclosure is not limited thereto. In the case where the display device is arranged in the form of a rectangular plate, one pair of the two pairs of sides may be longer than the other pair of sides. For ease of description, a case where the display device has a rectangular shape with a pair of long sides and a pair of short sides is shown. The direction along which the long side extends is represented as the second direction DR2, and the direction along which the short side extends is represented as the first direction DR1. In a display device arranged in a rectangular plane shape, each corner where a long side and a short side contact (or intersect) each other may have a rounded (chamfered) shape. However, the present disclosure is not limited thereto.

[0080] The substrate SUB may include a display area DA and a non-display area NDA along an edge or periphery of the display area DA.

[0081] The display area DA may be an area in which pixels PXL for displaying an image are disposed. The non-display area NDA may be an area in which a driver configured to drive the pixels PXL and a portion of a line assembly for connecting the pixels PXL to the driver are disposed. For ease of explanation, Figure 3 Only one pixel PXL is shown, but a plurality of pixels PXL may be substantially disposed in the display area DA of the substrate SUB.

[0082] The non-display area NDA may be disposed adjacent to the display area DA. The non-display area NDA may be disposed on at least one side of the display area DA. For example, the non-display area NDA may surround the periphery (or edge) of the display area DA. A line assembly connected to the pixel PXL, and a driver connected to the line assembly and configured to drive the pixel PXL may be disposed in the non-display area NDA.

[0083] The line assembly may electrically connect the driver to the pixel PXL. The line assembly may include a fan-out line connected to a signal line (e.g., a scan line, a data line, and an emission control line), the signal line being connected to each pixel PXL to provide a signal to the pixel PXL. In addition, in one or more embodiments, the line assembly may include a fan-out line connected to a signal line (e.g., a control line and a sensing line), the signal line being connected to each pixel PXL to compensate for changes in the electrical characteristics of the pixel PXL in real time. In addition, the line assembly may include a fan-out line connected to a power line, the power line being configured to provide a suitable voltage (e.g., a predetermined voltage) to the corresponding pixel PXL and being connected to the corresponding pixel PXL.

[0084] The substrate SUB may include a transparent insulating material to allow light to be transmitted. The substrate SUB may be a rigid substrate or a flexible substrate.

[0085] One area on the substrate SUB may be set as a display area DA in which the pixels PXL are disposed, and another area thereof may be set as a non-display area NDA. For example, the substrate SUB may include a display area DA including a plurality of pixel areas in which corresponding pixels PXL are disposed, and a non-display area NDA disposed around the periphery of the display area DA (or adjacent to the display area DA).

[0086] The pixels PXL may be disposed in the display area DA on the substrate SUB. In one or more embodiments, the pixels PXL may be arranged in stripes or The arrangement structure is arranged in the display area DA, but the present disclosure is not limited thereto. The arrangement structure may be referred to as an RGBG matrix structure (eg, Matrix structure or RGBG structure (for example, structure)). is a registered trademark of Samsung Display Co., Ltd. of Korea.

[0087] Each of the pixels PXL may include at least one light emitting element LD configured to be driven in response to a corresponding scan signal and a corresponding data signal. The light emitting element LD may have a small size ranging from nanometer level (or nanometer level) to micrometer level (micrometer level), and may be connected in parallel to a light emitting element LD disposed adjacent thereto, but the present disclosure is not limited thereto. The light emitting element LD may form a light source of each pixel PXL.

[0088] Each of the pixels PXL may include at least one light source (e.g., a first driving power source and a second driving power source) driven by a suitable signal (e.g., a predetermined signal (e.g., a scan signal and a data signal)) and / or a suitable power source (e.g., a predetermined power source (e.g., a first driving power source and a second driving power source)). Figure 1 and Figure 2 However, in one or more embodiments, the type of the light emitting element LD that can be used as the light source of each pixel PXL is not limited thereto.

[0089] The driver may supply a suitable signal (eg, a predetermined signal) and a suitable power voltage (eg, a predetermined power voltage) to each of the pixels PXL through the line assembly, and thus control the operation of the pixels PXL.

[0090] Figure 4 It shows that the Figure 3 0 is a circuit diagram of the electrical connection relationship of components in the pixel PXL shown in FIG.

[0091] For example, Figure 4The electrical connection relationship of components included in the pixel PXL that can be adopted in the active matrix type display device is shown. However, the electrical connection relationship between components included in the pixel PXL that can be applied to the embodiment is not limited thereto.

[0092] Reference Figures 1 to 4 The pixel PXL may include an emission unit EMU (or an emission layer) configured to generate light having brightness corresponding to the data signal. In addition, the pixel PXL may further selectively include a pixel circuit PXC configured to drive the emission unit EMU.

[0093] In one or more embodiments, the emission unit EMU may include a plurality of light emitting elements LD connected in parallel between a first power line PL1 and a second power line PL2, the first power line PL1 being connected to a first driving power source VDD and the voltage of the first driving power source VDD being applied to the first power line PL1, and the second power line PL2 being connected to a second driving power source VSS and the voltage of the second driving power source VSS being applied to the second power line PL2. For example, the emission unit EMU may include a first pixel electrode PE1 connected to the first driving power source VDD via a pixel circuit PXC and the first power line PL1, a second pixel electrode PE2 connected to the second driving power source VSS via the second power line PL2, and a plurality of light emitting elements LD connected in parallel to each other in the same direction between the first pixel electrode PE1 and the second pixel electrode PE2. In one or more embodiments, the first pixel electrode PE1 may be an anode, and the second pixel electrode PE2 may be a cathode.

[0094] Each of the light emitting elements LD included in the emission unit EMU may include one end connected to the first driving power source VDD through the first pixel electrode PE1, and the other end connected to the second driving power source VSS through the second pixel electrode PE2. The first driving power source VDD and the second driving power source VSS may have different potentials. For example, the first driving power source VDD may be set to a high potential power source, and the second driving power source VSS may be set to a low potential power source. Here, during the emission period of the pixel PXL, the potential difference between the first driving power source VDD and the second driving power source VSS may be set to a value equal to or greater than the threshold voltage of the light emitting element LD.

[0095] As described above, the light emitting elements LD connected in parallel to each other in the same direction (eg, in the forward direction) between the first pixel electrode PE1 and the second pixel electrode PE2 to which voltages of different power sources are supplied may form corresponding effective light sources.

[0096] The light emitting element LD of the emission unit EMU can emit light having a brightness corresponding to the driving current supplied thereto by the pixel circuit PXC. For example, during each frame period, the pixel circuit PXC can supply a driving current corresponding to the grayscale value of the corresponding frame data to the emission unit EMU. The driving current supplied to the emission unit EMU can be divided into a portion flowing into the corresponding light emitting element LD. Therefore, each of the light emitting elements LD can emit light having a brightness corresponding to the current applied thereto, so that the emission unit EMU can emit light having a brightness corresponding to the driving current.

[0097] Although an embodiment has been described in which the opposite ends of the light-emitting element LD are connected in the same direction between the first driving power supply VDD and the second driving power supply VSS, the present disclosure is not limited thereto. In one or more embodiments, the emission unit EMU may include at least one invalid light source (e.g., a reverse light-emitting element LDr) in addition to the light-emitting element LD forming the corresponding effective light source. The reverse light-emitting element LDr, together with the light-emitting element LD forming the effective light source, may be connected in parallel to each other between the first pixel electrode PE1 and the second pixel electrode PE2. Here, the reverse light-emitting element LDr may be connected between the first pixel electrode PE1 and the second pixel electrode PE2 in a direction opposite to the direction of the light-emitting element LD. Even if a specific driving voltage (e.g., a forward driving voltage) is applied between the first pixel electrode PE1 and the second pixel electrode PE2, the reverse light-emitting element LDr remains disabled. Therefore, current does not substantially flow through the reverse light-emitting element LDr.

[0098] The pixel circuit PXC may be connected to the scan line Si and the data line Dj of the pixel PXL. The pixel circuit PXC may be connected to the control line CLi and the sensing line SENj of the pixel PXL. For example, in the case where the pixel PXL is disposed on the i-th row and the j-th column of the display area DA, the pixel circuit PXC of the pixel PXL may be connected to the i-th scan line Si, the j-th data line Dj, the i-th control line CLi, and the j-th sensing line SENj of the display area DA.

[0099] The pixel circuit PXC may include first to third transistors T1 to T3 and a storage capacitor Cst.

[0100] The first transistor T1 may be a driving transistor configured to control a driving current to be applied to the emission unit EMU, and may be connected between the first driving power supply VDD and the emission unit EMU. In detail, the first terminal of the first transistor T1 may be connected (or coupled) to the first driving power supply VDD through the first power line PL1. The second terminal of the first transistor T1 may be connected to the second node N2. The gate electrode of the first transistor T1 may be connected to the first node N1. The first transistor T1 may control the amount of driving current to be applied to the emission unit EMU from the first driving power supply VDD through the second node N2 in response to the voltage applied to the first node N1. In one or more embodiments, the first terminal of the first transistor T1 may be a drain electrode, and the second terminal of the first transistor T1 may be a source electrode, but the present disclosure is not limited thereto. In one or more embodiments, the first terminal may be a source electrode and the second terminal may be a drain electrode.

[0101] The second transistor T2 may be a switching transistor that selects the pixel PXL in response to the scan signal and activates the pixel PXL, and may be connected between the data line Dj and the first node N1. The first terminal of the second transistor T2 may be connected to the data line Dj. The second terminal of the second transistor T2 may be connected to the first node N1. The gate electrode of the second transistor T2 may be connected to the scan line Si. The first terminal and the second terminal of the second transistor T2 are different terminals, for example, if the first terminal is a drain electrode, the second terminal may be a source electrode.

[0102] When a scan signal having a gate-on voltage (e.g., a high level voltage) is supplied from the scan line Si, the second transistor T2 may be turned on to electrically connect the data line Dj with the first node N1. The first node N1 may be a point at which the second terminal of the second transistor T2 and the gate electrode of the first transistor T1 are connected to each other. The second transistor T2 may transmit a data signal to the gate electrode of the first transistor T1.

[0103] The third transistor T3 can obtain a sensing signal through the sensing line SENj by connecting the first transistor T1 to the sensing line SENj, and use the sensing signal to detect the characteristics of the pixel PXL (such as the threshold voltage of the first transistor T1). Information about the characteristics of the pixel PXL can be used to convert image data so that the characteristic deviation between the pixels PXL can be compensated. The second terminal of the third transistor T3 can be connected to the second terminal of the first transistor T1. The first terminal of the third transistor T3 can be connected to the sensing line SENj. The gate electrode of the third transistor T3 can be connected to the control line CLi. In addition, in one or more embodiments, the first terminal of the third transistor T3 can be connected to an initialization power supply. In one or more embodiments, the third transistor T3 can be an initialization transistor configured to initialize the second node N2, and can be turned on when a sensing control signal is supplied thereto from the control line CLi, so that the voltage of the initialization power supply can be transmitted to the second node N2. Therefore, the second storage electrode of the storage capacitor Cst connected to the second node N2 can be initialized.

[0104] A first storage electrode of the storage capacitor Cst may be connected to the first node N1. A second storage electrode of the storage capacitor Cst may be connected to the second node N2. The storage capacitor Cst may be charged with a data voltage corresponding to a data signal supplied to the first node N1 during one frame period. Therefore, the storage capacitor Cst may store a voltage corresponding to a difference between a voltage of the gate electrode of the first transistor T1 and a voltage of the second node N2.

[0105] although Figure 4 An embodiment is shown in which all light emitting elements LD forming the emission unit EMU are connected in parallel to each other, but the present disclosure is not limited thereto. In one or more embodiments, the emission unit EMU may include at least one series group (or stage) including a plurality of light emitting elements LD connected in parallel to each other. In other words, the emission unit EMU may be formed by a series / parallel combination structure.

[0106] Figure 5 It is schematically shown Figure 3 A plan view of each pixel PXL shown in FIG.

[0107] exist Figure 5 In the figure, for the convenience of description, illustration of the transistor electrically connected to the light emitting element LD and the signal line electrically connected to the transistor T is omitted.

[0108] exist Figure 5 , for convenience of description, a transverse direction (or horizontal direction) in a plan view is indicated as a first direction DR1, and a longitudinal direction (or vertical direction) in a plan view is indicated as a second direction DR2.

[0109] Reference Figures 1 to 5 The pixel PXL may be disposed in a pixel area PXA disposed (or defined) on the substrate SUB. The pixel area PXA may include an emission area EMA and a non-emission area NEA.

[0110] In one or more embodiments, the pixel PXL may include a bank BNK disposed in the non-emission area NEA, and a light emitting element LD disposed in the emission area EMA.

[0111] In one or more embodiments, the bank BNK may be a structure for defining (or partitioning) a pixel PXL and a corresponding pixel area PXA (or a corresponding emission area EMA) of a pixel PXL adjacent thereto, and may be, for example, a pixel defining layer.

[0112] In one or more embodiments, the bank BNK may be a pixel defining layer or dam structure for defining each emission region EMA, and the light emitting element LD will be supplied to each emission region EMA during the process of supplying (or inputting) the light emitting element LD to the pixel PXL. In one or more embodiments, because the emission region EMA of the pixel PXL is defined by the bank BNK, a mixed solution (e.g., ink) including a target amount and / or type of light emitting element LD may be supplied (or inputted) to the emission region EMA. In addition, during the process of supplying the color conversion layer, the bank BNK may be a pixel defining layer, and the pixel defining layer may ultimately define each emission region EMA to which the color conversion layer will be supplied.

[0113] In one or more embodiments, the bank BNK may include at least one light shielding material and / or reflective material (or scattering material), thereby preventing or reducing a light leakage defect in which light (or rays) leaks between the pixel PXL and the pixel PXL adjacent thereto. In one or more embodiments, the bank BNK may include a transparent material (or a transparent substance). The transparent material may include, for example, a polyamide resin, a polyimide resin, etc., but the present disclosure is not limited thereto. In one or more embodiments, in order to enhance the efficiency of light emitted from the pixel PXL, a separate reflective material layer may be provided and / or formed on the bank BNK.

[0114] In one or more embodiments, the bank BNK may be surface-treated so that at least one surface of the bank BNK has hydrophobicity. For example, the bank BNK may be surface-treated by plasma to have hydrophobicity before the light emitting element LD is aligned, but the present disclosure is not limited thereto.

[0115] In one or more embodiments, the bank BNK may include at least one opening OP in the pixel area PXA that exposes a component disposed under the bank BNK. For example, the bank BNK may include a first opening OP1 and a second opening OP2 in the pixel area PXA that expose a component disposed under the bank BNK. In one or more embodiments, the emission area EMA of the pixel PXL and the first opening OP1 of the bank BNK may correspond to each other.

[0116] In one or more embodiments, in the pixel area PXA, the second opening OP2 may be disposed at a position spaced apart from the first opening OP1 and disposed adjacent to one side of the pixel area PXA (e.g., an upper side of the pixel area PXA). In one or more embodiments, the second opening OP2 may be an electrode separation region that separates at least one alignment electrode ALE from at least one alignment electrode ALE in a pixel PXL adjacent thereto in the second direction DR2.

[0117] In one or more embodiments, the pixel PXL may include a pixel electrode PE disposed in at least the emission area EMA, a light emitting element LD electrically connected to the pixel electrode PE, and a bank pattern BNKP and an alignment electrode ALE disposed at a position corresponding to the pixel electrode PE. For example, the pixel PXL may include a first pixel electrode PE1 and a second pixel electrode PE2 disposed in at least the emission area EMA, a light emitting element LD, a first alignment electrode ALE1 and a second alignment electrode ALE2, and a first bank pattern BNKP1 and a second bank pattern BNKP2. The pixel electrode PE and / or the alignment electrode ALE may be changed in number, shape, size, arrangement structure, etc. in various ways according to the structure of the pixel PXL (for example, specifically, the emission unit EMU).

[0118] In one or more embodiments, based on one surface of the substrate SUB on which the pixel PXL is disposed, the bank pattern BNKP, the alignment electrode ALE, the light emitting element LD, and the pixel electrode PE may be disposed in the order listed, but the present disclosure is not limited thereto. In one or more embodiments, the position and formation order of the electrode pattern forming the pixel PXL (or the emission unit EMU or the emission layer) may be changed in various ways. Figures 9 to 19 The stack structure of the pixel PXL is described.

[0119] In one or more embodiments, the bank patterns BNKP may be disposed in at least the emission area EMA, may be spaced apart from each other with respect to the first direction DR1 in the emission area EMA, and may each extend in the second direction DR2.

[0120] In one or more embodiments, each bank pattern BNKP (e.g., also referred to as a "wall pattern", "protrusion pattern" or "support pattern") may have a uniform width in the emission area EMA. For example, in a plan view, each of the first bank pattern BNKP1 and the second bank pattern BNKP2 may have a strip shape having a uniform width relative to their extension direction in the emission area EMA, but the present disclosure is not limited thereto. Each of the first bank pattern BNKP1 and the second bank pattern BNKP2 may have an irregular width in the extension direction, and may have two or more different widths in the extension direction.

[0121] In one or more embodiments, the bank patterns BNKP may have the same width or different widths. For example, the first bank pattern BNKP1 and the second bank pattern BNKP2 may have the same width or different widths with respect to the first direction DR1 in at least the emission area EMA.

[0122] In one or more embodiments, each of the first embankment pattern BNKP1 and the second embankment pattern BNKP2 may partially overlap with at least one alignment electrode ALE in at least the emission area EMA. For example, the first embankment pattern BNKP1 may be disposed below the first alignment electrode ALE1 to overlap with a region of the first alignment electrode ALE1. The second embankment pattern BNKP2 may be disposed below the second alignment electrode ALE2 to overlap with a region of the second alignment electrode ALE2. Alternatively, the first embankment pattern BNKP1 may be disposed above the first alignment electrode ALE1 to overlap with a region of the first alignment electrode ALE1. The second embankment pattern BNKP2 may be disposed above the second alignment electrode ALE2 to overlap with a region of the second alignment electrode ALE2.

[0123] In one or more embodiments, when the bank pattern BNKP and / or the alignment electrode ALE include a reflective material, a reflective wall structure may be formed around the light emitting element LD. Therefore, the light emitted from the light emitting element LD may be directed in an upward direction of the pixel PXL (e.g., in an image display direction of the display device), so that the light emitting efficiency of the pixel PXL may be further improved.

[0124] In one or more embodiments, the alignment electrodes ALE may be disposed in at least the emission area EMA, and may be spaced apart from each other in the emission area EMA relative to the first direction DR1, and may each extend in the second direction DR2. In addition, the alignment electrode ALE may be separated from the alignment electrodes ALE of the pixels PXL adjacent to each other in the second direction DR2 by removing a portion thereof in the second opening OP2 of the bank BNK.

[0125] In one or more embodiments, the alignment electrodes ALE may include first alignment electrodes ALE1 (or first alignment lines) and second alignment electrodes ALE2 (or second alignment lines) arranged at positions spaced apart from each other with respect to the first direction DR1.

[0126] In one or more embodiments, after the light emitting element LD is supplied to the pixel area PXA (or the emission area EMA) during the process of manufacturing the display device and the light emitting element LD is aligned in the pixel area PXA (or the emission area EMA), at least one of the first alignment electrode ALE1 and the second alignment electrode ALE2 may be separated from other electrodes (e.g., the alignment electrode ALE disposed in each of the pixels PXL adjacent thereto in the second direction DR2) in the second opening OP2 (or the electrode separation area) of the bank BNK. For example, one end of the first alignment electrode ALE1 may be separated from the first alignment electrode ALE1 of the pixel PXL disposed on the upper side of the corresponding pixel PXL in the second direction DR2 in the second opening OP2 of the bank BNK.

[0127] In one or more embodiments, the first alignment electrode ALE1 may be connected to the reference electrode through the first contact CNT1. Figure 4 The second alignment electrode ALE2 can be electrically connected to the reference electrode T1 through the second contact CNT2. Figure 4 The second power line PL2 described is electrically connected.

[0128] In one or more embodiments, the first contact CNT1 may be formed by removing a portion of at least one insulating layer disposed between the first alignment electrode ALE1 and the first transistor T1. The second contact CNT2 may be formed by removing a portion of at least one insulating layer disposed between the second alignment electrode ALE2 and the second power line PL2. The first contact CNT1 and the second contact CNT2 may be disposed in the non-emission area NEA and overlap the embankment BNK, but the present disclosure is not limited thereto. In one or more embodiments, the first contact CNT1 and the second contact CNT2 may be disposed in the second opening OP2 of the embankment BNK as an electrode separation area, and may be disposed in the emission area EMA.

[0129] Each of the first alignment electrode ALE1 and the second alignment electrode ALE2 may be supplied with a signal (or alignment signal) from an alignment pad (pad, also referred to as a "pad" or "pad") provided in the non-display area NDA in the step of aligning the light emitting element LD. For example, the first alignment electrode ALE1 may be supplied with a first alignment signal (or a first alignment voltage) from the first alignment pad. The second alignment electrode ALE2 may be supplied with a second alignment signal (or a second alignment voltage) from the second alignment pad. The above-mentioned first alignment signal and second alignment signal may be signals both having a voltage difference and / or a phase difference that enables the light emitting element LD to be aligned between the first alignment electrode ALE1 and the second alignment electrode ALE2. At least one of the first alignment signal and the second alignment signal may be an AC signal, but the present disclosure is not limited thereto.

[0130] In one or more embodiments, each alignment electrode ALE may have a strip shape having a uniform width with respect to the second direction DR2, but the present disclosure is not limited thereto. In one or more embodiments, each alignment electrode ALE may or may not have a bent portion in the second opening OP2 as an electrode separation region of the non-emission area NEA and / or the bank BNK, and the shape and / or size of each alignment electrode ALE in a region other than the emission area EMA may be changed in various ways without being specifically limited.

[0131] In one or more embodiments, two or more light emitting elements LD may be aligned and / or arranged in the emission area EMA (or pixel area PXA). In one or more embodiments, the number of light emitting elements LD aligned and / or arranged in the emission area EMA (or pixel area PXA) may be changed in various ways.

[0132] In one or more embodiments, the light emitting element LD may be disposed between the first alignment electrode ALE1 and the second alignment electrode ALE2. Each of the light emitting elements LD may be a reference Figure 1 and Figure 2 The light emitting elements LD described. Each of the light emitting elements LD may include a first end EP1 (or one end) and a second end EP2 (or the remaining end) opposite to each other in the extension direction. In one or more embodiments, the second semiconductor layer 13 including a p-type semiconductor layer may be disposed on the first end EP1, and the first semiconductor layer 11 including an n-type semiconductor layer may be disposed on the second end EP2. The light emitting elements LD may be connected in parallel to each other between the first alignment electrode ALE1 and the second alignment electrode ALE2.

[0133] In one or more embodiments, the light emitting elements LD may be arranged at positions spaced apart from each other and aligned substantially parallel to each other. The distance at which the light emitting elements LD are spaced apart from each other is not specifically limited. In one or more embodiments, a plurality of light emitting elements LD may be arranged adjacent to each other to form a group, and another plurality of light emitting elements LD may be spaced apart from each other at regular intervals to form a group. The light emitting elements LD may be aligned in one direction with an uneven density.

[0134] In one or more embodiments, each of the light emitting elements LD may emit any one of colored light and / or white light. Each of the light emitting elements LD may be aligned between the first alignment electrode ALE1 and the second alignment electrode ALE2 so that its longitudinal direction is parallel to the first direction DR1. In one or more embodiments, the light emitting elements LD may be aligned between the first alignment electrode ALE1 and the second alignment electrode ALE2 so that at least some of the light emitting elements LD are not completely parallel to the first direction DR1. For example, some of the light emitting elements LD may be aligned between the first alignment electrode ALE1 and the second alignment electrode ALE2 to be inclined relative to the first direction DR1. The light emitting element LD may be provided in a spray (or diffused) form in a solution and then supplied (or input) to the pixel area PXA (or emission area EMA).

[0135] In one or more embodiments, the light emitting element LD may be input (or supplied) to the pixel area PXA (or the emission area EMA) by inkjet printing, slit coating, or other various methods. For example, the light emitting element LD may be mixed with a volatile solvent and then input (or supplied) to the pixel area PXA by inkjet printing or slit coating. Here, if the first alignment electrode ALE1 and the second alignment electrode ALE2 are respectively supplied with corresponding alignment signals, an electric field may be formed between the first alignment electrode ALE1 and the second alignment electrode ALE2. Therefore, the light emitting element LD may be aligned between the first alignment electrode ALE1 and the second alignment electrode ALE2. After aligning the light emitting element LD, the solvent may be removed by volatilization or other methods. In this way, the light emitting element LD may be reliably aligned between the first alignment electrode ALE1 and the second alignment electrode ALE2.

[0136] In one or more embodiments, each of the light emitting elements LD may be a light emitting diode made of a material having an inorganic crystal structure and having an ultra-small size ranging from nanometer level (or nanometer level) to micrometer level (or micrometer level). Figure 1 and Figure 2 The light emitting element LD is described.

[0137] In one or more embodiments, the pixel electrodes PE (or electrodes) may be disposed in at least the emission area EMA, and may each be disposed at a position corresponding to at least one alignment electrode ALE and the light emitting element LD. For example, each of the pixel electrodes PE may be formed on the corresponding alignment electrode ALE and the corresponding light emitting element LD to overlap with the corresponding alignment electrode ALE and the corresponding light emitting element LD, and thus be electrically connected to at least the light emitting element LD.

[0138] In one or more embodiments, the first pixel electrode PE1 (also referred to as the "first electrode" or "anode") may be formed on the first alignment electrode ALE1 and the corresponding first end EP1 of the light emitting element LD, and thus be electrically connected to the corresponding first end EP1 of the light emitting element LD. In addition, the first pixel electrode PE1 may directly contact the first alignment electrode ALE1 exposed by removing a portion of at least one insulating layer disposed between the first pixel electrode PE1 and the first alignment electrode ALE1 in at least the emission area EMA, and may be electrically and / or physically connected to the first alignment electrode ALE1. Although the connection point (or contact point) between the first pixel electrode PE1 and the first alignment electrode ALE1 is located in the emission area EMA, the present disclosure is not limited thereto. In one or more embodiments, the connection point (or contact point) between the first pixel electrode PE1 and the first alignment electrode ALE1 may be located in the non-emission area NEA (e.g., the second opening OP2 of the embankment BNK as an electrode separation area).

[0139] The first pixel electrode PE1 may have a strip shape extending in the second direction DR2, but the present disclosure is not limited thereto. In one or more embodiments, the shape of the first pixel electrode PE1 may be changed in various ways, as long as the first pixel electrode PE1 can be reliably electrically and / or physically connected to the first end EP1 of the light emitting element LD. In addition, considering the connection relationship with the first alignment electrode AEL1 disposed thereunder, the shape of the first pixel electrode PE1 may be changed in various ways.

[0140] In one or more embodiments, the second pixel electrode PE2 (also referred to as the "second electrode" or "cathode") may be formed on the second alignment electrode ALE2 and the corresponding second end EP2 of the light emitting element LD, and thus be electrically connected to the corresponding second end EP2 of the light emitting element LD. In addition, the second pixel electrode PE2 may directly contact the second alignment electrode ALE2 exposed by removing a portion of at least one insulating layer disposed between the second pixel electrode PE2 and the second alignment electrode ALE2 in the emission area EMA, and may be electrically and / or physically connected to the second alignment electrode ALE2. The connection point (or contact point) between the second pixel electrode PE2 and the second alignment electrode ALE2 may be located in the emission area EMA or the non-emission area NEA.

[0141] In one or more embodiments, the second pixel electrode PE2 may have a strip shape extending in the second direction DR2, but the present disclosure is not limited thereto. In one or more embodiments, the shape of the second pixel electrode PE2 may be changed in various ways, as long as the second pixel electrode PE2 can be reliably electrically and physically connected to the second end EP2 of the light emitting element LD. In addition, considering the connection relationship with the second alignment electrode ALE2 disposed thereunder, the shape of the second pixel electrode PE2 may be changed in various ways.

[0142] exist Figure 6a to Figure 25 , a height direction in the cross-sectional view (also referred to as a “vertical direction” or a “thickness direction of the substrate SUB”) is denoted as a third direction DR3.

[0143] Figure 6a According to one or more embodiments, Figure 5 A cross-sectional view taken along line II-II'. Figures 6a to 6d According to one or more embodiments, Figure 5 A cross-sectional view taken along line II-II'.

[0144] Reference Figures 6a to 6d , the pixel circuit layer PCL and the display element layer DPL may be disposed on one surface of the substrate SUB and overlap each other. For example, the display area DA of the substrate SUB may include a pixel circuit layer PCL disposed on the one surface of the substrate SUB, and a display element layer DPL disposed on the pixel circuit layer PCL. However, the relative positions of the pixel circuit layer PCL and the display element layer DPL on the substrate SUB may be changed according to the embodiment. In the case where the pixel circuit layer PCL and the display element layer DPL are separated from each other as separate layers and overlap each other, a layout space sufficient to form each of the pixel circuit PXC and the emission unit EMU can be ensured.

[0145] In one or more embodiments, the substrate SUB may include a transparent insulating material to allow light transmission. The substrate SUB may be a rigid substrate or a flexible substrate. For example, the rigid substrate SUB may be one of a glass substrate, a quartz substrate, a glass ceramic substrate, and a crystallized glass substrate. The flexible substrate SUB may be a film substrate or a plastic substrate including a polymer organic material. For example, the flexible substrate SUB may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyether sulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate.

[0146] In one or more embodiments, in each pixel region PXA of the pixel circuit layer PCL, a circuit element (e.g., transistor T) for forming a pixel circuit PXC of a corresponding pixel PXL and a signal line electrically connected to the circuit element may be provided. In addition, in each pixel region PXA of the display element layer DPL, an alignment electrode ALE, a light emitting element LD, and / or a pixel electrode PE forming an emission unit EMU of the corresponding pixel PXL may be provided.

[0147] In one or more embodiments, the pixel circuit layer PCL may include at least one insulating layer in addition to the circuit elements and the signal line. For example, the pixel circuit layer PCL may include a buffer layer BFL, a gate insulating layer GI, an interlayer insulating layer ILD, a passivation layer PSV, and a via layer VIA sequentially stacked on the substrate SUB in the third direction DR3.

[0148] In one or more embodiments, the buffer layer BFL may prevent impurities from diffusing into the transistor T included in the pixel circuit PXC. The buffer layer BFL may be an inorganic layer including an inorganic material. The buffer layer BFL may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and such as aluminum oxide (AlO x ) is at least one of the metal oxides of the substrate SUB. The buffer layer BFL may be provided in the form of a single-layer structure, or in the form of a multi-layer structure having two or more layers. In the case where the buffer layer BFL is provided in the form of a multi-layer structure, the respective layers may be formed of the same material or different materials. Depending on the material or process conditions of the substrate SUB, the buffer layer BFL may be omitted.

[0149] In one or more embodiments, the pixel circuit PXC may include a transistor T. For convenience, Figure 6a FIG. 1 shows a transistor T configured to control the driving current of the light emitting element LD. The transistor T may be a reference Figure 4 A first transistor T1 is described.

[0150] In one or more embodiments, the transistor T may include a semiconductor pattern and a gate electrode GE overlapping at least a portion (or a region) of the semiconductor pattern. Here, the semiconductor pattern may include an active pattern ACT, a first contact region SE, and a second contact region DE. The first contact region SE may be a source region, and the second contact region DE may be a drain region.

[0151] In one or more embodiments, the gate electrode GE may have a single-layer structure formed of one or a combination selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), silver (Ag), and alloys thereof, or may have a double-layer or multi-layer structure formed of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or silver (Ag) to reduce line resistance.

[0152] In one or more embodiments, the gate insulating layer GI may be disposed and / or formed on the entire surface of the semiconductor pattern and the buffer layer BFL. The gate electrode GE may be disposed on the gate insulating layer GI to overlap with the active pattern ACT in the third direction DR3. The gate insulating layer GI may be formed of an inorganic layer including an inorganic material. For example, the gate insulating layer GI may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and such as aluminum oxide (AlO x ) is at least one of the metal oxides of the present invention. However, the material of the gate insulating layer GI is not limited to the materials of the aforementioned embodiments. In one or more embodiments, the gate insulating layer GI may be formed by an organic layer (e.g., an organic insulating layer) including an organic material. The gate insulating layer GI may be provided in the form of a single-layer structure, or in the form of a multi-layer structure having at least two layers.

[0153] In one or more embodiments, the active pattern ACT, the first contact region SE, and the second contact region DE may be semiconductor patterns formed of polysilicon, amorphous silicon, oxide semiconductor, etc. The active pattern ACT, the first contact region SE, and the second contact region DE may be formed of an undoped semiconductor layer or a semiconductor layer doped with impurities. For example, each of the first contact region SE and the second contact region DE may be formed of a semiconductor layer doped with impurities. The active pattern ACT may be formed of an undoped semiconductor layer. For example, n-type impurities may be used as impurities, but the present disclosure is not limited thereto.

[0154] In one or more embodiments, the active pattern ACT may be a region overlapping the gate electrode GE of the corresponding transistor T in the third direction DR3 and may be a channel region of the transistor T. For example, the active pattern ACT of the transistor T may overlap the gate electrode GE of the transistor T and thus form the channel region of the transistor T.

[0155] The first contact region SE of the transistor T may be connected to (or make contact with) one end of the active pattern ACT. In addition, the first contact region SE of the transistor T may be connected to the bridge pattern BRP through the first connector TE1.

[0156] In one or more embodiments, the first connector TE1 may be disposed and / or formed on the interlayer insulating layer ILD. One end of the first connector TE1 may be electrically connected and / or physically connected to the first contact region SE of the first transistor T1 through a contact hole sequentially passing through the interlayer insulating layer ILD and the gate insulating layer GI. In addition, the remaining end of the first connector TE1 may be electrically connected and / or physically connected to the bridge pattern BRP through a contact hole passing through a passivation layer PSV disposed on the interlayer insulating layer ILD. The first connector TE1 may include the same material as that of the gate electrode GE, or include one or more materials selected from the materials provided as examples of constituent materials for the gate electrode GE.

[0157] In one or more embodiments, the interlayer insulating layer ILD may be disposed and / or formed on the entire surface of the gate electrode GE and the gate insulating layer GI. The interlayer insulating layer ILD may include the same material as that of the gate insulating layer GI, or may include one or more materials selected from the materials provided as examples of constituent materials for the gate insulating layer GI.

[0158] In one or more embodiments, the bridge pattern BRP may be disposed and / or formed on the passivation layer PSV. One end of the bridge pattern BRP may be connected to the first contact region SE of the transistor T through the first connector TE1. In addition, the remaining end of the bridge pattern BRP may be electrically and / or physically connected to the bottom conductive layer BML through a contact hole sequentially passing through the passivation layer PSV, the interlayer insulating layer ILD, the gate insulating layer GI, and the buffer layer BFL. The bottom conductive layer BML and the first contact region SE of the transistor T may be electrically connected to each other through the bridge pattern BRP and the first connector TE1.

[0159] In one or more embodiments, the bottom conductive layer BML may be a first conductive layer among the conductive layers disposed on the substrate SUB. For example, the bottom conductive layer BML may be a first conductive layer disposed between the substrate SUB and the buffer layer BFL. The bottom conductive layer BML may be electrically connected to the transistor T and thus increase the driving range of a specific voltage to be supplied to the gate electrode GE of the transistor T. For example, the bottom conductive layer BML may be electrically connected to the first contact region SE of the transistor T and stabilize the channel region of the transistor T. In addition, the bottom conductive layer BML may be electrically connected to the first contact region SE of the transistor T, thus preventing the bottom conductive layer BML from floating.

[0160] In one or more embodiments, the second contact region DE of the transistor T may be connected to the remaining end of the active pattern ACT (or the second contact region DE of the transistor T may be in contact with the remaining end of the active pattern ACT). In addition, the second contact region DE of the transistor T may be connected to the second connector TE2 (or the second contact region DE of the transistor T may be in contact with the second connector TE2).

[0161] In one or more embodiments, the second connector TE2 may be disposed and / or formed on the interlayer insulating layer ILD. One end of the second connector TE2 may be electrically connected and / or physically connected to the second contact region DE of the transistor T through a contact hole passing through the interlayer insulating layer ILD and the gate insulating layer GI. The remaining end of the second connector TE2 may be electrically connected and / or physically connected to the first alignment electrode ALE1 of the display element layer DPL through the first contact CNT1 sequentially passing through the via layer VIA and the passivation layer PSV. In one or more embodiments, the second connector TE2 may be a medium for connecting the transistor T of the pixel circuit layer PCL with the first alignment electrode ALE1 of the display element layer DPL.

[0162] An interlayer insulating layer ILD may be disposed and / or formed on the transistor T described above.

[0163] Although the case where the transistor T is a thin film transistor having a top gate structure has been shown in the foregoing embodiments, the present disclosure is not limited thereto. The structure of the transistor T may be changed in various ways.

[0164] A passivation layer PSV may be disposed and / or formed on the transistor T and the first and second connectors TE1 and TE2 .

[0165] In one or more embodiments, a passivation layer PSV (or referred to as a "protective layer") may be disposed and / or formed on the entire surface of the first and second connectors TE1 and TE2 and the interlayer insulating layer ILD. The passivation layer PSV may be formed of an inorganic layer (or inorganic insulating layer) including an inorganic material, or of an organic layer (or organic insulating layer) including an organic material.

[0166] For example, the inorganic layer may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ) and such as aluminum oxide (AlO x The organic layer may include, for example, at least one of polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene resin.

[0167] In one or more embodiments, the passivation layer PSV may be partially opened to include the first contact CNT1 exposing a region of the second connector TE2. In addition, the passivation layer PSV may be partially opened to expose a region of the first connector TE1 and a region of the bottom conductive layer BML.

[0168] In one or more embodiments, the pixel circuit layer PCL may include a power line disposed and / or formed on the passivation layer PSV. For example, the power line may include a second power line PL2. The second power line PL2 may be disposed at the same layer as the layer of the bridge pattern BRP. The voltage of the second driving power source VSS may be applied to the second power line PL2. In one or more embodiments, the pixel circuit layer PCL may also include a reference Figure 4 The first power line PL1 described. The first power line PL1 may be arranged at the same layer as the layer of the second power line PL2, or may be arranged at a different layer from the layer of the second power line PL2. Although the second power line PL2 has been described as being arranged and / or formed on the passivation layer PSV in the aforementioned embodiments, the present disclosure is not limited thereto. In one or more embodiments, the second power line PL2 may be arranged on an insulating layer, and any one of the conductive layers arranged on the pixel circuit layer PCL is arranged on the insulating layer. In other words, the position of the second power line PL2 in the pixel circuit layer PCL may be changed in various ways.

[0169] In one or more embodiments, the second power line PL2 may include a conductive material (or conductive substance). For example, the second power line PL2 may have a single-layer (or single-film) structure formed by one or a combination selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), silver (Ag), and their alloys, or may have a double-layer (or double-film) structure or a multi-layer (or multi-film) structure formed by molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or silver (Ag) as a low-resistance material to reduce line resistance. For example, the second power line PL2 may be formed by a double-layer structure (or double-film) structure formed by stacking layers in the order of titanium (Ti) and copper (Cu).

[0170] In one or more embodiments, a via layer VIA may be disposed and / or formed on the bridge pattern BRP and the second power line PL2 .

[0171] In one or more embodiments, the via layer VIA may be disposed and / or formed on the entire surface of the bridge pattern BRP, the second power line PL2, and the passivation layer PSV. The via layer VIA may be formed by a single layer including an organic layer, or by a multilayer having a double layer or more layers. In one or more embodiments, the via layer VIA may include an inorganic layer and an organic layer disposed on the inorganic layer. In the case where the via layer VIA has a multilayer structure, the organic layer forming the via layer VIA may be located at the topmost layer of the via layer VIA. The via layer VIA may include at least one of a polyacrylate resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, and a benzocyclobutene resin.

[0172] In one or more embodiments, the via layer VIA may include a first contact CNT1 and a second contact CNT2, the first contact CNT1 corresponding to the first contact CNT1 of the passivation layer PSV exposing the second connection TE2 electrically connected to the transistor T, and the second contact CNT2 exposing the second power line PL2. In one or more embodiments, the via layer VIA may be used as a planarization layer in the pixel circuit layer PCL, which reduces the step difference caused by the components (e.g., transistor T, power line, bridge pattern BRP, etc.) disposed below the via layer VIA.

[0173] In one or more embodiments, the display element layer DPL may be disposed and / or formed on the via layer VIA.

[0174] In one or more embodiments, the display element layer DPL may include a bank pattern BNKP, an alignment electrode ALE, a bank BNK, a light emitting element LD, and a pixel electrode PE. In addition, the display element layer DPL may include at least an insulating layer disposed between the aforementioned components.

[0175] In one or more embodiments, the bank pattern BNKP may protrude in the third direction DR3 on the one surface of the via layer VIA. Therefore, one region of each of the alignment electrodes ALE disposed on the bank pattern BNKP may protrude in the third direction DR3 (or the thickness direction of the substrate SUB).

[0176] In one or more embodiments, the bank pattern BNKP may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. In one or more embodiments, each of the bank patterns BNKP may include an organic layer having a single-layer structure and / or an inorganic layer having a single-layer structure, but the present disclosure is not limited thereto. In one or more embodiments, the bank pattern BNKP may be provided as a multilayer structure formed by stacking at least one organic insulating layer and at least one inorganic insulating layer. However, the material of the bank pattern BNKP is not limited to the aforementioned embodiment. In one or more embodiments, the bank pattern BNKP may include a conductive material (or conductive substance).

[0177] In one or more embodiments, each of the bank patterns BNKP can be used as a reflector. For example, the bank pattern BNKP together with the alignment electrode ALE disposed thereon can be used as a reflector to guide the light emitted from each light emitting element LD in a desired direction, so that the light output efficiency of the pixel PXL can be enhanced.

[0178] Reference Figure 6a , Figure 6b and Figure 6d , the first alignment electrode ALE1 and the second alignment electrode ALE2 may be disposed and / or formed on the dyke pattern BNKP. In one or more embodiments, the first alignment electrode ALE1 and the second alignment electrode ALE2 may be disposed on the same plane and have the same thickness in the third direction DR3. For example, the first alignment electrode ALE1 and the second alignment electrode ALE2 may be disposed on the via layer VIA and the corresponding dyke pattern BNKP and have the same thickness relative to the third direction DR3. The first alignment electrode ALE1 and the second alignment electrode ALE2 may be formed synchronously (e.g., simultaneously) by the same process.

[0179] In one or more embodiments, the first alignment electrode ALE1 may have a shape corresponding to the inclination of the first bank pattern BNKP1 disposed thereunder. The second alignment electrode ALE2 may have a shape corresponding to the inclination of the second bank pattern BNKP2 disposed thereunder.

[0180] In one or more embodiments, the first alignment electrode ALE1 and the second alignment electrode ALE2 may be formed of a material having a specific (e.g., substantially uniform or uniform) reflectivity to allow light emitted from the light emitting element LD to travel in the image display direction (e.g., the third direction DR3) of the display device. For example, the first alignment electrode ALE1 and the second alignment electrode ALE2 may be formed of a conductive material (or a conductive substance). The conductive material may include an opaque metal suitable for reflecting light emitted from the light emitting element LD in the image display direction (e.g., the third direction DR3) of the display device. For example, the opaque metal may include metals such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and alloys thereof. The materials of the first alignment electrode ALE1 and the second alignment electrode ALE2 are not limited to the above materials. In one or more embodiments, the first alignment electrode ALE1 and the second alignment electrode ALE2 may be formed of a transparent conductive material (or a transparent substance). The transparent conductive material (or transparent conductive substance) may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x ), transparent conductive oxides such as indium gallium zinc oxide (IGZO) and indium tin zinc oxide (ITZO), and conductive polymers such as PEDOT (poly (3,4-ethylenedioxythiophene)). In the case where the alignment electrode ALE includes a transparent conductive material (or a transparent conductive substance), a separate conductive layer formed of an opaque metal for reflecting light emitted from the light emitting element LD in an image display direction (e.g., a third direction DR3) of the display device may be added. However, the material of the alignment electrode ALE is not limited to the aforementioned materials.

[0181] In one or more embodiments, the first alignment electrode ALE1 may be electrically connected to the transistor T of the pixel circuit layer PCL through the first contact CNT1. The second alignment electrode ALE2 may be electrically connected to the second power line PL2 of the pixel circuit layer PCL through the second contact CNT2.

[0182] In one or more embodiments, a first insulating layer INS1 may be disposed and / or formed on the first alignment electrode ALE1 and the second alignment electrode ALE2 .

[0183] In one or more embodiments, the first insulating layer INS1 may be formed of an inorganic layer or an organic layer, the inorganic layer is formed of an inorganic material, and the organic layer is formed of an organic material. The first insulating layer INS1 may be formed of an inorganic layer suitable for protecting the light emitting element LD from the pixel circuit layer PCL. For example, the first insulating layer INS1 may include silicon nitride (SiN x ), silicon oxide (SiO x), silicon oxynitride (SiO x N y ) and such as aluminum oxide (AlO x ) at least one of the metal oxides, but the present disclosure is not limited thereto.

[0184] In one or more embodiments, the first insulating layer INS1 may be provided in the form of a single-layer structure or a multi-layer structure. In the case where the first insulating layer INS1 is provided in the form of a multi-layer structure, the first insulating layer INS1 may have a distributed Bragg reflector (DBR) structure formed by alternately stacking first and second layers formed of inorganic layers and having different refractive indices.

[0185] In one or more embodiments, a bank BNK may be formed on the first insulating layer INS1. In one or more embodiments, the bank BNK may be formed to surround the emission area EMA of the pixel PXL between adjacent pixels PXL, thus forming a pixel defining layer for defining the emission area EMA of the corresponding pixel PXL.

[0186] In one or more embodiments, the light emitting element LD may be supplied to and aligned in the emission area EMA of the pixel PXL in which the first insulating layer INS1 and the bank BNK are formed. For example, the light emitting element LD may be supplied (or input) to the emission area EMA by an inkjet printing method or the like. The light emitting element LD may be aligned between the alignment electrodes ALE by an electric field formed by a specific signal (or alignment signal) applied to each of the alignment electrodes ALE. For example, the light emitting element LD may be aligned on the first insulating layer INS1 between the first alignment electrode ALE1 on the first bank pattern BNKP1 and the second alignment electrode ALE2 on the second bank pattern BNKP2.

[0187] In one or more embodiments, each of the light emitting elements LD may include an emission stack (or an emission stack pattern) including first semiconductor layers (e.g., Figure 1 The first semiconductor layer 11), the active layer (for example, Figure 1 active layer 12) and a second semiconductor layer (eg, Figure 1 In one or more embodiments, the second semiconductor layer 13 may be located at the first end EP1 of each light emitting element LD. The first semiconductor layer 11 may be located at the second end EP2 of the corresponding light emitting element LD.

[0188] In one or more embodiments, the first pixel electrode PE1 and the second pixel electrode PE2 may be disposed on opposite sides of the light emitting element LD in the emission area EMA. The first pixel electrode PE1 may be disposed on the first end EP1 of each of the light emitting elements LD. The first pixel electrode PE1 may be in direct contact with the first alignment electrode ALE1 through an opening in the first insulating layer INS1 and may be electrically connected to the first alignment electrode ALE1. The second pixel electrode PE2 may be disposed on the second end EP2 of each of the light emitting elements LD. The second pixel electrode PE2 may be in direct contact with the second alignment electrode ALE2 through an opening in the first insulating layer INS1 and may be electrically connected to the second alignment electrode ALE2.

[0189] In one or more embodiments, the first insulating pattern INP1 may be disposed and / or formed under the light emitting element LD. The first insulating pattern INP1 may be disposed on the first insulating layer INS1 and fix the light emitting element LD disposed between the first alignment electrode ALE1 and the second alignment electrode ALE2.

[0190] In one or more embodiments, the first pixel electrode PE1 and the second pixel electrode PE2 may be disposed on the light emitting element LD and may be spaced apart from each other.

[0191] In one or more embodiments, the first pixel electrode PE1 and the second pixel electrode PE2 may be formed of various transparent conductive materials to allow light emitted from each of the light emitting elements LD to travel in an image display direction of the display device (e.g., in the third direction DR3) without significant optical loss. For example, the first pixel electrode PE1 and the second pixel electrode PE2 may include a transparent conductive material including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x ), indium gallium zinc oxide (IGZO) and indium tin zinc oxide (ITZO), and may be substantially transparent or translucent to meet the desired transmittance (e.g., a predetermined transmittance or a transmittance). The materials of the first pixel electrode PE1 and the second pixel electrode PE2 are not limited to the materials of the aforementioned embodiments. In one or more embodiments, the first pixel electrode PE1 and the second pixel electrode PE2 may also be formed of various opaque conductive materials (e.g., various opaque conductive substances). The first pixel electrode PE1 and the second pixel electrode PE2 may be formed of a single layer or multiple layers.

[0192] In one or more embodiments, the first pixel electrode PE1 and the second pixel electrode PE2 may be disposed and / or formed at the same layer. In one or more embodiments, the first pixel electrode PE1 and the second pixel electrode PE2 may be disposed at the same plane and may be spaced apart from each other by a specific distance and electrically separated from each other.

[0193] In one or more embodiments, the organic transmittance layer OPL may be disposed and / or formed on the first pixel electrode PE1 and the second pixel electrode PE2 .

[0194] In one or more embodiments, the organic transmittance layer OPL may include a first organic transmittance layer OPLa disposed to overlap the first pixel electrode PE1, and a second organic transmittance layer OPLb disposed to overlap the second pixel electrode PE2.

[0195] In one or more embodiments, the organic transmittance layer OPL may be disposed on the first pixel electrode PE1 and the second pixel electrode PE2 and cover the opposite ends of the light emitting element LD. In one or more embodiments, the first organic transmittance layer OPLa may be disposed to cover the first end EP1 of each of the light emitting elements LD. The second organic transmittance layer OPLb may be disposed to cover the second end EP2 of each of the light emitting elements LD.

[0196] In one or more embodiments, the first end EP1 and the second end EP2 of the light emitting element LD may not directly contact the color conversion layer CCL to be described below due to the organic transmission layer OPL.

[0197] In one or more embodiments, the organic transmittance layer OPL can be set to cover the first end EP1 and the second end EP2 of each of the light emitting elements LD, so that degradation phenomena can be prevented from occurring at the first end EP1 and the second end EP2 of the light emitting element LD, which degradation phenomena may be caused when the color conversion layer CCL including the color conversion particles QD directly contacts the first end EP1 and the second end EP2 of each of the light emitting elements LD.

[0198] In one or more embodiments, the organic transmission layer OPL may include a nano-scale light scatterer having dispersibility in an organic solvent. For example, the light scatterer may include titanium oxide (TiO 2 )、ZrO 2 ), aluminum oxide (Al 2 O 3 ), indium oxide (In 2 O 3 ), zinc oxide (ZnO) and tin oxide (SnO 2 ) at least one of.

[0199] In one or more embodiments, the organic transmission layer OPL includes a light scatterer so that light emitted from the light emitting element LD may be diffused at a relatively large angle.

[0200] In one or more embodiments, the thickness of the organic transmission layer OPL may be changed according to the wavelength of light emitted from the light emitting element LD. For example, in the case where blue-based light is emitted from the light emitting element LD, the thickness of the organic transmission layer OPL may be less than the thickness of the organic transmission layer OPL in the case where green-based light is emitted from the light emitting element LD.

[0201] In one or more embodiments, in the case where the light emitting element LD emits blue-based light, the thickness of the organic transmittive layer OPL may be about 1.5 μm or more and may be less than about 2.5 μm.

[0202] In one or more embodiments, the color conversion layer CCL may be disposed and / or formed on the organic transmission layer OPL.

[0203] In one or more embodiments, the color conversion layer CCL may be disposed on the organic transmission layer OPL in the emission area EMA surrounded by the bank BNK of the pixel PXL. In one or more embodiments, the color conversion layer CCL may be directly located on the organic transmission layer OPL and may directly contact a region of the light emitting element LD except for the first end EP1 and the second end EP2 of the light emitting element LD.

[0204] In one or more embodiments, the color conversion layer CCL may include color conversion particles QD corresponding to a specific color. For example, the color conversion layer CCL may include color conversion particles QD that convert light of a first color emitted from the light emitting element LD into light of a second color (or a specific color). In the case where the pixel PXL is a red pixel, the color conversion layer CCL of the corresponding pixel PXL may include color conversion particles QD formed by red quantum dots that convert light of a first color emitted from the light emitting element LD into light of a second color (e.g., red light). In the case where the pixel PXL is a green pixel (or a green sub-pixel), the color conversion layer CCL of the corresponding pixel PXL may include color conversion particles QD formed by green quantum dots that convert light of a first color emitted from the light emitting element LD into light of a second color (e.g., green light). In the case where the pixel PXL is a blue pixel (or a blue sub-pixel), the color conversion layer CCL of the corresponding pixel PXL may include color conversion particles QD formed by blue quantum dots that convert light of a first color emitted from the light emitting element LD into light of a second color (e.g., blue light). In one or more embodiments, when the pixel PXL is a blue pixel (or a blue sub-pixel), a light scattering layer having light scattering particles SCT may be provided instead of the color conversion layer CCL having the color conversion particles QD. For example, when the pixel PXL is a blue pixel (or a blue sub-pixel) and the light emitting element LD emits blue-based light, the pixel PXL may include a light scattering layer including light scattering particles SCT. According to an embodiment, the light scattering layer may be omitted. In one or more embodiments, when the pixel PXL is a blue pixel (or a blue sub-pixel), a transparent polymer may be provided instead of the color conversion layer CCL.

[0205] In one or more embodiments, a capping layer CPL may be disposed on the color conversion layer CCL and the bank BNK.

[0206] In one or more embodiments, the cap layer CPL may be disposed on the entire surface (or the entirety) in the pixel area PXA, and may be disposed directly on the color conversion layer CCL. The cap layer CPL may be an inorganic layer (or an inorganic insulating layer) including an inorganic material. The cap layer CPL may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and such as aluminum oxide (AlO x ). The cover layer CPL may be disposed on the color conversion layer CCL and cover the color conversion layer CCL, thus protecting the color conversion layer CCL.

[0207] In one or more embodiments, the cover layer CPL may reduce the step difference formed by the components disposed thereunder and have a planar surface. For example, the cover layer CPL may include an organic layer including an organic material. The cover layer CPL may be a common layer commonly provided in the display area DA including the pixel area PXA, but the present disclosure is not limited thereto.

[0208] In one or more embodiments, a color filter CF and a light shielding pattern LBP may be disposed and / or formed on the cover layer CPL. The color filter CF may allow light of a specific color to selectively pass through it. The color filter CF together with the color conversion layer CCL may form a light conversion pattern LCP, and may include a color filter material that allows light of a specific color converted by the color conversion layer CCL to selectively pass through it. The color filter CF may include a red filter, a green filter, and a blue filter. The color filter CF may be disposed on one surface of the cover layer CPL and correspond to the color conversion layer CCL. The light conversion pattern LCP including the color conversion layer CCL and the color filter CF may correspond to the emission area EMA of the pixel PXL.

[0209] In one or more embodiments, the light shielding pattern LBP may be disposed on a surface of the cover layer CPL at a position adjacent to the color filter CF. For example, the light shielding pattern LBP may be disposed on a surface of the cover layer CPL and correspond to the non-emission area NEA. The light shielding pattern LBP may correspond to the embankment BNK. In one or more embodiments, the light shielding pattern LBP may include a light shielding material for preventing a light leakage defect in which light (or rays) leaks between the pixel PXL and the pixel PXL adjacent thereto. For example, the light shielding pattern LBP may include a black matrix. The light shielding pattern LBP may prevent light of different colors emitted from the corresponding adjacent pixels PXL from mixing.

[0210] In one or more embodiments, a cover layer CVL may be disposed and / or formed on the light blocking pattern LBP and the color filter CF.

[0211] In one or more embodiments, the cover layer CVL may be formed of an inorganic layer (or inorganic insulating layer) including an inorganic material, or an organic layer (or organic insulating layer) including an organic material. The cover layer CVL may cover the entire assembly disposed thereunder, and prevent water, moisture, etc. from being introduced into the light emitting element LD and the light conversion pattern LCP from the outside. In one or more embodiments, the cover layer CVL may be an organic layer disposed on the entire surface in the display area DA including the pixel area PXA by an inkjet printing method.

[0212] In the display device according to the aforementioned embodiment, the light conversion pattern LCP may be disposed on the light emitting element LD so that light having excellent color reproducibility may be emitted through the light conversion pattern LCP, thereby enhancing light output efficiency of the display device.

[0213] Figure 6b According to one or more embodiments, Figure 5 A cross-sectional view taken along line II-II'.

[0214] Reference Figure 6b , except for the second insulating pattern INP2, the structure is the same as Figure 6a The configuration shown in FIG. 1 is the same as that shown in FIG. 1 ; therefore, the same reference numerals will be used to denote the same or corresponding components, and redundant explanations thereof will be omitted.

[0215] Reference Figure 6b , the second insulating pattern INP2 may be disposed on the light emitting element LD. The second insulating pattern INP2 may be disposed on the light emitting element LD aligned between the first pixel electrode PE1' and the second pixel electrode PE2', and may be partially disposed on only one region of each of the light emitting elements LD including the central region thereof. The second insulating pattern INP2 may be formed integrally with the first insulating pattern INP1. In one or more embodiments, the second insulating pattern INP2 may be formed as an independent pattern separated from the first insulating pattern INP1.

[0216] In one or more embodiments, the first pixel electrode PE1 ′ and the second pixel electrode PE2 ′ may be disposed at positions spaced apart from each other based on the second insulating pattern INP2 .

[0217] In one or more embodiments, the first organic transmittance layer OPLa' and the second organic transmittance layer OPLb' may overlap the first pixel electrode PE1' and the second pixel electrode PE2', and may be disposed at positions spaced apart from each other based on the second insulating pattern INP2 to cover opposite ends of the light emitting element LD. In one or more embodiments, the first organic transmittance layer OPLa' may be formed to cover the first end EP1 of the light emitting element LD. The second organic transmittance layer OPLb' may be formed to cover the second end EP2 of the light emitting element LD.

[0218] In one or more embodiments, after alignment of the light emitting element LD in the pixel PXL has been completed, a second insulating pattern INP2 may be formed on each of the light emitting elements LD so that the light emitting element LD may be prevented from being removed from its aligned position.

[0219] Figure 6c According to one or more embodiments, Figure 5 A cross-sectional view taken along line II-II'.

[0220] Reference Figure 6c , except for the first alignment electrode ALE1' and the second alignment electrode ALE2'. Figure 6a The configuration shown in FIG. 1 is the same as that shown in FIG. 1 ; therefore, the same reference numerals will be used to denote the same or corresponding components, and redundant explanations thereof will be omitted.

[0221] Reference Figure 6c , the first alignment electrode ALE1' and the second alignment electrode ALE2' may be disposed on the via layer VIA at positions spaced apart from each other. The first bank pattern BNKP1 may be disposed on the first alignment electrode ALE1'. The second bank pattern BNKP2 may be disposed on the second alignment electrode ALE2'.

[0222] In one or more embodiments, the first insulating layer INS1 may be formed along the outlines (or shapes) of the first and second bank patterns BNKP1 and BNKP2 .

[0223] Figure 6d According to one or more embodiments, Figure 5 A cross-sectional view taken along line II-II'.

[0224] Reference Figure 6d , except for the first bank pattern BNKP1', the second bank pattern BNKP2' and the bank BNK' Figure 6a The configuration shown in FIG. 1 is the same as that shown in FIG. 1 ; therefore, the same reference numerals will be used to denote the same or corresponding components, and redundant explanations thereof will be omitted.

[0225] Reference Figure 6d , the first bank pattern BNKP1', the first bank pattern BNKP1, the second bank pattern BNKP2, and the second bank pattern BNKP2' may be sequentially arranged along one direction and protrude in the third direction DR3. Therefore, a region of the first insulating layer INS1, a region of the first pixel electrode PE1, and a region of the first organic transmissive layer OPLa disposed on the first bank pattern BNKP1' may protrude in the third direction DR3. A region of the first insulating layer INS1, a region of the second pixel electrode PE2, and a region of the second organic transmissive layer OPLb disposed on the second bank pattern BNKP2' may protrude in the third direction DR3.

[0226] although Figure 6d It is shown that the first insulating layer INS1, the first pixel electrode PE1, and the first organic transmittance layer OPLa are sequentially disposed on the first bank pattern BNKP1', but the first pixel electrode PE1 may not be disposed on the first bank pattern BNKP1'.

[0227] In one or more embodiments, the bank BNK' may be disposed to cover the first bank pattern BNKP1' and the second bank pattern BNKP2'. In one or more embodiments, the bank BNK' may be disposed to overlap the first bank pattern BNKP1' and the second bank pattern BNKP2'.

[0228] Figure 7a A graph representing the penetration depth of light through an organic layer is shown. Figure 7b Shown is a representation of passing through Figure 5 Graph showing the penetration depth of light through the organic transmission layer OPL shown in FIG.

[0229] Figure 8a Shown is the representation according to Figure 5 Graph showing the brightness maintenance rate of the organic transmission layer OPL set as shown in FIG. Figure 8b Shown is the representation according to Figure 5 Graph showing the color conversion retention rate of the color conversion layer CCL provided with the organic transmission layer OPL shown in FIG.

[0230] Figure 7a The penetration depth of light emitted from the light emitting element is shown when an organic layer having a thickness of about 1.5 μm is disposed between the light emitting element LD and the color conversion layer CCL. In one or more embodiments, although the organic layer may include polyacrylate, the present disclosure is not limited thereto. For example, the organic layer may include at least one material among acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene resin, polyphenylene sulfide resin, and benzocyclobutene (BCB).

[0231] Figure 7b It is shown that in an organic transmission layer (eg, Figure 5 The organic transmission layer OPL) is disposed between the light emitting element LD and the color conversion layer (eg, Figure 5 In the case where the color conversion layer CCL) is between the light emitting elements (e.g., Figure 5 The penetration depth of light emitted by the light-emitting element LD).

[0232] Reference Figure 7a and Figure 7b , the light transmittance of the light emitting element LD in the case where the organic transmittance layer OPL is disposed on the light emitting element LD may be lower than the light transmittance of the light emitting element LD in the case where the polyacrylic acid layer is disposed.

[0233] In one or more embodiments, since the organic transmittance layer OPL is disposed between the light emitting element LD and the color conversion layer CCL, heat generated by light emitted from opposite ends of the light emitting element LD may be alleviated or prevented from being transferred to the color conversion layer CCL.

[0234] That is, the degradation phenomenon that may be caused on the opposite ends of the light emitting element LD may be improved (eg, reduced) in proportion to the reduction in light transmittance.

[0235] Figure 8a Shown according to Figure 5 The brightness maintenance rate of the organic transmission layer OPL set as shown in FIG.

[0236] Figure 8a “Ref1” of FIG. 1 represents luminance degradation of a green pixel in a case where the color conversion layer directly contacts the light emitting element.

[0237] Figure 8a “Ex1” of FIG. 1 represents luminance degradation of a green pixel in a case where an organic transmission layer OPL having a thickness of about 4 μm is provided on the light emitting element LD.

[0238] Reference Figure 8a , a luminance reduction rate in a case where the organic transmission layer OPL including light diffusing particles is disposed on the light emitting element LD may be smaller than a luminance reduction rate in a case where the color conversion layer is in direct contact with the light emitting element LD.

[0239] In one or more embodiments, since light emitted from the light emitting element LD is diffused by the light diffusion particles included in the organic transmission layer OPL, a reduction in brightness may be substantially alleviated.

[0240] Figure 8b Shown according to Figure 5 0044] The color conversion retention rate in the color conversion layer CCL of the arrangement of the organic transmission layer OPL shown in FIG.

[0241] Figure 8b “Ref2” represents the color conversion maintenance rate of the color conversion layer CCL of the green pixel in the case where the color conversion layer CCL directly contacts the light emitting element LD.

[0242] Figure 8b “Ex2” of FIG. 1 represents a color conversion maintenance rate of the color conversion layer CCL of the green pixel in a case where the organic transmission layer OPL including light diffusing particles is disposed on the light emitting element LD.

[0243] Reference Figure 8b , a color conversion retention rate of the color conversion layer CCL in a case where the organic transmission layer OPL including light diffusing particles is disposed on the light emitting element LD may be higher than a color conversion retention rate of the color conversion layer CCL in a case where the color conversion layer CCL directly contacts the light emitting element LD.

[0244] In one or more embodiments, since the light emitting element LD and the color conversion layer CCL are spaced apart from each other by the organic transmittance layer OPL, degradation of opposite ends of the light emitting element LD may be mitigated, so that a light conversion retention rate of the color conversion layer CCL may be relatively increased.

[0245] Figures 9 to 19 is a cross-sectional view for schematically describing a method of manufacturing the display element layer DPL of the pixel PXL according to an embodiment.

[0246] In the following, reference will be made to Figures 9 to 19 Description of manufacturing basis Figure 6a A method of displaying a pixel PXL and a display element layer DPL.

[0247] Here, a case is shown where the steps of manufacturing the pixel PXL are performed sequentially according to the cross-sectional view, but without changing the spirit and scope of the present disclosure, some steps shown as being performed sequentially may be performed synchronously (e.g., simultaneously), the order of the steps may be changed, some steps may be skipped, or another step may be further included between the steps.

[0248] Reference Figures 9 to 19 The description will focus on the differences from the above-described embodiments to avoid redundant description.

[0249] Reference Fig. 9 A pixel circuit layer PCL is formed on the substrate SUB, and a first bank pattern BNKP1 and a second bank pattern BNKP2 spaced apart from each other are formed on the via layer VIA of the pixel circuit layer PCL.

[0250] Reference Fig. 9 and Fig.10 , a first alignment electrode ALE1 is formed on the first bank pattern BNKP1, and a second alignment electrode ALE2 is formed on the second bank pattern BNKP2.

[0251] In one or more embodiments, the first alignment electrode ALE1 and the second alignment electrode ALE2 may be formed by the same process and may be disposed at the same layer, and may include the same material.

[0252] Reference Fig.11 A first insulating layer INS1 is formed on the first alignment electrode ALE1 and the second alignment electrode ALE2 and the via layer VIA.

[0253] In one or more embodiments, the first insulating layer INS1 may be partially opened to expose a region of the first alignment electrode ALE1 and a region of the second alignment electrode ALE2. The first insulating layer INS1 may be formed of an inorganic layer (or inorganic insulating layer) including an inorganic material.

[0254] In one or more embodiments, in response to the operation of forming the first insulating layer INS1 , an electric field is formed between the first alignment electrode ALE1 and the second alignment electrode ALE2 by applying corresponding alignment signals to the first alignment electrode ALE1 and the second alignment electrode ALE2 , respectively.

[0255] Thereafter, after the electric field has been formed, ink including the light emitting element LD is input to the pixel region PXA of the pixel PXL by an inkjet printing method or the like. For example, at least one inkjet nozzle may be provided on the first insulating layer INS1, and ink mixed with a plurality of light emitting elements LD may be input to the pixel region PXA of the pixel PXL by the inkjet nozzle. The method of inputting the light emitting element LD to the pixel region PXA is not limited to that of the aforementioned embodiment. The method of inputting the light emitting element LD may be changed in various ways.

[0256] In one or more embodiments, in the case where the light emitting element LD is input to the pixel area PXA, self-alignment of the light emitting element LD on the first insulating layer INS1 between the first alignment electrode ALE1 and the second alignment electrode ALE2 may be induced.

[0257] Reference Fig.12 , an insulating material layer may be formed on the entire surface of the emission area EMA. An insulating material layer may be applied (or formed by coating) on ​​the light emitting element LD. The insulating material layer may include an insulating material having viscosity (e.g., a suitable viscosity). After applying the insulating material layer, a first insulating pattern INP1 may be formed by a front exposure process. In one or more embodiments, the first insulating pattern INP1 may fix the light emitting element LD after the light emitting element LD has been self-aligned to prevent the light emitting element LD from being removed during the process of removing the solvent from the first insulating layer INS1.

[0258] Reference Fig.11 and Fig.12 Before forming the first insulating pattern INP1, a gap VD may be formed between the first insulating layer INS1 and the light emitting element LD. During the process of forming the first insulating pattern INP1, the gap VD may be filled with the first insulating pattern INP1. Therefore, the light emitting element LD may be more stably supported.

[0259] Reference Fig.13 , a bank BNK is formed on the first insulating layer INS1. The first insulating layer INS1 may be formed on the first insulating layer INS1 in the non-emission area NEA.

[0260] In one or more embodiments, the bank BNK may be formed immediately after the first insulating layer INS1 is provided. In one or more embodiments, the bank BNK may be formed after the light emitting element LD is sprayed to and aligned in the emission area EMA.

[0261] Reference Fig.14 , the conductive layer CDL may be applied to the entire surface of the first insulating layer INS1 and the light emitting element LD in the emission area EMA. In one or more embodiments, the conductive layer CDL may be formed of various transparent conductive materials. For example, the conductive layer CDL may be formed of a transparent conductive oxide.

[0262] Reference Fig.15 , the organic transmittive layer OPL may be applied to the entire surface of the conductive layer CDL.

[0263] In one or more embodiments, the following will refer to Figures 26a to 28b A method of applying the organic transmittive layer OPL is described in detail.

[0264] Reference Fig.16 and Fig.17 , the coating layer CTL may be applied to the entire surface of the organic transmission layer OPL, and then the coating layer CTL, a portion of the conductive layer CDL, and a portion of the organic transmission layer OPL may be removed through patterning and etching processes.

[0265] Reference Fig.17 , shows an example in which the entire coating layer CTL is removed, but only a portion of the coating layer CTL may be removed.

[0266] In one or more embodiments, since a portion of the conductive layer CDL is removed through the aforementioned process, the first pixel electrode PE1 and the second pixel electrode PE2 electrically separated from each other may be formed. A method of removing a region of the conductive layer CDL may include a wet etching method.

[0267] In one or more embodiments, the first organic transmittance layer OPLa and the second organic transmittance layer OPLb may be formed by removing a portion of the organic transmittance layer OPL through the aforementioned process.

[0268] Reference Fig.18 , a color conversion layer CCL is formed in a space surrounded by the bank BNK. In one or more embodiments, the color conversion layer CCL may be formed by deposition or inkjet, but the present disclosure is not limited thereto.

[0269] In one or more embodiments, light emitted from the first end EP1 and the second end EP2 of the light emitting element LD may pass through the organic transmission layer OPL in the third direction DR3 and then may be transmitted to the color conversion layer CCL. Light emitted from the first end EP1 and the second end EP2 of the light emitting element LD may be diffused by light diffusion particles included in the organic transmission layer OPL and then may be transmitted to the color conversion layer CCL.

[0270] Reference Figure 6a and Fig.19 , thereafter a cap layer CPL, a light blocking pattern LBP, and a cover layer CVL may be formed on the color conversion layer CCL.

[0271] Figure 20 to Figure 25 is a cross-sectional view for schematically describing a method of manufacturing the display element layer DPL of the pixel PXL according to one or more embodiments.

[0272] In the following, reference will be made to Figure 20 to Figure 25 Description of manufacturing basis Figure 6b Here, operations other than the operation of forming the second insulating pattern INP2 and operations related thereto will be referred to as Figures 9 to 11 as well as Figure 18 to Figure 19 , and its redundant explanation will be omitted.

[0273] Reference Fig.11 and Fig. 20 Before forming the first and second insulating patterns INP1 and INP2 , a gap VD may be formed between the first insulating layer INS1 and the light emitting element LD.

[0274] Reference Fig. 20 , the first and second insulating patterns INP1 and INP2 may be formed by applying an insulating material to the light emitting element LD and the first insulating layer INS1 and performing a photolithography process using a mask.

[0275] Reference Fig.21 , a bank BNK is formed on the first insulating layer INS1. The bank BNK may be formed on the first insulating layer INS1 in the non-emission area NEA.

[0276] Reference Fig. 22 , the conductive layer CDL' may be applied to the entire surface of the first insulating layer INS1 and the second insulating pattern INP2 in the emission area EMA. The conductive layer CDL' may be disposed along the contours (or shapes) of the first insulating layer INS1 and the second insulating pattern INP2.

[0277] Reference Fig.23 , the organic transmission layer OPL' may be disposed on the entire surface of the conductive layer CDL'.

[0278] Reference Fig.24 and Fig.25 , the coating layer CTL' may be applied to the entire surface of the organic transmission layer OPL', and then the coating layer CTL', a portion of the conductive layer CDL', and a portion of the organic transmission layer OPL' may be removed through a patterning and etching process using a first mask.

[0279] In one or more embodiments, since a portion of the conductive layer CDL' is removed through the aforementioned process, the first pixel electrode PE1' and the second pixel electrode PE2' electrically separated from each other may be formed.

[0280] In one or more embodiments, the first organic transmittance layer OPLa′ and the second organic transmittance layer OPLb′ may be formed by removing a portion of the organic transmittance layer OPL′ through the aforementioned process.

[0281] Afterwards, you can Fig.18 and Fig.19 The following process is performed in the same manner.

[0282] In the following, reference will be made to Figures 26a to 28b Describes forming an organic transmission layer (eg, Figure 6a A method of an organic transmittive layer (OPL) is provided.

[0283] Reference Figures 26a to 28b , the pixel PXL may include a first pixel PXL1 configured to emit red light, a second pixel PXL2 configured to emit green light, and a third pixel PXL3 configured to emit blue light.

[0284] In one or more embodiments, a color conversion layer (eg, Figure 6a The color conversion layer CCL) is a color conversion layer (eg, Figure 6a The color conversion layer CCL includes color conversion particles (eg, red quantum dots) that convert the light emitted from the first light emitting element LD1 into red light. Figure 6a A color conversion layer CCL including color conversion particles QD of green quantum dots that convert light emitted from the second light emitting element LD2 into green light may be provided in the emission area EMA of the second pixel PXL2.

[0285] In one or more embodiments, a color conversion layer CCL including color conversion particles QD of blue quantum dots that convert light emitted from the third light emitting element LD3 into blue light may be provided in the emission area EMA of the third pixel PXL3. In one or more embodiments, in the case where the third light emitting element LD3 emits blue-based light, light scattering particles (e.g., light scattering particles) instead of the color conversion layer CCL including the color conversion particles QD of blue quantum dots may be provided in the emission area EMA of the third pixel PXL3. Figure 6a light scattering particles (SCT).

[0286] Fig.26a and 26b is a diagram showing the formation of a Figure 6a A cross-sectional view of the method of forming an organic transmission layer OPL is shown in FIG.

[0287] Reference Fig.26a and Figure 26b After the conductive layer CDL is set in each of the first pixel PXL1, the second pixel PXL2 and the third pixel PXL3, the organic transmittance layers OPL1, OPL2 and OPL3 can be sprayed into the corresponding emission areas EMA of the first pixel PXL1, the second pixel PXL2 and the third pixel PXL3 separated from each other by the dam BNK by an inkjet method.

[0288] In one or more embodiments, the organic transmission layers OPL1, OPL2, and OPL3 may be sprayed into the emission areas EMA of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 in the form of an organic solvent including light diffusion particles.

[0289] In one or more embodiments, the thicknesses of the organic transmission layers OPL1, OPL2, and OPL3 sprayed into the corresponding emission areas EMA of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may be the same as each other. In one or more embodiments, the thicknesses of the organic transmission layers OPL1, OPL2, and OPL3 sprayed into the emission area EMA may be different from each other. For example, the thickness of the organic transmission layer OPL1 diffused into the emission area EMA of the first pixel PXL1 may be greater than the thickness of the organic transmission layer OPL2 diffused into the emission area EMA of the second pixel PXL2.

[0290] Figures 27a to 27d is a diagram showing the formation of a Figure 6a A cross-sectional view of the method of forming an organic transmission layer OPL is shown in FIG.

[0291] Reference Fig.27a and Fig.27cIn the first pixel PXL1 , the second pixel PXL2 , and the third pixel PXL3 , the first bank BNK1 may be formed after forming the first and second alignment electrodes ALE1 and ALE2 and the first insulating layer INS1 .

[0292] In one or more embodiments, the first bank BNK1 may be a defining layer that separates the first pixel PXL1 , the second pixel PXL2 , and the third pixel PXL3 from each other.

[0293] In embodiments, after forming the first bank BNK1 , the conductive layer CDL may be disposed.

[0294] Reference Fig.27a After the conductive layer CDL is provided, the organic transmission layers OPL1, OPL2, and OPL3 may be patterned to overlap with the emission areas EMA except the non-emission areas NEA of the corresponding pixels. The organic transmission layers OPL1, OPL2, and OPL3 may be synchronously (e.g., simultaneously) patterned to overlap with the emission areas EMA of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3.

[0295] Reference Fig.27c After the conductive layer CDL is set, the organic transmission layers OPL1 and OPL2 may be synchronously (eg, simultaneously) patterned to overlap with the emission area EMA of the first pixel PXL1 and the emission area EMA of the second pixel PXL2 except for the emission area EMA of the third pixel PXL3.

[0296] In one or more embodiments, since the third light emitting element LD3 emits blue-based light, the third pixel PXL3 emitting blue light may include light scattering particles (eg, Figure 6a light scattering layer of light scattering particles SCT) without including a color conversion layer (e.g., Figure 6a Therefore, due to the contact between the light emitting element LD and the color conversion layer CCL, the degradation phenomenon can be prevented from occurring on the opposite end of the light emitting element LD. Therefore, there is no need to set an organic transmission layer to prevent the degradation phenomenon, so that the organic transmission layers OPL1 and OPL2 can be respectively formed by patterning only in the first pixel PXL1 and the second pixel PXL2 except the third pixel PXL3.

[0297] Reference Figure 27b , after the organic transmission layers OPL1, OPL2, and OPL3 are patterned, the second bank BNK2 may be disposed on the first bank BNK1.

[0298] Reference Fig.27d, after the organic transmission layers OPL1 and OPL2 are patterned, the second bank BNK2 may be disposed on the first bank BNK1.

[0299] In one or more embodiments, the first bank BNK1 may be formed to a height suitable for patterning the organic transmittance layers OPL1, OPL2, and OPL3 to overlap with the corresponding emission areas EMA. In one or more embodiments, the height of the first bank BNK1 may be similar to the heights of the first bank pattern BNKP1 and the second bank pattern BNKP2.

[0300] In one or more embodiments, the second bank BNK2 may be a structure that finally defines the emission area EMA. The second bank BNK2 may be a structure that finally defines a color conversion layer (eg, Figure 5 The structure of the emission area EMA of the color conversion layer (CCL).

[0301] In one or more embodiments, the second bank BNK2 may be formed of the same material as that of the first bank BNK1 .

[0302] In one or more embodiments, the shape of the combination of the first bank BNK1 and the second bank BNK2 may be similar to Fig.26a The shape of the bank BNK shown in FIG.

[0303] Fig.28a and Fig.28b is a diagram showing the formation of a Figure 6a FIG. 4 is a cross-sectional view of a method of forming an organic transmittance layer (OPL) as shown in FIG.

[0304] Reference Fig.28a In the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3, the first bank BNK1' may be formed to overlap the non-emission area NEA after forming the first and second alignment electrodes ALE1 and ALE2 and the first insulating layer INS1.

[0305] In one or more embodiments, after forming the first bank BNK1 ′, the conductive layer CDL may be disposed on the first insulating layer INS1 and overlap the corresponding emission areas EMA of the first pixel PXL1 , the second pixel PXL2 , and the third pixel PXL3 .

[0306] In one or more embodiments, the height of the first bank BNK1 ′ may be similar to the heights of the first and second bank patterns BNKP1 and BNKP2 .

[0307] In one or more embodiments, after forming the conductive layer CDL to overlap the emission area EMA of each pixel, an organic transmission layer OPL" may be disposed on the entire surface of each pixel to cover the first bank BNK1' and the conductive layer CDL of each pixel.

[0308] In one or more embodiments, the organic transmittance layer OPL" may be formed by applying an organic solvent including light diffusion particles to the entire surface to cover the conductive layer CDL and the first bank BNK1' formed in each of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3, and by hardening the organic solvent. The organic solvent including the light diffusion particles may correspond to an organic photoresist material.

[0309] In one or more embodiments, an organic transmittive layer OPL" may be disposed on the first bank BNK1'.

[0310] Reference Fig.28b , after forming the organic transmittive layer OPL″, the second bank BNK2′ may be formed to overlap the first bank BNK1′.

[0311] In one or more embodiments, the second bank BNK2' may be a structure that finally defines the emission area EMA. The second bank BNK2' may be a structure that finally defines a color conversion layer (eg, Figure 5 The structure of the emission area EMA of the color conversion layer (CCL).

[0312] In one or more embodiments, the second bank BNK2 ′ may be formed of the same material as that of the first bank BNK1 ′.

[0313] Although the embodiments of the present disclosure have been described above, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the disclosure as claimed in the accompanying claims and their equivalents.

Claims

1. A display device, comprising a substrate and a pixel on the substrate and including an emission region and a non-emission region, wherein: The pixels include: a light emitting element, wherein in the emission region, the light emitting element comprises a first end and a second end; a first pixel electrode, electrically connected to the first end of the light emitting element; a second pixel electrode, electrically connected to the second end of the light emitting element; an organic transmission layer covering the first end and the second end of the light emitting element, the organic transmission layer comprising light diffusing particles; and A color conversion layer is formed on the organic transmission layer, and includes color conversion particles that convert the light of a first color emitted from the light emitting element into light of a second color.

2. The display device according to claim 1, wherein: The thickness of the organic transmission layer is based on the wavelength of light emitted from the light emitting element.

3. The display device according to claim 1, wherein: The light diffusion particles of the organic transmission layer include a light scatterer having dispersibility in an organic solvent.

4. The display device according to claim 3, wherein: The light scatterer includes at least one of titanium oxide (TiO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), indium oxide (In2O3), zinc oxide (ZnO) or tin oxide (SnO2). 5 . The display device according to claim 1 , further comprising a coating layer between the organic transmission layer and the color conversion layer.

6. The display device according to claim 1, further comprising: a pixel circuit layer including a transistor electrically connected to the light emitting element and a power line; a first bank pattern and a second bank pattern, located on the pixel circuit layer in the emission region and spaced apart from each other; a first alignment electrode on the first bank pattern and electrically connected to the transistor; a second alignment electrode on the second bank pattern and electrically connected to the power line; as well as an insulating layer on the first alignment electrode and the second alignment electrode, The light emitting element is on the insulating layer and between the first alignment electrode and the second alignment electrode in a plan view. 7 . The display device according to claim 6 , further comprising a first insulating pattern between the insulating layer and the light emitting element.

8. The display device according to claim 7, further comprising a second insulating pattern on the light emitting element, wherein: The first end and the second end of the light emitting element are exposed from the second insulating pattern.

9. The display device according to claim 1, wherein: The pixels include: a first pixel configured to emit red light; and a second pixel configured to emit green light.

10. The display device according to claim 9, in, The organic transmission layer includes: a first organic transmission layer in the first pixel; and a second organic transmission layer in the second pixel, and Wherein, the thickness of the first organic transmission layer is smaller than the thickness of the second organic transmission layer.

11. The display device according to claim 9, wherein: The color conversion layer comprises: a first color conversion layer in the first pixel and including red color conversion particles that convert light emitted from the light emitting element of the first pixel into the red light; and The second color conversion layer is in the second pixel and includes green color conversion particles that convert light emitted from the light emitting element of the second pixel into the green light.

12. The display device according to claim 1, wherein: The thickness of the organic transmission layer is 1.5 μm or more and less than 2.5 μm.

13. A display device comprising a substrate and a pixel on the substrate and including an emission region and a non-emission region, wherein: The pixels include: a pixel circuit layer, including transistors and power lines on the substrate; A via layer between the transistor and the power line; a first alignment electrode and a second alignment electrode on the via layer and spaced apart from each other; a first bank pattern on the first alignment electrode; a second bank pattern on the second alignment electrode; an insulating layer on the first bank pattern and the second bank pattern; a light emitting element on the insulating layer and between the first alignment electrode and the second alignment electrode, and including a first end and a second end in a longitudinal direction; a first pixel electrode, electrically connected to the first end of the light emitting element; a second pixel electrode, electrically connected to the second end of the light emitting element; an organic transmission layer covering the first end and the second end of the light emitting element, the organic transmission layer comprising light diffusing particles; and A color conversion layer is formed on the organic transmission layer, and includes color conversion particles that convert the light of a first color emitted from the light emitting element into light of a second color.

14. A method for manufacturing a display device, the method comprising: A pixel including an emission region and a non-emission region is formed on a substrate, wherein the step of forming the pixel comprises: forming a first alignment electrode and a second alignment electrode spaced apart from each other on the substrate; forming an insulating layer on the substrate, the first alignment electrode and the second alignment electrode; forming a first bank defining the emission region and the non-emission region on the insulating layer; aligning a light emitting element on the insulating layer between the first alignment electrode and the second alignment electrode using an electric field formed between the first alignment electrode and the second alignment electrode; forming a conductive layer on the light emitting element and the insulating layer; forming an organic transmission layer including light diffusing particles on the conductive layer; forming a coating layer on the organic transmission layer; removing the organic transmission layer and a portion of the coating layer using a first mask to expose a portion of the conductive layer; removing the exposed portion of the conductive layer, and forming a first pixel electrode electrically connected to a first end of the light emitting element and a second pixel electrode electrically connected to a second end of the light emitting element; and A color conversion layer is formed on the organic transmission layer, the color conversion layer including color conversion particles that convert light of a first color emitted from the light emitting element into light of a second color.

15. The method according to claim 14, wherein: The step of forming the organic transmission layer includes spraying an organic solvent including the light diffusion particles in the emission area.

16. The method according to claim 14, wherein: The forming of the organic transmission layer includes patterning the organic transmission layer so that the organic transmission layer overlaps the emission area except the non-emission area.

17. The method according to claim 14, in, The step of forming the organic transmission layer includes applying an organic solvent including the light diffusing particles to the emission area and the non-emission area, and performing a front exposure operation, Wherein, the organic transmission layer is located on the first bank in the emission area.

18. The method according to claim 16, wherein: The step of forming the organic transmission layer includes forming a second bank on the first bank after forming the organic light emitting layer.

19. The method according to claim 14, wherein: The thickness of the organic transmission layer is based on the wavelength of light emitted from the light emitting element.

20. The method according to claim 14, wherein: The light diffusion particles of the organic transmission layer include a light scatterer having dispersibility in an organic solvent.

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