Bulk silicon manufacturing method and bulk silicon structure
Deep grooves are formed by dry etching and erecting on the side walls to form side grooves, which solves the complexity and cost problems in the traditional bulk silicon manufacturing process, and achieves process simplification and product quality improvement.
Patent Information
- Application Number
- CN202411588711.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-08
- Publication Date
- 2025-02-18
AI Technical Summary
In the traditional bulk silicon manufacturing process, the combination of dry etching and wet etching increases the complexity and cost of the processing process. At the same time, wet etching may cause damage to the silicon wafer, affecting product quality and performance.
The deep groove is formed by dry etching process, and the side walls of the deep groove are etched horizontally through polymer deposition process to form side grooves, avoiding the use of wet etching.
The process flow is simplified, process steps and equipment replacement times are reduced, production efficiency is improved and costs are reduced, while avoiding surface damage of silicon wafers, ensuring product quality and performance.
Smart Images
Figure CN119461239A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a method for manufacturing bulk silicon and a bulk silicon structure. Background Art
[0002] Bulk silicon manufacturing plays an important role in microelectromechanical systems (MEMS) and is widely used in various sensors and microfluidic systems, such as biological detection and chemical sensors. However, the traditional bulk silicon manufacturing process has many challenges.
[0003] In the prior art, the manufacturing of bulk silicon usually starts with dry etching, which forms a deep hole structure. Subsequently, in order to form side grooves on the side walls of the deep hole or create a cavity at the bottom of the deep hole, wet etching is often required. This method of combining dry etching and wet etching not only requires the replacement of workbenches during the production process, increasing the complexity of the processing flow, but also brings additional costs and time consumption.
[0004] In addition, wet etching usually requires descaling, a process that may cause unavoidable damage to the silicon wafer, thus affecting the overall quality and performance of the product. Summary of the invention
[0005] The object of the present invention is to provide a method for manufacturing bulk silicon which can effectively simplify the process flow.
[0006] To achieve the above object, the present invention provides the following technical solution: a method for manufacturing bulk silicon, comprising:
[0007] S1. providing a silicon wafer having an upper surface and a lower surface;
[0008] S2, depositing silicon oxide on the upper surface to form a mask layer, coating the mask layer with photoresist; removing part of the photoresist and the mask layer by a dry etching process to form a mask pattern on the mask layer;
[0009] S3, etching in a direction from the upper surface to the lower surface using a dry etching process according to the mask pattern to form a deep groove;
[0010] S4. Performing isotropic bottom etching with sidewall protection on the sidewalls of the deep trench using a polymer deposition process to widen the side trench laterally to form side trenches.
[0011] Furthermore, the method for manufacturing bulk silicon also includes: the step S4 includes: connecting the side grooves to each other to form a cavity inside the silicon wafer.
[0012] Furthermore, the method for manufacturing bulk silicon further comprises:
[0013] S5. Continue etching from the upper surface to the lower surface of the silicon wafer using a dry etching process below the cavity to further form a deep groove.
[0014] Furthermore, the deep groove formed in step S5 passes through the lower surface of the silicon wafer.
[0015] Furthermore, the method for manufacturing bulk silicon further comprises:
[0016] S6. Filling the deep groove and the side groove with filling material.
[0017] Furthermore, the method for manufacturing bulk silicon further includes: repeating step S4 to form a multi-layer cavity inside the silicon wafer, wherein adjacent cavities are interconnected via deep grooves.
[0018] Furthermore, the method for manufacturing bulk silicon further comprises:
[0019] S5', filling the deep trench and the cavity with dielectric material or polysilicon material.
[0020] Furthermore, in the step S3, the dry etching process adopts the Bosch process.
[0021] The present invention also provides a bulk silicon structure, including a silicon wafer, wherein a deep groove and a side groove formed by transverse etching on the side wall of the deep groove are formed in the silicon wafer, and the deep groove and the side groove are formed by the above-mentioned bulk silicon manufacturing method.
[0022] Furthermore, a cavity is formed in the silicon wafer, and the cavity is formed by interconnecting the side grooves.
[0023] The beneficial effects of the present invention are as follows: the method for manufacturing bulk silicon of the present application first forms a deep groove by a dry etching process, and then forms a side groove by etching laterally on the side wall of the deep groove by a polymer deposition process. During the conversion process between the two, there is no need to interrupt the entire deep silicon etching process, so there is no need to replace the workbench, and the process flow is effectively simplified, which helps to reduce the number of process steps and equipment replacement times, improve production efficiency and reduce costs; in addition, in the stage of forming the side groove, the method abandons the traditional wet etching method, effectively avoiding the surface damage that wet etching may cause to the silicon wafer, thereby ensuring the quality and performance of the final product.
[0024] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention and implement it according to the contents of the specification, the following is a detailed description of the preferred embodiments of the present invention in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] Figure 1 is a flow chart of a method for manufacturing bulk silicon according to an embodiment of the present invention;
[0026] Figure 2 is a schematic diagram of the structure formed by step S2;
[0027] Figure 3 is a schematic diagram of a structure formed at some stages by the Bosch process in step S3;
[0028] Figure 4 is a schematic diagram of a structure formed by other processes in step S3;
[0029] Figure 5a to Figure 5f is a schematic diagram of a structure formed when passing through some stages in step S4;
[0030] Figure 6 is a schematic diagram of the structure formed by step S43;
[0031] Figure 7 A schematic diagram of the structure of forming multi-layer cavities inside a silicon wafer;
[0032] Figure 8 It is a schematic diagram of the structure in which a deep groove penetrates the lower surface of a silicon wafer;
[0033] Fig. 9 It is a schematic diagram of a part of the structure formed by step S6.
[0034] Fig.10 A schematic diagram of a portion of the structure when a dielectric material or polysilicon material is filled; DETAILED DESCRIPTION
[0035] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0036] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.
[0037] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0038] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.
[0039] See also Figure 1 The method for manufacturing bulk silicon shown in one embodiment of the present invention includes:
[0040] S1, providing a silicon wafer 1 having an upper surface 11 and a lower surface 12;
[0041] S2, depositing silicon oxide on the upper surface 11 of the silicon wafer 1 to form a mask layer 2, coating the mask layer 2 with a photoresist 3; removing part of the photoresist 3 and the mask layer 2 by a dry etching process to form a mask pattern 21 on the mask layer 2, please combine Figure 2 ;
[0042] S3, according to the mask pattern 21, using a dry etching process to etch in the direction from the upper surface 11 to the lower surface 12, to form a deep groove 4 (the deep groove 4 can be a groove structure or a hole structure, which is not limited here);
[0043] S4, using a polymer deposition process to perform isotropic etching on the sidewalls of the deep groove 4 with sidewall protection, so as to widen the side grooves 5 in the lateral direction, Figure 5c .
[0044] The above-mentioned method for manufacturing bulk silicon first uses a dry etching process to form a deep groove 4, and then uses a polymer deposition process to laterally etch the side wall of the deep groove 4 to form a side groove 5. During the conversion process between the two, there is no need to interrupt the entire deep silicon etching process. In this way, there is no need to replace the workbench, and the process flow is effectively simplified, which helps to reduce the number of process steps and equipment replacement times, improve production efficiency and reduce costs; in addition, in the formation stage of the side groove 5, this method abandons the traditional wet etching method, effectively avoiding the surface damage that wet etching may cause to the silicon wafer 1, thereby ensuring the quality and performance of the final product.
[0045] In step S3, the dry etching process adopts the Bosch process, and the etching depth of the deep groove 4 is 10-100um. The specific parameters of the Bosch process are as follows: the etching gas is SF6, the protective gas is C4F8, the upper electrode power in the Bosch process is 1000-5000W, the lower electrode power is 50-1000W, the chamber pressure is 10-100mT, the flow rate of the protective gas is 200-1000sccm, the single ventilation time of the protective gas is 5-15s, the flow rate of the etching gas is 400-2000sccm, the single ventilation time of the etching gas is 5-30s, and the temperature during the etching process is controlled between 0℃-20℃. When the Bosch process is adopted, it can be repeated many times to form multiple scallop patterns 41 so that the deep groove 4 reaches a specified depth. The structure of the deep groove 4 is as shown in FIG. Figure 3 shown.
[0046] Of course, in other embodiments, other dry etching processes may also be used to form the deep groove 4. The structure of the deep groove 4 is as follows: Figure 4 As shown, the specific parameters are as follows: the chamber pressure is 10-100mT, the etching source RF power supply (upper electrode) power is 100-1000W, the bias RF power supply (lower electrode) power is 50-500W, the SF6 flow rate is 50-150sccm, and the O2 flow rate is 20-100sccm.
[0047] Step S4 specifically includes:
[0048] S41, please combine Figure 5a , depositing a polymer on the sidewall of the deep trench 4 to form a passivation protection layer 42; in this step, by controlling the deposition conditions, the polymer can evenly cover the sidewall to form the passivation protection layer 42, thereby preventing the subsequent etching steps from causing unnecessary damage to the sidewall;
[0049] S42, please combine Figure 5b , using an anisotropic etching process to remove the passivation protection layer 6 at the bottom of the deep trench 4, thereby opening the deep trench 4; in this step, the characteristics of anisotropic etching are utilized to ensure that only the passivation protection layer 6 at the bottom of the deep trench 4 is removed, while the passivation protection layer 6 on the side wall is retained;
[0050] S43, please combine Figure 5c , continue etching to increase the lateral etching distance at the specified depth position while keeping the critical dimension (CD) of the channel position unchanged to form a side groove 5 on the side wall; in this step, by precisely controlling the etching conditions and parameters, the lateral expansion at a specific depth position is achieved while ensuring the overall dimensional stability of the channel. Figure 5d to Figure 5f The side groove 5 can be realized by changing the single-step parameters of the Bosch process.
[0051] The process parameters used in step S41 are: chamber pressure is 10-150mT, upper electrode power is 1000-5000w, lower electrode power is 0-1000w, passivation deposition gas includes C4F8, wherein the flow rate of C4F8 is 200-1000SCCM, and the passivation deposition time is 30-90s; the process parameters of step S42 are: etching chamber pressure is 10-100mT, upper electrode power is 1000-5000w, lower electrode power is 50-1000w The etching gas includes SF6 and O2, wherein the flow rate of SF6 is 100-1000SCCM, the flow rate of O2 is 50-300SCCM, and the etching time is 10-30s; the process parameters of step S43 are: the process parameters are: etching chamber pressure 10-100mT, upper electrode power 1000-5000w, lower electrode power 0-100w, etching gas is SF6, its flow rate is 100-1000SCCM, and the etching time is 60-300s.
[0052] In the above step S43, the lateral etching distance can be deepened to make the side grooves 5 interconnected, thereby forming a cavity 51 inside the silicon wafer 1. Figure 6 .
[0053] After the cavity 51 is completed, step S4 can be repeated to form multiple layers of cavities 51 inside the silicon wafer 1, wherein adjacent cavities 51 are interconnected through deep grooves 4. Figure 7 Alternatively, the deep groove 4 is further generated, specifically: S5, below the cavity 51, continue etching from the upper surface of the silicon wafer 1 to the lower surface 12 using a dry etching process to further form a deep groove 4. In one embodiment, the deep groove 4 formed in step S5 passes through the lower surface 12 of the silicon wafer 1, as shown in FIG. Figure 8 In other embodiments, the deep trench 4 may not penetrate the silicon wafer 1. In addition, the step S5 may be performed after forming the multi-layer cavity 51.
[0054] After the deep trench 4 passes through the lower surface, a filling material 8 may be filled therein, such as polysilicon, metal or other compounds, depending on the required performance and application scenario. Specifically, the method for manufacturing bulk silicon further includes: S6, filling the deep trench 4 and the side trench 5 with the filling material 8, so that the deep trench 4 and the side trench 5 are closed. In one embodiment, the deep trench 4 may be multiple, see Fig. 9 In this structure, the side groove 5 can be used to limit the filling material 8, thereby improving the reliability of the sealing.
[0055] In another embodiment, the deep trench may not be formed by etching, but a dielectric material or a polysilicon material may be filled in the cavity. Specifically, the method for manufacturing bulk silicon further includes: S5', filling the deep trench and the cavity with a dielectric material or a polysilicon material to form a filling layer 71, and the process parameters are a critical dimension (CD) of 0.5-10 microns, such as Fig.10 .
[0056] Figure 5c The bulk silicon structure shown is a basic structure, which is formed by the aforementioned bulk silicon manufacturing method, and the bulk silicon structure includes a silicon wafer 1, a photoresist 3 formed on the silicon wafer 1, and a mask layer 2. A deep groove 4 and a side groove 5 formed by lateral etching on the side wall of the deep groove 4 are formed in the silicon wafer 1. It should be noted that the basic structure of the bulk silicon structure may not include the photoresist 3 and the mask layer 2.
[0057] Please combine Figure 6 In the bulk silicon structure, a cavity 51 is formed in the silicon wafer 1, and the cavities 51 are interconnected through side grooves. The cavity 51 can be a layer, such as Figure 6 As shown, it can also be multi-layered, such as Figure 7 As shown, the multi-layer cavities 51 are interconnected. Figure 8 In the bulk silicon structure, the deep groove 4 penetrates the lower surface 12. Specifically, the deep groove 4 includes two parts, which are respectively located at the upper side and the lower side of the cavity 51. Fig. 9 The deep groove 4 and the cavity 51 are filled with filling material. Fig.10 ,exist Figure 6 Based on the bulk silicon structure shown, a filling layer 71 is formed in the deep trenches and cavities.
[0058] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0059] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for those of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.
Claims
1. A method for manufacturing bulk silicon, characterized in that: include: S1. providing a silicon wafer having an upper surface and a lower surface; S2, depositing silicon oxide on the upper surface to form a mask layer, and coating the mask layer with photoresist; Removing a portion of the photoresist and the mask layer by a dry etching process to form a mask pattern on the mask layer; S3, etching in a direction from the upper surface to the lower surface using a dry etching process according to the mask pattern to form a deep groove; S4. Performing isotropic bottom etching with sidewall protection on the sidewalls of the deep trench using a polymer deposition process to widen the side trench laterally to form side trenches.
2. The method for manufacturing bulk silicon according to claim 1, wherein: The step S4 includes: connecting the side grooves to each other to form a cavity inside the silicon wafer.
3. The method for manufacturing bulk silicon according to claim 2, wherein: The method for manufacturing bulk silicon further comprises: S5. Below the cavity, continue etching from the upper surface to the lower surface of the silicon wafer using a dry etching process to further form a deep groove.
4. The method for manufacturing bulk silicon according to claim 3, wherein: The deep groove formed in the step S5 passes through the lower surface of the silicon wafer.
5. The method for manufacturing bulk silicon according to claim 4, wherein: The method for manufacturing bulk silicon further comprises: S6. Filling the deep groove and the side groove with filling material.
6. The method for manufacturing bulk silicon according to claim 3, wherein: The method for manufacturing bulk silicon further includes: repeating step S4 to form a multi-layer cavity inside the silicon wafer, wherein adjacent cavities are interconnected via deep trenches.
7. The method for producing bulk silicon according to claim 2 or 5, characterized in that: The method for manufacturing bulk silicon further comprises: S5', filling the deep trench and the cavity with dielectric material or polysilicon material.
8. The method for manufacturing bulk silicon according to claim 1, wherein: In the step S3, the dry etching process adopts the Bosch process.
9. A bulk silicon structure, characterized in that: It comprises a silicon wafer, in which a deep groove and a side groove formed by transverse etching on the side wall of the deep groove are formed, and the deep groove and the side groove are formed by the manufacturing method of bulk silicon as described in any one of claims 1-9.
10. The bulk silicon structure according to claim 9, wherein: A cavity is formed in the silicon wafer, and the cavity is connected to each other through the side grooves.