Test circuit and working method thereof

Abstract

The invention relates to a test circuit and a working method thereof, the test circuit is used for carrying out performance test on a standard unit, the test circuit comprises even number stages of units to be tested which are connected in series, each unit to be tested comprises a main test unit, each main test unit comprises a main test input end and a main test output end, and the main test input end is connected with the main test output end; the main measurement output end of each main measurement unit is connected with the main measurement input end of the next stage of main measurement unit; the output end of the anti-phase voltage source is connected with the main measurement input end of the first-stage main measurement unit, the input end of the anti-phase voltage source is connected with the main measurement output end of the last-stage main measurement unit, and the anti-phase voltage source and the even-stage units to be measured form an annular oscillation loop. The test circuit can test the units to be tested of all combinational logic units, and the application range of the test circuit is expanded.

Description

Technical Field

[0001] The present invention relates to the field of testing technology, and in particular to a testing circuit and a working method of the testing circuit. Background Art

[0002] In semiconductor design, a standard cell is a method for designing application-specific integrated circuits (ASICs) with primarily digital logic features. A standard cell is a group of transistors and interconnects that provide a Boolean logic function (e.g., AND, OR, XOR, XNOR, inverter) or a memory function (flip-flop or latch).

[0003] The key performance indicators of standard cell design are frequency and power consumption, and these two parameters also affect the frequency and power consumption results of the final chip. Improving the accuracy of standard cell frequency and power consumption evaluation and verification, so that they are closer to actual manufacturing test values, can improve the accuracy of subsequent chip design, reduce design verification deviations, and improve chip quality from design to final manufacturing.

[0004] However, existing test circuits connect an odd number of inverters end-to-end to form a ring oscillator loop. Performance and power consumption are determined by measuring the delay time and current in this loop. However, this method is only applicable to standard cells with inverter-like functionality, such as inverters (INV), NAND gates (NAND gates), NOR gates (NOR gates), and AOI gates. It cannot evaluate cells without inversion functionality, such as buffers (BUF), AND gates (AND gates), OR gates (OR gates), AO gates, and multiplexers (MUX gates). Summary of the Invention

[0005] The technical problem solved by the present invention is that it is impossible to test the performance of all types of standard units.

[0006] To solve the above technical problems, an embodiment of the present invention provides a test circuit for performing performance testing on a standard unit, comprising: an even number of units to be tested connected in series, each of the units to be tested including a main test unit, each of the main test units including a main test input terminal and a main test output terminal, the main test output terminal of each main test unit being connected to the main test input terminal of the next-stage main test unit; an inverting voltage source, the output terminal of the inverting voltage source being connected to the main test input terminal of the first-stage main test unit, the input terminal of the inverting voltage source being connected to the main test output terminal of the last-stage main test unit, the inverting voltage source and the even-numbered units to be tested forming a ring oscillation loop.

[0007] Optionally, each of the units under test further includes: M-1 first load units connected to the main test input terminal, the main test unit and the first load units are the same standard unit, and M is a positive integer.

[0008] Optionally, the test circuit further includes: M first load units, wherein input ends of the M first load units are connected to the main test output end of the last stage main test unit.

[0009] Optionally, the number of first loads in the units to be tested at different levels is the same.

[0010] Optionally, the delay time of the inverting voltage source is 0.

[0011] Optionally, the main test units in the units to be tested at different levels are the same standard units.

[0012] Optionally, the main test unit is a combination of one or more of an AND gate circuit standard unit, an OR gate circuit standard unit, a NOT gate circuit standard unit, and a multiplexer standard unit.

[0013] Optionally, the main testing unit has at least one input terminal, and one of the at least one input terminal is the main testing input terminal.

[0014] Optionally, each of the units to be tested also includes a power supply voltage terminal; the test circuit also includes: a test module, which is used to apply a first voltage V1 to each of the power supply voltage terminals, apply a start signal to the main test input terminal of the first-level main test unit, generate an oscillation signal in the ring oscillation loop, and obtain the electrical parameters of the main test unit.

[0015] Optionally, the electrical parameters include current and delay time.

[0016] Optionally, the test module is used to obtain a first frequency on the main test input terminal.

[0017] Optionally, the test module is also used to: measure the first current I1 flowing through the power supply voltage end; obtain the effective resistance value R=V1 / I1 and the power consumption P=V1*I1 of the unit under test based on the first current I1 and the first voltage V1.

[0018] Optionally, the test module is further used to: obtain the delay time t according to the time difference between the oscillation signals delay According to the effective resistance value R and the delay time t delay , get the effective capacitance value C=t delay / R.

[0019] An embodiment of the present invention also provides a working method of the above-mentioned test circuit, including: applying a first voltage V1 to each power supply voltage terminal, applying a start signal to the main test input terminal of the first-level main test unit, generating an oscillation signal in a ring oscillation loop, and obtaining the electrical parameters of the main test unit.

[0020] Optionally, the electrical parameters include current and delay time.

[0021] Optionally, the method for obtaining the electrical parameters of the main measurement unit includes: obtaining a first frequency on the main measurement input terminal.

[0022] Optionally, the method for obtaining the electrical parameters of the main test unit includes: measuring the first current I1 flowing through the power supply voltage end; obtaining the effective resistance value R=V1 / I1 and the power consumption P=V1*I1 of the unit to be tested based on the first current I1 and the first voltage V1.

[0023] Optionally, the method for obtaining the electrical parameters of the main test unit includes: obtaining the delay time t according to the time difference between the oscillation signals delay According to the effective resistance value R and the delay time t delay , get the effective capacitance value C=t delay / R.

[0024] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0025] The test circuit provided in the technical solution of the present invention connects an even-numbered unit under test in series with an inverting voltage source so that the output signal of the unit under test is opposite to the input signal of the unit under test after being inverted by the inverting voltage source, thereby forming a ring oscillation loop, thereby enabling the unit under test of all combinational logic units to be tested, thereby expanding the application range of the test circuit. That is, when the unit under test has an inverter function or does not have an inverter function, the test circuit in the technical solution of the present invention can form a ring oscillation loop to test the performance of the unit under test.

[0026] Furthermore, the number of load cells in the technical solution of the present invention can be flexibly selected according to test requirements.

[0027] Furthermore, in the technical solution of the present invention, the delay time of the inverting voltage source is set to 0, so it will not affect the period of the ring oscillation loop, thereby improving the test accuracy.

[0028] The working method of the test circuit provided in the technical solution of the present invention obtains the electrical parameters of the main test unit during the oscillation of the ring oscillation loop, wherein by obtaining the first frequency, the first current I1, and the first voltage V1, the frequency parameters and power consumption parameters of the main test input end can be obtained, thereby realizing the performance test of the standard unit; by obtaining the effective resistance value R and the effective capacitance value C, the influence of different standard cell layouts on the effective resistance and effective capacitance can be analyzed, and the standard cell layout can be optimized. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a structural diagram of a test circuit;

[0030] Figure 2 is a schematic structural diagram of a test circuit in one embodiment of the present invention;

[0031] Figure 3 This is a schematic diagram of the structure of the main test unit in the test circuit in one embodiment of the present invention. Figure 1 ;

[0032] Figure 4 This is a schematic diagram of the structure of the main test unit in the test circuit in another embodiment of the present invention. Figure 2 . DETAILED DESCRIPTION

[0033] As can be seen from the background art, the test circuit in the prior art is only applicable to standard cells with inverter-like functions and cannot be used to test the performance of standard cells without an inverter function, thus resulting in a limited application range of the test circuit.

[0034] Figure 1 It is a structural diagram of a test circuit.

[0035] Please refer to Figure 1 The test circuit includes: a first-stage unit under test 11, a second-stage unit under test 12 to an X-th-stage unit under test 1X, wherein X is a positive odd number, and the unit under test is a standard unit with an inverting function. The X-stage units under test are connected in series from the first stage to the last stage, and the output of the last-stage unit under test 1X is connected to the input of the first-stage unit under test 11.

[0036] The above scheme involves connecting an odd number of UUTs end to end to form a ring oscillator circuit, measuring the circuit's delay time and current to determine performance and power consumption. Since the UUTs are standard cells with an inverting function, the output signal of the last UUT is opposite to the input signal of the first UUT, thus forming an oscillating signal in the ring circuit. However, for standard cells without an inverting function, the input signal of the first UUT is in phase with the output signal of the last UUT, so no oscillating signal is formed in the ring circuit, making it impossible to test the performance of the standard cells.

[0037] In order to solve the problem that the performance of standard units without inverting function cannot be tested in the above-mentioned test circuit, the technical solution of the present invention provides a test circuit, which connects an even-numbered unit to be tested in series with an inverting voltage source, so that the output signal of the unit to be tested is opposite to the input signal of the unit to be tested after being inverted by the inverting voltage source, thereby forming a ring oscillation loop, thereby realizing the testing of the units to be tested of all combinational logic units.

[0038] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0039] Figure 2 FIG. 1 is a schematic structural diagram of a test circuit in one embodiment of the present invention.

[0040] Please refer to Figure 2 The technical solution of the present invention provides a test circuit for performing performance testing on a standard unit. The test circuit comprises: an even number of test units (21 to 2N) connected in series, each of the test units comprises a main test unit (211 to 2N1), each of the main test units comprises a main test input terminal and a main test output terminal, and the main test output terminal of each main test unit is connected to the main test input terminal of the main test unit of the next stage.

[0041] In this embodiment, the test circuit includes: a first-level unit under test 21, a second-level unit under test 22, a third-level unit under test 23 to an N-th level unit under test 2N, where N is a positive even number.

[0042] Specifically, the number of levels of the unit under test can be 2, or any even number of levels such as 6, 8, etc., and the present invention does not impose any limitation thereto. The number of levels of the unit under test can be set according to actual test requirements.

[0043] In the above scheme, when the number of stages of the units to be tested is an even number, the test structure can test all types of units to be tested, because when the number of stages is an even number, the logic signal states of the main test input terminal and the main test output terminal in the units to be tested with an inverting function or the units to be tested without an inverting function are the same, so oscillation can be achieved after inversion by the inverting voltage source.

[0044] In other embodiments, when the number of stages of the unit to be tested is an odd number, the test structure can only test the unit to be tested that does not have an inverting function, because the logic signal states of the main test input terminal and the main test output terminal of the unit to be tested that does not have an inverting function are the same under the odd number of stages, so oscillation can be achieved after inversion by the inverting voltage source.

[0045] In this embodiment, the main test units in the units to be tested at different levels are the same standard units.

[0046] In this embodiment, the main test unit is a combination of one or more of an AND gate circuit standard unit, an OR gate circuit standard unit, a NOT gate circuit standard unit, and a multiplexer standard unit. The technical solution of the present invention is not limited to this, and combinations of other standard units are within the protection scope of the present invention.

[0047] Figure 3This is a schematic diagram of the structure of the main test unit in the test circuit in one embodiment of the present invention. Figure 1 .

[0048] Please refer to Figure 3 In some embodiments, the main measuring unit is a combination of a first AND gate 51, a second AND gate 52 and a first OR gate 53, and the output ends of the first AND gate 51 and the second AND gate 52 (not shown in the figure) are both connected to the input end Z1 of the first OR gate 53.

[0049] In this embodiment, the main testing unit has at least one input terminal, and one of the at least one input terminal is the main testing input terminal.

[0050] For details, please refer to Figure 3 The first AND gate 51 includes a first input terminal A1 and a second input terminal A2; the second AND gate 52 includes a third input terminal B1 and a fourth input terminal B2. Any input terminal is selected as the main test input terminal according to the test requirements.

[0051] Please continue to refer to Figure 2 The test circuit further includes: an inverting voltage source 3, the output end of the inverting voltage source 3 is connected to the main test input end of the first-stage main test unit 211, the input end of the inverting voltage source 3 is connected to the main test output end of the last-stage main test unit 2N1, and the inverting voltage source 3 and the even-numbered stages of the units to be tested (21 to 2N) form a ring oscillation loop.

[0052] The inverting voltage source 3 is used to invert the output signal of the main measurement output terminal of the last-stage main measurement unit 2N1, so that the output signal of the main measurement output terminal of the last-stage main measurement unit 2N1 is opposite to the input signal of the main measurement input terminal of the first-stage main measurement unit 211, thereby forming an oscillating signal in the ring loop.

[0053] In this embodiment, the delay time of the inverting voltage source 3 is 0, so that the inverting voltage source 3 can achieve the inverting function without affecting the oscillation period of the ring loop.

[0054] Please continue to refer to Figure 2 In this embodiment, each of the units under test further includes: M-1 first load units connected to the main test input terminal, the main test unit and the first load unit are the same standard unit, and M is a positive integer.

[0055] Specifically, the number of first loads in the units to be tested at different levels is the same.

[0056] In this embodiment, the test circuit further includes: M first load units (41 to 4M), the input ends of the M first load units being connected to the main test output end of the last stage main test unit.

[0057] Specifically, when any unit from the first-level main test unit to the N-1-th level main test unit is the current unit to be tested, all standard units in the next-level unit to be tested are fan-outs of the current unit to be tested, and N is a positive even number; when the last-level main test unit is the current unit to be tested, the M first load units (41 to 4M) are all fan-outs of the current unit to be tested.

[0058] In this embodiment, the fan-out quantities of the main testing units are the same.

[0059] In this embodiment, each of the units to be tested also includes a power supply voltage terminal; the test circuit also includes: a test module, which is used to apply a first voltage V1 to each of the power supply voltage terminals, apply a start signal to the main test input terminal of the first-level main test unit, generate an oscillation signal in the ring oscillation loop, and obtain the electrical parameters of the main test unit.

[0060] In some embodiments, the start signal includes a logic signal 1 and a logic signal 0, and the first voltage is 0.75V.

[0061] The electrical parameters include current, delay time t delay .

[0062] In one embodiment, the delay time t delay The acquisition process includes: in the input signal or output signal of any level main test unit, obtaining any node of the time corresponding to the Xth rising edge signal in the input signal or output signal as the first time node t1, obtaining any node of the time corresponding to the Yth rising edge signal in the input signal or output signal as the second time node t2, where Y>X, X and Y are both positive integers, and obtaining the delay time t according to the first time node t1 and the second time node t2. delay =(t2-t1) / (YX).

[0063] The testing module is used to obtain a first frequency on the main testing input terminal.

[0064] The test module is also used to: measure the first current I1 flowing through the power supply voltage terminal; obtain the effective resistance value R=V1 / I1 and the power consumption P=V1*I1 of the unit under test based on the first current I1 and the first voltage V1.

[0065] The test module is further used to obtain the delay time t according to the time difference between the oscillation signals. delay According to the effective resistance value R and the delay time t delay , and obtain the effective capacitance value C=t delay / R.

[0066] The technical solution of the present invention also provides a working method of a test circuit, applying a first voltage V1 to each power supply voltage end, applying a start signal to the main test input end of the first-level main test unit, generating an oscillation signal in a ring oscillation loop, and obtaining the electrical parameters of the main test unit.

[0067] In this embodiment, the electrical parameters include current and delay time.

[0068] In this embodiment, the method for obtaining the electrical parameters of the main measurement unit includes: obtaining a first frequency on the main measurement input terminal.

[0069] In this embodiment, the method for obtaining the electrical parameters of the main test unit includes: measuring the first current I1 flowing through the power supply voltage end; obtaining the effective resistance value R=V1 / I1 and the power consumption P=V1*I1 of the unit under test based on the first current I1 and the first voltage V1.

[0070] In this embodiment, the method for obtaining the electrical parameters of the main test unit includes: obtaining the delay time t according to the time difference between the oscillation signals delay According to the effective resistance value R and the delay time t delay , and obtain the effective capacitance value C=t delay / R.

[0071] The following combination Figure 3 The working process of the test circuit of this embodiment is described as follows:

[0072] Please continue to refer to Figure 3 The main measurement unit includes: a first AND gate 51, a second AND gate 52 and a first OR gate 53, wherein the first AND gate 51 includes a first input terminal A1, a second input terminal A2 and a first output terminal; the second AND gate 52 includes a third input terminal B1, a fourth input terminal B2 and a second output terminal; the first OR gate 53 includes a fifth input terminal, a sixth input terminal and a third output terminal Z1 (i.e., the main measurement output terminal), wherein the fifth input terminal is connected to the first output terminal, and the sixth input terminal is connected to the second output terminal.

[0073] In this embodiment, Figure 3 The truth table of the main test unit in is shown in Table 1:

[0074]

[0075] Table 1

[0076] The values ​​in each column of Table 1 represent the logic signal of any one of the first input terminal A1, the second input terminal A2, the third input terminal B1, the fourth input terminal B2 and the third output terminal Z1, and X represents a logic signal 1 or a logic signal 0.

[0077] According to the test requirements, any input terminal is selected as the main test input terminal, a start signal is applied to the main test input terminal, and other input terminals are configured as fixed potentials.

[0078] In this embodiment, when the first input terminal A1 needs to be tested, the first input terminal A1 is the main test input terminal A1, and a start signal (logic signal 1) is applied to the main test input terminal A1. The second input terminal A2 is configured as the logic signal 1, the third input terminal B1 is configured as the logic signal 0, and the fourth input terminal B2 is configured as the logic signal 0. It can be seen from the truth table of the AND gate that in this embodiment, the main test input terminal A1 (logic signal 1) and the second input terminal A2 (logic signal 1) are calculated to output the logic signal 1 to the fifth input terminal, and the third input terminal B1 (logic signal 0) and the fourth input terminal B2 (logic signal 0) are calculated to output the logic signal 0 to the sixth input terminal. It can be seen from the truth table of the OR gate that the third output terminal outputs the logic signal 1, and then outputs the logic signal 0 after being inverted by the inverting voltage source. At this time, the logic signal at the output terminal of the inverting voltage source is opposite to the start signal of the main test input terminal A1, so as to form oscillation.

[0079] In this embodiment, when the first input terminal A1 needs to be tested, the first input terminal A1 is the main test input terminal A1, and a start signal (logic signal 1) is applied to the main test input terminal A1. The second input terminal A2 is configured as the logic signal 1, the third input terminal B1 is configured as the logic signal 0, and the fourth input terminal B2 is configured as the logic signal 1. It can be seen from the truth table of the AND gate that in this embodiment, the main test input terminal A1 (logic signal 1) and the second input terminal A2 (logic signal 1) are operated to output the logic signal 1 to the fifth input terminal, and the third input terminal B1 (logic signal 0) and the fourth input terminal B2 (logic signal 1) are operated to output the logic signal 0 to the sixth input terminal. It can be seen from the truth table of the OR gate that the third output terminal outputs the logic signal 1, and then outputs the logic signal 0 after being inverted by the inverting voltage source. At this time, the logic signal at the output terminal of the inverting voltage source is opposite to the start signal of the main test input terminal A1, so as to form oscillation.

[0080] In this embodiment, when the first input terminal A1 needs to be tested, the first input terminal A1 is the main test input terminal A1, and a start signal (logic signal 1) is applied to the main test input terminal A1. The second input terminal A2 is configured as the logic signal 1, the third input terminal B1 is configured as the logic signal 1, and the fourth input terminal B2 is configured as the logic signal 0. It can be seen from the truth table of the AND gate that in this embodiment, the main test input terminal A1 (logic signal 1) and the second input terminal A2 (logic signal 1) are operated to output the logic signal 1 to the fifth input terminal, and the third input terminal B1 (logic signal 1) and the fourth input terminal B2 (logic signal 0) are operated to output the logic signal 0 to the sixth input terminal. It can be seen from the truth table of the OR gate that the third output terminal outputs the logic signal 1, and then outputs the logic signal 0 after being inverted by the inverting voltage source. At this time, the logic signal at the output terminal of the inverting voltage source is opposite to the start signal of the main test input terminal A1, so as to form oscillation.

[0081] After the above working process, the electrical parameters of the main test unit measured by the test circuit under different layouts are shown in Table 1:

[0082]

[0083]

[0084] Table 2

[0085] The first column in Table 2 represents the type of the main test unit layout, the second column represents the input terminal type of the main test unit in each layout, and the sixth to ninth columns represent the type and parameter value of the electrical parameters.

[0086] In different layouts, in this embodiment, when the main test input terminal is A1, the input terminal 1 in the third column of Table 2 is the second input terminal A2, the input terminal 2 in the fourth column is the third input terminal B1, and the input terminal 3 in the fifth column is the fourth input terminal B2.

[0087] The input terminals 1 to 3 are configured as follows:

[0088] Logic signal 1, logic signal 0, logic signal 0, or, logic signal 1, logic signal 0, logic signal 1, or, logic signal 1, logic signal 1, logic signal 0.

[0089] In another embodiment, when the main test input terminal is A2, the input terminal 1 in the third column of Table 2 is the first input terminal A1, the input terminal 2 in the fourth column is the third input terminal B1, and the input terminal 3 in the fifth column is the fourth input terminal B2.

[0090] The input terminals 1 to 3 are configured as follows:

[0091] Logic signal 1, logic signal 0, logic signal 0, or, logic signal 1, logic signal 0, logic signal 1, or, logic signal 1, logic signal 1, logic signal 0.

[0092] In this embodiment, when the main test input terminal is B1, the input terminal 1 in the third column of Table 2 is the first input terminal A1, the input terminal 2 in the fourth column is the second input terminal A2, and the input terminal 3 in the fifth column is the fourth input terminal B2.

[0093] The input terminals 1 to 3 are configured as follows:

[0094] Logic signal 0, logic signal 0, logic signal 1 or, logic signal 0, logic signal 1, logic signal 1 or, logic signal 1, logic signal 0, logic signal 1.

[0095] In this embodiment, when the main test input terminal is B2, the input terminal 1 in the third column of Table 2 is the first input terminal A1, the input terminal 2 in the fourth column is the second input terminal A2, and the input terminal 3 in the fifth column is the third input terminal B1.

[0096] The input terminals 1 to 3 are configured as follows:

[0097] Logic signal 0, logic signal 0, logic signal 1 or, logic signal 0, logic signal 1, logic signal 1 or, logic signal 1, logic signal 0, logic signal 1.

[0098] It should be noted that, for each main measurement input terminal, the three configuration modes of the logic signals of the other input terminals given in Table 2 are configuration modes that can measure electrical parameters. Since other configuration modes cannot measure electrical parameters, the present invention will not go into details here and will not be shown in Table 2.

[0099] In this embodiment, please continue to refer to Table 2. When the main test unit is applied to the critical path, the comparison version Figure 1 Japanese version Figure 2 The frequencies of the four input terminals in the circuit can be obtained: Figure 2 When the main test input B1 is tested and input terminals 1 to 3 are configured as: logic signal 0, logic signal 0, logic signal 1, the board Figure 2 The frequency of the main test input terminal B1 is the highest compared to the frequencies of other main test input terminals (1.35) in Table 2, so Figure 1 Japanese version Figure 2 In the comparison, the Figure 2 The main test input terminal B1 has the fastest speed, that is, Figure 2 The main test input terminal B1 has the best performance and can be used for subsequent board alignment. Figure 2The effective resistance and capacitance values ​​of the main test input terminal B1 are analyzed to guide the optimization direction of the layout.

[0100] In this embodiment, please continue to refer to Table 2. When the main test unit is applied to a non-critical path, the comparison version Figure 1 Japanese version Figure 2 The frequencies of the four input terminals can be obtained: Figure 1 The main test input terminal with the worst performance (frequency is 0.88) is: input terminal 1 to input terminal 3 are configured as: logic signal 0, logic signal 0, logic signal 1 when the main test input terminal A2; Figure 2 The main test input terminal with the worst performance (frequency is 1.01) is: input terminal 1 to input terminal 3 are configured as: logic signal 1, logic signal 1, logic signal 0 when the main test input terminal A2. Figure 2 The performance of the worst-performing main test input is still better than that of the Figure 1 The performance of the main test input terminal with the worst performance is better. Therefore, when the main test unit is used in a non-critical path, the version Figure 2 The standard unit is used as the main test unit.

[0101] The following combination Figure 4 The working process of the test circuit of this embodiment is described as follows:

[0102] Figure 4 This is a schematic diagram of the structure of the main test unit in the test circuit in another embodiment of the present invention. Figure 2 .

[0103] Please refer to Figure 4 The main testing unit includes: a second OR gate 61, and the second OR gate 61 includes a seventh input terminal C1, an eighth input terminal C2 and a fourth input terminal Z2.

[0104] In this embodiment, Figure 4 The truth table of the main test unit in is shown in Table 3:

[0105] Seventh input terminal C1 Eighth input terminal C2 Fourth input terminal Z2 0 0 0 X 1 1 1 X 1

[0106] Table 3

[0107] The numerical values ​​in each column of Table 3 represent the logic signal of any one of the seventh input terminal C1, the eighth input terminal C2 and the fourth input terminal Z2, and X represents a logic signal 1 or a logic signal 0.

[0108] According to the test requirements, any input terminal is selected as the main test input terminal, a start signal is applied to the main test input terminal, and other input terminals are configured as fixed potentials.

[0109] In one embodiment, when the seventh input terminal C1 needs to be tested, the seventh input terminal C1 is the main test input terminal, a start signal (logic signal 1) is applied to the main test input terminal, and the eighth input terminal C2 is configured as a logic signal 0. As can be seen from Table 3, in this embodiment, the main test input terminal (logic signal 1) and the eighth input terminal C2 (logic signal 0) are calculated to output a logic signal 1 to the fourth input terminal Z2, and then the logic signal 0 is output after being inverted by the inverting voltage source. At this time, the logic signal at the output terminal of the inverting voltage source is opposite to the start signal of the main test input terminal, so as to form oscillation.

[0110] In another embodiment, when the seventh input terminal C1 needs to be tested, the seventh input terminal C1 is the main test input terminal, and a start signal (logic signal 0) is applied to the main test input terminal. The eighth input terminal C2 is configured as logic signal 0. As can be seen from Table 3, in this embodiment, the main test input terminal (logic signal 0) and the eighth input terminal C2 (logic signal 0) are calculated to output logic signal 0 to the fourth input terminal Z2, and then the logic signal 1 is output after being inverted by the inverting voltage source. At this time, the logic signal at the output terminal of the inverting voltage source is opposite to the start signal of the main test input terminal, so as to form oscillation.

[0111] After the above working process, the electrical parameters of the main test unit measured by the test circuit under different layouts are shown in Table 4:

[0112]

[0113]

[0114] Table 4

[0115] The first column in Table 4 represents the type of the main test unit layout, the second column represents the input terminal type of the main test unit in each layout, and the third to fifth columns represent the type and parameter value of the electrical parameters.

[0116] In different layouts, when the main test input terminal is the seventh input terminal C1, the input terminal 1 in the third column of Table 2 is the eighth input terminal C2 and is configured as a logic signal 0.

[0117] When the main-test input terminal is the eighth input terminal C2 , the input terminal 1 in the third column of Table 2 is the seventh input terminal C1 and is configured as a logic signal 0.

[0118] It should be noted that, for each main measurement input terminal, the configuration method of the logic signal of the other input terminals given in Table 4 is a configuration method that can measure electrical parameters. Since other configuration methods cannot measure electrical parameters, the present invention will not be repeated here and will not be shown in Table 4.

[0119] In this embodiment, please continue to refer to Table 4. When the main test unit is applied to the critical path, the comparison version Figure 1 To the two input frequencies in the layout 5, we can get: Figure 4 The main input terminal C1 is measured, and when the eighth input terminal C2 is configured as a logic signal 0, the Figure 4 The main test input terminal C1 has the fastest speed, that is, Figure 4 The main test input terminal C1 has the highest performance and can be used for subsequent board Figure 4 The effective resistance and capacitance values ​​of the main test input terminal C1 are analyzed to guide the optimization direction of the layout.

[0120] When the master test unit is applied to the critical path, the comparison Figure 1 To the frequency of the two input terminals in Figure 5, we can get: Figure 4 The main test input terminal with the worst performance (frequency is 0.88) is: the seventh input terminal C1 is configured as the main test input terminal C2 of the logic signal 0. It can be seen that the Figure 4 The performance of the main test input terminal C2, which has the worst performance, is still better than that of the Figure 1 ,version Figure 2 ,version Figure 3 The performance of the main test input terminal with the worst performance in layout 5 is higher. Therefore, when the main test unit is used in a non-critical path, the layout 5 is still selected. Figure 4 The standard unit is used as the main test unit.

[0121] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A test circuit for performing performance testing on a standard unit, characterized in that: include: An even number of units to be tested are connected in series, each of which includes a main test unit, each of which includes a main test input terminal and a main test output terminal, and the main test output terminal of each main test unit is connected to the main test input terminal of the main test unit of the next stage; An inverting voltage source, wherein the output end of the inverting voltage source is connected to the main measurement input end of the first-stage main measurement unit, the input end of the inverting voltage source is connected to the main measurement output end of the last-stage main measurement unit, and the inverting voltage source and the even-numbered-stage units to be measured form a ring oscillation loop.

2. The test circuit according to claim 1, characterized in that: Each of the units under test further includes: M-1 first load units connected to the main test input terminal, the main test unit and the first load unit are the same standard unit, and M is a positive integer.

3. The test circuit according to claim 2, characterized in that: It also includes: M first load units, wherein input ends of the M first load units are connected to the main test output end of the last stage main test unit.

4. The test circuit according to claim 2, characterized in that: The number of first loads in the units under test of different levels is the same.

5. The test circuit according to claim 1, characterized in that: The delay time of the inverting voltage source is 0.

6. The test circuit according to claim 1, characterized in that: The main test units in the units to be tested at different levels are the same standard units.

7. The test circuit according to claim 1, characterized in that: The main test unit is one or a combination of a standard AND gate circuit unit, a standard OR gate circuit unit, a standard NOT gate circuit unit, and a standard multiplexer unit.

8. The test circuit according to claim 1, characterized in that: The main measuring unit has at least one input terminal, and one of the at least one input terminal is the main measuring input terminal.

9. The test circuit according to claim 1, characterized in that: Each of the units to be tested also includes a power supply voltage terminal; the test circuit also includes: a test module, which is used to apply a first voltage V1 to each of the power supply voltage terminals, apply a start signal to the main test input terminal of the first-level main test unit, generate an oscillation signal in the ring oscillation loop, and obtain the electrical parameters of the main test unit.

10. The test circuit according to claim 9, characterized in that: The electrical parameters include current and delay time.

11. The test circuit according to claim 9, characterized in that: The testing module is used to obtain a first frequency on the main testing input terminal.

12. The test circuit according to claim 9, characterized in that: The test module is also used to: measure a first current I1 flowing through the power supply voltage terminal; and obtain an effective resistance value R=V1 / I1 and a power consumption P=V1*I1 of the unit under test according to the first current I1 and the first voltage V1.

13. The test circuit according to claim 12, characterized in that: The test module is also used to: obtain the delay time t according to the time difference between the oscillation signals delay ; According to the effective resistance value R and the delay time t delay , and obtain the effective capacitance value C = t delay / R.

14. A working method of the test circuit according to any one of claims 1 to 13, characterized in that: include: A first voltage V1 is applied to each power supply voltage terminal, a start signal is applied to a main test input terminal of a first-stage main test unit, an oscillation signal is generated in a ring oscillation loop, and electrical parameters of the main test unit are obtained.

15. The operating method of the test circuit according to claim 14, characterized in that: The electrical parameters include current and delay time.

16. The operating method of the test circuit according to claim 14, characterized in that: The method for acquiring the electrical parameters of the main test unit includes: acquiring a first frequency on the main test input terminal.

17. The operating method of the test circuit according to claim 14, characterized in that: The method for obtaining the electrical parameters of the main test unit includes: measuring a first current I1 flowing through the power supply voltage terminal; obtaining an effective resistance value R=V1 / I1 and a power consumption P=V1*I1 of the unit under test according to the first current I1 and the first voltage V1.

18. The operating method of the test circuit according to claim 17, characterized in that: The method for obtaining the electrical parameters of the main test unit includes: obtaining the delay time t according to the time difference between the oscillation signals delay ; According to the effective resistance value R and the delay time t delay , and obtain the effective capacitance value C = t delay / R.

Images