LED chip test management method and system

Abstract

The invention provides an LED chip test management method and system, and the method comprises the following steps: comparing the correction data of a wafer, and comparing first spot test calibration data with a standard value if the wafer is abnormal, so as to judge whether the qualified rate of each chip corresponding to the first spot test calibration data is greater than a preset value or not; if the qualified rate is greater than a preset value, calculating the slope of a linear regression line of the change rate of each first spot test calibration data according to the coordinate data; and if the slope is smaller than a preset value, determining that the wafer is qualified. After chip testing is completed, wafer data abnormity, namely HOLD wafers, is analyzed, if the qualified rate of the part of chips is larger than the preset value and the slope is smaller than the preset value, the wafers are automatically judged to be qualified, HOLD of abnormal wafers meeting the conditions is automatically removed through analysis of the newly added abnormal data of the part, and the situation that the wafer data are abnormal due to large data errors is reduced. And therefore, the production and processing efficiency can be improved.

Description

Technical Field

[0001] The present invention relates to the field of chip testing technology, and in particular to a method and system for managing LED chip testing. Background Art

[0002] In the LED chip manufacturing industry, as production capacity increases, in wafer optoelectronic property testing, since there are tens of thousands of grains on a wafer, in order to improve test efficiency, MAP full test is usually used to perform batch rapid testing on the chips on the wafer through multiple probe groups at the same time. However, this method may cause data deviations due to problems such as differences in wear between probes. Therefore, it is also necessary to use the test data obtained by APC point test with higher accuracy to pull back and correct the full test data.

[0003] In the prior art, although the data has been corrected through APC point measurement, wafer judgment based on the corrected data will still result in a large number of abnormal HOLD wafers (approximately 20% of the total wafer quantity) due to the large data deviation. Subsequently, engineering personnel will need to perform secondary judgment on the abnormal HOLD wafers, affecting efficiency. Summary of the invention

[0004] In view of the deficiencies in the prior art, the purpose of the present invention is to provide an LED chip test management method and system, aiming to solve the technical problem in the prior art that a large number of abnormal HOLD wafers need to be determined and processed by engineering personnel, which affects efficiency.

[0005] In order to achieve the above object, the present invention is implemented by the following technical solution: a method for managing LED chip testing, comprising the following steps:

[0006] Performing MAP full test on each chip on the wafer to obtain test optoelectronic data of each chip;

[0007] Selecting some chips in the middle of the wafer for APC sampling test to obtain a plurality of first sampling calibration data, wherein the test photoelectric data includes first data corresponding to the coordinates of the first sampling calibration data;

[0008] A first correction coefficient is calculated based on the deviation value between the first sample calibration data and the first data, so as to correct the test photoelectric data based on the first correction coefficient to obtain corrected data;

[0009] Comparing the correction data corresponding to each chip in the wafer with a standard value to determine whether the wafer is abnormal;

[0010] If the wafer is abnormal, the first sampling calibration data is compared with the standard value to determine whether the qualified rate of each chip corresponding to the first sampling calibration data is greater than a preset value;

[0011] If the qualified rate of each chip corresponding to the first sampling calibration data is greater than a preset value, the slope of the linear regression line of the change rate of each first sampling calibration data is calculated according to the coordinate data;

[0012] If the slope is less than a preset value, the wafer is determined to be qualified.

[0013] According to one aspect of the above technical solution, after the step of determining whether the qualified rate of each chip corresponding to the first sampling calibration data is greater than a preset value, the method further includes:

[0014] If the qualified rate of each chip corresponding to the first sampling calibration data is less than a preset value, the wafer is determined to be unqualified.

[0015] According to one aspect of the above technical solution, after the step of calculating the slope of the linear regression line of the change rate of each of the first sampled calibration data according to the coordinate data, the method further includes:

[0016] If the slope is greater than a preset value, the wafer is determined to be unqualified.

[0017] According to one aspect of the above technical solution, after the step of determining that the wafer is unqualified, the method further includes:

[0018] A second APC sampling test is performed on some chips in the middle of the wafer to obtain the second sampling calibration data.

[0019] According to one aspect of the above technical solution, the calculation formula of the first correction coefficient is as follows:

[0020] p = m / n;

[0021] In the formula, p is the first correction coefficient, m is the mean value of each of the first sampled calibration data, and n is the mean value of each of the first data.

[0022] According to one aspect of the above technical solution, the step of selecting some chips in the middle of the wafer for APC sampling specifically includes:

[0023] Align the wafer with the APC test machine, and select chips in a row of the wafer center coordinate points for APC sampling testing.

[0024] According to one aspect of the above technical solution, the first sampling calibration data and the test photoelectric data both include: working voltage VF data, brightness IV data and wavelength WLD data.

[0025] On the other hand, the present invention also provides an LED chip test management system, comprising:

[0026] A full test data module is used to perform a MAP full test on each chip on the wafer to obtain test optoelectronic data of each chip;

[0027] A sampling data module, used for selecting some chips in the middle of the wafer for APC sampling to obtain a plurality of first sampling calibration data, wherein the test photoelectric data includes first data corresponding to the coordinates of the first sampling calibration data;

[0028] A first correction module, configured to calculate a first correction coefficient based on a deviation between the first sample calibration data and the first data, so as to correct the test photoelectric data based on the first correction coefficient to obtain corrected data;

[0029] A comparison module, used for comparing the correction data corresponding to each chip in the wafer with a standard value to determine whether the wafer is abnormal;

[0030] A qualified rate analysis module, used for comparing the first sampling calibration data with the standard value if the wafer is abnormal, so as to determine whether the qualified rate of each chip corresponding to the first sampling calibration data is greater than a preset value;

[0031] A slope analysis module, configured to calculate the slope of a linear regression line of the change rate of each of the first sampling calibration data according to the coordinate data if the qualified rate of each chip corresponding to the first sampling calibration data is greater than a preset value;

[0032] The first determination module is used to determine that the wafer is qualified if the slope is less than a preset value.

[0033] According to one aspect of the above technical solution, the system further includes:

[0034] The second determination module is used to determine that the wafer is unqualified if the qualified rate of each chip corresponding to the first sampling calibration data is less than a preset value.

[0035] According to one aspect of the above technical solution, the system further includes:

[0036] The third determination module is used to determine that the wafer is unqualified if the slope is greater than a preset value.

[0037] According to one aspect of the above technical solution, the system further includes:

[0038] The second correction module is used to perform a second APC sampling test on some chips in the middle of the wafer to obtain second sampling calibration data.

[0039] According to one aspect of the above technical solution, the sampling test module is specifically used for:

[0040] Align the wafer with the APC test machine, and select chips in a row of the wafer center coordinate points for APC sampling testing.

[0041] Compared with the prior art, the beneficial effect of the present invention lies in: after the chip test is completed, for the wafer data abnormality, that is, the HOLD wafer, the first sampling data is compared with the standard value to determine whether the corresponding chip qualification rate of this part is greater than the preset value, and whether the slope of the linear regression line of the change rate of each of the first sampling calibration data is less than the preset value. If the chip qualification rate of this part is greater than the preset value and the slope is less than the preset value, the wafer is automatically judged to be qualified. By adding the abnormal data analysis of this part, the HOLD is automatically released for the abnormal wafers that meet the conditions, reducing the impact of the problem of a high number of abnormal wafers caused by large data errors, and improving production and processing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 This is a flow chart of the LED chip test management method in the first embodiment of the present invention;

[0043] Figure 2 This is a schematic diagram of data distribution in which the slope of the linear regression line in step S600 in the first embodiment of the present invention is less than a preset value;

[0044] Figure 3 This is a schematic diagram of data distribution in which the slope of the linear regression line in step S600 in the first embodiment of the present invention is greater than a preset value;

[0045] Figure 4 This is a structural block diagram of an LED chip test management system in a second embodiment of the present invention;

[0046] The following specific implementation manner will further illustrate the present invention in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0047] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Several embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0048] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0050] See also Figure 1 , which is a flow chart of the LED chip test management method in the first embodiment of the present invention. As shown in the figure, the method includes the following steps:

[0051] Step S100, MAP full test is performed on each chip on the wafer to obtain the test photoelectric data of each chip. Specifically, in this step, the data of the above-mentioned MAP full test will deviate due to the wear difference between the probes and the different light receiving positions of the grain distance. That is, the above-mentioned MAP full test refers to the high-efficiency batch chip data detection with lower detection accuracy through the method of multi-crystal parallel testing.

[0052] In some applications of this embodiment, multi-crystal parallel testing is based on 8 groups of probes arranged longitudinally, moving along the X-axis direction until 8 horizontal columns of channel testing are completed, and then moving toward the Y-axis direction to continue to complete 8 horizontal columns of channel testing until all channels are tested.

[0053] Step S200, selecting some chips in the middle of the wafer for APC sampling to obtain a plurality of first sampling calibration data, wherein the test photoelectric data includes first data corresponding to the coordinates of the first sampling calibration data.

[0054] The above-mentioned APC sampling refers to the data detection of the chip with higher precision through the spot test machine. The above-mentioned first sampling calibration data is used to pull back and correct the deviation of the above-mentioned test photoelectric data, thereby reducing the impact of the overall data deviation caused by probe wear or alignment problems during multi-crystalline parallel measurement.

[0055] Preferably, in this embodiment, the step of selecting some chips in the middle of the wafer for APC sampling specifically includes:

[0056] Align the wafer with the APC test machine, and select chips in a row of the wafer center coordinate points for APC sampling testing.

[0057] Step S300, based on the deviation value between the first sample calibration data and the first data, a first correction coefficient is calculated to correct the test photoelectric data based on the first correction coefficient to obtain corrected data. Preferably, in this embodiment, the calculation formula of the first correction coefficient is as follows:

[0058] p = m / n;

[0059] Wherein, p is the first correction coefficient, m is the mean of each of the first sampling calibration data, and n is the mean of each of the first data. When the mean of the first sampling calibration data is high, it means that the sampling value of the test photoelectric data is low, and the value of the first correction data is greater than 1; when the mean of the first sampling calibration data is low, it means that the sampling value of the test photoelectric data is high, and the value of the first correction data is less than 1.

[0060] The first sampling calibration data and the test photoelectric data include: working voltage VF data, brightness IV data and wavelength WLD data. It can be understood that the correction coefficients in the above text and the data comparison below all need to be corrected and compared with the working voltage VF data, brightness IV data and wavelength WLD data in sequence.

[0061] The expression of the above correction data is:

[0062] K = k*p;

[0063] Where K is the correction data and k is the test photoelectric data.

[0064] Step S400, comparing the correction data corresponding to each chip in the wafer with a standard value to determine whether the wafer is abnormal.

[0065] Specifically, in this embodiment, the data after wafer correction needs to meet the following rules:

[0066] Working voltage VF data: ±0.04V;

[0067] Brightness IV data: ±5% mcd;

[0068] Wavelength WLD data: ±0.5nm;

[0069] If the above comparison rules are met, it means that the chip is qualified. When the proportion of qualified chips in the wafer reaches the standard value, that is, the yield meets the requirements, it means that the wafer is qualified, otherwise it is judged as an abnormal wafer.

[0070] Step S500: if the wafer is abnormal, the first sampling calibration data is compared with the standard value to determine whether the qualified rate of each chip corresponding to the first sampling calibration data is greater than a preset value.

[0071] Specifically, in this embodiment, the preset value is 95%, that is, when the number of compared chips is 600, only 30 or less defective chips (NG chips) are allowed. It should be noted that the working voltage VF data, brightness IV data and wavelength WLD data need to be considered during the comparison. As long as one of the data is unqualified, the chip is a defective chip. The specific comparison method can refer to the above comparison rules.

[0072] Step S600: if the qualified rate of each chip corresponding to the first sampling calibration data is greater than a preset value, the slope of the linear regression line of the change rate of each first sampling calibration data is calculated according to the coordinate data.

[0073] Step S700: If the slope is less than a preset value, the wafer is determined to be qualified. 2 When it is close to 0, it indicates that the data deviation is small. In the present embodiment, the preset value is preferably 0.2, that is, when the slope is ≤ 0.2, it indicates that the wafer is qualified and the wafer is judged to be PASS.

[0074] Specifically, in this embodiment, a linear regression line may be established according to the data changes corresponding to the coordinate distribution rule, and the slope of the linear regression line may be calculated.

[0075] Specifically, in some application scenarios of this embodiment, such as Figure 2 This is a data diagram of linear distribution data satisfying: y = -0.000016532x + 1.009716129, and its slope satisfies: R 2 =0.003030358; as shown in the figure, the data is evenly distributed and the wafer is qualified.

[0076] like Figure 3 This is a data diagram of linear distribution data satisfying: y = -0.006121371x + 1.084974194, and its slope satisfies: R 2 =0.913635053; As shown in the figure, the data distribution deviation is large, and the wafer is judged to be unqualified. In order to reduce the amount of data calculation, the sampling of data points can be sampled at intervals according to the distribution of coordinates. For example, among 600 chip data, 30 data are sampled at uniform intervals for linear distribution analysis.

[0077] When the abnormal wafer satisfies both step S600 and step S700, it indicates that at least some chips tested by the spot test data have a high pass rate, and the abnormality is most likely caused by a large deviation in the full test data. This can replace manual judgment to release the HOLD and reduce workload.

[0078] It can be understood that after the step of determining that the wafer is unqualified, the method further includes:

[0079] A second APC sampling test is performed on some chips in the middle of the wafer to obtain the second sampling calibration data. The reason for the abnormal data of normal wafers, in addition to the large deviation of the full test data, may also be a problem with the sampling of the sampling calibration data, such as a problem with the coordinate alignment. After the comparison of the above steps S600 and S700 has problems, the sampling data is re-acquired to obtain the second sampling calibration data, and then the new correction coefficient is re-obtained based on the second sampling calibration data, and the steps of steps 400-600 are repeated in sequence based on the new data to compare and analyze the data. It can be understood that after obtaining the new sampling data, if the wafer still fails, the wafer is judged to be HOLD and it is necessary to wait for the engineering personnel to make a judgment.

[0080] In summary, the LED chip test management method in the above-mentioned embodiment of the present invention, after the chip test is completed, for the wafer data abnormality, that is, the HOLD wafer, compares the first sampled data with the standard value to determine whether the corresponding chip qualification rate of this part is greater than the preset value, and determines whether the slope of the linear regression line of the change rate of each of the first sampled calibration data is less than the preset value. If the chip qualification rate of this part is greater than the preset value and the slope is less than the preset value, the wafer is automatically determined to be qualified. By adding the abnormal data analysis of this part, the HOLD is automatically released for the abnormal wafers that meet the conditions, reducing the impact of the problem of a high number of abnormal wafers caused by large data errors, and improving production and processing efficiency.

[0081] Please refer to Figure 2 , which is a structural block diagram of the LED chip test management system in the second embodiment of the present invention. As shown in the figure, the system includes a full test data module 100, a sampling data module 200, a first correction module 300, a comparison module 400, a pass rate analysis module 500, a slope analysis module 600 and a first determination module 700.

[0082] The full test data module 100 is used to perform MAP full test on each chip on the wafer to obtain test optoelectronic data of each chip;

[0083] The sampling data module 200 is used to select some chips in the middle of the wafer for APC sampling to obtain a plurality of first sampling calibration data, wherein the test photoelectric data includes first data and second data corresponding to the coordinates of the first sampling calibration data;

[0084] The first correction module 300 is used to calculate a first correction coefficient based on the deviation value between the first sampling calibration data and the first data, so as to correct the test photoelectric data based on the first correction coefficient to obtain corrected data;

[0085] The comparison module 400 is used to compare the correction data corresponding to each chip in the wafer with the standard value to determine whether the wafer is abnormal;

[0086] The qualified rate analysis module 500 is used to compare the first sampling calibration data with the standard value if the wafer is abnormal, so as to determine whether the qualified rate of each chip corresponding to the first sampling calibration data is greater than a preset value;

[0087] The slope analysis module 600 is used to calculate the slope of the linear regression line of the change rate of each of the first sampling calibration data according to the coordinate data if the qualified rate of each chip corresponding to the first sampling calibration data is greater than a preset value;

[0088] The first determination module 700 is used to determine that the wafer is qualified if the slope is less than a preset value.

[0089] Preferably, in this embodiment, the system further includes:

[0090] The second determination module is used to determine that the wafer is unqualified if the qualified rate of each chip corresponding to the first sampling calibration data is less than a preset value.

[0091] Preferably, in this embodiment, the system further includes:

[0092] The third determination module is used to determine that the wafer is unqualified if the slope is greater than a preset value.

[0093] Preferably, in this embodiment, the system further includes:

[0094] The second correction module is used to perform a second APC sampling test on some chips in the middle of the wafer to obtain second sampling calibration data.

[0095] Preferably, in this embodiment, the sampling module is specifically used for:

[0096] Align the wafer with the APC test machine, and select chips in a row of the wafer center coordinate points for APC sampling testing.

[0097] In summary, the LED chip test management system of the present invention and the above-mentioned embodiments tests the chip photoelectric data through the sampling data module 200, the full test data module 100, the first correction module 300 and the comparison module. After the chip test is completed, for the wafer data abnormality, that is, the HOLD wafer, the first sampling data is compared with the standard value based on the qualification rate analysis module 500 to determine whether the corresponding chip qualification rate of this part is greater than the preset value, and the slope analysis module 600 determines whether the slope of the linear regression line of the change rate of each of the first sampling calibration data is less than the preset value. If the chip qualification rate of this part is greater than the preset value and the slope is less than the preset value, the wafer is automatically determined to be qualified through the first judgment module 700. By adding the abnormal data analysis of this part, the HOLD is automatically released for the abnormal wafer that meets the conditions, thereby reducing the impact of the problem of a high number of abnormal wafers caused by large data errors and improving production and processing efficiency.

[0098] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0099] The above-described embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the present invention. It should be pointed out that, for a person of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the attached claims.

Claims

1. A LED chip test management method, characterized in that: The following steps are involved: Performing MAP full test on each chip on the wafer to obtain test optoelectronic data of each chip; Selecting some chips in the middle of the wafer for APC sampling test to obtain a plurality of first sampling calibration data, wherein the test photoelectric data includes first data corresponding to the coordinates of the first sampling calibration data; A first correction coefficient is calculated based on the deviation value between the first sample calibration data and the first data, so as to correct the test photoelectric data based on the first correction coefficient to obtain corrected data; Comparing the correction data corresponding to each chip in the wafer with a standard value to determine whether the wafer is abnormal; If the wafer is abnormal, the first sampling calibration data is compared with the standard value to determine whether the qualified rate of each chip corresponding to the first sampling calibration data is greater than a preset value; If the qualified rate of each chip corresponding to the first sampling calibration data is greater than a preset value, the slope of the linear regression line of the change rate of each first sampling calibration data is calculated according to the coordinate data; If the slope is less than a preset value, the wafer is determined to be qualified.

2. The LED chip test management method according to claim 1, characterized in that: After the step of determining whether the qualified rate of each chip corresponding to the first sampling calibration data is greater than a preset value, the method further includes: If the qualified rate of each chip corresponding to the first sampling calibration data is less than a preset value, the wafer is determined to be unqualified.

3. The LED chip test management method according to claim 1, characterized in that: After the step of calculating the slope of the linear regression line of the change rate of each of the first sampled calibration data according to the coordinate data, the method further comprises: If the slope is greater than a preset value, the wafer is determined to be unqualified.

4. The LED chip test management method according to claim 2 or 3, characterized in that: After the step of determining that the wafer is unqualified, the method further comprises: A second APC sampling test is performed on some chips in the middle of the wafer to obtain the second sampling calibration data.

5. The LED chip test management method according to claim 1, characterized in that: The calculation formula of the first correction coefficient is as follows: p = m / n; In the formula, p is the first correction coefficient, m is the mean value of each of the first sampled calibration data, and n is the mean value of each of the first data.

6. The LED chip test management method according to claim 1, characterized in that: The steps of selecting some chips in the middle of the wafer for APC sampling testing specifically include: Align the wafer with the APC test machine, and select chips in a row of the wafer center coordinate points for APC sampling testing.

7. The LED chip test management method according to claim 1, characterized in that: The first sampling calibration data and the test photoelectric data both include: working voltage VF data, brightness IV data and wavelength WLD data.

8. An LED chip test management system, characterized in that: include: A full test data module is used to perform a MAP full test on each chip on the wafer to obtain test optoelectronic data of each chip; A sampling data module, used for selecting some chips in the middle of the wafer for APC sampling to obtain a plurality of first sampling calibration data, wherein the test photoelectric data includes first data corresponding to the coordinates of the first sampling calibration data; A first correction module, configured to calculate a first correction coefficient based on a deviation between the first sample calibration data and the first data, so as to correct the test photoelectric data based on the first correction coefficient to obtain corrected data; A comparison module, used for comparing the correction data corresponding to each chip in the wafer with a standard value to determine whether the wafer is abnormal; A qualified rate analysis module, used for comparing the first sampling calibration data with the standard value if the wafer is abnormal, so as to determine whether the qualified rate of each chip corresponding to the first sampling calibration data is greater than a preset value; A slope analysis module, configured to calculate the slope of a linear regression line of the change rate of each of the first sampling calibration data according to the coordinate data if the qualified rate of each chip corresponding to the first sampling calibration data is greater than a preset value; The first determination module is used to determine that the wafer is qualified if the slope is less than a preset value.

9. The LED chip test management system according to claim 8, characterized in that: The system further comprises: The second determination module is used to determine that the wafer is unqualified if the qualified rate of each chip corresponding to the first sampling calibration data is less than a preset value.

10. The LED chip test management system according to claim 8, characterized in that: The system further comprises: The second correction module is used to perform a second APC sampling test on some chips in the middle of the wafer to obtain second sampling calibration data.

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