Testing device and testing method

Abstract

The invention provides a testing device and a testing method, the testing device comprises a power supply module, a switch module, a load module, a single-chip microcomputer control module and a counter module, the switch module comprises a first switch, a second switch and a third switch; a first voltage output end of the power supply module is connected to an enabling end of a to-be-tested device after being connected in series with the second switch, and is connected to an input end of the to-be-tested device after being connected in series with the third switch, the load module is connected to an output end of the to-be-tested device after being connected in series with the first switch, and the load module is connected to different loads to the to-be-tested device under the control of the first switch; the counter is used for monitoring rising edge and falling edge times, high level duration time and low level duration time of an output signal of the device to be detected; the single-chip microcomputer control module outputs a first control signal to the first switch, outputs a second control signal to the second switch, outputs a third control signal to the third switch according to the test instruction, and judges whether the test is qualified or not according to the monitoring result.

Description

Technical Field

[0001] The present disclosure relates to the field of circuit testing technology, and more specifically, to a testing device and a testing method. Background Art

[0002] In the field of information technology, the USB interface is a widely used standard interface. Since its invention in 1996, it has not only greatly promoted the connection and data transmission between devices, but also realized the function of energy transfer. It is widely used in information technology equipment, audio and video equipment, communication technology equipment and other fields. In order to ensure the safe and stable use of the USB interface in various devices, especially when connecting additional devices, its power, current, temperature and other parameters need to be strictly controlled and limited to prevent equipment damage or information loss caused by current surges and other reasons. Therefore, as a key component, the USB current limiting IC plays a vital role in the design of USB interface circuits.

[0003] However, in practical applications, in addition to meeting specific specifications and functional requirements, USB current limiting ICs must also pass rigorous reliability tests to ensure that they can maintain stability and safety during long-term and frequent use. In the GB4943.1-2022 standard, clear requirements are put forward for the safety protection of connected additional devices and the power limitation delivered to connected devices or accessories. In particular, Chapter G.9 provides detailed provisions for the reliability test of USB current limiting ICs.

[0004] At present, the traditional USB current limiting IC test methods and devices have significant shortcomings when conducting the reliability test specified in Section G.9.2. On the one hand, these test methods usually rely on a large number of laboratory test resources, such as repeated cyclic operations, long test cycles, etc., resulting in low test efficiency and the inability to complete the test tasks quickly and conveniently. On the other hand, the traditional test process is cumbersome and complex, lacking an intuitive fault feedback mechanism. Once a fault or failure occurs during the test, it is difficult to quickly locate the problem, thus affecting the accuracy and effectiveness of the test. Summary of the invention

[0005] The purpose of the present disclosure is to provide a testing device and a testing method to solve the technical problems of low testing efficiency, difficulty in locating test problems, and poor testing accuracy and effectiveness in the related art.

[0006] In order to achieve the above objectives, the present invention adopts the following technical solutions:

[0007] A first aspect of the present disclosure provides a test device, which is suitable for testing a device under test, wherein the device under test includes an input terminal, an output terminal, an enable terminal, a ground terminal, and a setting terminal, and the test device includes a power module, a switch module, a load module, a single-chip control module, and a counter module, wherein the switch module includes a first switch, a second switch, and a third switch connected to the single-chip control module;

[0008] The power supply module comprises a first voltage output terminal and a second voltage output terminal, the first voltage output terminal is connected in series with the second switch and then connected to the enable terminal of the device under test, and is connected in series with the third switch and then connected to the input terminal of the device under test, and the second voltage output terminal is connected to the ground terminal and the setting terminal of the device under test;

[0009] The first end of the load module is connected to the ground end of the device under test, the second end of the load module is connected in series with the first switch and then connected to the output end of the device under test, and the load module is used to connect different loads to the device under test under the control of the first switch;

[0010] The input end of the counter module is connected to the output end of the device under test, and the output end of the counter module is connected to the single-chip control module, for monitoring the number of rising and falling edges, high level duration and low level duration of the output signal of the device under test, and transmitting the monitoring result to the single-chip control module;

[0011] The single-chip control module is used to output a first control signal to the first switch, a second control signal to the second switch, and a third control signal to the third switch according to a test instruction. The second switch, under the control of the second control signal, turns on or off the connection between the first voltage output terminal and the enable terminal of the device under test, and the third switch, under the control of the third control signal, turns on or off the connection between the first voltage output terminal and the input terminal of the device under test. The first switch, under the control of the first control signal, adjusts the load of the load module connected to the device under test. The single-chip control module is also used to determine that the device under test is normal when the monitoring result of the counter module is that the number of rising edges and falling edges reaches a preset number of cycles, determines that the device under test is short-circuited when the monitoring result is a continuous high level, and determines that the device under test is open-circuited when the monitoring result is a continuous low level.

[0012] Optionally, the test instruction includes at least one of a first test instruction, a second test instruction, a third test instruction, a fourth test instruction, a fifth test instruction, a sixth test instruction, and a seventh test instruction:

[0013] The single-chip control module performs a startup test on the device under test under a first load condition according to the first test instruction, during which the connection between the enable terminal of the device under test and the first voltage output terminal is cyclically turned on and off, the connection between the input terminal of the device under test and the first voltage output terminal is turned on, and the output terminal of the device under test is connected to a first load;

[0014] The single-chip control module performs a startup test on the device under test under a second load condition according to the second test instruction, during which the connection between the enable terminal of the device under test and the first voltage output terminal is cyclically turned on and off, the connection between the input terminal of the device under test and the first voltage output terminal is turned on, and the output terminal of the device under test is connected to a second load;

[0015] The single-chip control module performs a startup test on the device under test under a second load condition according to the third test instruction, during the test, the connection between the enable terminal of the device under test and the first voltage output terminal is turned on and off, the connection between the input terminal of the device under test and the first voltage output terminal is cyclically turned on and off, the output terminal of the device under test is connected to a second load, and when it is determined that a fault occurs in the device under test, the connection between the enable terminal of the device under test and the first voltage output terminal is controlled to be disconnected, the connection between the input terminal of the device under test and the first voltage output terminal is turned on, and the output terminal of the device under test is connected to the second load;

[0016] The single-chip control module performs a short-circuit test on the device under test under a third load condition according to the fourth test instruction, during the test, the connection between the enable terminal of the device under test and the first voltage output terminal is turned on, the connection between the input terminal of the device under test and the first voltage output terminal is turned on, the output terminal of the device under test is cyclically connected to the third load, and when it is determined that the device under test fails, the connection between the enable terminal of the device under test and the first voltage output terminal is controlled to be disconnected, the connection between the input terminal of the device under test and the first voltage output terminal is turned on, and the output terminal of the device under test is connected to the first load;

[0017] The single-chip control module performs an overload test on the device under test under a fourth load condition according to the fifth test instruction, during which the connection between the enable terminal of the device under test and the first voltage output terminal is turned on, the output terminal of the device under test is connected to a fourth load, and the connection between the input terminal of the device under test and the first voltage output terminal is cyclically turned on and off;

[0018] The single-chip control module performs an overload test on the device under test under a fourth load condition according to the sixth test instruction, during the test, the connection between the enable terminal of the device under test and the first voltage output terminal is turned on, the connection between the input terminal of the device under test and the first voltage output terminal is cyclically turned on and off, the output terminal of the device under test is connected to a fourth load, and when it is determined that a fault occurs in the device under test, the connection between the enable terminal of the device under test and the first voltage output terminal is controlled to be disconnected, the connection between the input terminal of the device under test and the first voltage output terminal is turned on, and the output terminal of the device under test is connected to the first load;

[0019] The single-chip control module performs the test processes corresponding to the first test instruction, the second test instruction, the third test instruction, the fourth test instruction, the fifth test instruction and the sixth test instruction on the device under test in sequence according to the seventh test instruction.

[0020] Optionally, the first switch is a four-way switch, and the load module includes a first load, a second load, a third load and a fourth load. The first load, the second load, the third load and the fourth load are respectively connected in series with one of the switches of the first switch and then connected to the output end of the device under test.

[0021] Optionally, the testing device further comprises a key input module, which is connected to the single-chip microcomputer control module and is used to generate a test instruction in response to a user operation and input the test instruction into the single-chip microcomputer control module.

[0022] Optionally, the key input module includes keys corresponding one-to-one to the first test instruction, the second test instruction, the third test instruction, the fourth test instruction, the fifth test instruction, the sixth test instruction and the seventh test instruction.

[0023] Optionally, the testing device further comprises a display module, and the display module is connected to the single-chip microcomputer control module;

[0024] The single-chip microcomputer control module is also used to output the number of cycles and test results in the current test process to the display module for display. The number of cycles is the number of rising edges and falling edges monitored by the counter module, and the test results include whether the device under test is normal, short-circuited, and open-circuited.

[0025] Optionally, the display module includes a digital tube, a first latch and a second latch, the digital tube includes a bit selection end and an input end, the output end of the single-chip control module is respectively connected to the input data ends of the first latch and the second latch, the data output end of the first latch is connected to the bit selection end of the digital tube, and the output end of the second latch is connected to the input end of the digital tube.

[0026] Optionally, the testing device further comprises a constant humidity and constant temperature box, and the constant humidity and constant temperature box is used to provide the standard temperature and marked humidity required during the testing process of the device under test.

[0027] A second aspect of the present disclosure provides a testing method, which is applicable to the testing device as described above, and is characterized in that the testing method comprises the following steps:

[0028] Get test instructions;

[0029] Outputting a first control signal to the first switch, a second control signal to the second switch, and a third control signal to the third switch according to a test instruction, wherein the second switch switches on or off the connection between the first voltage output terminal and the enable terminal of the device under test under the control of the second control signal, and the third switch switches on or off the connection between the first voltage output terminal and the input terminal of the device under test under the control of the third control signal, and the first switch adjusts the load of the load module connected to the device under test under the control of the first control signal;

[0030] Acquire the monitoring result of the counter module, and determine that the device under test is normal when the number of rising edges and falling edges reaches a preset number of cycles; determine that the device under test is short-circuited when the monitoring result is a continuous high level; and determine that the device under test is open-circuited when the monitoring result is a continuous low level.

[0031] Optionally, the test instruction includes at least one of a first test instruction, a second test instruction, a third test instruction, a fourth test instruction, a fifth test instruction, a sixth test instruction and a seventh test instruction;

[0032] When the single-chip control module performs a startup test on the device under test under the first load condition according to the first test instruction, the connection between the enable terminal of the device under test and the first voltage output terminal is cyclically turned on and off, the connection between the input terminal of the device under test and the first voltage output terminal is turned on, and the output terminal of the device under test is connected to the first load;

[0033] When the single-chip control module performs a startup test on the device under test under a second load condition according to the second test instruction, the connection between the enable terminal of the device under test and the first voltage output terminal is cyclically turned on and off, the connection between the input terminal of the device under test and the first voltage output terminal is turned on, and the output terminal of the device under test is connected to a second load;

[0034] When the single-chip control module performs a startup test on the device under test under a second load condition according to the third test instruction, the connection between the enable terminal of the device under test and the first voltage output terminal is turned on and off, the connection between the input terminal of the device under test and the first voltage output terminal is cyclically turned on and off, the output terminal of the device under test is connected to a second load, and when it is determined that a fault occurs in the device under test, the connection between the enable terminal of the device under test and the first voltage output terminal is controlled to be disconnected, the connection between the input terminal of the device under test and the first voltage output terminal is turned on, and the output terminal of the device under test is connected to the second load;

[0035] When the single-chip control module performs a short-circuit test on the device under test under a third load condition according to the fourth test instruction, the connection between the enable terminal of the device under test and the first voltage output terminal is turned on, the connection between the input terminal of the device under test and the first voltage output terminal is turned on, the output terminal of the device under test is cyclically connected to the third load, and when it is determined that a fault occurs in the device under test, the connection between the enable terminal of the device under test and the first voltage output terminal is controlled to be disconnected, the connection between the input terminal of the device under test and the first voltage output terminal is turned on, and the output terminal of the device under test is connected to the first load;

[0036] When the single-chip control module performs an overload test on the device under test under a fourth load condition according to the fifth test instruction, the connection between the enable terminal of the device under test and the first voltage output terminal is turned on, the output terminal of the device under test is connected to a fourth load, and the connection between the input terminal of the device under test and the first voltage output terminal is turned on and off cyclically;

[0037] When the single-chip control module performs an overload test on the device under test under a fourth load condition according to the sixth test instruction, the connection between the enable terminal of the device under test and the first voltage output terminal is turned on and off, the connection between the input terminal of the device under test and the first voltage output terminal is cyclically turned on and off, the output terminal of the device under test is connected to a fourth load, and when it is determined that a fault occurs in the device under test, the connection between the enable terminal of the device under test and the first voltage output terminal is controlled to be disconnected, the connection between the input terminal of the device under test and the first voltage output terminal is turned on, and the output terminal of the device under test is connected to the first load;

[0038] The single-chip control module performs the test processes corresponding to the first test instruction, the second test instruction, the third test instruction, the fourth test instruction, the fifth test instruction and the sixth test instruction on the device under test in sequence according to the seventh test instruction.

[0039] The beneficial effects of the present disclosure are as follows:

[0040] The test device of the disclosed embodiment includes a power module, a switch module, a load module, a single-chip microcomputer control module and a counter module. The single-chip microcomputer control module controls the first switch, the second switch and the third switch in the switch module, and the input voltage of the input terminal and the enable terminal of the device under test and the connected load of the output terminal can be changed. The single-chip microcomputer control module can realize multiple tests of a certain performance by cyclically outputting control signals. The single-chip microcomputer control module can determine whether the device under test fails and locate the fault type, such as short circuit or open circuit, according to the number of rising and falling edges, continuous high level time and continuous low level time of the output signal of the device under test monitored by the counter module, thereby realizing automated testing of the device under test, such as automatically executing part or all of the test contents specified in Chapter G.9.2 of GB4943.1-2022. On the one hand, it can improve the test efficiency and save manpower and time. On the other hand, it can also locate the fault type, thereby improving the test accuracy and effectiveness. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The specific implementation methods of the present disclosure are further described in detail below with reference to the accompanying drawings.

[0042] Figure 1 A structural block diagram of a test device provided in an embodiment of the present disclosure;

[0043] Figure 2 for Figure 1 The circuit structure diagram of the test device;

[0044] Figure 3 A schematic diagram of the input signal of the second switch K2 and the monitoring signal of the counter module;

[0045] Figure 4 A flow chart of a testing method provided for an embodiment of the present disclosure;

[0046] Figure 5 A flow chart of executing a first test instruction for the test method provided by an embodiment of the present disclosure;

[0047] Figure 6 A flow chart of executing a second test instruction for the test method provided by an embodiment of the present disclosure;

[0048] Figure 7 A flow chart of executing a third test instruction for the test method provided by an embodiment of the present disclosure;

[0049] Figure 8 A flowchart of executing a fourth test instruction for the test method provided by an embodiment of the present disclosure;

[0050] Fig. 9 A flowchart of executing a fifth test instruction for the test method provided by an embodiment of the present disclosure;

[0051] Fig.10 A flowchart of executing a sixth test instruction for the test method provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0052] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0053] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0054] The test device and test method provided in the embodiments of the present disclosure can perform semi-automatic or fully automatic testing on the reliability of the device under test. The device under test includes an input terminal Vin, an output terminal Vout, an enable terminal EN, a ground terminal GND, and a setting terminal IADJ. Optionally, the device under test is a current limiting IC, such as a current limiting IC of a USB interface circuit. Exemplarily, it can be a current limiting IC of a model such as PW15XX. It can be understood that in addition to being a USB current limiting IC, the device under test in the embodiments of the present disclosure can also be other devices, such as a USB current limiting switch, a power adapter output circuit management IC for a non-USB port similar to the working principle of the current limiting IC. In addition, the test device and test method of the embodiments of the present disclosure, in addition to testing an independent current limiting IC, can also be tested in a final product containing the device under test, or simulated The circuit environment of the terminal product is tested.

[0055] For reliability testing of current limiting ICs, Table G.11 in Section G.9.2 of the standard GB4943.1-2022 discloses the specific test procedures as follows:

[0056] Table G.11 IC current limiter performance test procedure

[0057]

[0058]

[0059] Please refer to Figure 1 to Figure 2 , Figure 1 A structural block diagram of a test device provided in an embodiment of the present disclosure, Figure 2 for Figure 1 The circuit structure diagram of the test device is as follows: Figure 1 to Figure 2 As shown, the testing device includes a power module 110 , a switch module, a load module 130 , a single chip control module 140 and a counter module 150 .

[0060] The switch module includes a first switch K1 , a second switch K2 and a third switch K3 connected to the single chip control module 140 .

[0061] The power module 110 includes a first voltage output terminal Vout+ and a second voltage output terminal Vout-, wherein the first voltage output terminal Vout+ is connected in series with the second switch K2 and then connected to the enable terminal EN of the device under test 200, and is connected in series with the third switch K3 and then connected to the input terminal Vin of the device under test 200, and the second voltage output terminal Vout- is connected to the ground terminal (GND) and the setting terminal (IADJ) of the device under test 200. In addition, the setting terminal IADJ of the device under test 200 is connected in series with an adjustable resistor R0 and then grounded, the ground terminal GND of the device under test 200 is connected in series with a capacitor C4 and then grounded, and the input terminal Vin of the device under test 200 is connected in series with a capacitor C5 and then grounded. Optionally, the power module 110 is a DC power supply, which can output a DC voltage in the range of 3.3V-20V. In addition to outputting voltage to the device under test 200, the power module 110 can also provide working voltage for the entire test device, for example, providing a +5V working voltage for the single-chip control module 140.

[0062] The first end of the load module 130 is connected to the ground terminal GND of the device under test 200, and the second end of the load module 130 is connected in series with the first switch K1 and then connected to the output terminal Vout of the device under test 200. The load module 130 is used to connect different loads to the device under test 200 under the control of the first switch K1.

[0063] The input end of the counter module 150 is connected to the output end Vout of the device under test 200, and the output end of the counter module 150 is connected to the single-chip control module 140, for monitoring the number of rising and falling edges, high level duration and low level duration of the output signal of the device under test 200, and transmitting the monitoring results to the single-chip control module 140.

[0064] The single-chip control module 140 is used to output a first control signal to the first switch K1, a second control signal to the second switch K2, and a third control signal to the third switch K3 according to a test instruction. The second switch K2, under the control of the second control signal, turns on or off the connection between the first voltage output terminal Vout+ and the enable terminal EN of the device under test 200. The third switch K3, under the control of the third control signal, turns on or off the connection between the first voltage output terminal Vout+ and the input terminal Vin of the device under test 200. The first switch K1, under the control of the first control signal, adjusts the load of the load module 130 connected to the device under test 200. The single-chip control module 140 is also used to determine that the device under test 200 is normal when the monitoring result of the counter module 150 is that the number of rising edges and falling edges reaches a preset number of cycles, determines that the device under test 200 is short-circuited when the monitoring result is a continuous high level, and determines that the device under test 200 is open-circuited when the monitoring result is a continuous low level.

[0065] In the embodiment of the present disclosure, when the reliability test is performed on the device under test 200, each test program needs to be executed multiple times. For example, for the test program with the serial number 1 in Table G11, it needs to be tested 10,000 times in a cycle. For this purpose, the single-chip control module 140 needs to control the second switch K2 to perform the "close and then open" action 10,000 times in a cycle. Therefore, the single-chip control module 140 needs to input a periodic pulse signal to the second switch K2. Please refer to Figure 3 , Figure 3 The K2 signal represents the pulse signal input to the second switch K2 by the single-chip control module 140. Each pulse period T corresponds to one cycle. One cycle includes a high level time t1 and a low level time t2. The counter module 150 can monitor the output signal of the device under test 200, specifically including: monitoring the rising edge and falling edge of the output signal. If a rising edge and a falling edge are detected, the count value is increased by 1. When the device under test 200 is normal, the count value of the counter module 150 is the same as the number of cycles of the K2 signal. Figure 3 As shown, "normal" indicates the waveform of the output signal monitored by the counter module 150 when the device under test 200 is normal. At this time, the number of rising edges or falling edges monitored by the counter module 150 is the same as the number of cycles of the K2 signal. Figure 3 In the figure, "short circuit" means the waveform of the output signal monitored by the counter module 150 when the device under test 200 has a short circuit fault at time t, that is, the output signal is continuously at a high level after the device under test 200 has a short circuit fault, and "open circuit" means the waveform of the output signal monitored by the counter module 150 when the device under test 200 has an open circuit fault at time t, that is, the output signal is continuously at a low level after the device under test 200 has an open circuit fault. In specific implementation, the counter module 150 can be implemented by a separate counter, or a separate single-chip microcomputer can be used to implement the function of the counter module 150.

[0066] In the disclosed embodiment, the test instruction includes at least one of the first test instruction, the second test instruction, the third test instruction, the fourth test instruction, the fifth test instruction, the sixth test instruction and the seventh test instruction. Among them, the first test instruction, the second test instruction, the third test instruction, the fourth test instruction, the fifth test instruction and the sixth test instruction can realize the semi-automatic test of the device under test, that is, the tester can manually select to perform any part of the tests in sequence numbers 1-8 on the device under test. Specifically, the first test instruction corresponds to the test indicated by sequence number 1 in Table G.11, the second test instruction corresponds to the test indicated by sequence numbers 2 and 3 in Table G.11, the third test instruction corresponds to the test indicated by sequence numbers 4 and 5 in Table G.11, the fourth test instruction corresponds to the test indicated by sequence number 6 in Table G.11, the fifth test instruction corresponds to the test indicated by sequence number 7 in Table G.11, and the sixth test instruction corresponds to the test indicated by sequence number 8 in Table G.11. Among them, the seventh test instruction can realize semi-automatic testing of the device under test, that is, when the user inputs the seventh test instruction, the single-chip control module 140 will perform the test processes corresponding to the first test instruction, the second test instruction, the third test instruction, the fourth test instruction, the fifth test instruction and the sixth test instruction on the device under test 200 in sequence according to the seventh test instruction, so as to realize full-automatic testing. When the test results of the first test instruction, the second test instruction, the third test instruction, the fourth test instruction, the fifth test instruction and the sixth test instruction are all that the device under test is normal, the device under test can be finally determined to be qualified.

[0067] Compared with the related art, the test device of the embodiment of the present disclosure includes a power supply module, a switch module, a load module, a single-chip microcomputer control module and a counter module. The single-chip microcomputer control module controls the first switch, the second switch and the third switch in the switch module, which can change the input voltage of the input end and the enable end of the device under test and the connected load of the output end. The single-chip microcomputer control module can realize multiple tests of a certain performance by cyclically outputting control signals. The single-chip microcomputer control module can determine whether the device under test fails and locate the fault type, such as short circuit or open circuit, according to the number of rising and falling edges, continuous high level time and continuous low level time of the output signal of the device under test monitored by the counter module, thereby realizing automated testing of the device under test, such as automatically executing part or all of the test contents specified in Chapter G.9.2 of GB4943.1-2022. On the one hand, it can improve the test efficiency and save manpower and time. On the other hand, it can also locate the fault type, thereby improving the test accuracy and effectiveness.

[0068] In a possible implementation, the single-chip microcomputer control module 140 includes a single-chip microcomputer U1. For example, the model of the single-chip microcomputer U1 may be S89C52. The power input terminal VCC of the single-chip microcomputer U1 is connected to a +5V voltage, and the ground terminal GND of the single-chip microcomputer U1 is grounded. In addition, the single-chip microcomputer control module 140 also includes a clock circuit, which provides a stable clock signal for the single-chip microcomputer U1, drives the timing circuit inside the single-chip microcomputer U1, and enables the single-chip microcomputer U1 to execute the program step by step. Figure 2 As shown, the clock circuit includes capacitor C2, capacitor C3 and crystal oscillator Y1, one end of capacitor C2 is connected to one end of crystal oscillator Y1 and pin 19 of single-chip computer U1, one end of capacitor C3 is connected to the other end of crystal oscillator Y1 and pin 18 of single-chip computer U1, and the other ends of capacitor C2 and capacitor C3 are grounded. Exemplarily, crystal oscillator Y1 is a 11.0592MHz crystal oscillator, and the resistance values ​​of capacitor C2 and capacitor C3 are both 30pF.

[0069] Optional, such as Figure 1 to Figure 2 As shown, the test device further includes a key input module 160 , which is connected to the single-chip control module 140 and is used to generate a test instruction in response to a user operation and input the test instruction to the single-chip control module 140 .

[0070] Further, the key input module 160 includes at least keys corresponding to the first test instruction, the second test instruction, the third test instruction, the fourth test instruction, the fifth test instruction, the sixth test instruction and the seventh test instruction, such as keys S1, S2, S3, S4, S5, S6, S7, respectively. Figure 2The switches connected to P2.7-P2.1 of the single-chip microcomputer U1 are S1-S7. When the user presses the button S1, the single-chip microcomputer control module 140 determines that the first test instruction is detected. When the user presses the button S2, the single-chip microcomputer control module 140 determines that the second test instruction is detected, and so on.

[0071] Optionally, the key input module 160 is a matrix key module SW, which is composed of multiple rows and columns of conductive circuits to form a grid layout. Each key corresponds to an intersection in the grid. When the key is pressed, the row and column of the intersection will form a closed circuit, thereby triggering a signal. This design enables the matrix key module to provide input functions of multiple keys while saving IO resources.

[0072] Optionally, the first switch K1 is a four-way switch, and the load module 130 includes a first load, a second load, a third load, and a fourth load, and the first load, the second load, the third load, and the fourth load are respectively connected in series with one of the switches of the first switch K1 and connected to the output terminal Vout of the device under test 200. In the embodiment of the present disclosure, the switch module can be a relay switch, a transistor switch, a programmable soft switch, or a single-chip triggerable switch circuit. The embodiment of the present disclosure is described only by taking the relay switch as an example.

[0073] Specifically, Figure 2 As shown, the first switch K1, the second switch K2 and the third switch K3 are all relay switches, and the first switch K1 is a four-way relay, that is, the first switch K1 includes four-way relays, which are respectively recorded as the first relay K11, the second relay K12, the third relay K13, and the fourth relay K14. The first load R1 is the load required for the test of No. 1 in Table G.11, that is, the resistance value of R1 is the maximum (rated) load, the second load is the load required for the tests of No. 2 to 5 in Table G.11, which is composed of a parallel resistor R2 and a capacitor C1, wherein the resistance value of the resistor R2 is 0Ω, and the capacitance value of the capacitor C1 is 470μF, the third load R3 is the load required for the test of No. 6 in Table G.11, and its resistance value is 0, and the fourth load R4 is the load required for the tests of No. 7 and 8 in Table G.11, and its resistance value is 150% of the maximum load, that is, the resistance value of the resistor R4 is 1.5 times the resistance value of the resistor R1.

[0074] In a possible implementation, the testing device also includes a display module 170, which is connected to the single-chip control module 140; the single-chip control module 140 is also used to output the number of cycles and test results in the current test process to the display module 170 for display, the number of cycles is the number of rising edges and falling edges monitored by the counter module, and the test results include whether the device under test is normal, short-circuited, and open-circuited.

[0075] Optional, such as Figure 2 As shown, the display module 170 is a digital tube display module, which includes a digital tube DS1, a first latch U8 and a second latch U9. The digital tube DS1 includes a bit selection end and an input end. The output end of the single-chip control module 140 is respectively connected to the input data ends of the first latch U8 and the second latch U9, the data output end of the first latch U8 is connected to the bit selection end of the digital tube DS1, and the output end of the second latch U9 is connected to the input end of the digital tube DS1.

[0076] Exemplarily, the digital tube DS1 is an 8-bit common cathode digital tube, and the first latch U8 and the second latch U9 are 74HC573 latches. The anode of each digital tube, that is, the pins of a, b, c, d, e, f, g, and h are all connected together, and then connected to the data output end (A, B, C, D, E, F, G, H) of the second latch U9, and the data input end of the second latch U9 is connected to the P0 port (D0-D7) of the single-chip microcomputer. Each digital tube corresponds to a bit selection end (WE1, WE2, WE3, WE4, WE5, WE6, WE7, WE8), and the bit selection ends WE1-WE8 are respectively connected to the data output end of the first latch U8, and the data input end of the first latch U8 is also connected to the P0 port (D0-D7) of the single-chip microcomputer. At the same time, the latch terminals LE of the first latch U8 and the second latch U9 are connected to P3.0 and P3.1 of the microcontroller respectively. The microcontroller U1 is used to control the latch terminal LE of the latch, thereby controlling the data output of the latch. This time-sharing control can conveniently control any digital tube to display any number.

[0077] It is understandable that the display module 170 in the embodiment of the present disclosure can also be other types of display modules, such as an LCD display screen, etc., but the digital tube display module has the advantages of simple operation, easy implementation, low price, and wide availability, which can reduce the cost of the testing device. Therefore, the digital tube display module is preferably used in the embodiment of the present disclosure.

[0078] Optionally, the test device further includes a constant humidity and constant temperature box, which is used to provide the temperature and humidity required during the test of the device under test. In one implementation, the humidity and temperature parameters required by the first test instruction to the sixth test instruction can be set in advance, and the constant humidity and constant temperature box can automatically switch to the humidity and temperature required by each test instruction. In other implementations, the constant humidity and constant temperature box can also be switched by the single-chip control module. For example, when the single-chip control module obtains the first test instruction, it first sets the temperature and humidity of the constant humidity and constant temperature box to the temperature and humidity required by the first test instruction, and uses the temperature and humidity detection sensor to detect in real time whether the current humidity and temperature reach the set value. When the set value is reached, the test process of the first test instruction is executed. Similarly, when the second test instruction is required, the temperature and humidity of the constant humidity and constant temperature box are set to the temperature and humidity required by the second test instruction, and the test process of the second test instruction is executed when the current environment reaches the set value. The temperature and humidity control principles required for other test processes are similar and will not be described in detail here.

[0079] The test device of the disclosed embodiment adopts components such as a single-chip microcomputer, a relay, a digital tube module, a keyboard module, and a counter to implement the test of the device to be tested. On the one hand, the components constituting the test device are generally easy to obtain and inexpensive, and the cost is low. On the other hand, the test process is simple and easy to operate, and the test purpose can be easily achieved.

[0080] In addition, the test device and test method of the embodiments of the present disclosure can not only be applicable to the test content of Appendix G.9.2 of IEC62368-1:2023, but also can be used to perform G.9.2 test of Appendix IEC62368-1:2014 on the device under test by setting different number of cycles and loads in the load module.

[0081] The second aspect of the present disclosure also provides a testing method, which is applicable to the testing device shown above. Figure 4 As shown, the test method includes the following steps:

[0082] Step S10, obtaining a test instruction.

[0083] Step S20, outputting a first control signal to the first switch, a second control signal to the second switch, and a third control signal to the third switch according to the test instruction, wherein the second switch switches on or off the connection between the first voltage output terminal and the enable terminal of the device under test under the control of the second control signal, and the third switch switches on or off the connection between the first voltage output terminal and the input terminal of the device under test under the control of the third control signal, and the first switch adjusts the load of the load module connected to the device under test under the control of the first control signal;

[0084] Step S30, obtaining the monitoring result of the counter module, and determining that the device under test is normal when the number of rising edges and falling edges reaches a preset number of cycles; determining that the device under test is short-circuited when the monitoring result is a continuous high level; and determining that the device under test is open-circuited when the monitoring result is a continuous low level.

[0085] Optionally, when the user presses the button S1, the single-chip microcomputer control module 140 receives a first test instruction, and the single-chip microcomputer control module 140 performs a startup test under a first load condition on the device under test 200 according to the first test instruction. During the test, the connection between the enable terminal EN of the device under test 200 and the first voltage output terminal Vout+ is cyclically turned on and off, the connection between the input terminal Vin of the device under test 200 and the first voltage output terminal Vout+ is turned on, and the output terminal Vout of the device under test 200 is connected to the first load R1.

[0086] Please refer to Figure 5 , Figure 5 The test flow chart when the test device executes the first test instruction is as follows: Figure 5 As shown, the following steps are included:

[0087] Step S101, the single-chip control module sets the initial values ​​of N-K2, NC, and N-C1 to 0, N-K2 represents the number of cycles of the second switch K2 inputting the second control signal, that is, Figure 3 The number of cycles T, NC is the counting cycle in the counter module, NC and N-K2 have the same value, N-C1 is the number of rising edges and falling edges monitored by the counter module. Specifically, the initial value of N-C1 is 0. When the counter module detects a rising edge and a falling edge in a cycle T, the value of N-C1 is increased by 1, that is, N-C1=N-C1+1.

[0088] In step S102, the single-chip control module outputs a first control signal to the first relay K11 to close the first relay K11, and outputs a third control signal to the third switch K3 to close the third switch K3. At this time, the first load R1 is connected to the output end of the device under test 200, and the input end Vin of the device under test 200 is connected to the first voltage output end Vout+ of the power module 110, that is, the input end input voltage, which is the maximum (rated) voltage value of the device under test.

[0089] In step S103, the single chip control module outputs a period of the second control signal to the second switch K2, and executes one cycle. At this time, N-K2=N-K2+1, NC=N-C+1.

[0090] The second switch K2 is closed when a first level signal (such as a high level signal) is input, and is opened when a second level signal (such as a low level signal) is input. When the second switch K2 is closed, the connection between the enable terminal EN of the device under test 200 and the first voltage output terminal Vout+ is turned on. When the second switch K2 is turned on, the connection between the enable terminal EN of the device under test 200 and the first voltage output terminal Vout+ is turned off. The single-chip control module 140 controls the high and low level switching of the second control signal to control the input of the enable terminal EN of the device under test 200 to be turned off and on. The single-chip control module outputs multiple cycles of the second control signal to achieve multiple cycle tests.

[0091] In step S104, the counter module feeds back the monitoring result to the single-chip control module, and the single-chip control module determines whether N-C1 in the monitoring result is equal to N-K2. If the judgment result is yes, it means that the device under test 200 is normal. Therefore, the counting result N-C1 of the counter module is the same as the number of cycles N-K2 of the second control signal. At this time, step S105 is further executed. If the judgment result is no, it means that the device under test has a fault, and it is necessary to further determine the fault type and execute step S106.

[0092] Step S105, determine whether N-K2 is less than the preset number of cycles, for example, in the test process corresponding to the first test instruction, the preset number of cycles is 10000. If the judgment result is yes, it means that the test has not reached 10000 times, repeat the cycle and execute step S103. Otherwise, it means that the test has been performed for the preset number of cycles, and the device under test is normal in 10000 cycles, indicating that the device under test is normal, and execute step S109.

[0093] Step S106, determine whether the output signal in the monitoring result is a continuous high level or a continuous low level. If it is a continuous high level, it means that the device under test is short-circuited, and execute step S107. If the judgment result is a continuous low level, it means that the device under test is open-circuited, and execute step S108.

[0094] Step S107, determining that the device under test is short-circuited and does not meet the requirements of G.9.2.

[0095] Step S108 , determining that the device under test is short-circuited, replacing the device under test and retesting, that is, replacing the device under test and testing the replaced device under test.

[0096] Step S109 , determining that the device under test is normal, that is, the test performance corresponding to the first test instruction is normal, and the device under test needs to be subjected to the next test, that is, the second test instruction is performed.

[0097] Optionally, when the user presses the button S2, the single-chip control module 140 receives a second test instruction, and the single-chip control module 140 performs a startup test under a second load condition on the device under test 200 according to the second test instruction. During the test, the connection between the enable terminal EN of the device under test 200 and the first voltage output terminal Vout+ is cyclically turned on and off, the connection between the input terminal Vin of the device under test 200 and the first voltage output terminal Vout+ is turned on, and the output terminal Vout of the device under test 200 is connected to the second load.

[0098] The difference between the second test instruction and the first test instruction is that the pretreatment temperature of the device under test 200 is different, the preset number of cycles is different, the connected load is different, and the other test processes are the same.

[0099] Please refer to Figure 6 , Figure 6 The test flow chart when the test device executes the second test instruction is as follows: Figure 6 As shown, the following steps are included:

[0100] Step S201, the single-chip control module sets the initial values ​​of N-K2, NC, and N-C1 to 0, N-K2 represents the number of cycles of the second switch K2 inputting the second control signal, that is, Figure 3 The number of cycles T, NC is the counting cycle in the counter module, NC has the same value as N-K2, N-C1 is the number of rising and falling edges detected by the counter module, specifically, the initial value of N-C1 is 0

[0101] In step S202, the single-chip control module outputs a first control signal to the second relay K12 to close the second relay K12, and outputs a third control signal to the third switch K3 to close the third switch K3. At this time, the second load (R1 in parallel with C1) is connected to the output end of the device under test 200, and the input end Vin of the device under test 200 is connected to the first voltage output end Vout+ of the power module 110, that is, the input end input voltage, which is the maximum (rated) voltage value of the device under test 200.

[0102] In step S203, the single-chip control module outputs a second control signal of one cycle to the second switch K2, and executes one cycle. At this time, N-K2=N-K2+1, NC=N-C+1.

[0103] In step S204, the counter module feeds back the monitoring result to the single-chip control module, and the single-chip control module determines whether N-C1 is equal to N-K2 in the monitoring result. If the judgment result is yes, step S205 is executed; if the judgment result is no, step S206 is executed.

[0104] Step S205, determine whether N-K2 is less than a preset number of cycles, for example, in the test process corresponding to the second test instruction, the preset number of cycles is 50. If the determination result is yes, execute step S203, otherwise, execute step S209.

[0105] Step S206, determine whether the output signal in the monitoring result is a continuous high level or a continuous low level. If it is a continuous high level, it means that the device under test is short-circuited, and execute step S207. If the judgment result is a continuous low level, it means that the device under test is open-circuited, and execute step S208.

[0106] Step S207, determining that the device under test is short-circuited and does not meet the requirements of G.9.2.

[0107] Step S208, determining that the device under test is short-circuited, replacing the device under test and retesting.

[0108] Step S209 , determining that the device under test is normal, that is, the test performance corresponding to the second test instruction is normal, and the device under test needs to be subjected to the next test, that is, the third test instruction.

[0109] Optionally, when the user presses the button S3, the single-chip microcomputer control module receives a third test instruction, and the single-chip microcomputer control module performs a startup test under the second load condition on the device under test 200 according to the third test instruction. During the test, the connection between the enable terminal EN of the device under test 200 and the first voltage output terminal Vout+ is turned on and off, the connection between the input terminal Vin of the device under test 200 and the first voltage output terminal Vout+ is cyclically turned on and off, the output terminal of the device under test 200 is connected to the second load, and when it is determined that the device under test fails, the connection between the enable terminal EN of the device under test 200 and the first voltage output terminal Vout+ is controlled to be disconnected, the connection between the input terminal Vin of the device under test 200 and the first voltage output terminal Vout+ is turned on, and the output terminal Vout of the device under test 200 is connected to the second load.

[0110] Among them, the difference between the third test instruction and the second test instruction is that when the second test instruction is tested, the enable terminal EN cycles and the input terminal Vin remains input, while when the third test instruction is tested, the input terminal Vin cycles and the enable terminal EN remains input, and when the microcontroller control module determines that the device under test may have a fault based on the monitoring result fed back by the counter module, it is necessary to further test whether the fault is a short circuit or an open circuit.

[0111] Please refer to Figure 7 , Figure 7 The test flow chart when the test device executes the third test instruction is as follows: Figure 7 As shown, the following steps are included:

[0112] Step S301, set the initial values ​​of N-K3, NC, and N-C1 to 0, where N-K3 represents the number of cycles of the third switch K3 inputting the third control signal.

[0113] In step S302, the single-chip control module outputs a first control signal to the second relay K12 to close the second relay K12, and outputs a second control signal to the second switch K2 to close the second switch K2. At this time, the second load (R1 in parallel with C1) is connected to the output end of the device under test 300, and the enable end EN of the device under test 300 is connected to the first voltage output end Vout+ of the power module 110, that is, the enable end EN inputs a voltage.

[0114] In step S303, the single-chip control module outputs a period of the third control signal to the third switch K3, and executes one cycle. At this time, N-K3=N-K3+1, NC=N-C+1.

[0115] In step S304, the counter module feeds back the monitoring result to the single-chip control module, and the single-chip control module determines whether N-C1 is equal to N-K3 in the monitoring result. If the judgment result is yes, step S305 is executed. If the judgment result is no, it means that the device under test fails and the fault type needs to be further determined, and step S306 is executed.

[0116] Step S305, determine whether N-K3 is less than a preset number of cycles, for example, in the test process corresponding to the third test instruction, the preset number of cycles is 50. If the determination result is yes, execute step S303, otherwise, execute step S310.

[0117] Step S306, the single chip control module outputs a first control signal to the first relay K11 to close the first relay K11, outputs a third control signal to the third switch K3 to close the third switch K3, and inputs a second control signal to the second switch K2 to open the second switch K2.

[0118] Step S307, determining whether the monitoring result is continuously at a high level or continuously at a low level, if continuously at a high level, executing step S308, if continuously at a low level, executing step S309.

[0119] Step S308, determining that the device under test is short-circuited and does not meet the requirements of G.9.2.

[0120] Step S309, determining that the device under test is short-circuited, and replacing the device under test to retest.

[0121] Step S310, determining whether the device under test is normal.

[0122] Optionally, when the user presses the button S4, the single-chip microcomputer control module receives a fourth test instruction, and the single-chip microcomputer control module performs a short-circuit test under a third load condition on the device under test 200 according to the fourth test instruction. During the test, the connection between the enable terminal EN of the device under test 200 and the first voltage output terminal Vout+ is turned on, the connection between the input terminal Vin of the device under test 200 and the first voltage output terminal Vout+ is turned on, and the output terminal Vout of the device under test is cyclically connected to the third load R3, and when it is determined that the device under test fails, the connection between the enable terminal EN of the device under test 200 and the first voltage output terminal Vout+ is controlled to be disconnected, the connection between the input terminal Vin of the device under test 200 and the first voltage output terminal Vout+ is turned on, and the output terminal Vout of the device under test 200 is connected to the first load R1.

[0123] Please refer to Figure 8 , Figure 8 This is a test flow chart when the test device executes the fourth test instruction, such as Figure 8 As shown, the following steps are included:

[0124] Step S401, the single chip control module sets the initial values ​​of N-K13, NC, and N-C1 to 0, and N-K13 represents the number of cycles of the third control signal input by the third relay K13.

[0125] In step S402, the single-chip control module outputs a second control signal to the second switch K2 to close the second switch K2, and outputs a third control signal to the third switch K3 to close the third switch K3. At this time, the connection between the enable terminal EN of the device under test 300 and the first voltage output terminal Vout+ of the power module 110 is turned on, that is, the enable terminal EN is input with a voltage, and the connection between the input terminal Vin of the device under test 300 and the first voltage output terminal Vout+ is turned on.

[0126] In step S403, the single-chip control module 140 outputs a first control signal of one cycle to the third relay K13, and executes one cycle. At this time, N-K13=N-K13+1, NC=N-C+1.

[0127] Step S404, determine whether N-C1 is equal to N-K13. If the determination result is yes, execute step S405. If the determination result is no, it indicates that the device under test fails and the fault type needs to be further determined, and execute step S406.

[0128] Step S405, determine whether N-K13 is less than a preset number of cycles, for example, in the test process corresponding to the fourth test instruction, the preset number of cycles is 50. If the determination result is yes, execute step S403, otherwise, execute step S410.

[0129] In step S406, the single chip control module outputs a first control signal to the first relay K11 to close the first relay K11, outputs a third control signal to the third switch K3 to turn on the third switch K3, and inputs a second control signal to the second switch K2 to turn off the second switch K2.

[0130] Step S407, determining whether the monitoring result is continuously at a high level or continuously at a low level, if continuously at a high level, executing step S408, if continuously at a low level, executing step S409.

[0131] Step S408, determining that the device under test is short-circuited and does not meet the requirements of G.9.2.

[0132] Step S409, determining that the device under test is short-circuited, and replacing the device under test to retest.

[0133] Step S410, determining whether the device under test is normal.

[0134] Optionally, when the user presses the button S5, the single-chip control module receives the fifth test instruction, and the single-chip control module performs an overload test under the fourth load R4 condition on the device under test 200 according to the fifth test instruction. During the test, the connection between the enable terminal EN of the device under test 200 and the first voltage output terminal Vout+ is turned on, the output terminal of the device under test 200 is connected to the fourth load R4, and the connection between the input terminal Vin of the device under test 200 and the first voltage output terminal Vout+ is cyclically turned on and off.

[0135] For details, please refer to Fig. 9 , Fig. 9 This is a test flow chart when the test device executes the fifth test instruction, such as Fig. 9 As shown, the following steps are included:

[0136] Step S501, the single-chip control module sets the initial values ​​of N-K2, NC, and N-C1 to 0, N-K2 represents the number of cycles of the second switch K2 inputting the second control signal, that is, Figure 3 The number of cycles T, NC is the counting cycle in the counter module, NC has the same value as N-K2, N-C1 is the number of rising and falling edges detected by the counter module, specifically, the initial value of N-C1 is 0

[0137] In step S502, the single-chip control module outputs a first control signal to the fourth relay K14 to close the fourth relay K14, and outputs a third control signal to the third switch K3 to close the third switch K3. At this time, the fourth load is connected to the output end of the device under test 200, and the input end Vin of the device under test 200 is connected to the first voltage output end Vout+ of the power module 110.

[0138] In step S503, the single-chip control module outputs a second control signal of one cycle to the second switch K2, and executes one cycle. At this time, N-K2=N-K2+1, NC=N-C+1.

[0139] In step S504, the counter module feeds back the monitoring result to the single-chip control module, and the single-chip control module determines whether N-C1 is equal to N-K2 in the monitoring result. If the judgment result is yes, step S505 is executed; if the judgment result is no, step S506 is executed.

[0140] Step S505, determine whether N-K2 is less than a preset number of cycles, for example, in the test process corresponding to the second test instruction, the preset number of cycles is 50. If the determination result is yes, execute step S503, otherwise, execute step S509.

[0141] Step S506, determine whether the output signal in the monitoring result is a continuous high level or a continuous low level. If it is a continuous high level, it means that the device under test is short-circuited, and execute step S507. If the judgment result is a continuous low level, it means that the device under test is open-circuited, and execute step S508.

[0142] Step S507, determining that the device under test is short-circuited and does not meet the requirements of G.9.2.

[0143] Step S508, determining that the device under test is short-circuited, replacing the device under test and retesting.

[0144] Step S509: determine whether the device under test is normal.

[0145] Optionally, when the user presses the button S6, the single-chip microcomputer control module receives the sixth test instruction, and the single-chip microcomputer control module performs an overload test on the device under test under the fourth load condition according to the sixth test instruction. During the test, the connection between the enable terminal EN of the device under test 200 and the first voltage output terminal Vout+ is turned on and off, the connection between the input terminal Vin of the device under test 200 and the first voltage output terminal Vout+ is cyclically turned on and off, the output terminal of the device under test 200 is connected to the fourth load R4, and when it is determined that the device under test fails, the connection between the enable terminal EN of the device under test 200 and the first voltage output terminal Vout+ is controlled to be disconnected, the connection between the input terminal Vin of the device under test 200 and the first voltage output terminal Vout+ is turned on, and the output terminal of the device under test 200 is connected to the first load R1.

[0146] Please refer to Fig.10 , Fig.10 This is a test flow chart when the test device executes the sixth test instruction, such as Fig.10 As shown, the following steps are included:

[0147] Step S601, the single chip control module sets the initial values ​​of N-K3, NC, and N-C1 to 0, and N-K3 represents the number of cycles of the third switch K3 inputting the third control signal.

[0148] In step S602 , the single chip control module outputs a first control signal to the fourth relay K14 to close the fourth relay K14 , and outputs a second control signal to the second switch K2 to close the second switch K2 . At this time, the fourth load is connected to the output end of the device under test 200 .

[0149] In step S603, the single chip control module 140 outputs a period of the third control signal to the third switch K3, and executes one cycle. At this time, N-K3=N-K3+1, NC=N-C+1.

[0150] Step S604, determine whether N-C1 is equal to N-K3. If the judgment result is yes, execute step S605. If the judgment result is no, it means that the device under test fails and the fault type needs to be further determined, and execute step S606.

[0151] Step S605, determine whether N-K3 is less than a preset number of cycles, for example, in the test process corresponding to the sixth test instruction, the preset number of cycles is 50. If the determination result is yes, execute step S603, otherwise, execute step S610.

[0152] In step S606, the single chip control module outputs a first control signal to the first relay K11 to close the first relay K11, outputs a third control signal to the third switch K3 to turn on the third switch K3, and inputs a second control signal to the second switch K2 to turn off the second switch K2.

[0153] Step S607, determine whether the monitoring result is continuously at a high level or continuously at a low level, if it is continuously at a high level, execute step S608, if it is continuously at a low level, execute step S609.

[0154] Step S608, determining that the device under test is short-circuited and does not meet the requirements of G.9.2.

[0155] Step S609, determine if the device under test is short-circuited, and replace the device under test to retest.

[0156] Step S610, determining whether the device under test is normal.

[0157] For any device under test, when Figures 5 to 10 In the test procedures shown, the device under test is considered qualified only when the test results are normal.

[0158] Obviously, the above embodiments of the present disclosure are merely examples for clearly illustrating the present disclosure, and are not limitations on the implementation methods of the present disclosure. For ordinary technicians in this field, other different forms of changes or modifications can be made on the basis of the above description. It is impossible to list all the implementation methods here. All obvious changes or modifications derived from the technical solution of the present disclosure are still within the protection scope of the present disclosure.

Claims

1. A testing device, suitable for testing a device to be treated, characterized in that: The device under test includes an input terminal, an output terminal, an enable terminal, a ground terminal and a setting terminal, the test device includes a power module, a switch module, a load module, a single-chip control module and a counter module, and the switch module includes a first switch, a second switch and a third switch connected to the single-chip control module; The power supply module comprises a first voltage output terminal and a second voltage output terminal, the first voltage output terminal is connected in series with the second switch and then connected to the enable terminal of the device under test, and is connected in series with the third switch and then connected to the input terminal of the device under test, and the second voltage output terminal is connected to the ground terminal and the setting terminal of the device under test; The first end of the load module is connected to the ground end of the device under test, the second end of the load module is connected in series with the first switch and then connected to the output end of the device under test, and the load module is used to connect different loads to the device under test under the control of the first switch; The input end of the counter module is connected to the output end of the device under test, and the output end of the counter module is connected to the single-chip control module, for monitoring the number of rising and falling edges, high level duration and low level duration of the output signal of the device under test, and transmitting the monitoring result to the single-chip control module; The single-chip microcomputer control module is used to output a first control signal to the first switch, a second control signal to the second switch, and a third control signal to the third switch according to a test instruction. The second switch, under the control of the second control signal, turns on or off the connection between the first voltage output terminal and the enable terminal of the device under test, and the third switch, under the control of the third control signal, turns on or off the connection between the first voltage output terminal and the input terminal of the device under test. The first switch, under the control of the first control signal, adjusts the load of the load module connected to the device under test. The single-chip microcomputer control module is also used to determine that the device under test is normal when the monitoring result of the counter module is that the number of rising edges and falling edges reaches a preset number of cycles, determines that the device under test is short-circuited when the monitoring result is a continuous high level, and determines that the device under test is open-circuited when the monitoring result is a continuous low level.

2. The testing device according to claim 1, characterized in that: The test instruction includes at least one of a first test instruction, a second test instruction, a third test instruction, a fourth test instruction, a fifth test instruction, a sixth test instruction, and a seventh test instruction: The single-chip control module performs a startup test on the device under test under a first load condition according to the first test instruction, during which the connection between the enable terminal of the device under test and the first voltage output terminal is cyclically turned on and off, the connection between the input terminal of the device under test and the first voltage output terminal is turned on, and the output terminal of the device under test is connected to a first load; The single-chip control module performs a startup test on the device under test under a second load condition according to the second test instruction, during which the connection between the enable terminal of the device under test and the first voltage output terminal is cyclically turned on and off, the connection between the input terminal of the device under test and the first voltage output terminal is turned on, and the output terminal of the device under test is connected to a second load; The single-chip control module performs a startup test on the device under test under a second load condition according to the third test instruction, during the test, the connection between the enable terminal of the device under test and the first voltage output terminal is turned on and off, the connection between the input terminal of the device under test and the first voltage output terminal is cyclically turned on and off, the output terminal of the device under test is connected to a second load, and when it is determined that a fault occurs in the device under test, the connection between the enable terminal of the device under test and the first voltage output terminal is controlled to be disconnected, the connection between the input terminal of the device under test and the first voltage output terminal is turned on, and the output terminal of the device under test is connected to the second load; The single-chip control module performs a short-circuit test on the device under test under a third load condition according to the fourth test instruction, during the test, the connection between the enable terminal of the device under test and the first voltage output terminal is turned on, the connection between the input terminal of the device under test and the first voltage output terminal is turned on, the output terminal of the device under test is cyclically connected to the third load, and when it is determined that the device under test fails, the connection between the enable terminal of the device under test and the first voltage output terminal is controlled to be disconnected, the connection between the input terminal of the device under test and the first voltage output terminal is turned on, and the output terminal of the device under test is connected to the first load; The single-chip control module performs an overload test on the device under test under a fourth load condition according to the fifth test instruction, during which the connection between the enable terminal of the device under test and the first voltage output terminal is turned on, the output terminal of the device under test is connected to a fourth load, and the connection between the input terminal of the device under test and the first voltage output terminal is cyclically turned on and off; The single-chip control module performs an overload test on the device under test under a fourth load condition according to the sixth test instruction, during the test, the connection between the enable terminal of the device under test and the first voltage output terminal is turned on, the connection between the input terminal of the device under test and the first voltage output terminal is cyclically turned on and off, the output terminal of the device under test is connected to a fourth load, and when it is determined that a fault occurs in the device under test, the connection between the enable terminal of the device under test and the first voltage output terminal is controlled to be disconnected, the connection between the input terminal of the device under test and the first voltage output terminal is turned on, and the output terminal of the device under test is connected to the first load; The single-chip control module performs the test processes corresponding to the first test instruction, the second test instruction, the third test instruction, the fourth test instruction, the fifth test instruction and the sixth test instruction on the device under test in sequence according to the seventh test instruction.

3. The testing device according to claim 2, characterized in that: The first switch is a four-way switch, the load module includes a first load, a second load, a third load and a fourth load, and the first load, the second load, the third load and the fourth load are respectively connected in series with one of the switches of the first switch and then connected to the output end of the device under test.

4. The testing device according to claim 2, characterized in that: The testing device further comprises a key input module, which is connected to the single-chip control module and is used for generating a test instruction in response to a user operation and inputting the test instruction into the single-chip control module.

5. The testing device according to claim 4, characterized in that: The key input module includes keys corresponding to the first test instruction, the second test instruction, the third test instruction, the fourth test instruction, the fifth test instruction, the sixth test instruction and the seventh test instruction.

6. The testing device according to claim 1, characterized in that: The testing device further comprises a display module, and the display module is connected to the single-chip control module; The single-chip microcomputer control module is also used to output the number of cycles and test results in the current test process to the display module for display. The number of cycles is the number of rising edges and falling edges monitored by the counter module, and the test results include whether the device under test is normal, short-circuited, and open-circuited.

7. The testing device according to claim 6, characterized in that: The display module includes a digital tube, a first latch and a second latch. The digital tube includes a bit selection end and an input end. The output end of the single-chip control module is respectively connected to the input data ends of the first latch and the second latch. The data output end of the first latch is connected to the bit selection end of the digital tube. The output end of the second latch is connected to the input end of the digital tube. 8 . The testing device according to claim 1 , further comprising a constant humidity and constant temperature box, wherein the constant humidity and constant temperature box is used to provide the standard temperature and marked humidity required during the testing process of the device under test.

9. A testing method, applicable to the testing device according to any one of claims 1 to 8, characterized in that: The test method comprises the following steps: Get test instructions; Outputting a first control signal to the first switch, a second control signal to the second switch, and a third control signal to the third switch according to a test instruction, wherein the second switch switches on or off the connection between the first voltage output terminal and the enable terminal of the device under test under the control of the second control signal, and the third switch switches on or off the connection between the first voltage output terminal and the input terminal of the device under test under the control of the third control signal, and the first switch adjusts the load of the load module connected to the device under test under the control of the first control signal; Acquire the monitoring result of the counter module, and determine that the device under test is normal when the number of rising edges and falling edges reaches a preset number of cycles; determine that the device under test is short-circuited when the monitoring result is a continuous high level; and determine that the device under test is open-circuited when the monitoring result is a continuous low level.

10. The testing method according to claim 9, characterized in that: The test instruction includes at least one of a first test instruction, a second test instruction, a third test instruction, a fourth test instruction, a fifth test instruction, a sixth test instruction, and a seventh test instruction; When the single-chip control module performs a startup test on the device under test under the first load condition according to the first test instruction, the connection between the enable terminal of the device under test and the first voltage output terminal is cyclically turned on and off, the connection between the input terminal of the device under test and the first voltage output terminal is turned on, and the output terminal of the device under test is connected to the first load; When the single-chip control module performs a startup test on the device under test under a second load condition according to the second test instruction, the connection between the enable terminal of the device under test and the first voltage output terminal is cyclically turned on and off, the connection between the input terminal of the device under test and the first voltage output terminal is turned on, and the output terminal of the device under test is connected to a second load; When the single-chip control module performs a startup test on the device under test under a second load condition according to the third test instruction, the connection between the enable terminal of the device under test and the first voltage output terminal is turned on and off, the connection between the input terminal of the device under test and the first voltage output terminal is cyclically turned on and off, the output terminal of the device under test is connected to a second load, and when it is determined that a fault occurs in the device under test, the connection between the enable terminal of the device under test and the first voltage output terminal is controlled to be disconnected, the connection between the input terminal of the device under test and the first voltage output terminal is turned on, and the output terminal of the device under test is connected to the second load; When the single-chip control module performs a short-circuit test on the device under test under a third load condition according to the fourth test instruction, the connection between the enable terminal of the device under test and the first voltage output terminal is turned on, the connection between the input terminal of the device under test and the first voltage output terminal is turned on, the output terminal of the device under test is cyclically connected to the third load, and when it is determined that a fault occurs in the device under test, the connection between the enable terminal of the device under test and the first voltage output terminal is controlled to be disconnected, the connection between the input terminal of the device under test and the first voltage output terminal is turned on, and the output terminal of the device under test is connected to the first load; When the single-chip control module performs an overload test on the device under test under a fourth load condition according to the fifth test instruction, the connection between the enable terminal of the device under test and the first voltage output terminal is turned on, the output terminal of the device under test is connected to a fourth load, and the connection between the input terminal of the device under test and the first voltage output terminal is turned on and off cyclically; When the single-chip control module performs an overload test on the device under test under a fourth load condition according to the sixth test instruction, the connection between the enable terminal of the device under test and the first voltage output terminal is turned on and off, the connection between the input terminal of the device under test and the first voltage output terminal is cyclically turned on and off, the output terminal of the device under test is connected to a fourth load, and when it is determined that a fault occurs in the device under test, the connection between the enable terminal of the device under test and the first voltage output terminal is controlled to be disconnected, the connection between the input terminal of the device under test and the first voltage output terminal is turned on, and the output terminal of the device under test is connected to the first load; The single-chip control module performs the test processes corresponding to the first test instruction, the second test instruction, the third test instruction, the fourth test instruction, the fifth test instruction and the sixth test instruction on the device under test in sequence according to the seventh test instruction.

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