Alignment mark, mask, semiconductor device and preparation method thereof

Abstract

The embodiment of the invention relates to an alignment mark, a mask, a semiconductor device and a preparation method thereof. The alignment mark comprises a main mark structure which comprises a plurality of first mark lines arranged periodically, the distance between every two adjacent first mark lines is a first interval, and the gap size between every two adjacent first mark lines is a first key size; the pseudo mark structure comprises a plurality of second mark lines which are periodically arranged, the second mark lines are inserted into gaps among the first mark lines, the second mark lines and the first mark lines are alternately arranged at intervals, and the distance between every two adjacent second mark lines is a second interval; the gap size between the adjacent second mark lines is a second key size; wherein the second interval is the same as the first interval, and the first key size is different from the second key size. When the alignment mark is formed, the pseudo mark structure slows down the etching load effect, and the probability that the alignment mark is damaged is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to an alignment mark, a mask, a semiconductor device and a method for manufacturing the same. Background Art

[0002] Alignment marks are set on the film layer of the wafer to determine whether the position and direction of the mask or wafer are accurate.

[0003] When forming alignment marks, etching loading problems often occur, causing the alignment marks to be damaged and difficult to be identified by alignment detection instruments. Summary of the invention

[0004] Based on this, it is necessary to provide an alignment mark, a mask, a semiconductor device and a method for manufacturing the same in order to solve the etching load problem that occurs when forming an alignment mark in the prior art.

[0005] In order to achieve the above object, on the one hand, an embodiment of the present invention provides an alignment mark, including:

[0006] The main marking structure includes a plurality of periodically arranged first marking lines, the distance between adjacent first marking lines is a first spacing, and the gap size between adjacent first marking lines is a first critical size;

[0007] A pseudo-marking structure, comprising a plurality of periodically arranged second marking lines, wherein the second marking lines are inserted into gaps between the first marking lines, and the second marking lines are alternately arranged with the first marking lines, the distance between adjacent second marking lines is a second spacing, and the size of the gap between adjacent second marking lines is a second critical size;

[0008] The second spacing is the same as the first spacing, and the first critical dimension is different from the second critical dimension.

[0009] In one embodiment, the first critical dimension accounts for 50% of the first spacing.

[0010] In one embodiment, the first marking line has a plurality of first sub-lines arranged in parallel and at intervals, and the second marking line has a plurality of second sub-lines arranged in parallel and at intervals.

[0011] In one embodiment, an extension direction of the first sub-line is different from an extension direction of the second sub-line.

[0012] In one embodiment, the first marking lines include a first line and a second line that are axially symmetrically arranged and intersecting, and the second marking lines include a third line and a fourth line that are axially symmetrically arranged and intersecting, the third line is located between adjacent first lines, and the fourth line is located between adjacent second lines.

[0013] An embodiment of the present invention further provides a mask having a first pattern and a second pattern, wherein the first pattern is a pattern corresponding to the aforementioned alignment mark, and the second pattern is a pattern corresponding to a preset structure.

[0014] An embodiment of the present invention further provides a method for manufacturing a semiconductor device, using the above-mentioned mask, comprising:

[0015] providing a substrate;

[0016] forming a photoresist layer on the substrate;

[0017] Based on the mask, exposing the photoresist layer to form a patterned photoresist layer;

[0018] Based on the patterned photoresist layer, the substrate is etched to form the alignment mark.

[0019] In one embodiment, after the photoresist layer is exposed and etched based on the mask to form a patterned photoresist layer, the method further comprises:

[0020] Measuring a first position of a portion of the patterned photoresist layer formed based on the first pattern;

[0021] The first position is compared with the position of the front layer alignment mark.

[0022] In one embodiment, etching the substrate based on the patterned photoresist layer to form the alignment mark comprises:

[0023] measuring a second position of the alignment mark;

[0024] The second position is compared with the position of the front layer alignment mark.

[0025] An embodiment of the present invention further provides a semiconductor device, comprising:

[0026] substrate;

[0027] The aforementioned alignment mark is located on the substrate;

[0028] The preset structure is formed in the same layer as the alignment mark.

[0029] In the alignment mark, mask, semiconductor device and manufacturing method thereof of the embodiments of the present invention, the alignment mark includes a main mark structure and a dummy mark structure, and the second mark line of the dummy mark structure is inserted into the gap between the first mark lines. When forming the alignment mark, the dummy mark structure mitigates the etching load effect and reduces the probability of damage to the alignment mark. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0031] Figure 1 is a schematic diagram of an alignment mark provided in an embodiment;

[0032] Figure 2 is a schematic diagram of a symmetry axis of an alignment mark provided in an embodiment;

[0033] Figure 3 is a flow chart of a method for preparing a semiconductor structure provided in an embodiment;

[0034] Figure 4 A scanning diagram of a semiconductor structure provided in an embodiment after development and inspection;

[0035] Figure 5 A scanning diagram of a semiconductor structure detected after etching provided in an embodiment.

[0036] Description of the reference numerals: alignment mark 100; main mark structure 110; first mark line 111; first sub-line 1111; first line 1112; second line 1113; dummy mark structure 120; second mark line 121; second sub-line 1211; third line 1212; fourth line 1213. DETAILED DESCRIPTION

[0037] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0039] It should be understood that when an element or layer is referred to as being "on...", "adjacent to..." other elements or layers, it may be directly on, adjacent to, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on...", "directly adjacent to..." other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, and layers, these elements, components, regions, and layers should not be limited by these terms. These terms are merely used to distinguish one element, component, region, or layer from another element, component, region, or layer. Therefore, without departing from the teachings of the present invention, the first element, component, region, or layer discussed below may be represented as a second element, component, region, or layer.

[0040] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0041] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0042] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic representations of idealized embodiments (and intermediate structures) of the invention, and variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are contemplated. Thus, embodiments of the invention should not be limited to the particular shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. The regions shown in the figures are schematic in nature, and their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the invention.

[0043] As described in the background art, when forming an alignment mark, an etching load problem often occurs, causing the alignment mark to be damaged.

[0044] As an example, when it is necessary to form an alignment mark on a wafer, a film layer is first deposited on the entire surface of the wafer. The film layer has a mark area for forming an alignment mark and an array area for forming a storage array. Then, the film layer is etched to form multiple grooves in the mark area and the array area. Finally, an alignment mark is formed in the mark area, and a pattern structure is formed in the array area.

[0045] In this process, since the critical dimension (CD) of the alignment mark is significantly different from the critical dimension of the graphic structure, the etching rates of the etching gas or etching liquid in the mark area and the array area are different, resulting in an etching load effect, which leads to different groove depths in the mark area and the array area.

[0046] In traditional technology, the critical dimension of the alignment mark is larger than the critical dimension of the graphic structure, and the etching gas or liquid is distributed more in the mark area, so the groove in the mark area is deeper, which not only makes the line of the control mark easily damaged, but also makes the control mark difficult to identify.

[0047] In one embodiment, see Figure 1 An embodiment of the present invention provides an alignment mark 100 . The alignment mark 100 includes a main mark structure 110 and a dummy mark structure 120 .

[0048] The main marking structure 110 includes a plurality of periodically arranged first marking lines 111. The distance between adjacent first marking lines 111 is a first spacing. The gap size between adjacent first marking lines 111 is a first critical size.

[0049] As an example, Figure 1 The midline segment AB is represented by the distance between adjacent first marking lines 111, that is, Figure 1 The length of the midline segment AB is the first spacing. Figure 1 The center line segment CD is represented by the gap between adjacent first marking lines 111, that is, Figure 1 The length of the center line segment CD is the first critical dimension.

[0050] The dummy marking structure 120 includes a plurality of periodically arranged second marking lines 121. The second marking lines 121 are inserted into the gaps between the first marking lines 111. The plurality of second marking lines 121 and the plurality of first marking lines 111 are alternately arranged.

[0051] The distance between adjacent second marking lines 121 is the second spacing, and the gap size between adjacent second marking lines 121 is the second critical size. As an example, Figure 1 The middle line segment EF is represented by the distance between adjacent second marking lines 121, that is, Figure 1 The length of the middle line segment EF is the second spacing. Figure 1 The middle line segment GH is represented by the gap between adjacent second marking lines 121, that is, Figure 1 The length of the center line segment GH is the second critical dimension.

[0052] In this embodiment, no specific limitation is imposed on the specific shape and size of the first marking line 111 and the specific shape and size of the second marking line 121 .

[0053] The second spacing is the same as the first spacing. As an example, Figure 1 The length of line segment AB is the same as the length of line segment EF. At the same time, the first critical dimension is different from the second critical dimension. As an example, Figure 1 The length value of the middle line segment CD is different from the length value of the line segment GH.

[0054] The difference between the first critical dimension and the second critical dimension can distinguish the main mark structure 110 from the dummy mark structure 120, so that when the alignment detection instrument scans the alignment mark, the main mark structure 110 and the dummy mark structure 120 can generate independent diffraction waveforms. The diffraction waveforms of the two are superimposed to form the diffraction waveform of the alignment mark 100 for position measurement.

[0055] At the same time, the second spacing is the same as the first spacing, so that the waveform periods of the diffraction waveforms of the main mark structure 110 and the dummy mark structure 120 can be the same, and the peaks of the diffraction waveforms of the two are at the same positions, and the troughs are at the same positions, so that the diffraction waveform finally formed by the alignment mark 100 has the same period as the diffraction waveform of the main mark structure 110, and the peaks and troughs are at the same positions. Therefore, the position measured by the diffraction waveform finally formed by the alignment mark 100 is the same as the position measured by the diffraction waveform of the main mark structure 110. Therefore, the setting of the dummy mark structure 120 does not affect the position measurement of the alignment mark 100.

[0056] As an example, the first critical dimension may be greater than the second critical dimension. Figure 1The length of the middle line segment CD is smaller than the length of the line segment GH. Of course, the first critical dimension may also be smaller than the second critical dimension.

[0057] In this embodiment, the first mark lines 111 and the second mark lines 121 are alternately arranged, and the second mark lines 121 are inserted in the gaps between the first mark lines 111, so that the line density of the alignment mark 100 is increased, thereby reducing the difference between the critical dimension of the alignment mark 100 and the critical dimension of the pattern structure. When forming the alignment mark 100, the etching gas or etching liquid can be more evenly distributed in the mark area and the array area, thereby reducing the etching load effect of the groove in the mark area, obtaining a more uniform line of the alignment mark 100, thereby improving the accuracy of the diffraction waveform of the alignment mark 100 obtained by the alignment detection instrument. At the same time, the probability of damage to the alignment mark 100 can also be reduced.

[0058] In this process, when scanning the first mark line 111 and the second mark line 121, by setting the second spacing to be the same as the first spacing, the diffraction waveform finally formed by the alignment mark 100 has the same period as the diffraction waveform of the main mark structure 110. Therefore, the setting of the dummy mark structure 120 does not affect the position measurement of the alignment mark 100.

[0059] In one embodiment, the first critical dimension accounts for 50% of the first pitch.

[0060] If the first critical dimension accounts for too much of the first spacing, the etching load effect will be increased. If the first critical dimension accounts for too little of the first spacing, it will be disadvantageous for the alignment detection instrument to obtain accurate patterns. In this embodiment, when the first critical dimension accounts for 50% of the first spacing, the alignment quality parameter of the alignment mark 100 is relatively high. (For example, the alignment quality parameter is the percentage of the alignment signal actually received by the alignment detection instrument to the ideal signal value.) For example, please refer to Figure 1 , the length value of line segment CD accounts for 50% of the length value of line segment AB.

[0061] As an example, the value range of the first spacing is 3um-4um, and the first critical dimension is 1.5um-2um. For example, the value of the first spacing is 3.2um, and the first critical dimension is 1.6um. The above data are only examples. In actual embodiments, the values ​​of the first spacing and the first critical dimension are not limited to the above data.

[0062] Of course, the proportion of the second critical dimension in the second spacing can also be 50%. For example, see Figure 1 , the length value of line segment GH accounts for 50% of the length value of line segment EF.

[0063] In one embodiment, the first marking line 111 has a plurality of first sub-lines 1111 that are parallel and spaced apart, and the second marking line 121 has a plurality of second sub-lines 1211 that are parallel and spaced apart.

[0064] Those skilled in the art should know that in this embodiment, the first sub-lines 1111 and the second sub-lines 1211 are multiple lines on the wafer. Grooves are provided between adjacent first sub-lines 1111. Grooves are also provided between adjacent second sub-lines 1211.

[0065] The extension direction of the first sub-line 1111 is different from the extension direction of the second sub-line 1211. Figure 1 , the extension direction of the first sub-line 1111 is the Y direction, and at the same time, the extension direction of the second sub-line 1211 is the X direction.

[0066] As an example, the extension direction of the first sub-line 1111 and the extension direction of the second sub-line 1211 may also form an angle of 30 degrees, 45 degrees or 60 degrees. In another example, the extension direction of the first sub-line 1111 may be perpendicular to the extension direction of the second sub-line 1211.

[0067] In this embodiment, the extension direction of the first sub-line 1111 is different from the extension direction of the second sub-line 1211, so that when forming the alignment mark 100, the etching gas or etching liquid can etch the film layer in multiple directions to form grooves extending in different directions, thereby further reducing the probability of uneven distribution of the etching gas, and further reducing the etching load effect.

[0068] Of course, the extension direction of the first sub-line 1111 may be the same as the extension direction of the second sub-line 1211. As an example, the extension direction of the first sub-line 1111 and the extension direction of the second sub-line 1211 may both be the X direction.

[0069] When the extension direction of the first sub-line 1111 is the same as the extension direction of the second sub-line 1211 , the first marking line 111 and the second marking line 121 are formed to be neatly arranged.

[0070] In one embodiment, the main mark structure 110 and the dummy mark structure 120 may be axisymmetric patterns.

[0071] For example, the first marking line 111 includes a first line 1112 and a second line 1113 that are axially symmetrically arranged and intersecting, and the second marking line 121 includes a third line 1212 and a fourth line 1213 that are axially symmetrically arranged and intersecting. In this case, the symmetry axis of the first marking line 111 and the symmetry axis of the second marking line 121 can be the same symmetry axis. Figure 2The symmetry axis of the first marking line 111 and the symmetry axis of the second marking line 121 are both symmetry axis II', the first line 1112 and the second line 1113 are symmetrically arranged based on symmetry axis II', and the third line 1212 and the fourth line 1213 are symmetrically arranged based on symmetry axis II'.

[0072] Of course, the symmetry axis of the first marking line 111 and the symmetry axis of the second marking line 121 may also be different.

[0073] In one example, the third line 1212 is located between adjacent first lines 1112 , or the fourth line 1213 is located between adjacent second lines 1113 .

[0074] In another example, the third line 1212 is located between adjacent first lines 1112, and the fourth line 1213 is located between adjacent second lines 1113. Figure 2 , the first line 1112, the second line 1113, the third line 1212 and the fourth line 1213 may all form an angle of 45 degrees with the symmetry axis II'. Of course, the first line 1112, the second line 1113, the third line 1212 and the fourth line 1213 may all form an angle of other angles with the symmetry axis II'.

[0075] Of course, the main mark structure 110 and the pseudo mark structure 120 may also be other forms of graphics.

[0076] Based on the same inventive concept, in one embodiment, a mask is provided. The mask is provided with a plurality of light shielding patterns. The mask is placed under a light source, and the light source irradiates the wafer below from the gaps between the light shielding patterns.

[0077] The plurality of light shielding patterns constitute a first pattern and a second pattern, wherein the first pattern corresponds to the aforementioned alignment mark 100, and the second pattern corresponds to a preset structure. As an example, the preset structure may include an active area structure, a contact hole structure, a bit line structure, and a word line structure.

[0078] At this time, see Figure 3 In one embodiment, a method for preparing a semiconductor device is also provided, using the above-mentioned mask. The method for preparing a semiconductor device comprises the following steps:

[0079] Step S100: providing a substrate.

[0080] Step S200: forming a photoresist layer on a substrate.

[0081] Step S300: exposing the photoresist layer based on the mask to form a patterned photoresist layer.

[0082] Step S500 : etching the substrate based on the patterned photoresist layer to form an alignment mark 100 .

[0083] In step S100 , the base includes a substrate and a film layer on the substrate.

[0084] The substrate may be made of semiconductor material, insulating material or any combination thereof. As an example, the substrate may include a silicon substrate, a silicon germanium substrate, a silicon germanium carbon substrate, etc.

[0085] The substrate may be provided with a single film layer or multiple film layers, wherein the top film layer on the substrate is the film layer on which the alignment mark 100 needs to be etched.

[0086] When the film layer can be deposited on the entire surface of the substrate, as an example, the deposition process can include but is not limited to one or more of a chemical vapor deposition process, an atomic layer deposition process, a high-density plasma deposition process, a plasma enhanced deposition process, and a spin-on dielectric layer process.

[0087] In step S200, forming a photoresist layer on the substrate may be forming the photoresist layer on the entire surface of the current film layer. As an example, the material of the photoresist layer may be a photosensitive resin.

[0088] In step S300, the mask is disposed above the photoresist layer, and a light source is disposed above the mask. Based on the mask, the photoresist layer is exposed and developed, and the mask pattern is transferred to the photoresist layer to form a patterned photoresist layer. The patterned photoresist layer defines the position of the alignment mark 100. As an example, the patterned photoresist layer can be formed by irradiating or radiating the photoresist layer with ultraviolet light, electron beam, ion beam, X-ray, etc.

[0089] In step S500 , based on the patterned photoresist layer, a dry etching method or a wet etching method is used to etch the film layer to form an alignment mark 100 .

[0090] As an example, the dry etching includes at least any one of reactive ion etching, inductively coupled plasma etching or high concentration plasma etching.

[0091] As another example, wet etching may include chemical liquid etching, etc.

[0092] In this embodiment, when etching the film layer to form the alignment mark 100, since the alignment mark 100 includes the first mark line 111 and the second mark line 121 alternately arranged, and the second mark line 121 is inserted in the gap between the first mark lines 111, the line density of the entire alignment mark 100 is increased, thereby reducing the difference between the critical dimension of the alignment mark 100 and the critical dimension of the graphic structure. When etching the film layer, the etching gas or etching liquid can be more evenly distributed in the mark area and the array area, thereby reducing the etching load effect of the groove in the mark area, thereby improving the accuracy of the diffraction waveform of the alignment mark 100 obtained by the alignment detection instrument. At the same time, the probability of damage to the alignment mark 100 can also be reduced.

[0093] In one embodiment, after step S300, the following steps are included:

[0094] Step S400: measuring a first position of a partially patterned photoresist layer formed based on a first pattern.

[0095] Step S410 : comparing the first position with the position of the front layer alignment mark 100 .

[0096] In step S400, the position of the patterned photoresist layer may be detected by using a post-development inspection (ADI) method. For example, an optical inspection tool may be used to measure the patterned photoresist layer. Figure 4 , Figure 4 A scan of a patterned photoresist layer inspected after development.

[0097] The first position may be coordinate data of a portion of the patterned photoresist layer formed based on the first pattern.

[0098] In step S410, the detected first position is compared with the position of the front layer alignment mark 100 to detect whether the first position is accurate. As an example, the first position may have a preset distance from the front layer alignment mark 100, or the first position may be the same as the position of the front layer alignment mark 100.

[0099] A photoresist alignment mark structure corresponding to the alignment mark 100 will also appear at a position corresponding to the first pattern in the patterned photoresist layer. At the same time, a photoresist array structure corresponding to the array will also appear at a position corresponding to the second pattern in the patterned photoresist layer.

[0100] In this embodiment, since the alignment mark 100 includes the main mark structure 110 and the dummy mark structure 120, during etching, the etching gas or etching liquid can be more evenly distributed in the area where the photoresist alignment mark structure is located and the area where the photoresist array structure is located, thereby reducing the etching load effect of each groove and obtaining a more uniform groove, thereby improving the accuracy of forming the alignment mark 100 and the graphic structure.

[0101] Of course, while measuring the first position, the key dimension information of the patterned photoresist layer can also be measured using the post-development detection method. For example, the actual width of the patterned photoresist layer and other data can be measured, and the deviation between the actual width of the patterned photoresist layer and the required width can be confirmed. Based on the deviation, the patterned photoresist layer is corrected.

[0102] In one embodiment, after step S500, the following steps are included:

[0103] Step S600 : measuring a second position of the alignment mark 100 .

[0104] Step S610 : comparing the second position with the position of the front layer alignment mark 100 .

[0105] In step S600, the alignment mark 100 may be inspected by a post-etching inspection (AEI) method to obtain the second position. Figure 5 , Figure 5 A scan of the substrate inspected after etching.

[0106] The second position may be coordinate data of the alignment mark 100 in the wafer.

[0107] In step S610 , the second position is compared with the position of the front layer alignment mark 100 to detect whether the second position is accurate. As an example, the second position can be offset from the front layer alignment mark 100 , or the second position can be the same as the front layer alignment mark 100 .

[0108] In this embodiment, the main mark structure 110 and the dummy mark structure 120 are provided to increase the line density of the entire alignment mark 100, thereby reducing the difference between the critical dimension of the alignment mark 100 and the critical dimension of the pattern structure. When forming the alignment mark 100, the etching gas or etching liquid can be more evenly distributed in the mark area and the array area, thereby reducing the etching load effect of each groove, thereby improving the accuracy of measuring the second position.

[0109] After step S500, the patterned photoresist layer may be stripped. As an example, the remaining patterned photoresist layer may be stripped by an ashing process.

[0110] It should be understood that although Figure 3 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 3 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0111] While forming the alignment mark 100, since the second pattern on the mask is a pattern corresponding to the preset structure, while etching to form the alignment mark 100, the current film layer will also be etched in the area of ​​the current film layer corresponding to the second pattern to form the preset structure.

[0112] As an example, when the film layer has a channel region and an array region, the alignment mark 100 is located in the channel region, and the preset structure is located in the array region. At this time, the preset structure includes an active region structure, a contact hole structure, a bit line structure, and a word line structure.

[0113] At this time, in one embodiment, a semiconductor device is provided, including: a substrate, the aforementioned alignment mark 100 and a preset structure.

[0114] The preset structure is also formed while forming the alignment mark 100. Therefore, the preset structure is formed in the same layer as the alignment mark 100. As an example, while forming the alignment mark 100 in the channel region, an active region structure, a contact hole structure, a bit line structure, and a word line structure are formed in the array region.

[0115] The semiconductor structure includes a plurality of film layers, and each film layer may be provided with an alignment mark 100. Meanwhile, each alignment mark 100 may be formed using the aforementioned method.

[0116] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0117] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. An alignment mark, characterized in that: include: The main marking structure includes a plurality of periodically arranged first marking lines, wherein the distance between adjacent first marking lines is a first spacing, and the gap size between adjacent first marking lines is a first critical size; A pseudo-marking structure, comprising a plurality of periodically arranged second marking lines, wherein the second marking lines are inserted into gaps between the first marking lines, and the second marking lines are alternately arranged with the first marking lines, the distance between adjacent second marking lines is a second spacing, and the size of the gap between adjacent second marking lines is a second critical size; The second spacing is the same as the first spacing, and the first critical dimension is different from the second critical dimension.

2. The alignment mark according to claim 1, characterized in that The first critical dimension accounts for 50% of the first spacing.

3. The alignment mark according to claim 1, characterized in that The first marking line has a plurality of first sub-lines arranged in parallel and at intervals, and the second marking line has a plurality of second sub-lines arranged in parallel and at intervals.

4. The alignment mark according to claim 3, characterized in that An extending direction of the first sub-line is different from an extending direction of the second sub-line.

5. The alignment mark according to claim 1, characterized in that: The first marking lines include a first line and a second line that are axially symmetrically arranged and intersecting, and the second marking lines include a third line and a fourth line that are axially symmetrically arranged and intersecting, the third line is located between adjacent first lines, and the fourth line is located between adjacent second lines.

6. A mask, characterized in that: It has a first graphic and a second graphic, wherein the first graphic is a graphic corresponding to the alignment mark according to any one of claims 1 to 5, and the second graphic is a graphic corresponding to a preset structure.

7. A method for preparing a semiconductor device, using the mask according to claim 6, characterized in that: include: providing a substrate; forming a photoresist layer on the substrate; Based on the mask, exposing the photoresist layer to form a patterned photoresist layer; Based on the patterned photoresist layer, the substrate is etched to form the alignment mark.

8. The method for preparing a semiconductor device according to claim 7, characterized in that: After the photoresist layer is exposed and etched based on the mask to form a patterned photoresist layer, the method further comprises: Measuring a first position of a portion of the patterned photoresist layer formed based on the first pattern; The first position is compared with the position of the front layer alignment mark.

9. The method for preparing a semiconductor device according to claim 7, characterized in that: The method of etching the substrate based on the patterned photoresist layer to form the alignment mark comprises: measuring a second position of the alignment mark; The second position is compared with the position of the front layer alignment mark.

10. A semiconductor device, characterized in that: include: substrate; The alignment mark according to any one of claims 1 to 5, located on the substrate; The preset structure is formed in the same layer as the alignment mark.

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