Synchronous wave recording method considering compensation delay

Abstract

The invention discloses a synchronous wave recording method considering compensation time delay, which comprises the following steps: after a master controller and a slave controller synchronize time, the master controller sets communication compensation time delay which is the same as communication time delay after receiving a synchronous wave recording command, and after the communication compensation time delay, the input capture interruption of a timer of a master controller MCU (Microprogrammed Control Unit) is triggered; after receiving the synchronous wave recording command of the master controller FPGA, the slave controller FPGAs trigger timers of the MCUs of the slave controllers in a delayed manner according to respective compensation delay components to input capture interrupts, wave recording of the slave controllers is started, and it can be guaranteed that the master controller and other slave line controllers start the wave recording function at the same time. The synchronous wave recording function data pre-recording time of all the master controllers and the slave controllers is consistent, and the subsequent recording time is consistent.

Description

Technical Field

[0001] The invention relates to the technical field of fault monitoring, and in particular to a synchronous wave recording method considering delay compensation. Background Art

[0002] Automatic control devices need to measure external analog quantities for status detection, limit protection or control calculations, and require switch input and output to display the switch status and internal limit protection status. The data composed of these analog quantities and switch outputs can be stored in a fixed-length data area. The data area records this data in a loop, which is called waveform recording.

[0003] Current automatic control equipment may have multiple controllers working in coordination. If the waveforms of these controllers are obtained at the same time when a fault occurs, the information obtained will be more comprehensive, which is conducive to fault analysis. If all controllers are notified to start recording by communication, the starting time of the waveforms of each controller may be inconsistent, which is not conducive to analysis and comparison. There is a clock deviation between different controllers. The master controller and the slave controller transmit signals through the network, and there is also a communication delay. It is very important to make the clocks of the master controller and the slave controller consistent and compensate for the communication delay to synchronize the recording and broadcasting of each slave controller. Summary of the invention

[0004] The present invention aims to provide a synchronous recording method considering delay compensation, which is used to enable the master controller to cooperate with other slave controllers to synchronously record after receiving a recording command from a human-machine interface or detecting a synchronous recording trigger event, so that all controllers send the recording data to the human-machine interface synchronously through a network port, including the following steps:

[0005] Step 1. The master controller and multiple slave controllers perform high-precision time synchronization of the master / slave controller clock sources, and measure the communication delay between the master controller and different slave controllers, and take the longest value among different communication delay values ​​as the compensation delay;

[0006] Step 2. The MCU of the master controller sends a synchronous recording command to the FPGA of the master controller. After receiving the synchronous recording command, the FPGA of the master controller sends the synchronous recording command to other slave controllers through optical fiber communication, and delays the triggering of the timer input capture interrupt of the corresponding recording function of the MCU of the master controller, and the delay duration is the compensation delay;

[0007] Step 3. After receiving the synchronous recording command, the FPGA of the slave controller triggers the timer input capture interrupt of the MCU of the slave controller according to the delay of each compensation delay component, and starts the recording of each slave controller;

[0008] The compensation delay component is equal to the difference between the compensation delay and the communication delay between each slave controller and the master controller;

[0009] After the compensation delay ends, the timer input capture interrupt of the MCU of the main controller is triggered immediately to start the recording of the main controller;

[0010] The time from when the FPGA of the master controller sends the synchronous recording command through the optical fiber to when the FPGA of other slave controllers receives the synchronous recording command is the communication delay between the master controller and each slave controller;

[0011] Step 4. The master controller and all slave controllers record the waveform data according to the same pre-recording time and subsequent recording time. After completing the waveform recording, the master controller and the slave controller transmit the waveform data to the human-machine interface via Ethernet, and the human-machine interface aggregates the waveform data of the master controller and the slave controllers into a waveform data file;

[0012] The master controller and all slave controllers include FPGA and MCU. The MCU sends the communication target ID and data to the FPGA through the parallel port or SPI, or reads and receives data from the FPGA. The pins of the FPGA are connected to the corresponding pins of the timer channel of the MCU. The timer capture interrupt is triggered by the FPGA output signal to start the MCU's recording function. Each MCU communicates with the human-machine interface through the network port, and each FPGA communicates through optical fiber.

[0013] In step 1, the master controller and multiple slave controllers perform high-precision time synchronization of the master / slave controller clock sources, including: enabling the master controller and the slave controllers to communicate end-to-end through the network, calculating the time deviation T between the master controller and the slave controller offset and communication delay T delay , and then calculate the frequency ratio of the clocks of the master controller and the slave controller, and finally adjust the frequency of the clock source of the slave controller and the master controller according to the frequency ratio to achieve high-precision time synchronization of the master / slave controller clock sources.

[0014] Furthermore, the time deviation T between the master controller and the slave controller is calculated. offset , and then calculate the frequency ratio of the master controller and the slave controller clock, including:

[0015] (1) Clock deviation and communication delay can be measured by IEEE 1588 protocol clock synchronization. First, the master controller sends a sync message to the slave controller and records the time T1 when the sync message leaves the master controller. After a delay, the sync message is received by the slave controller and the time T2 when the slave controller receives the sync message is recorded. After the master controller sends the sync message, it sends the timestamp T1 to the slave controller through a Follow Up message after a short period of time. The slave controller obtains the timestamp T1 by receiving the Follow Up message. The communication delay of the message from the master controller to the slave clock is defined as T delay, we can get the first calculation relationship between clock deviation and communication delay: T1+T offset +T delay =T2;

[0016] After receiving the Follow_Up message from the slave controller, after a random delay, the slave controller sends a delay_req message to the master controller, and records the time T3 when the delay_req message leaves the slave controller. After the master controller receives the delay_Req message, it records the time T4 when it receives it. After a short period of time, the master controller sends the timestamp T4 using the delay_Resp message, and the slave controller obtains the timestamp T4 after receiving the message. The communication delay of the message from the slave controller to the master controller is defined as T delay , we can get the second calculation relationship between clock deviation and communication delay: T3+T delay =T4+T offset ;

[0017] T delay =0.5[(T2-T1)+(T4-T3)];

[0018] T offset =0.5[(T2-T1)-(T4-T3)].

[0019] T offset >0 means that when the clock sources of the slave controller and the master controller output the same time, the slave controller outputs a later time than the master controller. offset <0 means that when the clock sources of the slave controller and the master controller output the same time, the slave controller outputs the clock source earlier than the master controller; then use T offset Correct the clock source of the slave controller;

[0020] (2) Calculate the ratio of the slave controller's clock source frequency fc to the master controller's clock source frequency fz:

[0021] fc / fz=(T delay +T offset ) / (T delay -T offset ).

[0022] After the master controller and the slave controller synchronize their time, the master controller sets the same communication compensation delay as the communication delay after receiving the synchronous recording command. After this communication compensation delay, the input capture interrupt of the timer of the master controller MCU is triggered. After the slave controller FPGA receives the synchronous recording command of the master controller FPGA, it triggers the timer input capture interrupt of the slave controller MCU according to the respective compensation delay components, and starts the recording of each slave controller. The compensation delay component is equal to the compensation delay minus the difference between the communication delay between each slave controller and the master controller, which can ensure that the master controller and other slave line controllers start the recording function at the same time. The pre-recording time of the synchronous recording function data of all master controllers and slave controllers is consistent, and the subsequent recording time is consistent. After completing the waveform recording, each master controller and slave controller transmits the recording data to the human-machine interface through Ethernet, and the human-machine interface summarizes the recording data of each master controller and slave controller into a recording data file. It is convenient to analyze and compare the actual cause-and-effect relationship of the output of different controllers. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a block diagram of the master controller or slave controller;

[0024] Figure 2 This is a schematic diagram of the FPGA output signal entering the timer;

[0025] Figure 3 Schematic diagram of synchronizing clocks for the IEEE 1588 protocol;

[0026] Figure 4 This is the timing diagram of synchronous recording. DETAILED DESCRIPTION

[0027] The present invention will be further described below in conjunction with preferred embodiments and accompanying drawings.

[0028] Example 1

[0029] A synchronous recording method considering delay compensation is used to make the main controller cooperate with other slave controllers to record synchronously after receiving the recording command of the human-machine interface or detecting the synchronous recording trigger event, so that all controllers send the recording data to the human-machine interface synchronously through the network port, such as Figure 1 and Figure 2The main controller and all slave controllers shown are provided with FPGA and MCU. The MCU of the main controller and all slave controllers communicate with the human-machine interface through the network port. The FPGA of the main controller and all slave controllers communicate with each other through optical fiber. The MCU is connected with the FPGA signal, which is used to make the MCU send the identity information and data of the MCU to the FPGA. The MCU also reads and receives data from the FPGA. The FPGA is also connected with the port signal corresponding to the timer channel of the MCU. The rising edge or falling edge of the output signal is set as a signal to trigger the timer capture interrupt of the MCU. The timer capture interrupt of the MCU is triggered by the change of the output signal of the FPGA. When the port of the triggered timer channel is configured as an input, the timer latches the current count value and enters the interrupt service program. It is used to start the recording function of the MCU.

[0030] like Figure 4 As shown in the timing diagram, when a master controller coordinates multiple slave controllers to record synchronously, due to the clock deviation between different slave controllers and the master controller, or the communication delay between the master controller and the same slave controller, the waveform starting time is inconsistent when different slave controllers record, which is conducive to fault analysis. The slave controllers include 1# slave controller, 2# slave controller, and 3# slave controller. A master controller coordinates multiple slave controllers to perform synchronous recording according to the following synchronous recording method that considers delay compensation:

[0031] Step 1. The master controller and multiple slave controllers perform high-precision time synchronization of the master / slave controller clock sources, and measure the communication delay between the master controller and different slave controllers, and take the longest value among different communication delay values ​​as the compensation delay;

[0032] Step 2. The MCU of the master controller sends a synchronous recording command to the FPGA of the master controller. After receiving the synchronous recording command, the FPGA of the master controller sends the synchronous recording command to other slave controllers through optical fiber communication, and delays the triggering of the timer input capture interrupt of the corresponding recording function of the MCU of the master controller, and the delay duration is the compensation delay;

[0033] Step 3. After receiving the synchronous recording command, the FPGA of the slave controller triggers the timer input capture interrupt of the MCU of the slave controller according to the delay of each compensation delay component, and starts the recording of each slave controller;

[0034] The compensation delay component is equal to the difference between the compensation delay and the communication delay between each slave controller and the master controller;

[0035] After the compensation delay ends, the timer input capture interrupt of the MCU of the main controller is triggered immediately to start the recording of the main controller;

[0036] The time from when the FPGA of the master controller sends the synchronous recording command through the optical fiber to when the FPGA of other slave controllers receives the synchronous recording command is the communication delay between the master controller and each slave controller;

[0037] Step 4. The master controller and all slave controllers record the waveform data according to the same pre-recording time and subsequent recording time. After completing the waveform recording, the master controller and the slave controller transmit the waveform data to the human-machine interface via Ethernet, and the human-machine interface summarizes the waveform data of the master controller and the slave controllers into a waveform data file.

[0038] In step 4, when the main controller and all slave controllers receive the recording command, they take the currently recorded data point as the time zero point, multiply the pre-recording time by the recording frequency to get the waveform starting point, and multiply the subsequent recording time by the recording frequency to get how many data points need to be recorded to complete the recording command.

[0039] In step 1, the master controller and multiple slave controllers perform high-precision time synchronization of the master / slave controller clock sources, including: enabling the master controller and the slave controllers to communicate end-to-end through the network, calculating the time deviation T between the master controller and the slave controller offset and communication delay T delay , then calculate the frequency ratio of the clocks of the master controller and the slave controller, and finally adjust the frequencies of the clock sources of the slave controller and the master controller according to the frequency ratio to achieve high-precision time synchronization of the master / slave controller clock sources.

[0040] Calculate the time deviation T between the master controller and the slave controller offset and communication delay T delay , and then calculate the frequency ratio of the master controller and the slave controller clock, including:

[0041] (1) First, the master controller sends a Sync message to the slave controller, and records the time T1 when the Sync message leaves the master controller, and records the time T2 when the slave controller receives the Sync message. After the master controller sends the Sync message, it sends the timestamp T1 to the slave controller via a Follow Up message after a short period of time. The slave controller obtains the timestamp T1 by receiving the Follow Up message.

[0042] After receiving the Follow_Up message from the slave controller, after a random delay, the slave controller sends a delay_req message to the master controller, and records the time T3 when the delay_req message leaves the slave controller. After the master controller receives the delay_Req message, it records its receiving time T4. The master controller sends the timestamp T4 using the delay_Resp message, and obtains the timestamp T4 after receiving the message from the slave controller.

[0043] Tdelay =0.5[(T2-T1)+(T4-T3)];

[0044] T offset =0.5[(T2-T1)-(T4-T3)];

[0045] The master controller has the same timing cycle and base as the clock source of the slave controller; if the slave controller's clock is slower than the master controller's clock by T offset , the master controller and the slave controller send second pulse signals to each other at the 1st second. Although the master controller clock and the slave controller clock are at the same time coordinate, it is actually equal to the slave controller at the 1st second + T of the master controller. offset The second pulse signal is sent only at 1000 sec., that is, the slave controller is later than the master controller's clock source output time.

[0046] Therefore, T offset >0 means that when the clock sources of the slave controller and the master controller output the same time, the slave controller outputs a later time than the master controller. offset <0 means that when the clock sources of the slave controller and the master controller output the same time, the slave controller outputs the clock source earlier than the master controller; then use T offset Correct the clock source of the slave controller; for example, offset the clock source of the slave controller by -T offset ;

[0047] (2) Calculate the ratio of the slave controller's clock source frequency fc to the master controller's clock source frequency fz:

[0048] fc / fz=(T delay +T offset ) / (T delay -T offset ).

[0049] The frequency of the clock source of the slave controller is then adjusted according to the ratio fc / fz:

[0050] Achieve high-precision time synchronization of the master / slave controller clock sources.

[0051] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement made to the above embodiments without departing from the content of the technical solution of the present invention, based on the technical essence of the present invention, within the spirit and principles of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims

1. A synchronous recording method considering delay compensation, which is used to make the main controller cooperate with other slave controllers to record synchronously after receiving the recording command from the human-machine interface or detecting the synchronous recording trigger event, so that all controllers send the recording data to the human-machine interface synchronously through the network port, characterized in that: The following steps are involved: Step 1. The master controller and multiple slave controllers perform high-precision time synchronization of the master / slave controller clock sources, and measure the communication delay between the master controller and different slave controllers, and take the longest value among different communication delay values ​​as the compensation delay; Step 2. The MCU of the master controller sends a synchronous recording command to the FPGA of the master controller. After receiving the synchronous recording command, the FPGA of the master controller sends the synchronous recording command to other slave controllers through optical fiber communication, and delays the triggering of the timer input capture interrupt of the corresponding recording function of the MCU of the master controller, and the delay duration is the compensation delay; Step 3. After receiving the synchronous recording command, the FPGA of the slave controller triggers the timer input capture interrupt of the MCU of the slave controller according to the delay of each compensation delay component, and starts the recording of each slave controller; The compensation delay component is equal to the difference between the compensation delay and the communication delay between each slave controller and the master controller; After the compensation delay ends, the timer input capture interrupt of the MCU of the main controller is triggered immediately to start the recording of the main controller; The time from when the FPGA of the master controller sends the synchronous recording command through the optical fiber to when the FPGA of other slave controllers receives the synchronous recording command is the communication delay between the master controller and each slave controller; Step 4. The master controller and all slave controllers record the waveform data according to the same pre-recording time and subsequent recording time. After completing the waveform recording, the master controller and the slave controller transmit the waveform data to the human-machine interface via Ethernet, and the human-machine interface aggregates the waveform data of the master controller and the slave controllers into a waveform data file; The master controller and all slave controllers include FPGA and MCU. The MCU sends the communication target ID and data to the FPGA through the parallel port or SPI, or reads and receives data from the FPGA. The pins of the FPGA are connected to the corresponding pins of the timer channel of the MCU. The timer capture interrupt is triggered by the FPGA output signal to start the MCU's recording function. Each MCU communicates with the human-machine interface through the network port, and each FPGA communicates through optical fiber.

2. The synchronous recording method considering delay compensation according to claim 1 is characterized in that: In step 1, the master controller and multiple slave controllers perform high-precision time synchronization of the master / slave controller clock sources, including: enabling the master controller and the slave controllers to communicate end-to-end through the network, calculating the time deviation T between the master controller and the slave controller offset and communication delay T delay , then calculate the frequency ratio of the clocks of the master controller and the slave controller, and finally adjust the frequencies of the clock sources of the slave controller and the master controller according to the frequency ratio to achieve high-precision time synchronization of the master / slave controller clock sources.

3. The synchronous recording method considering delay compensation according to claim 2 is characterized in that: The time deviation T between the master controller and the slave controller is calculated offset and communication delay T delay , and then calculate the frequency ratio of the master controller and the slave controller clock, including: (1) First, the master controller sends a Sync message to the slave controller, and records the time T1 when the Sync message leaves the master controller, and records the time T2 when the slave controller receives the Sync message. After the master controller sends the Sync message, it sends the timestamp T1 to the slave controller via a Follow Up message after a short period of time. The slave controller obtains the timestamp T1 by receiving the Follow Up message. After receiving the Follow_Up message from the slave controller, after a random delay, the slave controller sends a delay_req message to the master controller, and records the time T3 when the delay_req message leaves the slave controller. After the master controller receives the delay_Req message, it records its receiving time T4. The master controller sends the timestamp T4 using the delay_Resp message, and obtains the timestamp T4 after receiving the message from the slave controller. T delay =0.5[(T2-T1)+(T4-T3)]; T offset =0.5[(T2-T1)-(T4-T3)]; T offset >0 means that when the clock sources of the slave controller and the master controller output the same time, the slave controller outputs a later time than the master controller. offset <0 means that when the clock sources of the slave controller and the master controller output the same time, the slave controller outputs the clock source earlier than the master controller; then use T offset Correct the clock source of the slave controller; (2) Calculate the ratio of the slave controller's clock source frequency fc to the master controller's clock source frequency fz: fc / fz=(T delay +T offset ) / (T delay -T offset )。

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