Pre-driving circuit structure for self-calibration of charging and discharging current

Abstract

The invention provides a charging and discharging current self-calibration pre-driving circuit structure, which comprises a driving current input end, a driving current output end, a reference unit, a current charging and discharging unit, a sampling unit, a voltage comparison unit and a calibration unit, and is characterized in that the input end of the reference unit is connected with a band-gap reference module, and the output end of the reference unit is connected with the output end of the current charging and discharging unit; the driving current input end is connected with the driving current output end through the current charging and discharging unit, the input end of the sampling unit is connected with the driving current output end, the output end is connected with the voltage comparison unit, the output end of the voltage comparison unit is connected with the calibration unit, and the calibration unit generates calibration codes according to comparison results of the voltage comparison unit. And inputting the calibration code into the current charging and discharging unit to calibrate the charging and discharging current.

Description

Technical Field

[0001] The present invention relates to the technical field of pre-driving circuits, and in particular to a pre-driving circuit structure with self-calibration of charging and discharging currents. Background Art

[0002] Pre-driver mainly adds a circuit before the drive circuit to process the input signal, protect the drive circuit and provide a larger gate drive voltage to better drive the subsequent circuit. Pre-driver circuits are widely used in motor control and high-speed communication.

[0003] Conventional pre-driver circuits such as Figure 1 As shown, it includes a reference unit and a current charging and discharging unit, and the input current is I current1 , M3, M5, M 20 、M 22 、M 28 、M 29 、M 24 、M 25 The equal current mirror is connected to the circuit to realize current amplification and charge the GATE line. The GATE voltage is increased until it is close to the clamp voltage and then the charging is stopped. The OFF signal controls M3, M4, and M 12 、M 14 、M 17 、M 19 The equal current mirror is connected to the circuit to discharge the GATE line and reduce the GATE voltage. The accuracy of the charge and discharge current of the pre-drive circuit depends on I current1 The accuracy of the current mirror and the matching degree between the current mirror, and because the clamp voltage is obtained by amplifying the power supply VDD through the current mirror, and when charging the GATE line, the GATE voltage will not stop charging until it is close to the clamp voltage, so the GATE voltage is affected by the power supply VDD. In normal use, the input current I current1 The error with the power supply VDD inside the chip is usually as high as ±10%, which makes it difficult to meet the design requirements for some high-precision GATE and charge and discharge current control needs. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a pre-driving circuit with high charging and discharging current accuracy.

[0005] In order to solve the above technical problems, the present invention provides a pre-driving circuit structure for self-calibration of charge and discharge current, comprising a drive current input terminal, a drive current output terminal, a reference unit, a current charge and discharge unit, a sampling unit, a voltage comparison unit and a calibration unit, wherein:

[0006] The reference unit includes a first operational amplifier, an output MOS tube, a ballast resistor and a first group of current mirror structures, wherein the positive input terminal of the first operational amplifier is connected to the bandgap reference module, the negative input terminal is grounded via the ballast resistor, and the output terminal is connected to the output terminal of the current charge and discharge unit via the output MOS tube and the first group of current mirror structures;

[0007] The current charge and discharge unit includes a charge signal control switch, a discharge signal control switch, a second group of current mirror structures and a third group of current mirror structures, the drive current input end is connected to the drive current output end through the charge signal control switch and the second group of current mirror structures, and is connected to the drive current output end through the discharge signal control switch and the third group of current mirror discharge structures;

[0008] The sampling unit includes a sampling resistor, a switching switch and a second operational amplifier, wherein the sampling resistor is connected in series between the output end of the current charging and discharging unit and the driving output end, the positive input end and the negative input end of the second operational amplifier are respectively connected to the two ends of the sampling resistor via the switching switch, and the output end is connected to the voltage comparison unit;

[0009] The voltage comparison unit includes a first voltage comparator, a second voltage comparator, a fourth current mirror structure and a fifth current mirror structure, wherein the positive input terminal of the first voltage comparator is connected to the output terminal of the second operational amplifier, the negative input terminal is connected to the reference unit through the fourth current mirror structure, and the output terminal is connected to the calibration unit, the positive input terminal of the second voltage comparator is connected to the output terminal of the operational amplifier, the negative input terminal is connected to the reference unit through the fifth current mirror structure, and the output terminal is connected to the calibration unit;

[0010] The calibration unit includes a self-calibration control logic structure and a calibration code input structure. The input end of the self-calibration control logic structure is respectively connected to the output end of the first voltage comparator and the output end of the second voltage comparator. The output end of the self-calibration control logic structure is connected to the calibration code input structure. The calibration code input structure is connected in series in the current charge and discharge unit. The self-calibration control logic structure generates a calibration code according to the comparison result between the first voltage comparator and the second voltage comparator. The calibration code is input into the current charge and discharge unit through the calibration code input structure to calibrate the charge and discharge current.

[0011] Furthermore, the output MOS tube is an N-type MOS tube, whose gate is connected to the output end of the first operational amplifier, the source is grounded via a ballast resistor, and the drain is connected to the output end of the current charge and discharge unit via a first set of current mirror structures.

[0012] Furthermore, the current charge and discharge unit includes a clamping circuit, and the output end of the first operational amplifier is connected to the output end of the current charge and discharge unit via the output MOS tube and the first group of current mirror structures. Specifically, the output end of the first operational amplifier is first connected to the output end of the current charge and discharge unit via the output MOS tube and the first group of current mirror structures, and then via the clamping circuit.

[0013] Furthermore, the current charge and discharge unit is provided with a charging voltage stabilizing device, a control end of which is connected to the second group of current mirror structures, and an output end is connected to the third group of current mirror structures. During charging, the charging voltage stabilizing device controls the third group of current mirror structures to be turned off according to the second group of current mirror structures to prevent the third group of current mirror structures from affecting charging stability.

[0014] Furthermore, the width-to-length ratio of the output stage devices to the input stage devices of the fourth group of current mirror structures is greater than the width-to-length ratio of the output stage devices to the input stage devices of the fifth group of current mirror structures.

[0015] The present invention has the following beneficial effects: since the positive input terminals of the first voltage comparator and the second voltage comparator are connected to the output terminal of the second operational amplifier, and the negative input terminals are respectively connected to the reference unit through the current mirror structure, the main factors affecting the comparison results of the first voltage comparator and the second voltage comparator are the input offset voltage of the second operational amplifier, the sampling resistor and the variation range of the bandgap reference voltage. In general, the influence of the input offset voltage of the second operational amplifier on the accuracy can be controlled within ±1% in the design, and in the resistor manufacturing process, the accuracy error of the sampling resistor can be guaranteed to be within ±1%, and the bandgap reference voltage is generated by the bandgap reference module. From the perspective of structural design, the bandgap reference module can ensure that the accuracy error of the bandgap reference voltage generated by it is within ±1%. In summary, the self-calibration control logic structure generates a calibration code according to the comparison results of the first voltage comparator and the second voltage comparator, and then uses the calibration code to calibrate the charge and discharge current to achieve a calibration accuracy error within ±3%, which is higher than the traditional pre-driving circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a circuit schematic diagram of a traditional pre-driver circuit.

[0017] Figure 2 The invention discloses a circuit principle diagram of a pre-driving circuit for self-calibration of charge and discharge current.

[0018] Figure 3 It is the circuit diagram of the toggle switch.

[0019] Figure 4 It is the circuit schematic diagram of the self-calibration control logic structure. DETAILED DESCRIPTION

[0020] The present invention is further described in detail below in conjunction with specific implementation methods.

[0021] This embodiment provides a pre-driving circuit structure for self-calibration of charge and discharge currents, such as Figure 2 As shown, the pre-driving circuit structure includes a driving current input terminal I current1 , driving current output terminal GATE, reference unit, current charging and discharging unit, sampling unit, voltage comparison unit and calibration unit.

[0022] The reference unit includes a first operational amplifier AMP1, an output MOS tube M1, a ballast resistor R1 and a first set of current mirror structures. The positive input terminal of the first operational amplifier AMP1 is connected to a bandgap reference module (bandgap reference), the negative input terminal is grounded via the ballast resistor R1, and the output terminal is connected to the gate of the output MOS tube M1. The bandgap reference module generates a bandgap reference voltage Vref that does not drift with temperature, and the first operational amplifier AMP1 inputs the bandgap reference voltage Vref through its positive input terminal.

[0023] The first group of current mirror structures includes three current mirrors, namely, a first current mirror, a second current mirror, and a third current mirror. The first current mirror includes a MOS tube M2 and a MOS tube M3, wherein the MOS tube M2 is an input stage device of the first current mirror, and the MOS tube M3 is an output stage device of the first current mirror, and the MOS tube M2 and the MOS tube M3 are specifically P-type MOS tubes. The second current mirror includes a MOS tube M4 and a MOS tube M5, wherein the MOS tube M4 is an input stage device of the second current mirror, and the MOS tube M5 is an output stage device of the second current mirror, and the MOS tube M4 and the MOS tube M5 are specifically N-type MOS tubes. The third current mirror includes a MOS tube M 25 、MOS tube M 26 、MOS tube M 27 And MOS tube M 28 , where MOS tube M 28 And MOS tube M 25 It is the input stage device of the third current mirror, MOS tube M 27 And MOS tube M 26 It is the output stage device of the third current mirror, MOS tube M 25 、MOS tube M 26 、MOS tube M 27 And MOS tube M 28 Specifically, it is a P-type MOS tube.

[0024] The output MOS tube M1 is specifically an N-type MOS tube, whose gate is connected to the output end of the first operational amplifier AMP1, the source is grounded via the ballast resistor R1, and the drain is connected to the output end of the current charge and discharge unit via the first group of current mirror structures (i.e., the first current mirror, the second current mirror, and the third current mirror). Then, the output end of the first operational amplifier AMP1 is connected to the output end of the current charge and discharge unit via the output MOS tube M1 and the first group of current mirror structures in sequence. The drain of the output MOS tube M1 is connected to the output end of the current charge and discharge unit through the first group of current mirror structures. Specifically: in the first current mirror, the MOS tube M2 is used as an input-stage device, the source of which is connected to the power supply VDD, the drain of which is connected to the drain of the output MOS tube M1, the gate of which is short-circuited with the drain and connected to the gate of the MOS tube M3, and the MOS tube M3 is used as an output-stage device, the gate of which is connected to the gate of the MOS tube M2, the source of which is connected to the power supply VDD, and the drain of which is connected to the drain of the MOS tube M4; in the second current mirror, the MOS tube M4 is used as an input-stage device, the drain of which is connected to the drain of the MOS tube M3, the source of which is grounded, the gate of which is short-circuited with the drain and connected to the gate of the MOS tube M5, and the MOS tube M5 is used as an output-stage device, the gate of which is connected to the gate of the MOS tube M4, and the drain of which is connected to the gate of the MOS tube M5. 25 The drain of the MOS tube M is grounded; in the third current mirror, 28 As an input stage device, its source is connected to the power supply VCP, and its drain is connected to the MOS tube M 25 The source of the MOS tube M is shorted to the gate and connected to the drain. 27 The gate connection of MOS tube M 25 As an input stage device, its source is connected to MOS tube M 28 The drain of the MOS tube M5 is connected to the drain of the MOS tube M5, and the gate is short-circuited to the drain and connected to the MOS tube M5. 26 The gate of the MOS tube M 27 As an output stage device, its gate is connected to MOS tube M 28 The gate of the MOS tube M is connected to the source of the MOS tube M. 26 The source of MOS tube M 26 As an output stage device, its gate is connected to MOS tube M 25 The gate and source of MOS tube M 27 The drain of the MOS tube M is connected to the SOURCE line through the resistor R4. 26 Between the resistor R4, the output end of the current charge and discharge unit is connected through the clamp line; in summary, the output end of the first operational amplifier AMP1 is connected to the output end of the current charge and discharge unit via the output MOS tube M1, the first current mirror, the second current mirror, and the third current mirror in sequence.

[0025] It should be noted that in the third current mirror, the MOS tube M 28 With MOS tube M 27A current mirror has been formed, and a MOS tube M is added on this basis 25 With MOS tube M 26 As the bias stage of the common source and common gate current mirror, it can improve the current replication accuracy. In addition, when the voltage difference between the power supply VCP and the SOURCE line is large, the MOS tube M 25 With MOS tube M 26 Selecting a high-voltage MOS tube can act as a protection tube.

[0026] The current charging and discharging unit includes a charging signal control switch, a discharging signal control switch, a second group of current mirror structures, a third group of current mirror structures and a clamping circuit. Among them, the charging signal control switch is specifically a MOS tube M 22 Its gate is used to input the ON signal output by the logic control unit inside the chip. After the ON signal is input, the MOS tube M 22 The discharge signal control switch is specifically a MOS tube M 21 Its gate is used to input the OFF signal output by the logic control unit inside the chip. After the OFF signal is input, the MOS tube M 21 The clamping circuit includes a MOS tube M 40 And MOS tube M 41 , MOS tube M 40 And MOS tube M 41 The output end of the first operational amplifier AMP1 described above is connected to the output end of the current charge and discharge unit through the output MOS tube M1 and the first current mirror structure in sequence, and specifically, the output end of the first operational amplifier AMP1 is connected to the output end of the current charge and discharge unit through the output MOS tube M1 and the first current mirror structure in sequence, and then through the clamping circuit.

[0027] The second group of current mirrors is a current mirror charging structure, which includes four current mirrors, namely the fourth current mirror, the fifth current mirror, the sixth current mirror and the seventh current mirror. The fourth current mirror includes MOS tube M6 and MOS tube M 26 MOS tube M6 is the input stage device of the fourth current mirror, and MOS tube M 26 It is the output stage device of the fourth current mirror, MOS tube M6 and MOS tube M 26 Specifically, it is an N-type MOS tube. The fifth current mirror includes a MOS tube M 34 、MOS tube M 35 、MOS tube M 36 And MOS tube M 37 , where MOS tube M 34 And MOS tube M 36 It is the input stage device of the fifth current mirror, MOS tube M 35 And MOS tube M 37It is the output stage device of the fifth current mirror, MOS tube M 34 、MOS tube M 35 、MOS tube M 36 And MOS tube M 37 Specifically, it is a P-type MOS tube. The sixth current mirror includes a MOS tube M 45 And MOS tube M 46 , where MOS tube M 45 It is the input stage device of the sixth current mirror, MOS tube M 46 It is the output stage device of the sixth current mirror, MOS tube M 45 And MOS tube M 46 Specifically, it is an N-type MOS tube. The seventh current mirror includes a MOS tube M 38 And MOS tube M 39 , where MOS tube M 38 It is the input stage device of the seventh current mirror, MOS tube M 39 It is the output stage device of the seventh current mirror, MOS tube M 38 And MOS tube M 39 Specifically, it is a P-type MOS tube.

[0028] Drive current input terminal I current1 The charging signal controls the switch (ie, MOS tube M 22 ), a second group of current mirror structures (i.e., the fourth current mirror, the fifth current mirror, the sixth current mirror, and the seventh current mirror) and a clamping circuit are connected to the drive current output terminal GATE. Specifically: in the fourth current mirror, the MOS tube M6 is used as an input stage device, and its drain is connected to the drive current input terminal I current1 , the source is grounded, the gate is short-circuited with the drain and connected to the MOS tube M 26 The gate of the MOS tube M 26 As an output stage device, its gate is connected to the gate of MOS tube M6, and its drain is connected to the gate of MOS tube M 22 The source of the charging signal control switch is grounded. 22 The gate is used to input the ON signal output by the logic control unit inside the chip, and the drain is connected to the MOS tube M 34 The drain and source of MOS tube M 26 In the fifth current mirror, the MOS tube M 36 As an input stage device, its source is connected to the power supply VCP, and its drain is connected to the MOS tube M 34 The source of the MOS tube M is shorted to the gate and connected to the drain. 37 The gate connection of MOS tube M 34 As an input stage device, its source is connected to MOS tube M 36 The drain of the MOS tube M 22The drain of the MOS tube M is shorted to the gate. 35 The gate of the MOS tube M 37 As an output stage device, its gate is connected to MOS tube M 36 The gate of the MOS tube M is connected to the source of the MOS tube M. 35 The source of MOS tube M 35 As an output stage device, its gate is connected to MOS tube M 34 The gate and source of MOS tube M 37 The drain of the MOS tube M 45 In the sixth current mirror, the MOS tube M 45 As an input stage device, its drain is connected to MOS tube M 35 The drain of the MOS tube M is connected to the source and the gate is short-circuited to the drain. 46 The gate of the MOS tube M 46 As an output stage device, its gate is connected to MOS tube M 45 The gate and drain of MOS tube M 40 The source of the MOS tube M is connected to the SOURCE line. 38 As an input stage device, its source is connected to the power supply VCP, and its drain is connected to the MOS tube M 40 The drain of the MOS tube M is shorted to the gate. 39 The gate of the MOS tube M 39 As an output stage device, its gate is connected to MOS tube M 38 The gate of the MOS tube M is connected to the source of the MOS tube M. 41 In the clamping circuit, the MOS tube M 40 Drain connected to MOS tube M 38 The drain and source of MOS tube M 46 The drain of the MOS tube M is connected to the reference unit through the clamp line. 41 Drain connected to MOS tube M 39 The drain and source of MOS tube M 46 The gate is connected to the drive current output terminal GATE through the sampling resistor R5. Since the clamp circuit is connected to the drive current output terminal GATE, the input current I current1 After being amplified by the second current mirror structure, the GATE line is charged until the GATE voltage reaches the clamp voltage and the charging stops.

[0029] It should be noted that in the fifth current mirror, the MOS tube M 36 With MOS tube M 37 A current mirror has been formed, and a MOS tube M is added on this basis 34With MOS tube M 35 As the bias stage of the common-source common-gate current mirror, it can improve the current replication accuracy, and when the voltage difference between the power supply VCP and the SOURCE line is large, the MOS tube M 34 With MOS tube M 35 Selecting a high-voltage MOS tube can act as a protection tube.

[0030] The third group of current mirror structures is a current mirror discharge structure, which includes three current mirrors, namely, an eighth current mirror, a ninth current mirror, and a tenth current mirror. The eighth current mirror includes a MOS tube M6 and a MOS tube M8, wherein the MOS tube M6 is an input stage device of the eighth current mirror, and the eighth current mirror and the fourth current mirror share the same input stage device, and the MOS tube M8 is an output stage device of the eighth current mirror, and the MOS tube M6 and the MOS tube M8 are specifically N-type MOS tubes. The ninth current mirror includes a MOS tube M 29 、MOS tube M 30 、MOS tube M 31 And MOS tube M 32 , where MOS tube M 29 And MOS tube M 31 It is the input stage device of the ninth current mirror, MOS tube M 30 And MOS tube M 32 It is the output stage device of the ninth current mirror, MOS tube M 29 、MOS tube M 30 、MOS tube M 31 And MOS tube M 32 Specifically, it is a P-type MOS tube. The tenth current mirror includes a MOS tube M 42 And MOS tube M 43 , where MOS tube M 42 It is the input stage device of the tenth current mirror, MOS tube M 43 It is the output stage device of the tenth current mirror, MOS tube M 42 And MOS tube M 43 Specifically, it is an N-type MOS tube.

[0031] Drive current input terminal I current1 The discharge signal also controls the switch (ie, MOS tube M 21 ), the third current mirror structure (i.e., the eighth current mirror, the ninth current mirror, and the tenth current mirror) is connected to the drive current output terminal GATE. Specifically: in the eighth current mirror, the MOS tube M6 is used as an input stage device, and its drain is connected to the drive current input terminal I current1 The source is grounded, the gate is short-circuited with the drain and connected to the gate of the MOS tube M8, and the MOS tube M8 is used as an output stage device, its gate is connected to the gate of the MOS tube M6, and its drain is connected to the MOS tube M 21The source of the MOS tube M is grounded; in the discharge signal control switch, the MOS tube M 21 The gate is used to input the OFF signal output by the logic control unit inside the chip, and the drain is connected to the MOS tube M 29 The drain of the MOS tube M8 is connected to the source of the MOS tube M9. 31 As an input stage device, its source is connected to the power supply VCP, and its drain is connected to the MOS tube M 29 The source of the MOS tube M is shorted to the gate and connected to the drain. 32 The gate connection of MOS tube M 29 As an input stage device, its source is connected to MOS tube M 31 The drain of the MOS tube M 21 The drain of the MOS tube M is shorted to the gate. 30 The gate of the MOS tube M 32 As an output stage device, its gate is connected to MOS tube M 31 The gate of the MOS tube M is connected to the source of the MOS tube M. 30 The source of MOS tube M 30 As an output stage device, its gate is connected to MOS tube M 29 The gate and source of MOS tube M 32 The drain of the MOS tube M 42 In the tenth current mirror, the MOS tube M 42 As an input stage device, its drain is connected to MOS tube M 30 The drain of the MOS tube M is connected to the source and the gate is short-circuited to the drain. 43 The gate of the MOS tube M 43 As an output stage device, its gate is connected to MOS tube M 42 The gate, the drain is connected to the drive current output terminal GATE through the sampling resistor R5, and the source is connected to the SOURCE line.

[0032] It should be noted that in the ninth current mirror, the MOS tube M 31 With MOS tube M 32 A current mirror has been formed, and a MOS tube M is added on this basis 29 With MOS tube M 30 As the bias stage of the common-source common-gate current mirror, it can improve the current replication accuracy, and when the voltage difference between the power supply VCP and the SOURCE line is large, the MOS tube M 29 With MOS tube M 30 Selecting a high-voltage MOS tube can act as a protection tube.

[0033] In this embodiment, the current charging and discharging unit is provided with a charging voltage stabilizing device, whose control end is connected to the second group of current mirror structures, and whose output end is connected to the third group of current mirror structures. When charging, the charging voltage stabilizing device controls the third group of current mirror structures to be turned off according to the second group of current mirror structures to prevent the third group of current mirror structures from affecting charging stability. Specifically: the charging voltage stabilizing device includes a MOS tube M 33 And MOS tube M 44 , MOS tube M 33 It is a P-type MOS tube, while the MOS tube M 44 It is an N-type MOS tube. 33 Gate connection MOS tube M 36 The gate of the MOS tube M is connected to the source of the MOS tube M. 31 The gate of MOS tube M 44 Gate connection MOS tube M 45 The gate of the MOS tube M is connected to the source of the MOS tube M. 43 When the ON signal is input to charge the GATE line, the MOS tube M 33 conduction, thereby turning on the MOS tube M 31 The gate voltage is pulled up to VCP potential, thereby turning off the MOS tube M 31 And MOS tube M 32 , and MOS tube M 45 、M 44 conduction, thereby turning on the MOS tube M 43 The gate voltage is pulled to the SOURCE potential to turn off the MOS tube M 43 , let MOS tube M 43 It does not affect the stability of the GATE voltage when the ON signal is input to charge the GATE line.

[0034] The sampling unit includes a sampling resistor R5, a switching switch SW1 and a second operational amplifier AMP2. The sampling resistor R5 is connected in series between the output end of the current charge and discharge unit and the driving output end GATE. The positive input end and the negative input end of the second operational amplifier AMP2 are respectively connected to the two ends of the sampling resistor R5 through resistors R6, R7 and the switching switch SW1. The output end Diff_gs is connected to the voltage comparison unit, and the positive input end is connected to the avss end through resistor R8, and the negative input end is connected to the output end Diff_gs through resistor R9.

[0035] The positive input terminal and the negative input terminal of the second operational amplifier AMP2 are connected to the two ends of the sampling resistor R5 through the resistor R6, the resistor R7 and the switch SW1. Specifically: the switch SW1 is as follows: Figure 3 As shown, it includes two charging signal control switches, two discharging signal control switches and four connection terminals a, b, c, d; the two charging signal control switches are MOS tubes M47 And MOS tube M 48 The two discharge signal control switches are MOS tube M 49 And MOS tube M 50 , MOS tube M 47 、MOS tube M 48 、MOS tube M 49 And MOS tube M 50 They are all N-type MOS tubes; terminal a is connected to the right end of resistor R5, terminal b is connected to the left end of resistor R5, terminal c is connected to the negative input terminal of the second operational amplifier AMP2 via resistor R6, and terminal d is connected to the positive input terminal of the second operational amplifier AMP2 via resistor R7; MOS tube M 47 The gate is used to input the ON signal output by the logic control unit inside the chip, the drain is connected to the terminal a, the source is connected to the terminal c, and the MOS tube M 48 The gate is used to input the ON signal output by the logic control unit inside the chip, the drain is connected to the terminal b, the source is connected to the terminal d, and the MOS tube M 49 The gate is used to input the OFF signal output by the logic control unit inside the chip, the drain is connected to the terminal a, the source is connected to the terminal d, and the MOS tube M 50 The gate is used to input the OFF signal output by the logic control unit inside the chip, the drain is connected to the terminal b, and the source is connected to the terminal c. After the ON signal is input, the MOS tube M 47 And MOS tube M 48 When the MOS tube M is turned on, the connection terminal a is connected to the connection terminal c, and the connection terminal b is connected to the connection terminal d, so that the positive input terminal of the second operational amplifier AMP2 is connected to the left end of the sampling resistor R5 through the resistor R7, and the negative input terminal of the second operational amplifier AMP2 is connected to the right end of the sampling resistor R5 through the resistor R6. 49 And MOS tube M 50 When the second operational amplifier AMP2 is turned on, the connection terminals a and d are connected, and the connection terminals b and c are connected, so that the negative input terminal of the second operational amplifier AMP2 is connected to the left end of the sampling resistor R5 via the resistor R6, and the positive input terminal of the second operational amplifier AMP2 is connected to the right end of the sampling resistor R5 via the resistor R7.

[0036] The voltage comparison unit includes a first voltage comparator COMP1, a second voltage comparator COMP2, a fourth current mirror structure and a fifth current mirror structure. The fourth current mirror structure includes an eleventh current mirror, and the eleventh current mirror includes a MOS tube M2 and a MOS tube M 23 MOS tube M2 is the input stage device of the eleventh current mirror, and MOS tube M 23 It is the output stage device of the eleventh current mirror, MOS tube M2 and MOS tube M 23Specifically, it is a P-type MOS tube. The fifth group of current mirror structures includes a twelfth current mirror, and the twelfth current mirror includes a MOS tube M2 and a MOS tube M 24 , where MOS tube M2 is the input stage device of the twelfth current mirror, MOS tube M 24 It is the output stage device of the twelfth current mirror, MOS tube M2 and MOS tube M 24 Specifically, it is a P-type MOS tube.

[0037] The positive input terminal of the first voltage comparator COMP1 is connected to the output terminal Diff_gs of the second operational amplifier AMP2, the negative input terminal is connected to the reference unit through the fourth current mirror structure, and the output terminal Comp_h is connected to the calibration unit. The negative input terminal of the first voltage comparator COMP1 is connected to the reference unit through the fourth current mirror structure. Specifically: In the eleventh current mirror, the MOS tube M2 is used as an input stage device, its source is connected to the power supply VDD, the drain is grounded through the output MOS tube M1 and the ballast resistor R1, and the gate is short-circuited with the drain and connected to the MOS tube M 23 The gate of the MOS tube M 23 As an output stage device, its gate is connected to the gate of the MOS tube M2, its source is connected to the power supply VDD, and its drain is connected to the negative input terminal of the first voltage comparator COMP1 and grounded via the resistor R2.

[0038] The positive input terminal of the second voltage comparator COMP2 is connected to the output terminal Diff_gs of the operational amplifier AMP2, the negative input terminal is connected to the reference unit through the fifth current mirror structure, and the output terminal Comp_1 is connected to the calibration unit. The negative input terminal of the second voltage comparator COMP2 is connected to the reference unit through the fifth current mirror structure. Specifically: In the twelfth current mirror, the MOS tube M2 is used as an input stage device, its source is connected to the power supply VDD, the drain is grounded through the output MOS tube M1 and the ballast resistor R1, and the gate is short-circuited with the drain and connected to the MOS tube M 23 The gate of the MOS tube M 24 As an output stage device, its gate is connected to the gate of the MOS tube M2, its source is connected to the power supply VDD, and its drain is connected to the negative input terminal of the second voltage comparator COMP2 and grounded via the resistor R3.

[0039] In this embodiment, the MOS tube M 23 The width-to-length ratio of MOS tube M2 is greater than that of MOS tube M 24 The width-to-length ratio of MOS tube M2 is 23 The voltage obtained after mirroring Vref_c is higher than that of MOS tube M 24 The voltage obtained by mirroring Vref_c. When the ON signal is input for charging, the first voltage comparator COMP1 converts the output voltage V Diff_gsThe second voltage comparator COMP2 compares the output voltage V Diff_gs Comparing with the low voltage obtains a comparison result Comp_1.

[0040] The calibration unit includes a self-calibration control logic structure and a calibration code input structure. The self-calibration control logic structure is as follows Figure 4 As shown, it includes a delayer DLY1, a delayer DLY2, a D flip-flop FD1, a D flip-flop FD2, a D flip-flop FD3, a D flip-flop FD4, a D flip-flop FD5, a D flip-flop FD6, a D flip-flop FD7, a D flip-flop FD8, a D flip-flop FD9, and a D flip-flop FD 10 , exclusive OR operation logic XOR1, exclusive OR operation logic XOR2, AND operation logic AND1, AND operation logic AND2, AND operation logic AND3, AND operation logic AND4, OR operation logic OR1, OR operation logic OR2, OR operation logic OR3, OR operation logic OR4.

[0041] The input end of the delayer DLY1 is used to input the ON signal output by the logic control unit inside the chip, and the output end is used to output the ON_dly signal. If the delayer DLY1 receives the ON signal, it will output the ON_dly signal. The input end of the delayer DLY2 is used to input the OFF signal output by the logic control unit inside the chip, and the output end is used to output the OFF_dly signal. If the delayer DLY2 receives the OFF signal, it will output the OFF_dly signal.

[0042] The D input terminal of the D flip-flop FD1 is connected to the output terminal of the first voltage comparator COMP1 for inputting the Comp_h signal; the clock input terminal of the D flip-flop FD1 is connected to the output terminal of the delayer DLY1 for inputting the ON_dly signal; when the Comp_h signal and the ON_dly signal are synchronously input to the D flip-flop FD1, the D flip-flop FD1 outputs the DComp_h_on signal through its output terminal.

[0043] The D input terminal of the D flip-flop FD2 is connected to the output terminal of the second voltage comparator COMP2, and is used to input the Comp_l signal; the clock input terminal of the D flip-flop FD2 is connected to the output terminal of the delayer DLY1, and is used to input the ON_dly signal; when the Comp_l signal and the ON_dly signal are synchronously input to the D flip-flop FD2, the D flip-flop FD2 outputs the DComp_l_on signal through its output terminal.

[0044] The D input terminal of the D flip-flop FD3 is connected to the output terminal of the first voltage comparator COMP1 for inputting the Comp_h signal; the clock input terminal of the D flip-flop FD3 is connected to the output terminal of the delayer DLY2 for inputting the OFF_dly signal; when the Comp_h signal and the OFF_dly signal are synchronously input to the D flip-flop FD3, the D flip-flop FD3 outputs the DComp_h_off signal through its output terminal.

[0045] The D input terminal of the D flip-flop FD4 is connected to the output terminal of the second voltage comparator COMP2, and is used to input the Comp_l signal; the clock input terminal of the D flip-flop FD4 is connected to the output terminal of the delayer DLY2, and is used to input the OFF_dly signal; when the Comp_l signal and the OFF_dly signal are synchronously input to the D flip-flop FD4, the D flip-flop FD4 outputs the DComp_l_off signal through its output terminal.

[0046] The first input terminal of the AND operation logic AND3 is connected to the output terminal of the D flip-flop FD1 for inputting the DComp_h_on signal, and the second input terminal is connected to the output terminal of the D flip-flop FD2 for inputting the DComp_l_on signal. When the DComp_h_on signal and the DComp_l_on signal are synchronously input to the AND operation logic AND3, the AND operation logic AND3 outputs the Input_on signal through its output terminal.

[0047] The first input terminal of the OR logic OR1 is connected to the output terminal of the D flip-flop FD1 for inputting the DComp_h_on signal, and the second input terminal is connected to the output terminal of the D flip-flop FD2 for inputting the DComp_l_on signal. When the DComp_h_on signal or the DComp_l_on signal is input to the OR logic OR1, the OR logic OR1 outputs the Reset_on signal through its output terminal.

[0048] The first input terminal of the OR logic OR3 is connected to the output terminal of the OR logic AND3 for inputting the Input_on signal, and the second input terminal is connected to the output terminal of the OR logic OR1 for inputting the Reset_on signal. When the Input_on signal or the Reset_on signal is input to the OR logic OR3, the OR logic OR3 outputs 1 through its output terminal.

[0049] The first input terminal of the XOR operation logic XOR1 is connected to the output terminal of the operation logic AND3 for inputting the Input_on signal, and the second input terminal is connected to the output terminal of the OR operation logic OR1 for inputting the Reset_on signal. When the Input_on signal and the Reset_on signal are different, the XOR operation logic XOR1 outputs 1 through its output terminal.

[0050] The first input terminal of the AND operation logic AND1 is connected to the output terminal of the XOR operation logic XOR1, and the second input terminal is connected to the output terminal of the delay device DLY1, which is used to input the ON_dly signal. When the output of the XOR operation logic XOR1 is 1 and the ON_dly signal is input, the AND operation logic AND1 outputs the Triger_on signal through its output terminal.

[0051] The D input terminal of the D flip-flop FD5 is connected to the output terminal of the OR logic OR3; the clock input terminal of the D flip-flop FD5 is connected to the output terminal of the AND logic AND1, and is used to input the Triger_on signal; when the output of the OR logic OR3 is 1 and the Triger_on signal is input to the D flip-flop FD5, the D flip-flop FD5 outputs the calibration code On_cur1 through its output terminal.

[0052] The D input terminal of the D flip-flop FD6 is connected to the output terminal of the D flip-flop FD5 for inputting the calibration code On_cur1; the clock input terminal of the D flip-flop FD6 is connected to the output terminal of the AND operation logic AND1 for inputting the Triger_on signal; when the calibration code On_cur1 and the Triger_on signal are synchronously input to the D flip-flop FD6, the D flip-flop FD6 outputs the calibration code On_cur2 through its output terminal.

[0053] The D input terminal of the D flip-flop FD7 is connected to the output terminal of the D flip-flop FD6 for inputting the calibration code On_cur2; the clock input terminal of the D flip-flop FD7 is connected to the output terminal of the AND arithmetic logic AND1 for inputting the Triger_on signal; when the calibration code On_cur2 and the Triger_on signal are synchronously input to the D flip-flop FD7, the D flip-flop FD7 outputs the calibration code On_cur3 through its output terminal.

[0054] The first input terminal of the AND operation logic AND4 is connected to the output terminal of the D flip-flop FD3 for inputting the DComp_h_off signal, and the second input terminal is connected to the output terminal of the D flip-flop FD4 for inputting the DComp_l_off signal. When the DComp_h_off signal and the DComp_l_off signal are synchronously input to the AND operation logic AND4, the AND operation logic AND4 outputs the Input_off signal through its output terminal.

[0055] The first input terminal of the OR logic OR2 is connected to the output terminal of the D flip-flop FD3 for inputting the DComp_h_off signal, and the second input terminal is connected to the output terminal of the D flip-flop FD4 for inputting the DComp_l_off signal. When the DComp_h_off signal or the DComp_l_off signal is input to the OR logic OR2, the OR logic OR2 outputs the Reset_off signal through its output terminal.

[0056] The first input terminal of the OR logic OR4 is connected to the output terminal of the OR logic AND4 for inputting the Input_off signal, and the second input terminal is connected to the output terminal of the OR logic OR2 for inputting the Reset_off signal. When the Input_off signal or the Reset_off signal is input to the OR logic OR4, the OR logic OR4 outputs 1 through its output terminal.

[0057] The first input terminal of the XOR operation logic XOR2 is connected to the output terminal of the operation logic AND4 for inputting the Input_off signal, and the second input terminal is connected to the output terminal of the OR operation logic OR2 for inputting the Reset_off signal. When the Input_off signal and the Reset_off signal are different, the XOR operation logic XOR2 outputs 1 through its output terminal.

[0058] The first input terminal of the AND operation logic AND2 is connected to the output terminal of the XOR operation logic XOR2, and the second input terminal is connected to the output terminal of the delay device DLY2, which is used to input the OFF_dly signal. When the output of the XOR operation logic XOR2 is 1 and the OFF_dly signal is input, the AND operation logic AND2 outputs the Triger_off signal through its output terminal.

[0059] The D input terminal of the D flip-flop FD8 is connected to the output terminal of the OR logic OR4; the clock input terminal of the D flip-flop FD8 is connected to the output terminal of the AND logic AND2, and is used to input the Triger_off signal; when the output of the OR logic OR4 is 1 and the Triger_off signal is input to the D flip-flop FD8, the D flip-flop FD8 outputs the calibration code Off_cur1 through its output terminal.

[0060] The D input terminal of the D flip-flop FD9 is connected to the output terminal of the D flip-flop FD8 for inputting the calibration code Off_cur1; the clock input terminal of the D flip-flop FD9 is connected to the output terminal of the AND arithmetic logic AND2 for inputting the Triger_off signal; when the calibration code Off_cur1 and the Triger_off signal are synchronously input into the D flip-flop FD9, the D flip-flop FD9 outputs the calibration code Off_cur2 through its output terminal.

[0061] D Flip Flop 10 The D input terminal of the D flip-flop FD9 is connected to the output terminal of the D flip-flop FD9 for inputting the calibration code Off_cur2; 10 The clock input terminal is connected to the output terminal of the arithmetic logic AND2, and is used to input the Triger_off signal; when the calibration code Off_cur2 and the Triger_off signal are synchronously input into the D flip-flop FD 10 When the D flip-flop FD 10 The calibration code Off_cur3 is outputted via its output terminal.

[0062] The calibration code input structure includes MOS tube M7, MOS tube M9, MOS tube M 10 、MOS tube M 11 、MOS tube M 12 、MOS tube M 13 、MOS tube M 14 、MOS tube M 15 、MOS tube M 17 、MOS tube M 18 、MOS tube M 19 And MOS tube M 20 , these MOS tubes are all N-type MOS tubes. The calibration code input structure is connected in series in the current charge and discharge unit, specifically: MOS tube M 11 The gate is connected to the output of the D flip-flop FD5 to input the calibration code On_cur1, and the drain is connected to the MOS tube M 21 The source of the MOS tube M7 is connected to the drain of the MOS tube M7, the source of the MOS tube M7 is grounded, and the gate is connected to the gate of the MOS tube M6, so that the MOS tube M6 and the MOS tube M7 form a current mirror. 12 The gate is connected to the output of the D flip-flop FD6 to input the calibration code On_cur2, and the drain is connected to the MOS tube M 21 The source of the MOS tube M9 is connected to the drain of the MOS tube M9, the source of the MOS tube M9 is grounded, and the gate is connected to the gate of the MOS tube M6, so that the MOS tube M6 and the MOS tube M9 form a current mirror. 13 The gate is connected to the output of the D flip-flop FD7 to input the calibration code On_cur3, and the drain is connected to the MOS tube M 21 The source of the MOS tube M 10 The drain of MOS tube M 10 The source is grounded, and the gate is connected to the gate of the MOS tube M6, so that the MOS tube M6 and the MOS tube M 10 Form a current mirror. MOS tube M 18 The gate is connected to the output of the D flip-flop FD8 to input the calibration code Off_cur1, and the drain is connected to the MOS tube M 22The source of the MOS tube M 14 The drain of MOS tube M 14 The source is grounded, and the gate is connected to the gate of the MOS tube M6, so that the MOS tube M6 and the MOS tube M 14 Form a current mirror. MOS tube M 19 The gate is connected to the output of the D flip-flop FD9 to input the calibration code Off_cur2, and the drain is connected to the MOS tube M 22 The source of the MOS tube M 15 The drain of MOS tube M 15 The source is grounded, and the gate is connected to the gate of the MOS tube M6, so that the MOS tube M6 and the MOS tube M 15 Form a current mirror. MOS tube M 20 Gate connection D flip-flop FD 10 The output terminal of the MOS tube M is connected to the input calibration code Off_cur3. 22 The source of the MOS tube M 17 The drain of MOS tube M 17 The source is grounded, and the gate is connected to the gate of the MOS tube M6, so that the MOS tube M6 and the MOS tube M 17 A current mirror is formed.

[0063] As can be seen from the above, the input end of the self-calibration control logic structure is connected to the output end of the first voltage comparator COMP1 and the output end of the second voltage comparator COMP2 respectively. Specifically, the output end of the first voltage comparator COMP1 is connected through the D input end of the D flip-flop FD1, the output end of the second voltage comparator COMP2 is connected through the D input end of the D flip-flop FD2, the output end of the first voltage comparator COMP1 is connected through the D input end of the D flip-flop FD3, and the output end of the second voltage comparator COMP2 is connected through the D input end of the D flip-flop FD4. In this way, when the ON signal is input for charging, the self-calibration control logic structure uses the first The comparison result Comp_h output by the first voltage comparator COMP1 and the comparison result Comp_l output by the second voltage comparator COMP2 are logically operated, and the outputs of the D flip-flops FD5, FD6, and FD7 are updated to obtain the calibration codes On_cur1, On_cur2, and On_cur3; when the OFF signal is input for charging, the self-calibration control logic structure uses the comparison result Comp_h output by the first voltage comparator COMP1 and the comparison result Comp_l output by the second voltage comparator COMP2 to perform a logical operation, and updates the D flip-flops FD8, FD9, and FD10. 10The output of the self-calibration control logic structure is connected to the calibration code input structure, specifically, the output of the D flip-flop FD5 is connected to the MOS tube M 11 The gate of the D flip-flop FD6 is connected to the MOS tube M 12 The gate of the D flip-flop FD7 is connected to the MOS tube M 13 The gate of the D flip-flop FD8 is connected to the MOS tube M 18 The gate of the D flip-flop FD9 is connected to the MOS tube M 19 The gate of the D flip-flop FD 10 The output end is connected to the MOS tube M 20 gate, so that when the ON signal is input for charging, the self-calibration control logic structure inputs the calibration codes On cur1, On cur2, and On_cur3 to the current charge and discharge unit through the calibration code input structure, and uses the calibration code in the next switching cycle, and iterates back and forth for multiple times to calibrate the charging current until the calibrated charging current is close to the preset value, and when the OFF signal is input for discharging, the self-calibration control logic structure inputs the calibration codes Off_cur1, Off_cur2, and Off_cur3 to the current charge and discharge unit through the calibration code input structure, and uses the calibration code in the next switching cycle, and iterates back and forth for multiple times to calibrate the discharge current until the calibrated discharge current is close to the preset value, thereby realizing the calibration of the charging and discharging current.

[0064] In the sampling unit, resistors R6, R7, R8, R9 and the second operational amplifier AMP2 form a subtraction circuit. The output voltage V Diff_gs The expression is:

[0065]

[0066] Wherein, Vinp is the voltage at the left end of the resistor R7, Vinn is the voltage at the left end of the resistor R6, and VOS is the input offset voltage of the second operational amplifier AMP2.

[0067] When R7 / R9=R6 / R8, the output voltage V Diff_gs The expression is:

[0068]

[0069] In the current charge and discharge unit, the calibration accuracy of the charge and discharge current depends on the comparison result of the first voltage comparator COMP1 and the second voltage comparator COMP2, and the relationship is:

[0070] Charging moment: Vinp = I ch ×R5(3);

[0071] Discharge instant: Vinn = I disch ×R5(4);

[0072] Where, Vinp is the voltage at the left end of resistor R7, Vinn is the voltage at the left end of resistor R6, and I ch is the charging current, I disch is the discharge current.

[0073] The negative input voltage VR2 of the first voltage comparator COMP1 is:

[0074]

[0075] Among them, W23 is MOS tube M 23 The channel width (width), L23 is the MOS tube M 23 : W2 is the channel length (length) of the MOS tube M2; W2 is the channel width (width) of the MOS tube M2, and L2 is the channel length (length) of the MOS tube M2.

[0076] The negative input voltage VR3 of the second voltage comparator COMP2 is:

[0077]

[0078] Among them, W24 is MOS tube M 24 The channel width (width), L23 is the MOS tube M 24 : W2 is the channel length (length) of the MOS tube M2; W2 is the channel width (width) of the MOS tube M2, and L2 is the channel length (length) of the MOS tube M2.

[0079] It can be seen intuitively from formulas (2), (3), (4), (5), and (6) that the main factors affecting the comparison results of the first voltage comparator COMP1 and the second voltage comparator COMP2 are the input offset voltage VOS of the second operational amplifier AMP2, the resistor R5, and the variation range of the bandgap reference voltage Vref. Usually, a reasonable The value controls the influence of the input offset voltage VOS of the second operational amplifier AMP2 on the accuracy within ±1%; and in the resistor manufacturing process, the accuracy error of the sampling resistor R5 can be guaranteed to be ±1%; and the bandgap reference voltage Vref is generated by the bandgap reference module, and the bandgap reference module can ensure the accuracy error of the bandgap reference voltage Vref generated by it within ±1% from the perspective of structural design. In summary, the self-calibration control logic structure generates calibration codes On_cur1, On_cur2, On_cur3, Off_cur1, Off_cur2, Off_cur3 according to the comparison results of the first voltage comparator COMP1 and the second voltage comparator COMP2, and then uses these calibration codes to calibrate the charge and discharge current to achieve a calibration accuracy error within ±3%, which is higher than the traditional pre-drive circuit.

[0080] The above is only an implementation method of the invention, and does not limit the scope of patent protection. Those skilled in the art can make non-substantial changes or substitutions based on the invention, which still fall within the scope of patent protection.

Claims

1. A pre-driving circuit structure for self-calibration of charge and discharge current, characterized in that: It includes a driving current input terminal, a driving current output terminal, a reference unit, a current charging and discharging unit, a sampling unit, a voltage comparison unit and a calibration unit, wherein: The reference unit includes a first operational amplifier, an output MOS tube, a ballast resistor and a first group of current mirror structures, wherein the positive input terminal of the first operational amplifier is connected to the bandgap reference module, the negative input terminal is grounded via the ballast resistor, and the output terminal is connected to the output terminal of the current charge and discharge unit via the output MOS tube and the first group of current mirror structures; The current charge and discharge unit includes a charge signal control switch, a discharge signal control switch, a second group of current mirror structures and a third group of current mirror structures, the drive current input end is connected to the drive current output end through the charge signal control switch and the second group of current mirror structures, and is connected to the drive current output end through the discharge signal control switch and the third group of current mirror discharge structures; The sampling unit includes a sampling resistor, a switching switch and a second operational amplifier, wherein the sampling resistor is connected in series between the output end of the current charging and discharging unit and the driving output end, the positive input end and the negative input end of the second operational amplifier are respectively connected to the two ends of the sampling resistor via the switching switch, and the output end is connected to the voltage comparison unit; The voltage comparison unit includes a first voltage comparator, a second voltage comparator, a fourth current mirror structure and a fifth current mirror structure, wherein the positive input terminal of the first voltage comparator is connected to the output terminal of the second operational amplifier, the negative input terminal is connected to the reference unit through the fourth current mirror structure, and the output terminal is connected to the calibration unit, the positive input terminal of the second voltage comparator is connected to the output terminal of the operational amplifier, the negative input terminal is connected to the reference unit through the fifth current mirror structure, and the output terminal is connected to the calibration unit; The calibration unit includes a self-calibration control logic structure and a calibration code input structure. The input end of the self-calibration control logic structure is respectively connected to the output end of the first voltage comparator and the output end of the second voltage comparator. The output end of the self-calibration control logic structure is connected to the calibration code input structure. The calibration code input structure is connected in series in the current charge and discharge unit. The self-calibration control logic structure generates a calibration code according to the comparison result between the first voltage comparator and the second voltage comparator. The calibration code is input into the current charge and discharge unit through the calibration code input structure to calibrate the charge and discharge current.

2. The pre-driving circuit structure for self-calibration of charge and discharge current according to claim 1 is characterized in that: The output MOS tube is an N-type MOS tube, whose gate is connected to the output end of the first operational amplifier, whose source is grounded via a ballast resistor, and whose drain is connected to the output end of the current charge and discharge unit via a first set of current mirror structures.

3. The pre-driving circuit structure for self-calibration of charge and discharge current according to claim 1 is characterized in that: The current charge and discharge unit includes a clamping circuit, and the output end of the first operational amplifier is connected to the output end of the current charge and discharge unit via the output MOS tube and the first group of current mirror structures. Specifically, the output end of the first operational amplifier is first connected to the output end of the current charge and discharge unit via the output MOS tube and the first group of current mirror structures, and then via the clamping circuit.

4. The pre-driving circuit structure for self-calibration of charge and discharge current according to claim 1 is characterized in that: The current charge and discharge unit is provided with a charging voltage stabilizing device, a control end of which is connected to the second group of current mirror structures, and an output end is connected to the third group of current mirror structures. During charging, the charging voltage stabilizing device controls the third group of current mirror structures to be turned off according to the second group of current mirror structures to prevent the third group of current mirror structures from affecting charging stability.

5. The pre-driving circuit structure for self-calibration of charge and discharge current according to claim 1 is characterized in that: The width-to-length ratio of the output stage devices to the input stage devices of the fourth group of current mirror structures is greater than the width-to-length ratio of the output stage devices to the input stage devices of the fifth group of current mirror structures.

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