NVMe SSD command timeout debugging method and device and medium

Abstract

The invention relates to the field of storage, in particular to an NVMe SSD command timeout debugging method and device and a medium. According to the method, interaction between the Host and the SSD is carried out based on an Aport command and a Get Log Page command in an NVMe protocol, the Aport command is a management command issued to the SSD by the host according to a timestamp of the Aport command when detecting that the command is overtime, and the command defines an SQID and a CID of the overtime command; and command timeout information is obtained through a Get Log Page command and is used for analyzing a command timeout reason. Through the method described by the invention, the timeout state of the command can be accurately analyzed, and after the command is timeout, the SSD command processing site is saved in time, so that the command timeout can be quickly debugged.

Description

Technical Field

[0001] The present invention relates to the field of storage, and in particular to an NVMe SSD command timeout debugging method, device and medium. Background Art

[0002] NVMe SSD is a solid state drive (SSD) that complies with the Non-Volatile Memory Express host controller interface specification. SSD consists of a controller and a memory. An excellent NVMe SSD controller can make full use of the low latency and parallelism of the PCIE channel, greatly improve the read and write performance of the SSD at a controllable storage cost, reduce the high latency caused by the AHCI interface, and completely unleash the ultimate performance of SSDs in the STAT era.

[0003] In the interaction between NVMe SSD and Host, the issuance and completion of IO commands are the most important links in the interaction. Ensuring the correct and efficient completion of IO commands is the goal pursued by every NVMe SSD manufacturer. However, various IO problems will inevitably occur during user use, such as IO timeout. After the IO timeout problem occurs, the host can only take limited measures, and the running status of the timeout command on the SSD side is unclear, and only a simple timestamp is recorded to the timeout. Therefore, it is impossible to take necessary measures for the timeout command on the host side, and it is impossible to obtain detailed information and execution status of the command.

[0004] Therefore, it is particularly important to invent a method for debugging timeout commands on the NVMe SSD side. Summary of the invention

[0005] In view of the defects of the prior art, the present invention provides an NVMe SSD command timeout debugging method, device and medium, which can record the timeout problems occurring in the IO process, save logs and export logs, which can greatly shorten the debugging cycle after the command timeout.

[0006] In order to solve the technical problem, the technical solution adopted by the present invention is: an NVMe SSD command timeout debugging method, comprising the following steps: S01. The host determines that the IO has timed out and sends an Abort command to the NVMe SSD. The Abort command is a management command sent by the host to the NVMe SSD based on its own timestamp when a command timeout is detected. The Abort command specifies the SQID and CID of the timed-out command. S02, the NVMe SSD receives the Abort command and checks the legality of the Abort command. If it is legal, it takes out the SQID and CID in the Abort command; S03, the NVMe SSD determines whether the SQID is an IQ SQ. If so, it traverses the IO command cache until an IO command with the same SQID and CID as those in the Abort command is found; S04, the NVMe SSD applies for a memory, and copies the IO command found in step S03 to the applied memory; S05, the NVMe SSD searches for relevant information of the IO command found in step S03, and copies the found relevant information to the requested memory; S06, the host sends a Get Log Page command to obtain an IO command timeout result; S07, the NVMe SSD receives the Get Log Page command and starts DMA to upload the timeout command related information in the memory to the host; S08. The host parses the IO timeout command information content and performs debugging.

[0007] Furthermore, the method also includes log acquisition and analysis, the specific process is as follows: S21, the host sends a Get Log Page command to obtain timeout command information; S22, NVMe SSD starts DMA to upload the timeout command and related information in the local memory to the host; S23. Analyze the log on the host side and draw conclusions.

[0008] Furthermore, the relevant information of the IO command includes the physical address of the command, the L2P table entry, the command execution status, and the step-by-step time consumption of the command.

[0009] Furthermore, the NVMe SSD finds out relevant information of the command through the starting LBA and LBA offset fields of the IO command.

[0010] Furthermore, the NVMe SSD applies for a local memory to store IO commands and related information.

[0011] The present invention also discloses an NVMe SSD command timeout debugging device, comprising a processor and a memory storing program instructions, wherein the processor is configured to execute the NVMe SSD command timeout debugging method as described above when running the program instructions.

[0012] The present invention also discloses a storage medium storing program instructions, which execute the above-mentioned NVMe SSD command timeout debugging method when running.

[0013] Beneficial effects of the present invention: The present invention performs interaction between the Host and the SSD based on the Abort command and the Get Log Page command in the NVMe protocol. The Abort command is a management command issued by the host to the SSD based on its own timestamp when a command timeout is detected. The command clarifies the SQID and CID of the timed-out command; the command timeout information is obtained through the Get Log Page command to analyze the reason for the command timeout. The method described in the present invention can accurately analyze the timeout status of the command, and save the SSD command processing site in time after a command timeout, so as to quickly debug the command timeout. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is the Abort command processing flow chart; Figure 2 Get the analysis flow chart for the log. DETAILED DESCRIPTION

[0015] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0016] The terms "first", "second", etc. in the embodiments of the present disclosure are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so as to describe the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0017] Unless otherwise stated, the term "plurality" means two or more.

[0018] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.

[0019] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0020] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.

[0021] Example 1 This embodiment discloses a NVMe SSD command timeout debugging method, which includes two parts: Abort command processing and log acquisition and analysis. Figure 1 As shown in the figure, the Abort command processing flow is as follows: S01. The host determines that the IO has timed out and sends an Abort command to the NVMe SSD. The Abort command is a management command sent by the host to the NVMe SSD based on its own timestamp when a command timeout is detected. The Abort command specifies the SQID and CID of the timed-out command. S02, the NVMe SSD receives the Abort command and checks the legitimacy of the Abort command. If it is legal, the SQID and CID in the Abort command are taken out. In this embodiment, the legitimacy of the Abort command is judged by the legitimacy of the SQID and CID values ​​in the Abort command. If the SQID and CID values ​​in the Abort command are legal, the SQID and CID are used in the next step. If they are illegal, the process is terminated. S03, the NVMe SSD determines whether the SQID is an IQ SQ. If so, the IO command cache is traversed until an IO command with the same SQID and CID as those in the Abort command is found. In this embodiment, whether the SQID is 0 is used to determine whether it is an IQ SQ. If the SQID is not 0, the SQID is an IO SQ, and the IO command cache is traversed. S04, the NVMe SSD applies for a memory, and copies the IO command found in step S03 to the applied memory; S05, the NVMe SSD searches for relevant information of the IO command found in step S03, and copies the found relevant information to the requested memory; S06, the host sends a Get Log Page command to obtain an IO command timeout result; S07, the NVMe SSD receives the Get Log Page command and starts DMA to upload the timeout command related information in the memory to the host; S08. The host parses the IO timeout command information content and performs debugging.

[0022] like Figure 2 As shown in the figure, the log acquisition and analysis process is as follows: S21, the host sends a Get Log Page command to obtain timeout command information; S22, NVMe SSD starts DMA to upload the timeout command and related information in the local memory to the host; S23. Analyze the log on the host side and draw conclusions.

[0023] In this embodiment, the relevant information of the IO command includes the physical address of the command, the L2P table entry, the command execution status, and the command step-by-step time. The NVMe SSD finds the relevant information of the command through the starting LBA and LBA offset fields of the IO command.

[0024] In this embodiment, the NVMe SSD applies for a local memory to store the IO command and related information.

[0025] In this embodiment, SQID indicates which queue the Aborted NVMe command comes from, CID indicates the Command ID of the Aborted command, and the Get Log Page command is a command to get the log page. LBA indicates a logical block address. DMA stands for direct memory access, which is a data transfer technology that exchanges data directly with the system memory without going through the CPU.

[0026] Example 2 This embodiment discloses an NVMe SSD command timeout debugging device, including a processor and a memory. Optionally, the device may also include a communication interface and a bus. The processor, the communication interface, and the memory may communicate with each other through the bus. The communication interface may be used for information transmission. The processor may call the logic instructions in the memory 301 to execute the NVMe SSD command timeout debugging method of the above embodiment.

[0027] In addition, the logic instructions in the above-mentioned memory can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product.

[0028] The memory, as a computer-readable storage medium, can be used to store software programs and computer executable programs, such as program instructions / modules corresponding to the method in the embodiment of the present disclosure. The processor executes functional applications and data processing by running the program instructions / modules stored in the memory, that is, implementing the NVMe SSD command timeout debugging method in the above embodiment.

[0029] The memory may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required for at least one function; the data storage area may store data created according to the use of the terminal device, etc. In addition, the memory 3 may include a high-speed random access memory and may also include a non-volatile memory.

[0030] Example 3 An embodiment of the present disclosure provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are configured to execute the above-mentioned NVMe SSD command timeout debugging method.

[0031] The computer-readable storage medium mentioned above may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.

[0032] The technical solution of the embodiment of the present disclosure can be embodied in the form of a software product, which is stored in a storage medium and includes one or more instructions for enabling a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the embodiment of the present disclosure. The aforementioned storage medium may be a non-transient storage medium, including: a USB flash drive, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a disk or an optical disk, and other media that can store program codes, or a transient storage medium.

[0033] The above description and the accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent only possible changes. Unless explicitly required, separate components and functions are optional, and the order of operation may vary. The parts and features of some embodiments may be included in or replace the parts and features of other embodiments. Moreover, the words used in this application are only used to describe the embodiments and are not used to limit the scope of protection. As used in the description in the text, unless the context clearly indicates, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of one or more associated listings. In addition, when used in this application, the term "comprise" and its variants "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, the elements defined by the sentence "including one..." do not exclude the presence of other identical elements in the process, method or device including the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.

[0034] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software may depend on the specific application and design constraints of the technical solution. The technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of the present disclosure. The technicians may clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here.

Claims

1. A NVMe SSD command timeout debugging method, characterized in that: The following steps are involved: S01. The host determines that the IO has timed out and sends an Abort command to the NVMe SSD. The Abort command is a management command sent by the host to the NVMe SSD based on its own timestamp when a command timeout is detected. The Abort command specifies the SQID and CID of the timed-out command. S02, the NVMe SSD receives the Abort command and checks the legality of the Abort command. If it is legal, it takes out the SQID and CID in the Abort command; S03, the NVMe SSD determines whether the SQID is an IQ SQ. If so, it traverses the IO command cache until an IO command with the same SQID and CID as those in the Abort command is found; S04, the NVMe SSD applies for a memory, and copies the IO command found in step S03 to the applied memory; S05, the NVMe SSD searches for relevant information of the IO command found in step S03, and copies the found relevant information to the requested memory; S06, the host sends a Get Log Page command to obtain an IO command timeout result; S07, the NVMe SSD receives the Get Log Page command and starts DMA to upload the timeout command related information in the memory to the host; S08. The host parses the IO timeout command information content and performs debugging.

2. The NVMe SSD command timeout debugging method according to claim 1, characterized in that: This method also includes log acquisition analysis, the specific process is as follows: S21, the host sends a Get Log Page command to obtain timeout command information; S22, NVMe SSD starts DMA to upload the timeout command and related information in the local memory to the host; S23. Analyze the log on the host side and draw conclusions.

3. The NVMe SSD command timeout debugging method according to claim 1 or 2, characterized in that: The relevant information of the IO command includes the physical address of the command, L2P table entry, command execution status, and command step-by-step time.

4. The NVMe SSD command timeout debugging method according to claim 3, characterized in that: NVMe SSD finds relevant information of the command through the starting LBA and LBA offset fields of the IO command.

5. The NVMe SSD command timeout debugging method according to claim 1, characterized in that: NVMe SSD applies for a local memory to store IO commands and related information.

6. An NVMe SSD command timeout debugging device, comprising a processor and a memory storing program instructions, characterized in that: The processor is configured to execute the NVMe SSD command timeout debugging method according to any one of claims 1 to 5 when running the program instructions.

7. A storage medium storing program instructions, characterized in that: When the program instructions are run, they execute the NVMe SSD command timeout debugging method as described in any one of claims 1 to 5.

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