Methods for locating faults in complex RiscV core operation situations

Abstract

The present invention provides a method for locating faults in the complex operation of RiscV core, including: step 1, preparing a database containing chip hardware design and building a hardware simulation working environment; step 2, making firmware for the chip containing RiscV core; step 3, downloading the database and firmware to an FPGA board card, generating a simulated chip containing RiscV core; step 4, configuring a trigger; step 5, after the firmware is loaded into the chip containing RiscV core simulated in step 3, it starts to execute, starts the trigger to capture the hardware signal waveform, saves the hardware signal waveform and analyzes it. The present invention can quickly find the waveform position corresponding to the fault and the corresponding fault position in the source file by means of the value of mscratch in the waveform, and conveniently traces back by comparing the waveform and the source file, so as to facilitate rapid analysis of the cause of the fault.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a method for locating faults in a RiscV core complex operation situation. Background Art

[0002] RiscV is a widely used open source instruction set architecture. When it comes to the specific application of RiscV core (RiscV is an open source instruction set architecture based on the principle of reduced instruction set computers; RISC-V core is a processing unit implemented based on this instruction set architecture), all instructions may be RiscV standard instructions, or most instructions may be RiscV standard instructions, while there are also some instructions specially customized by users. The instruction execution logic of the specific hardware design of RiscV core can be initially verified by software simulation, and then chip-level verification can be performed in a hardware simulation environment. The latter generally uses FPGA boards to simulate the chip of RiscV core and run some executable codes of RiscV core to verify the correctness of RiscVcore instructions in various complex situations, especially to verify the correctness of user-customized instructions, which is of great significance for the tape-out and production of RiscVcore chips.

[0003] There are many ways to verify the correctness of RiscV core, such as running related instructions and checking the execution results, setting breakpoints and monitoring related signals, setting trigger mechanisms to capture hardware signal waveforms to check the signal status in the waveform, etc. For more complex execution code scenarios, the debugging and verification of RiscV core is also more complicated. Summary of the invention

[0004] Purpose of the invention: The technical problem to be solved by the present invention is to address the deficiencies of the prior art and propose a method for locating faults in the complex operation of the RiscV core, including the following steps:

[0005] Step 1: Prepare a database containing chip hardware design and build a hardware simulation working environment;

[0006] Step 2, adding debugging information to the RiscV core source code, compiling it into a RiscV core executable file, and encapsulating the executable file and the boot code loader used to load the executable file to make firmware for the chip containing the RiscV core;

[0007] Step 3, downloading the database containing the chip hardware design and the firmware to the FPGA board on the host side to generate a simulated chip containing the RiscV core;

[0008] Step 4, configure the trigger;

[0009] Step 5, the firmware is loaded into the chip containing the RiscV core simulated in step 3 and then starts to execute, starts a trigger to capture the hardware signal waveform, saves the hardware signal waveform and performs analysis.

[0010] Furthermore, in step 1, the database contains a binary file for burning the chip hardware design into the FPGA board.

[0011] Furthermore, step 2 includes: obtaining a code file for testing the RiscV core (generally written by the user), inserting a code for verifying the correctness of execution into the code file, wherein the code for verifying the correctness of execution is used to observe the execution state and is also used to trigger the capture of hardware signal waveforms; after the code for verifying the correctness of execution is inserted, cross-compiling it into a RiscV executable file, and encapsulating it into firmware with the boot code loader that boots the RiscV core.

[0012] Furthermore, in step 2, the RiscV core executable file includes RiscV core instructions, and the RiscV core instructions are machine codes that can be read and executed by RiscV core.

[0013] Furthermore, step 4 includes: selecting a special register mscratch of the RiscV core, configuring a special value (a value written according to a certain rule, which generally does not appear) as a trigger condition, and generating a trigger.

[0014] Further, in step 5, the firmware is loaded into the chip containing the RiscV core simulated in step 3 and then starts to execute, which specifically includes:

[0015] After the RiscV core in the simulated chip containing the RiscV core is initialized by the boot code loader, the RiscV core instructions are executed from the entry address; when debugging information is added to the RiscV core source code, an interrupt function is added, and the value of the interrupt vector register is set to the entry address of the interrupt function. When an abnormal situation occurs during the execution process, the RiscV core will enter the interrupt function; initialize the time interrupt, configure the timeout time to be the value of the current time plus the delay time, and then make the time interrupt effective; the source file code corresponding to the RiscV core executable file is divided into more than two code segments, and the timeout time must be reconfigured to be the value of the current time plus the delay time after each code segment, and ensure that the execution time of each code segment is less than the configured time interval for generating the time interrupt. If each code segment is executed normally, the time interrupt will not be triggered;

[0016] After each code segment, the execution is judged to be correct according to the function call return value or register status value. If an execution error is found, the value of the special register mscratch of RiscV is set to a special value (such as 0x12345678abcdef, which is a value that does not generally appear), and then enters an infinite loop waiting. The special value will trigger the capture of the hardware signal waveform, and the saved hardware signal waveform is used to analyze the cause of the fault;

[0017] If a certain instruction of a certain code segment is stuck at a certain position, a time interrupt will be triggered when the time reaches the timeout period, and RiscV core will enter the interrupt processing code segment; in the interrupt processing code segment, the value of RiscV's special register mscratch is set to a special value (such as 0x12345678abcdef), and then enter an infinite loop waiting. The special value will trigger the capture of the hardware signal waveform, and the saved hardware signal waveform is used to analyze the cause of the fault;

[0018] If the RiscV core instruction execution is abnormal (for example, the Risc V core reads an unrecognizable or unexecutable instruction) and triggers an interrupt, in the interrupt processing code segment, the value of the RiscV special register mscratch is set to a special value, and then an infinite loop wait is entered. The special value will trigger the capture of the hardware signal waveform, and the saved hardware signal waveform is used to analyze the cause of the fault;

[0019] If each code segment is executed correctly, the time interrupt function is disabled when the code is executed to the end, and an infinite loop wait is entered.

[0020] Furthermore, in step 5, when the value of the special register mscratch is used to monitor the internal state (the internal state includes: the corresponding progress in the source code when the RiscV core is running, the intermediate results of the execution and the source code variables, etc.), the value of the special register mscratch is uniformly encoded, and the encoding is divided into two categories. The first category is the encoding used to record the execution state, and the second category is the encoding used to trigger the capture of the hardware signal waveform; the first category of encoding is used to record various states or variables of the execution process and the execution line number into the special register mscratch, and the second category of encoding is used to configure special values ​​to trigger the capture of the hardware signal waveform when an execution error occurs.

[0021] Furthermore, in step 5, the first category of codes is divided into three subcategories, namely, the first code, the second code, and the third code;

[0022] In the first encoding, the highest 1 to 2 bytes are used to identify the current encoding method (such as 0xfedc), the last 1 to 3 bytes are used to record the line number, and the middle 3 to 6 bytes are used to record the execution progress, intermediate results or variables;

[0023] In the second encoding, a continuous serial method is used to record each state or variable in the special register mscratch in sequence. After the recording is completed, the last record is used to mark the position of the current record; the front part of the last record uses a special value (such as 0xedcba9876543, which is a value that does not generally appear and should be distinguished from the special value that triggers the capture waveform) to mark that the current is the last record, and the following 1~2 bytes are used to record the current line number;

[0024] In the third encoding, each state or variable is split into two or more parts, and then stored in the special register mscratch in the order of splitting from the first part to the last part; after all parts of all states or variables are stored, the part before the last record uses a special value (such as 0xdcba98765432, which is a value that does not generally appear and should be distinguished from the special value that triggers the capture of the waveform) to mark that the current record is the last record, and the 1-2 bytes after the last record are used to record the current line number;

[0025] For situations where the state value or variable value to be recorded is relatively small (generally speaking: the mscratch register is 64 bits, after removing the bytes storing the line number and the characteristic value, the remaining bits can store two or more state values), the first code is used to record the execution state;

[0026] When the size of the state value or variable value is moderate (generally speaking: the mscratch register is 64 bits, after removing the bytes storing the line number and the characteristic value, the remaining bits are only enough to store one state value), the second encoding is used to record the execution state;

[0027] When the state value or variable value to be recorded is too large (generally speaking: the mscratch register is 64 bits, and after removing the bytes storing the line number and the characteristic value, the remaining bits cannot store a state value), the third encoding is used to record the execution state.

[0028] Further, in step 5, if the RiscV core test case code runs correctly, after the RiscV core test case code in the firmware is executed, no hardware signal waveform will be captured;

[0029] If an error occurs during the execution of the RiscV core test case code, the trigger will cause the hardware signal waveform to be captured and saved. The errors include execution jam, return value error, and instruction execution exception. The saved hardware signal waveform is used to locate the specific cause of the fault, and then the position of the faulty code segment is located based on the value of the RiscV core register and the value of the selected special register mscratch.

[0030] Furthermore, the present invention also provides an electronic device, including a processor and a memory, wherein the memory stores program code, and when the program code is executed by the processor, the processor executes the steps of the described method.

[0031] In this method, several debugging and positioning codes are inserted into the C language source code of the test case. These debugging codes innovatively use the special register mscratch of RiscV core to record the process and status of RiscV core execution, and when an execution error occurs, a special coding value is written to the special register mscratch to trigger the capture of hardware signal waveforms. Therefore, in the captured hardware signal waveform, the process and status values ​​recorded in the special register mscratch are used as clues to quickly locate the C source code and faulty instructions where the fault is located by comparing the C language source code, RiscV machine instructions and hardware signal waveforms, so that hardware engineers can repair the bug of RiscV core.

[0032] The present invention has the following beneficial effects: when verifying RiscV core, the present invention can monitor the value of the special register mscratch, and can quickly and intuitively know the approximate position of the instruction currently executed by RiscVcore in the source code file, the intermediate result corresponding to the RiscV source file, and the value of the source code variable by maintaining the original execution speed (the execution speed of a small number of instructions written to the special register mscratch is very fast) and the chip operation logic related to the speed while maintaining the original execution speed. When verifying any type of fault in RiscV core, the special value of the special register mscratch can be used as the same trigger condition to capture the hardware signal waveform, so that it is convenient to insert a unified debugging code into various possible fault points in the source code; when analyzing the captured hardware signal waveform, the waveform position corresponding to the fault and the corresponding fault position in the source file can be quickly found by means of the value of mscratch in the waveform, and it is convenient to trace back by comparing the waveform and the source file, so as to facilitate the rapid analysis of the cause of the fault. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments, and the above and / or other advantages of the present invention will become more clear.

[0034] Figure 1 It is a schematic diagram of the working environment of monitoring signals and capturing waveforms of the present invention.

[0035] Figure 2 It is a schematic diagram of the operation steps of verifying RiscV core of the present invention.

[0036] Figure 3 It is a schematic diagram of the operation mechanism of the present invention for verifying the correctness of the complex operation of RiscV core.

[0037] Figure 4 It is a schematic diagram of the encoding method of the numerical value written into the special register mscratch of the RiscV core in the present invention. DETAILED DESCRIPTION

[0038] The present invention provides a method for locating faults in a RiscV core under complex operation conditions. This embodiment is based on the architecture of the RiscV instruction set. In a simulated RiscV chip, the RiscV core of the simulated chip is allowed to execute a series of instructions for complex situations in a RiscV privileged mode, while monitoring the operating status of the RiscV core, verifying the correctness of the RiscV core operation, and capturing hardware signal waveforms when an error occurs to analyze the cause of the error.

[0039] The working environment relied on by this embodiment needs to have the following functions:

[0040] 1. Ability to download the database file and RiscV executable file of the chip design containing RiscV core from the host to the FPGA hardware board to generate a simulated chip containing RiscV core.

[0041] 2. Ability to monitor the real-time values ​​of registers in the RiscV core of the simulated chip on the host.

[0042] 3. Ability to set the value of the monitored register on the host as a trigger condition to capture the hardware signal waveform in the analog chip.

[0043] The components of the hardware simulation environment related to the present invention are listed in Table 1 below:

[0044] Table 1

[0045] Component Name Component Function Host The host connected to the FPGA board. Users can download the database containing chip design and the executable files running on the RiscV core on this host, and can also monitor and capture signal waveforms of the chip simulated by the FPGA board on this host. Download the interactive interface of the hardware design database The host can be used to download the specified chip hardware design database and the interactive interface of the executable file running on the RiscV core. Monitoring interface Interface for monitoring hardware signals and capturing signal waveforms. FPGA Board The hardware design database will be written into the FPGA board, and then the chip corresponding to the hardware design database will be simulated. The simulated chip can run the RiscV executable file downloaded together with the hardware design database. Hardware emulated chip After the database corresponding to the chip's hardware design is written into the FPGA board, the simulated chip has a much lower operating frequency and much worse performance than the real chip, but the functions are exactly the same. RiscVcore The RiscV core contained in the simulated chip is the core for parsing and executing RiscV instructions. Special register mscratch A special register of the simulated RiscV core that is not used in the functional code of the test case. When the test case uses the instruction logic in machine mode and does not involve context information, the mscratch register is idle and can be used as a special register. If the test case uses mscratch, select another free special register. For general instruction logic verification of RiscV, the mscratch register is sufficient. Analog chip interaction interface The interface is used to observe and control the interactive state of the analog chip, including multiple sub-interfaces for monitoring signals, creating triggers, and capturing waveforms. Subinterface for monitoring signals The sub-interface of the analog chip interaction interface can monitor the values ​​of various hardware registers in the analog chip, including the RiscV core registers. Create a subinterface for the trigger The sub-interface of the analog chip interaction interface can set the trigger for capturing waveforms according to various conditions. For example, a certain value of a hardware register can be used as a trigger condition. Sub-interface for capturing waveforms The sub-interface of the analog chip interaction interface can capture waveforms according to the set trigger. When the trigger condition corresponding to the trigger takes effect, the waveform of the hardware signal in the analog chip within the two time periods before and after the set trigger moment is captured according to the time length requirements.

[0046] Among these components, the host controls the FPGA board by downloading the interactive interface of the hardware design database, and generates a simulated chip containing the RiscV core by writing the FPGA board (such as Figure 1 As shown in the figure). In terms of software, the host monitors the execution of RiscV core through the three sub-interfaces of the analog chip interaction interface: the sub-interface for monitoring signals, the sub-interface for creating triggers, and the sub-interface for capturing waveforms. When a fault occurs, the host automatically captures the waveform according to the configured triggers.

[0047] The method of this embodiment specifically includes the following contents:

[0048] like Figure 2 As shown, when verifying the RiscV core, you must first follow Figure 1 Build a working environment for hardware simulation to ensure the hardware control path between the host and the FPGA board. Then make the firmware for the chip. The hardware design database (including the binary file used to burn the chip hardware design to the FPGA board) that matches the hardware design of the chip to be verified and the hardware simulation environment also needs to be prepared in advance. Then establish communication with the FPGA board on the host side, and download the hardware design database and firmware of the chip hardware design to the FPGA board. After the download is complete, open the simulated chip interaction interface.

[0049] In the monitoring sub-interface of the simulated chip interaction interface, select the signal to be monitored to monitor the value of the RiscVcore register in the chip and observe the execution of the RiscV core at any time. When the RiscV core test case code in the firmware is executed (the value of the special register mscratch can be used to indicate that the code has been executed), check whether the final value of the RiscVcore register is correct to determine whether the test case has been executed and is running correctly.

[0050] In the sub-interface of creating triggers in the simulated chip interaction interface, select the special register mscratch of the RiscV core, configure the special value as the trigger condition, and generate the trigger. In the sub-interface of capturing waveforms in the simulated chip interaction interface, use the newly created trigger to capture the waveform. Since special values ​​generally only appear when there is a running error, if the RiscV core runs correctly, the hardware signal waveform will not be captured after the RiscV core test case code in the firmware is executed.

[0051] Otherwise, if the RiscV core test case code execution fails (execution stuck, return value error, or instruction execution exception), the trigger will trigger the capture waveform. The saved hardware signal waveform is used to locate the specific cause of the fault, and the value of the RiscV core register obtained in the monitoring sub-interface and the value of the selected special register mscratch can be used to make a preliminary judgment and locate the approximate location of the faulty code segment. The combination of these two can quickly locate the problem.

[0052] After downloading the hardware design database, it takes some time to download and prepare the firmware. During this time, the simulated chip interaction interface can be configured to ensure that the trigger is turned on before RiscV actually starts to execute. If the configuration is more complicated and takes a long time, you can re-power on the simulated chip after the configuration to ensure that the entire operation process of RiscV is under monitoring and the capture behavior of the captured waveform.

[0053] For the steps to make firmware, refer to Figure 2The dotted arrow in the figure points to the process. After the user writes the program code file for testing RiscVcore (which can be all C code files, all assembly files, or part C code files and part assembly files), insert the code for verifying the correctness of execution into the file. These verification codes can be used by the sub-interface of the monitoring signal to observe the execution status, and can also be used by the interface to simulate the chip interaction interface to capture the hardware signal waveform based on the trigger. After the code is inserted, it is cross-compiled into a RiscV executable file and encapsulated into firmware with the loader (boot code for loading executable files) that boots the RiscV core.

[0054] After the prepared firmware is loaded into the chip simulated by the FPGA board, the loader will hand over the RiscVcore executable code in the firmware to the RiscV core for execution. After the RiscV core in the simulated chip is initialized by the loader, it starts executing from the entry address ( Figure 3 For execution flow). In addition to normal initialization, the RiscV executable code must set up an interrupt function with the verification code inserted. Then initialize the time interrupt, configure the timeout time as the current time + delay time, and then make the time interrupt effective. The source file code corresponding to the following executable instructions is divided into multiple code segments. After each code segment, the timeout time must be reconfigured to the current time + delay time, and ensure that the execution time of each code segment is less than the delay time of the configured time interrupt. In this way, if each code segment is executed normally, the time interrupt will not be triggered.

[0055] After each code segment, the execution is judged to be correct according to the function call return value or register status value. If an execution error is found, the value of RiscV's special register mscratch is set to a special value, and then enters an infinite loop waiting. Since the trigger is configured in the analog chip interaction interface before executing the code, the special value of the RiscV special register mscratch will trigger the capture of the waveform. The saved waveform is used to analyze the cause of the fault. Since the simplest infinite loop waiting is currently entered, the values ​​of various registers or signals can also be viewed in the monitoring sub-interface to preliminarily understand the cause of the error, and the value of the special register mscratch can be used to assist in viewing and analyzing the captured hardware signal waveform.

[0056] If a certain instruction in a certain code segment is executed and stuck at a certain position, then when the time reaches the configured time interrupt timeout, the time interrupt will be triggered, and the RiscV core will enter the interrupt processing code segment. In the interrupt processing code segment, the value of the RiscV special register mscratch is set to a special value, and then enter an infinite loop waiting. Similarly, the special value of the RiscV special register mscratch will trigger the capture of waveforms, and the saved waveforms are used to analyze the cause of the fault.

[0057] If the interrupt is triggered by other instruction execution exceptions, the interrupt processing code segment will also trigger the capture of the waveform, just like the time interrupt is triggered.

[0058] After the above two interrupts occur and enter the interrupt processing code, they will eventually enter an infinite loop waiting. At this time, you can also view the values ​​of various registers or signals in the monitoring sub-interface to preliminarily understand the cause of the error, and the value of the special register mscratch can be used to assist in viewing and analyzing the captured hardware signal waveform.

[0059] No matter which execution error occurs, the special register mscratch will have the same special value, thus triggering the capture of the hardware signal waveform and entering an infinite loop. In this way, the same configuration can be used to adapt to different fault conditions.

[0060] If each code segment is executed correctly, then when the program is executed to the end, the time interrupt is stopped and an infinite loop wait is entered. At this time, the values ​​of various registers or signals of the monitoring sub-interface can be observed, especially the value of the special register mscratch which is the focus here. These values ​​can be used to determine the progress and status of the RiscV core execution.

[0061] In general, the value of the special register mscratch is used here to monitor the execution status, and a special value is used to capture the hardware signal waveform. In general, printing is an auxiliary means, but the printing execution time is long, which will affect the execution timing logic of the RiscV core (especially in multi-threaded situations). However, the monitoring mechanism using the RiscV special register mscratch to assist in the hardware simulation environment will have little impact on the original RiscV core execution timing, and the impact on the execution time of a large number of loops is also minimal. The unified trigger for capturing waveforms also facilitates the capture of multiple faults at the same time, and can deal with random faults.

[0062] When using the value of the special register mscratch to monitor the internal status, the value of the special register mscratch needs to be uniformly encoded. This makes it easier to see the execution status of the RiscV core in the monitoring sub-interface. For the encoding method of the value of the special register mscratch, see Figure 4 Block diagram. The codes are divided into two categories. The first category is used to record the execution status, and the second category is used to trigger the capture of hardware signal waveforms in the hardware simulation environment. The first category of codes is used to record various states or variables of the execution process and the execution line number into the special register mscratch, and the second category of codes is used to configure special values ​​to trigger the capture of hardware signal waveforms when an execution error occurs.

[0063] The codes for recording the execution status are divided into three subcategories. For situations where the status value or variable value to be recorded is relatively small, you can use the code 1 method. The top two bytes (the number of bytes can be increased or decreased depending on the situation) can be a value like 0xfedc, ensuring that these bytes of the value of the special register mscratch will not or are unlikely to appear normally in the same program. The last few bytes record the line number (to ensure that the line number of a test case will not overflow these bytes). The empty part in the middle is divided into blocks to record various states or variables.

[0064] When the size of the state value or variable value needs to occupy all the bits of the special register mscratch, then code 2 can be used to record the execution state. Using a continuous serial method, first record each state or variable in turn into the special register mscratch. After the recording is completed, the last record is used to mark the position of the current record. Similarly, the front part of the last record uses a special value to mark that the current is the last record, and the following bytes are used to record the current line number. When recording data in this way, you can only view the recording of several states in the captured waveform.

[0065] When the state value or variable value to be recorded exceeds all bits of the special register mscratch, code 3 can be used to record the execution state. At this time, each state or variable is split into several parts, and then stored in the special register mscratch in sequence. After all parts of all states or variables are stored, the first part of the last record uses a special value to mark the current record as the last record, and the following several bytes are used to record the current line number. When recording data in this way, you can only view the record of several states in the captured waveform.

[0066] The special value used to trigger the capture of the hardware signal waveform is similar to the special value of marking the line number. It can also take the value of the byte changing according to a certain rule. For example, 32 bits can be set to 0x12345678, 64 bits can be set to 0x123456789abcdef, etc. Under normal circumstances, such special values ​​are unlikely to appear. They are used to trigger the capture of the waveform when an execution error occurs.

[0067] In a specific implementation, the present application provides a computer storage medium and a corresponding data processing unit, wherein the computer storage medium can store a computer program, and when the computer program is executed by the data processing unit, the invention content of the method for locating faults in complex operation of RiscV core provided by the present invention and some or all steps in each embodiment can be executed. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0068] Those skilled in the art can clearly understand that the technical solutions in the embodiments of the present invention can be implemented by means of computer programs and their corresponding general hardware platforms. Based on this understanding, the technical solutions in the embodiments of the present invention are essentially or the part that contributes to the prior art can be embodied in the form of a computer program, i.e., a software product, which can be stored in a storage medium and includes several instructions for enabling a device including a data processing unit (which can be a personal computer, a server, a single-chip microcomputer, a MUU or a network device, etc.) to execute the methods described in various embodiments of the present invention or certain parts of the embodiments.

[0069] The present invention provides a method for locating faults in the complex operation of RiscV core. There are many methods and ways to implement the technical solution. The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, several improvements and modifications can be made, and these improvements and modifications should also be regarded as the scope of protection of the present invention. All components not specified in this embodiment can be implemented by existing technologies.

Claims

1. A method for locating faults in a complex operation of a RiscV core, characterized in that: The following steps are involved: Step 1: Prepare a database containing chip hardware design and build a hardware simulation working environment; Step 2, adding debugging information to the RiscV core source code, compiling it into a RiscV core executable file, and encapsulating the executable file and the boot code loader used to load the executable file to make firmware for the chip containing the RiscV core; Step 3, downloading the database containing the chip hardware design and the firmware to the FPGA board on the host side to generate a simulated chip containing the RiscV core; Step 4, configure the trigger; Step 5, the firmware is loaded into the chip containing the RiscV core simulated in step 3 and then starts to execute, starts a trigger to capture the hardware signal waveform, saves the hardware signal waveform and analyzes it; In step 5, the firmware is loaded into the chip containing the RiscV core simulated in step 3 and then starts to execute, which specifically includes: After the RiscV core in the simulated chip containing the RiscV core is initialized by the boot code loader, the RiscV core instructions are executed from the entry address; when debugging information is added to the RiscV core source code, an interrupt function is added, and the value of the interrupt vector register is set to the entry address of the interrupt function. When an abnormal situation occurs during the execution process, the RiscV core will enter the interrupt function; initialize the time interrupt, configure the timeout time to be the value of the current time plus the delay time, and then make the time interrupt effective; the source file code corresponding to the RiscV core executable file is divided into more than two code segments, and the timeout time must be reconfigured to be the value of the current time plus the delay time after each code segment, and ensure that the execution time of each code segment is less than the configured time interval for generating the time interrupt. If each code segment is executed normally, the time interrupt will not be triggered; After each code segment, the execution is judged to be correct according to the function call return value or register status value. If an execution error is found, the value of the special register mscratch of RiscV is set to a special value, and then an infinite loop wait is entered. The special value will trigger the capture of the hardware signal waveform, and the saved hardware signal waveform is used to analyze the cause of the fault; If a certain instruction of a certain code segment is stuck at a certain position, a time interrupt will be triggered when the time reaches the timeout period, and RiscV core will enter the interrupt processing code segment; in the interrupt processing code segment, the value of RiscV's special register mscratch is set to a special value, and then enter an infinite loop waiting, the special value will trigger the capture of the hardware signal waveform, and the saved hardware signal waveform is used to analyze the cause of the fault; If the execution of the RiscV core instruction triggers an interrupt due to an exception, in the interrupt handling code segment, the value of the RiscV special register mscratch is set to a special value, and then an infinite loop wait is entered. The special value triggers the capture of the hardware signal waveform, and the saved hardware signal waveform is used to analyze the cause of the fault; If each code segment is executed correctly, the time interrupt function is disabled when the code is executed to the end, and an infinite loop wait is entered.

2. The method according to claim 1, characterized in that In step 1, the database contains a binary file for burning the chip hardware design into the FPGA board.

3. The method according to claim 2, characterized in that Step 2 includes: obtaining a code file for testing the RiscV core, inserting a code for verifying the execution correctness into the code file, wherein the code for verifying the execution correctness is used to observe the execution state and is also used to trigger the capture of hardware signal waveforms; after the code for verifying the execution correctness is inserted, cross-compiling it into a RiscV executable file, and encapsulating it into firmware with the boot code loader that boots the RiscV core.

4. The method according to claim 3, characterized in that In step 2, the RiscV core executable file includes RiscV core instructions, and the RiscV core instructions are machine codes that can be read and executed by RiscV core.

5. The method according to claim 4, characterized in that Step 4 includes: selecting a special register mscratch of the RiscV core, configuring a special value as a trigger condition, and generating a trigger.

6. The method according to claim 5, characterized in that In step 5, when the value of the special register mscratch is used to monitor the internal state, the value of the special register mscratch is uniformly encoded, and the encoding is divided into two categories. The first category is the encoding used to record the execution state, and the second category is the encoding used to trigger the capture of the hardware signal waveform; the first category of encoding is used to record various states or variables of the execution process and the execution line number into the special register mscratch, and the second category of encoding is used to configure special values ​​to trigger the capture of the hardware signal waveform when an execution error occurs.

7. The method according to claim 6, characterized in that In step 5, the first category of codes is divided into three subcategories, namely, the first code, the second code, and the third code; In the first code, the highest 1 to 2 bytes are used to identify the current coding mode, the last 1 to 3 bytes are used to record the line number, and the middle 3 to 6 bytes are used to record the execution progress, intermediate results or variables; In the second encoding, a continuous serial method is used to record each state or variable in the special register mscratch in sequence. After the recording is completed, the last record is used to mark the position of the current record; the front part of the last record uses a special value to mark that the current is the last record, and the following 1 to 2 bytes are used to record the current line number; In the third encoding, each state or variable is split into two or more parts, and then stored in the special register mscratch in the order of splitting from the first part to the last part; after all parts of all states or variables are stored, the part before the last record uses a special value to mark that the current record is the last record, and the 1 to 2 bytes after the last record are used to record the current line number; In the case where the state value or variable value to be recorded is relatively small, the first code is used to record the execution state; the relatively small means that the mscratch register is 64 bits, and after removing the bytes storing the row number and the characteristic value, the remaining bits can store two or more state values; When the size of the state value or variable value is moderate, the second encoding is used to record the execution state; the moderate size means that the mscratch register is 64 bits, and after removing the bytes storing the row number and the characteristic value, the remaining bits are only enough to store one state value; When the state value or variable value to be recorded is too large, the third encoding is used to record the execution state; the too large means that the mscratch register is 64 bits, and after removing the bytes storing the row number and the characteristic value, the remaining bits cannot store a state value.

8. The method according to claim 7, characterized in that In step 5, if the RiscV core test case code runs correctly, the hardware signal waveform will not be captured after the RiscV core test case code in the firmware is executed; If an error occurs during the execution of the RiscV core test case code, the trigger will cause the hardware signal waveform to be captured and saved. The errors include execution jam, return value error, and instruction execution exception. The saved hardware signal waveform is used to locate the specific cause of the fault, and then the position of the faulty code segment is located based on the value of the RiscV core register and the value of the selected special register mscratch.

9. An electronic device, characterized in that: The method comprises a processor and a memory, wherein the memory stores program codes, and when the program codes are executed by the processor, the processor executes the steps of the method according to any one of claims 1 to 8.

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