Simulation debugging system and method with fault judgment function

Abstract

The invention discloses a simulation debugging system and method with fault judgment. The simulation debugging system comprises a simulator mainboard, a simulator state monitoring module, a chip state monitoring module, an interface state monitoring module, an error state analysis module and a display module, wherein the simulator state monitoring module, the chip state monitoring module, the interface state monitoring module, the error state analysis module and the display module are integrated on the simulator mainboard. The error state analysis module is respectively connected with the display module, and the chip state monitoring module, the interface state monitoring module and the error state analysis module are respectively connected with a tested chip; and the simulator state monitoring module is connected with the simulator mainboard. By analyzing the transmission data between the emulator mainboard and the tested chip, the current state of the chip can be known in time, and the debugging efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip simulation debugging fault detection, and in particular to a simulation debugging system and method with fault judgment. Background Art

[0002] In the process of debugging the chip, the debugger needs to use the integrated development environment and use the simulator to simulate and debug the debugged chip. Due to problems with the hardware environment preparation, bugs in the debugger, problems with the chip's peripherals or data links, the simulator may not be able to debug the chip correctly. At this time, if the simulator cannot provide information about the current status of the chip and the simulator, the debugger will spend a lot of time and energy to analyze the cause of the error. Therefore, a good simulator can help debuggers achieve twice the result with half the effort in chip debugging progress.

[0003] With the development of chip design and manufacturing industry, the types of simulators are also increasing. Simulation debugging of chips is becoming more and more important, and simulator is an important object used to debug development programs and test chip functions during the chip R&D and development stages. The simulator can perform single-step tracking debugging of chip test programs with the integrated development environment, and can also use debugging methods such as software breakpoints, hardware breakpoints, and full-speed operation. In addition, it can observe the values ​​of various variables in the program, SDRAM, DDR and other types of storage space, as well as the real-time data of the chip's core registers and peripheral registers in the development environment, and provide real-time feedback on the execution of the chip program.

[0004] Among the existing products, a certain model of simulator developed by a Beijing Technology Co., Ltd. has the following problems:

[0005] 1. There are too many indicator lights on the emulator, and the COM1 indicator light, COM2 indicator light, COM3 indicator light and EMU1 indicator light have no prompt function for chip debugging, and the indicator light name has no direct relationship with the indicator light function. When the emulator has a debugging failure, the debugger needs to spend a lot of time analyzing the cause of the failure;

[0006] 2. The function of the simulator indicator light is not obvious. The simulator indicator light can only simply feedback the status of the simulator; therefore, the entire debugging process is time-consuming and inefficient. Summary of the invention

[0007] The present invention provides a simulation debugging system and method with fault judgment to solve the technical problems mentioned in the background technology.

[0008] To achieve the above object, the technical solution of the present invention is achieved as follows:

[0009] The present invention provides a simulation debugging system with fault judgment, comprising a simulator mainboard and a simulator status monitoring module, a chip status monitoring module, an interface status monitoring module, and an error status analysis module integrated on the simulator mainboard. 、 Display module:

[0010] The emulator status monitoring module, chip status monitoring module, interface status monitoring module and error status analysis module are respectively connected to the display module, and the chip status monitoring module, interface status monitoring module and error status analysis module are respectively connected to the chip under test; the emulator status monitoring module is connected to the emulator mainboard.

[0011] Furthermore, the interface status monitoring module is a JTAG interface status monitoring module, and the JTAG interface status monitoring module is connected to the JTAG interface of the chip under test.

[0012] Furthermore, the simulation debugging system also includes an information interaction module, and the information interaction module is connected to the simulator status monitoring module, the chip status monitoring module, the interface status monitoring module, and the error status analysis module respectively.

[0013] Furthermore, the specific functions of each module are as follows:

[0014] The simulator status monitoring module is used to monitor the power-on status of the simulator mainboard, the startup status of the FPGA program, and the startup status of the simulator control program;

[0015] A chip status monitoring module is used to monitor the status of the chip program; the status of the chip program includes a normal running state, a software breakpoint pause state, and an abnormal state;

[0016] JTAG interface status monitoring module, used to monitor the chip board power-on status, JTAG interface data transmission status, and JTAG data abnormality;

[0017] Error status analysis module, used to monitor the operation of ET components, chip register startup, and program address access;

[0018] The information interaction module is used to receive and feedback the error information output by the emulator status monitoring module, chip status monitoring module, JTAG interface status monitoring module and error status analysis module, and then print the error information output by the four modules on the startup log.

[0019] Further, the display module includes four different three-color indicator lights, namely a POWER indicator light, a STATE indicator light, a RUN indicator light, and an ERROR indicator light;

[0020] Among them, the POWER indicator light is electrically connected to the emulator state monitoring module, the RUN indicator light is electrically connected to the chip state monitoring module; the STATE indicator light is electrically connected to the JTAG interface state monitoring module; and the ERROR indicator light is electrically connected to the error state analysis module.

[0021] On the other hand, the present invention also provides a debugging method for a simulation debugging system with fault judgment, which uses the above simulation debugging system to perform debugging, and specifically includes the following steps:

[0022] S1, first connect the simulator mainboard to the chip under test, then use the simulator status monitoring module to monitor the power-on status of the simulator mainboard, the startup status of the FPGA program and the startup status of the simulator control program, and feed back the monitoring results to the display module and the information interaction module; if the monitoring results are abnormal, do not enter S2, and debug the simulator mainboard until the monitoring results are normal;

[0023] S2, using the JTAG interface status monitoring module to monitor the chip board power-on status, JTAG interface data transmission status, and JTAG data abnormality, and feed back the monitoring results obtained by S2 to the display module and the information interaction module; if the monitoring results obtained by S2 are abnormal, it will not enter S3, and debug the emulator mainboard and the chip under test until the monitoring results are normal;

[0024] S3, using the chip status monitoring module to monitor and determine the status of the chip program of the chip under test, and feeding back the monitoring result obtained in S3 to the display module and the information interaction module;

[0025] S4, using the error status analysis module to monitor the ET component operation status, chip register startup status, and program address access status of the chip under test, and feeding back the monitoring results obtained in S4 to the display module and the information interaction module;

[0026] S5. After receiving the above feedback information, the information interaction module prints the feedback error information about the monitoring result in the startup log file, so that the debugging personnel can debug the simulator mainboard and the chip under test according to the startup log file.

[0027] Furthermore, the S1 specifically includes the following steps:

[0028] S11, first connect the emulator mainboard to the chip under test;

[0029] S12, read the voltage value of the power supply pin connected to the emulator mainboard microcontroller through the emulator control program. If the voltage value is within the set voltage value range, it is determined that the emulator mainboard is powered on normally, and the PWOER indicator on the display module is lit red; otherwise, it is determined that the emulator mainboard is powered on abnormally, the POWER indicator on the display module is not lit, and the information of the abnormal power-on of the emulator mainboard is fed back to the information interaction module, and the emulator mainboard will not perform other subsequent status monitoring work until the debugger debugs the emulator mainboard and determines that the emulator mainboard is powered on normally before entering S13;

[0030] S13, then use the simulator status monitoring module to monitor the startup of the simulator control program. If the simulator control program can be started normally, the PWOER indicator light changes from red to yellow; otherwise, the PWOER indicator light remains red, and the information that the simulator control program cannot be started normally is fed back to the information interaction module, and the simulator main board will not perform other subsequent status monitoring work until the debugger debugs the simulator main board and determines that the simulator control program can be started normally before entering S14;

[0031] S14. After the FPGA program on the emulator mainboard is started, the FPGA sends status flag information to the emulator control program. The emulator control program determines whether the FPGA program is started normally through the status flag information. If the FPGA program is started normally, the color of the PWOER indicator light changes from yellow to green. If the POWER light remains green, it indicates that the emulator mainboard is working normally. If the FPGA program fails to start, the color of the PWOER indicator light remains unchanged, and the information that the FPGA program fails to start is fed back to the information interaction module. S2 will not be entered until the FPGA program can start normally after debugging.

[0032] Furthermore, the S2 specifically includes the following steps:

[0033] S21, using the JTAG interface status monitoring module to monitor the power-on status of the chip board under test, the emulator control program will detect whether the PD voltage in the JTAG pin is the set value, if the PD voltage is the set value, it is determined that the chip board under test can be powered on normally, and at the same time, the STATE indicator light will light up green; if the PD voltage is not the set value, it is determined that the chip board under test cannot be powered on normally, and at the same time, the STATE indicator light on the display module will light up yellow, and the information that the chip board under test cannot be powered on normally is fed back to the information interaction module, and S22 will not be entered until the chip board under test is debugged and the chip board under test can be powered on normally;

[0034] S22, using the JTAG interface status monitoring module to monitor the JTAG interface data transmission function. During the monitoring, the emulator mainboard transmits data with the chip under test through the JTAG interface. During the data transmission process, the emulator control program will make the STATE indicator light flash at a set frequency, indicating that data is being transmitted normally. When the STATE indicator light is always green, it indicates that the JTAG interface data transmission is abnormal, and the abnormal information of the JTAG interface is fed back to the information interaction module, and S23 will not be entered until the JTAG interface is debugged and the JTAG interface data transmission is normal;

[0035] S23. Use the JTAG interface status monitoring module to monitor the data on TDO. If the data on TDO is normal, the STATE indicator light is off. If the data on TDO has an abnormal format, or the data is all zeros or all 1s, the JTAG data is judged to be abnormal. At this time, the STATE indicator light will light up in red to prompt the tester to debug the abnormality, and the information about the JTAG data abnormality will be fed back to the information interaction module, and S3 will not be entered until the JTAG interface is debugged and the data on TDO is normal.

[0036] Furthermore, the S3 specifically includes the following steps:

[0037] S31, the simulator mainboard reads the status register of the chip under test and determines whether the chip program is in a normal operating state through the valid bit. If the chip program is in a normal operating state, the simulator control program will make the RUN indicator light on the display module light green;

[0038] S32, the emulator mainboard reads the status register of the chip under test, and determines whether the chip under test is in a software breakpoint pause state through the valid bit of the data. If the chip program is in a software breakpoint pause state, the emulator control program will make the RUN indicator light yellow;

[0039] S33. The emulator mainboard reads the status register of the chip under test and performs logical judgment based on whether the valid bits of the data are normal values, or all zeros or all 1s, so as to determine whether the chip program is in an abnormal state; if the chip program is in an abnormal state, the emulator control program will control the RUN indicator light to make it light red, and feed back the information that the chip program is in an abnormal state to the information interaction module.

[0040] Furthermore, the S4 specifically includes the following steps:

[0041] S41, the simulator mainboard sends link scan data to the ET component of the chip under test, and determines whether the ET component is operating normally through the return value of the data on TDO. If the ET component is operating normally, the ERROR indicator on the display module lights up green; otherwise, it is determined that the ET component cannot operate normally, the ERROR indicator lights up red, and the information that the ET component cannot operate normally is fed back to the information interaction module;

[0042] S42, judging whether the corresponding register of the chip under test is started normally according to the corresponding register value, if the corresponding register of the chip under test can be started normally, the ERROR indicator light is yellow; otherwise, the ERROR indicator light is red, and the information that the corresponding register of the chip under test cannot be started normally is fed back to the information interaction module;

[0043] S43. The emulator mainboard determines the program address access situation through the data return value on TDO; when the program accesses illegal storage space, the data displayed on TDO will become all zero or all 1, and the ERROR indicator light will light up red. Then, the information that the program accessed illegal storage space is fed back to the information interaction module to prompt the tester to debug the abnormality and to re-power on the emulator mainboard and the chip under test.

[0044] Furthermore, the information interaction module is driven by a simulator control program.

[0045] Beneficial effects of the present invention:

[0046] 1. The present invention discloses a simulation debugging system with fault judgment. Combined with the ET component design architecture of the chip, the current state of the chip can be quickly judged through the data information on TDO in JTAG, and the information can be quickly fed back to the debugger through four indicator lights, which can improve the work efficiency of the debugger.

[0047] In addition, by analyzing the transmission data between the emulator mainboard and the chip under test, the current status of the chip under test can be known in a timely manner, which can ensure the normal operation of the debugging program. Detecting the power-on status of the emulator mainboard and the power-on status of the chip under test board helps with problem analysis and further improves the efficiency of debugging work.

[0048] 2. The simulation debugging system of the present invention is provided with four indicator lights, namely, the POWER indicator light, the STATE indicator light, the RUN indicator light, and the ERROR indicator light; all four indicators are three-color lights, and different colors provide different debugging information to the debugger. The name of the indicator light is closely related to the function, so that the tester can quickly obtain the debugging information of the chip under test and the emulator motherboard.

[0049] In contrast, a certain model of simulator in the existing product has 6 status indicator lights, which is two more than the present invention, but the simulator cannot directly reflect the status of the simulator and the chip. The 6 indicator lights not only have similar names, but also have no direct connection with the functions of the indicator lights, and the debugger needs to check the user manual. The four indicator lights in the present invention can more intuitively reflect the status of the simulator and the chip, and the debugger does not need to check the user manual, which is more convenient and efficient to use.

[0050] 3. The present invention also discloses a debugging method. Compared with the traditional debugging method, the method provided by the present invention adopts a simulation debugging system, and the display module and the information interaction module can quickly provide the debugging personnel with error information during the debugging process. Therefore, the debugging method in the present invention is more efficient than the traditional method, the errors occurring during the debugging process are more intuitive, and it is more convenient to use. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 It is a connection block diagram of the simulation debugging system in the present invention;

[0052] Figure 2 The diagram shows the layout differences between the multiple indicator lights in the simulation and debugging system of the present invention and the multiple indicator lights in the existing DSP simulator, wherein (a) is the layout diagram of the multiple indicator lights in the existing DSP simulator; and (b) is the layout diagram of the multiple indicator lights in the simulation and debugging system of the present invention. DETAILED DESCRIPTION

[0053] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Preferred embodiments of the present invention are provided in the drawings. However, the present invention can be implemented in many other different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0054] In the prior art, a certain model of simulator developed by a Beijing Technology Co., Ltd. has 6 status indicator lights, the functions of which are shown in Table 1. The names of the indicator lights are COM1, COM2, COM3, EMU1, EMU2, and EMU3. Each status indicator light has a different function, providing relevant information during power supply, operation, and configuration.

[0055] Table 1: Overview of the functions of the six status indicators in a certain model of simulator developed by a Beijing technology company;

[0056]

[0057]

[0058] At present, the above-mentioned model simulator has the following problems:

[0059] a. There are too many indicator lights on the emulator. The COM1 indicator light is the emulator ready indicator light, the COM2 indicator light is the emulator FPGA (Field Programmable Gate Array) loading completion indicator light, and the COM3 indicator light is the emulator system Boot indicator light. The three indicator lights can be combined into one emulator ready indicator light, and the name COM can be changed to Ready. This is more intuitive and convenient for debuggers to remember the function of the indicator light. The EMU1 indicator light is the emulator's Trace indicator light. This indicator light is rarely used by debuggers and lacks practical value. It can be removed. These four indicator lights have no prompt effect on chip debugging, and the indicator light names have no direct relationship with the functions of the indicators. When a debugging failure occurs in the emulator, debuggers need to spend a lot of time analyzing the cause of the failure. Some emulators have too few indicator lights, and there is only one STATUS indicator light, which provides debuggers with less information.

[0060] b. The function of the indicator lights on the emulator is not obvious. The indicator lights on the emulator can only simply feedback the status of the emulator. For example, the EMU2 indicator light is the host communication indicator light, which can only feedback that the host and the emulator have information communication, and has no function to detect whether the data is correct; the EMU3 indicator light is the CCS connection indicator light, which can only feedback whether the emulator is connected to the board, and cannot directly feedback the status of the chip, and has no direct relationship with chip simulation debugging. Therefore, it causes a lot of inconvenience for debuggers when debugging chips. They cannot quickly troubleshoot emulator problems, nor can they directly judge the chip status.

[0061] The reasons for the above problems are: 1. There are many emulator designers and manufacturers, and there is no unified standard in the industry, resulting in differences in the indicator lights of each type of emulator. 2. Emulator designers and manufacturers only pay attention to the emulator debugging function, and have not yet realized the importance of the emulator's fault diagnosis function.

[0062] For the above technical issues, refer to Figure 1 The embodiment of the present application provides a simulation debugging system with fault judgment, including a simulator mainboard and a simulator status monitoring module, a chip status monitoring module, an interface status monitoring module, and an error status analysis module integrated on the simulator mainboard. 、 Display module:

[0063] The emulator status monitoring module, chip status monitoring module, interface status monitoring module and error status analysis module are respectively connected to the display module, and the chip status monitoring module, interface status monitoring module and error status analysis module are respectively connected to the chip under test; the emulator status monitoring module is connected to the emulator mainboard.

[0064] In some embodiments, the interface status monitoring module is a JTAG interface status monitoring module, and the JTAG interface status monitoring module is connected to the JTAG interface of the chip under test.

[0065] In some embodiments, the simulation debugging system further includes an information interaction module, and the information interaction module is respectively connected to the simulator status monitoring module, the chip status monitoring module, the interface status monitoring module, and the error status analysis module.

[0066] In some embodiments, the specific functions of each module are as follows:

[0067] The simulator status monitoring module is used to monitor the power-on status of the simulator mainboard, the startup status of the FPGA program, and the startup status of the simulator control program;

[0068] A chip status monitoring module is used to monitor the status of the chip program; the status of the chip program includes a normal running state, a software breakpoint pause state, and an abnormal state;

[0069] JTAG (Joint Test Action Group) interface status monitoring module, used to monitor the chip board power-on status, JTAG interface data transmission status, and JTAG data abnormality;

[0070] Error status analysis module, used to monitor the operation of ET (Emulation / Test) components, the startup of chip registers, and the access of program addresses;

[0071] The information interaction module is used to receive and feedback the error information output by the emulator status monitoring module, chip status monitoring module, JTAG interface status monitoring module and error status analysis module, and then print the error information output by the four modules on the startup log (log.txt file). It can effectively prevent the debugger from misunderstanding the specific meaning of the four indicator lights, reduce the debugging pressure, and reduce the probability of misunderstanding the prompt information. Further improve the debugging efficiency.

[0072] In some embodiments, the display module includes four different three-color indicator lights, namely a POWER indicator light, a STATE indicator light, a RUN indicator light, and an ERROR indicator light;

[0073] Among them, the POWER indicator light is electrically connected to the emulator state monitoring module, the RUN indicator light is electrically connected to the chip state monitoring module; the STATE indicator light is electrically connected to the JTAG interface state monitoring module; and the ERROR indicator light is electrically connected to the error state analysis module.

[0074] The simulation debugging system of the present invention is provided with four indicator lights, namely, a POWER indicator light, a STATE indicator light, a RUN indicator light, and an ERROR indicator light; all four indicators are three-color lights, and different colors are used to provide different debugging information to the debugger. The name of the indicator light is closely related to the function, so that the tester can quickly obtain the debugging information of the chip under test and the simulator motherboard.

[0075] In contrast, a certain model of simulator in the existing products has 6 status indicator lights, which is two more than the present invention, but the simulator cannot directly reflect the status of the simulator mainboard and the chip under test. The 6 indicator lights not only have similar names, but also have no direct connection with the functions of the indicator lights, and the debugger needs to check the user manual. The four indicator lights in the present invention can more intuitively reflect the status of the simulator mainboard and the chip under test, and the debugger does not need to check the user manual, which is more convenient and efficient to use.

[0076] The simulation debugging system disclosed in the present invention combines the ET component design architecture of the chip under test, and can quickly determine the current state of the chip under test through the data information on the TDO (Test Data Output, JTAG pin) in JTAG, and quickly feed back information to the debugger through four indicator lights, thereby improving the work efficiency of the debugger.

[0077] In addition, by analyzing the transmission data between the emulator mainboard and the chip under test, the current status of the chip under test can be known in a timely manner, which can ensure the normal operation of the debugging program. Detecting the power-on status of the emulator mainboard and the chip board is helpful for problem analysis and further improves the efficiency of debugging work.

[0078] On the other hand, the present invention also provides a debugging method for a simulation debugging system with fault judgment, which uses the above simulation debugging system to perform debugging, and specifically includes the following steps:

[0079] S1, first connect the simulator mainboard to the chip under test, then use the simulator status monitoring module to monitor the power-on status of the simulator mainboard, the startup status of the FPGA program and the startup status of the simulator control program, and feed back the monitoring results to the display module and the information interaction module; if the monitoring results are abnormal, do not enter S2, and debug the simulator mainboard until the monitoring results are normal;

[0080] S2, using the JTAG interface status monitoring module to monitor the chip board power-on status, JTAG interface data transmission status, and JTAG data abnormality, and feed back the monitoring results obtained by S2 to the display module and the information interaction module; if the monitoring results obtained by S2 are abnormal, it will not enter S3, and debug the emulator mainboard and the chip under test until the monitoring results are normal;

[0081] S3, using the chip status monitoring module to monitor and determine the status of the chip program of the chip under test, and feeding back the monitoring result obtained in S3 to the display module and the information interaction module;

[0082] S4, using the error status analysis module to monitor the operation of the ET components, the startup of the chip registers, and the access of the program address, and feeding back the monitoring results obtained in S4 to the display module and the information interaction module;

[0083] S5. After receiving the above feedback information, the information interaction module prints the feedback error information about the monitoring result in the log.txt (startup log) file, so that the debugging personnel can debug the simulator mainboard and chip according to the startup log file.

[0084] In some embodiments, the S1 specifically includes the following steps:

[0085] S11, first connect the emulator mainboard to the chip under test;

[0086] S12, read the voltage value of the power supply pin connected to the emulator mainboard microcontroller through the emulator control program. If the voltage value is within the set voltage value range, it is determined that the emulator mainboard is powered on normally, and the PWOER indicator on the display module is lit red; otherwise, it is determined that the emulator mainboard is powered on abnormally, the POWER indicator on the display module is not lit, and the information of the abnormal power-on of the emulator mainboard is fed back to the information interaction module, and the emulator mainboard will not perform other subsequent status monitoring work until the debugger debugs the emulator mainboard and determines that the emulator mainboard is powered on normally before entering S13;

[0087] S13, then use the simulator status monitoring module to monitor the startup of the simulator control program. If the simulator control program can be started normally, the PWOER indicator light changes from red to yellow; otherwise, the PWOER indicator light remains red, and the information that the simulator control program cannot be started normally is fed back to the information interaction module, and the simulator main board will not perform other subsequent status monitoring work until the debugger debugs the simulator main board and determines that the simulator control program can be started normally before entering S14;

[0088] Specifically, the method for determining whether the simulator control program can be started normally is as follows:

[0089] The following two operations are performed only when the simulator control program is started normally: 1. Generate a log.txt file through the information interaction module; 2. Output error information about the monitoring results in the log.txt file; Therefore, the above two operations can be used to determine whether the simulator control program is started normally.

[0090] S14. Use the simulator status monitoring module to monitor the startup of the FPGA program. After the FPGA program on the simulator mainboard is started, the FPGA sends status flag information to the simulator control program. The simulator control program determines whether the FPGA program is started normally through the status flag information. If the FPGA program is started normally, the color of the PWOER indicator light changes from yellow to green. If the POWER light is always green, it means that the simulator mainboard is working normally. If the FPGA program fails to start, the color of the PWOER indicator light remains unchanged, and the information that the FPGA program fails to start is fed back to the information interaction module. It will not enter S2 until the FPGA program can start normally after debugging. During the chip debugging process, if the POEWR indicator light is other colors or is off, the simulator mainboard needs to be powered on again.

[0091] In some embodiments, S2 specifically includes the following steps:

[0092] S21, using the JTAG interface status monitoring module to monitor the power-on status of the chip board, the emulator control program will detect whether the PD voltage in the JTAG pin is 3.3V. If the PD voltage is 3.3V, it is determined that the chip board under test can be powered on normally, and the STATE indicator light will light up green; if the PD voltage is not 3.3V, it is determined that the chip board under test cannot be powered on normally, and the STATE indicator light on the display module will light up yellow, and the information that the chip board under test cannot be powered on normally is fed back to the information interaction module; and it will not enter S22 until the chip board under test is debugged and the chip board under test can be powered on normally;

[0093] S22, using the JTAG interface status monitoring module to monitor the JTAG interface data transmission function. During the monitoring, the emulator mainboard transmits data with the chip under test through the JTAG interface. During the data transmission process, the emulator control program will make the STATE indicator light flash at a set frequency, indicating that data is being transmitted normally. When the STATE indicator light is always green, it indicates that the JTAG interface data transmission is abnormal, and the abnormal information of the JTAG interface is fed back to the information interaction module, and S23 will not be entered until the JTAG interface is debugged and the JTAG interface data transmission is normal;

[0094] S23. Use the JTAG interface status monitoring module to monitor the data on TDO. If the data on TDO is normal, the STATE indicator light is off. If the data on TDO has an abnormal format, or the data is all zeros or all 1s, the JTAG data is judged to be abnormal. At this time, the STATE indicator light will light up in red to prompt the tester to debug the abnormality, and the information about the JTAG data abnormality will be fed back to the information interaction module, and S3 will not be entered until the JTAG interface is debugged and the data on TDO is normal.

[0095] In some embodiments, S3 specifically includes the following steps:

[0096] S31, the simulator mainboard reads the status register of the chip under test and determines whether the chip program is in a normal operating state through the valid bit. If the chip program is in a normal operating state, the simulator control program will make the RUN indicator light on the display module light green;

[0097] S32, the simulator mainboard reads the status register of the chip under test, and determines whether the chip is in a software breakpoint pause state through the valid bit of the data. If the chip program is in a software breakpoint pause state, the simulator control program will make the RUN indicator light yellow;

[0098] S33, the simulator mainboard reads the status register of the chip under test, and makes a logical judgment based on whether the valid bits of the data are normal values, or all zeros or all 1s, so as to determine whether the chip program is in an abnormal state; if the chip program is in an abnormal state, the simulator control program will control the RUN indicator light to make the RUN indicator light red, and feed back the information that the chip program is in an abnormal state to the information interaction module. The red RUN indicator light can prompt the debugger that the program has an abnormality.

[0099] In some embodiments, the S4 specifically includes the following steps:

[0100] S41, the simulator mainboard sends link scan data to the ET component of the chip under test, and determines whether the ET component is operating normally through the return value of the data on TDO. If the ET component is operating normally, the ERROR indicator on the display module lights up green; otherwise, it is determined that the ET component cannot operate normally, the ERROR indicator lights up red, and the information that the ET component cannot operate normally is fed back to the information interaction module;

[0101] S42. Some registers of the chip are read-only and cannot be written, and the registers have fixed values, such as the ID (Identity document) register and the CSR (Control status register) register of the chip. Whether the corresponding register of the chip under test is started normally is determined based on the corresponding register value. If the corresponding register of the chip under test can be started normally, the ERROR indicator light is yellow; otherwise, the ERROR indicator light is red, and the information that the corresponding register of the chip under test cannot be started normally is fed back to the information interaction module;

[0102] S43. Some memory spaces of the chip need to be initialized. After power-on, some storage spaces of the chip need to be configured with the values ​​of related registers before they can be used. This process is collectively referred to as initialization. When the emulator motherboard accesses these storage spaces, if the initialization is not completed, the data displayed on TDO will be all zero or all 1, such as DDR (double data rate synchronous dynamic random access memory), EMIF (external memory interface), etc. Before the initialization is completed, the program cannot access it. The emulator motherboard determines the program address access situation through the data return value on TDO; when the data on TDO is all zero or all 1, it means that the program has accessed an illegal storage space (that is, a storage space that has not been initialized). At this time, the ERROR indicator lights up in red, and then the information that the program has accessed an illegal storage space is fed back to the information interaction module to prompt the tester to debug the abnormality and to re-power on the emulator motherboard and chip.

[0103] In some embodiments, the information interaction module is driven by a simulator control program.

[0104] A debugging method disclosed in the present invention has a higher debugging efficiency than the traditional debugging method, and the errors occurring during the debugging process are more intuitive and more convenient to use because the method provided by the present invention adopts a simulation debugging system, and the display module and the information interaction module can quickly provide the debugging personnel with error information during the debugging process.

[0105] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be covered within the protection scope of the present invention. In addition, the technical solutions between the various embodiments of the present invention can be combined with each other, but it must be based on the ability of ordinary technicians in the field to implement. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A simulation debugging system with fault judgment, characterized in that: It includes an emulator mainboard and an emulator status monitoring module, a chip status monitoring module, an interface status monitoring module, and an error status analysis module integrated on the emulator mainboard. 、 Display module: The emulator status monitoring module, chip status monitoring module, interface status monitoring module and error status analysis module are respectively connected to the display module, and the chip status monitoring module, interface status monitoring module and error status analysis module are respectively connected to the chip under test; the emulator status monitoring module is connected to the emulator mainboard.

2. The simulation debugging system according to claim 1, characterized in that: The interface status monitoring module is a JTAG interface status monitoring module, and the JTAG interface status monitoring module is connected to the JTAG interface of the chip under test.

3. The simulation debugging system according to claim 2, characterized in that: It also includes an information interaction module, which is respectively connected to the simulator status monitoring module, the chip status monitoring module, the interface status monitoring module, and the error status analysis module.

4. The simulation debugging system according to claim 3, characterized in that: The specific functions of each module are as follows: The simulator status monitoring module is used to monitor the power-on status of the simulator mainboard, the startup status of the FPGA program, and the startup status of the simulator control program; A chip status monitoring module is used to monitor the status of the chip program; the status of the chip program includes a normal running state, a software breakpoint pause state, and an abnormal state; JTAG interface status monitoring module, used to monitor the chip board power-on status, JTAG interface data transmission status, and JTAG data abnormality; Error status analysis module, used to monitor the operation of ET components, chip register startup, and program address access; The information interaction module is used to receive and feedback the error information output by the emulator status monitoring module, chip status monitoring module, JTAG interface status monitoring module and error status analysis module, and then print the error information output by the four modules on the startup log.

5. The simulation debugging system according to claim 3, characterized in that: The display module includes four different three-color indicator lights, namely a POWER indicator light, a STATE indicator light, a RUN indicator light, and an ERROR indicator light; Among them, the POWER indicator light is electrically connected to the emulator state monitoring module, the RUN indicator light is electrically connected to the chip state monitoring module; the STATE indicator light is electrically connected to the JTAG interface state monitoring module; and the ERROR indicator light is electrically connected to the error state analysis module.

6. A debugging method for a simulation debugging system with fault judgment, characterized in that: Debugging using the simulation debugging system according to any one of claims 3 to 5 specifically comprises the following steps: S1, first connect the simulator mainboard to the chip under test, then use the simulator status monitoring module to monitor the power-on status of the simulator mainboard, the startup status of the FPGA program and the startup status of the simulator control program, and feed back the monitoring results to the display module and the information interaction module; if the monitoring results are abnormal, do not enter S2, and debug the simulator mainboard until the monitoring results are normal; S2, using the JTAG interface status monitoring module to monitor the chip board power-on status, JTAG interface data transmission status, and JTAG data abnormality, and feed back the monitoring results obtained by S2 to the display module and the information interaction module; if the monitoring results obtained by S2 are abnormal, it will not enter S3, and debug the emulator mainboard and the chip under test until the monitoring results are normal; S3, using the chip status monitoring module to monitor and determine the status of the chip program of the debugged chip, and feeding back the monitoring result obtained in S3 to the display module and the information interaction module; S4, using the error status analysis module to monitor the operation of the ET components, the startup of the chip registers, and the access of the program address, and feeding back the monitoring results obtained in S4 to the display module and the information interaction module; S5. After receiving the above feedback information, the information interaction module prints the feedback error information about the monitoring result in the startup log file, so that the debugging personnel can debug the simulator mainboard and the chip under test according to the startup log file.

7. The debugging method according to claim 6, characterized in that: The S1 specifically includes the following steps: S11, first connect the emulator mainboard to the chip under test; S12, read the voltage value of the power supply pin connected to the emulator mainboard microcontroller through the emulator control program. If the voltage value is within the set voltage value range, it is determined that the emulator mainboard is powered on normally, and the PWOER indicator on the display module is lit red; otherwise, it is determined that the emulator mainboard is powered on abnormally, the POWER indicator on the display module is not lit, and the information of the abnormal power-on of the emulator mainboard is fed back to the information interaction module, and the emulator mainboard will not perform other subsequent status monitoring work until the debugger debugs the emulator mainboard and determines that the emulator mainboard is powered on normally before entering S13; S13, then use the simulator status monitoring module to monitor the startup of the simulator control program. If the simulator control program can be started normally, the PWOER indicator light changes from red to yellow; otherwise, the PWOER indicator light remains red, and the information that the simulator control program cannot be started normally is fed back to the information interaction module, and the simulator main board will not perform other subsequent status monitoring work until the debugger debugs the simulator main board and determines that the simulator control program can be started normally before entering S14; S14. After the FPGA program on the emulator mainboard is started, the FPGA sends status flag information to the emulator control program. The emulator control program determines whether the FPGA program is started normally through the status flag information. If the FPGA program is started normally, the color of the PWOER indicator light changes from yellow to green. If the POWER light remains green, it indicates that the emulator mainboard is working normally. If the FPGA program fails to start, the color of the PWOER indicator light remains unchanged, and the information that the FPGA program fails to start is fed back to the information interaction module. S2 will not be entered until the FPGA program can start normally after debugging.

8. The debugging method according to claim 6, characterized in that: The S2 specifically includes the following steps: S21, using the JTAG interface status monitoring module to monitor the power-on status of the chip board under test, the emulator control program will detect whether the PD voltage in the JTAG pin is the set value, if the PD voltage is the set value, it is determined that the chip board under test can be powered on normally, and at the same time, the STATE indicator light will light up in yellow; if the PD voltage is not the set value, it is determined that the chip board under test cannot be powered on normally, and at the same time, the STATE indicator light on the display module will light up in red, and the information that the chip board under test cannot be powered on normally is fed back to the information interaction module, and S22 will not be entered until the chip board under test is debugged and the chip board under test can be powered on normally; S22, using the JTAG interface status monitoring module to monitor the JTAG interface data transmission function. During the monitoring, the emulator mainboard transmits data with the chip under test through the JTAG interface. During the data transmission process, the emulator control program will make the STATE indicator light flash at a set frequency, indicating that data is being transmitted normally. When the STATE indicator light is always green, it indicates that the JTAG interface data transmission is abnormal, and the abnormal information of the JTAG interface is fed back to the information interaction module, and S23 will not be entered until the JTAG interface is debugged and the JTAG interface data transmission is normal; S23. Use the JTAG interface status monitoring module to monitor the data on TDO. If the data on TDO is normal, the STATE indicator light is off. If the data on TDO has an abnormal format, or the data is all zeros or all 1s, the JTAG data is judged to be abnormal. At this time, the STATE indicator light will light up in red to prompt the tester to debug the abnormality, and the information about the JTAG data abnormality will be fed back to the information interaction module, and S3 will not be entered until the JTAG interface is debugged and the data on TDO is normal.

9. The debugging method according to claim 6, characterized in that: The S3 specifically includes the following steps: S31, the simulator mainboard reads the status register of the chip under test and determines whether the chip program of the chip under test is in a normal operating state through the valid bit. If the chip program is in a normal operating state, the simulator control program will make the RUN indicator light on the display module light green; S32, the emulator mainboard reads the status register of the chip under test, and determines whether the chip under test is in a software breakpoint pause state through the valid bit of the data. If the chip program is in a software breakpoint pause state, the emulator control program will make the RUN indicator light yellow; S33, the emulator mainboard reads the status register of the chip under test, and performs a logical judgment based on whether the valid bits of the data are normal values, or all zeros or all 1s, thereby determining whether the chip program is in an abnormal state; If the chip program is in an abnormal state, the simulator control program will control the RUN indicator light to make it light red, and feed back the information that the chip program is in an abnormal state to the information interaction module.

10. The debugging method according to claim 6, characterized in that: The S4 specifically includes the following steps: S41, the simulator mainboard sends link scan data to the ET component of the chip under test, and determines whether the ET component is operating normally through the return value of the data on TDO. If the ET component is operating normally, the ERROR indicator on the display module lights up green; otherwise, it is determined that the ET component cannot operate normally, the ERROR indicator lights up red, and the information that the ET component cannot operate normally is fed back to the information interaction module; S42, judging whether the corresponding register of the chip under test is started normally according to the corresponding register value, if the corresponding register of the chip under test can be started normally, the ERROR indicator light is yellow; Otherwise, the ERROR indicator lights up red, and the information that the corresponding register of the chip under test cannot be started normally is fed back to the information interaction module; S43. The emulator mainboard determines the program address access situation through the data return value on TDO; when the program accesses illegal storage space, the data displayed on TDO will become all zero or all 1, and the ERROR indicator light will light up red. Then, the information that the program accessed illegal storage space is fed back to the information interaction module to prompt the tester to debug the abnormality and to re-power on the emulator mainboard and the chip under test.

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