PSRAM control method and apparatus, and electronic device
By evaluating and adjusting the loopback burst boundary in the PSRAM controller, the problem of low bus transmission efficiency in the prior art is solved, efficient matching between PSRAM and bus is achieved, and the efficiency of bus accessing PSRAM is improved.
Patent Information
- Application Number
- CN202411660492.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-20
- Publication Date
- 2025-02-18
AI Technical Summary
The existing PSRAM controller lacks the ability to independently optimize loopback burst boundaries, resulting in a decrease in bus transmission efficiency, especially in multi-Master concurrent access scenarios.
By analyzing the bus signal, determining the transmission requirements, and combining the historical matching between the PSRAM loopback burst boundary and the bus burst transmission requirements, it is necessary to evaluate whether the loopback burst boundary of PSRAM needs to be adjusted. If adjustment is required, first modify the loop burst boundary and then process the transmission requirements; if adjustments are not required, directly process the transmission requirements.
It achieves a high degree of compatibility between the PSRAM loopback burst boundary and bus transmission requirements, improves the efficiency of bus accessing PSRAM, reduces dependence on software, and maintains the transparency of hardware interfaces.
Smart Images
Figure CN119473955A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of memory, and in particular to a PSRAM control method, device and electronic equipment. Background Art
[0002] With the diversification of SoC (system-on-chip) application scenarios, PSRAM (Pseudo Static Random Access Memory) has become one of the commonly used external storage solutions for SoC due to its advantages such as large capacity and small number of pins. In addition to being limited by the number of PSRAM pins, the bandwidth performance of the PSRAM controller also depends on the matching degree between the bus transmission requirements and the PSRAM transmission configuration. Only when the two are fully matched can the efficiency of bus access to PSRAM be maximized.
[0003] The memory cell array inside the PSRAM can be regarded as a table structure consisting of multiple rows and columns, and the amount of data in each row of memory cells is defined as the Page Size. After receiving a legal instruction and address field, the PSRAM will activate a series of memory cells including the target cell pointed to by the address according to the parsing result of the address field.
[0004] Similar to WRAP type read and write requests, for PSRAMs that do not have the Row Boundary Cross (RBX) feature, subsequent data access will be limited to these activated cells. If the bus needs to access other memory cells that have not yet been activated, it must first end the current access and then resend a valid instruction and address field to activate the next group of storage cells. Otherwise, when the access address exceeds the range of the currently activated cell array, the actual access object will be automatically redirected to the starting cell of the array, resulting in an access error. Therefore, the amount of data in these activated storage cells is also called the "Wrapped Burst Boundary".
[0005] In order to meet the diversified transmission requirements, some models of PSRAM have adjustable loop burst boundaries. Under the default setting, their loop burst boundaries are equal to their own Page Size. After receiving legal instructions, their loop burst boundaries can also be configured to 16Bytes, 32Bytes, and 64Bytes to meet the engineering requirements of three transmission requests, namely WRAP4, WRAP8, and WRAP16.
[0006] When processing various types of burst transfers initiated by the bus, selecting the appropriate PSRAM loop burst boundary is the key to improving the efficiency of bus access to PSRAM. If the loop burst boundary is too small, the bus cannot obtain all the required data through a single access to PSRAM for both INCR and WRAP read and write requests. If the loop burst boundary is too large, although the impact on INCR type read and write requests is limited, for WRAP type read and write requests, it will still cause the bus to be unable to fully obtain the required data in a single PSRAM access. Therefore, reasonably setting the PSRAM loop burst boundary is crucial to optimizing the interaction between the bus and PSRAM.
[0007] However, the current PSRAM controller does not have the function of autonomously optimizing the PSRAM loop burst boundary. Therefore, to achieve dynamic adjustment of the PSRAM loop burst boundary, flexible software polling and configuration are required. However, this will not only increase the dependence on software, but also reduce the bus transmission efficiency, especially in the scenario of multiple masters accessing concurrently. Summary of the invention
[0008] In order to improve the matching degree between bus transmission requirements and PSRAM transmission configuration while reducing the dependence on software, the present application provides a PSRAM control method, device and electronic device.
[0009] The technical solution adopted by the present invention to solve the above problems is:
[0010] PSRAM control method, including:
[0011] When the bus initiates a new transmission request, the bus signal is parsed to determine the current transmission requirements, and combined with the historical matching of the PSRAM loop burst boundary and the bus burst transmission requirements, it is evaluated whether the PSRAM loop burst boundary needs to be adjusted at present;
[0012] If the loop burst boundary of the PSRAM needs to be adjusted, the operation of modifying the loop burst boundary is first initiated to the PSRAM, and then the transmission demand is processed and the data access operation is initiated to the PSRAM;
[0013] If there is no need to adjust the loop burst boundary of the PSRAM, the transmission requirement is directly processed and a data access operation is initiated to the PSRAM.
[0014] Furthermore, the transmission requirements include: an access address, an access sequence, and an access quantity to a target storage unit.
[0015] Furthermore, in combination with the historical matching of the PSRAM loop burst boundary and the bus burst transmission requirements, the implementation method of evaluating whether the PSRAM loop burst boundary needs to be adjusted involves the following three judgments:
[0016] First judgment: judge whether the current loop burst boundary of PSRAM is applicable to the current transmission demand; if applicable, it is considered that there is no need to adjust the loop burst boundary of PSRAM at present; otherwise, according to the mapping relationship between the preset transmission demand and the expected value of the PSRAM loop burst boundary, determine the expected value of the PSRAM loop burst boundary, and make a second judgment;
[0017] Second judgment: judge whether the current loop burst boundary of PSRAM is consistent with the determined expected value; if it is consistent, it is considered that there is no need to adjust the loop burst boundary of PSRAM at present; otherwise, count the number of consecutive appearances of the expected value in the historical data and make a third judgment;
[0018] The third judgment: judge whether the statistical result has reached the corresponding preset threshold; if it has reached the preset threshold, it is considered that the loop burst boundary of the PSRAM needs to be adjusted; otherwise, it is considered that the loop burst boundary of the PSRAM does not need to be adjusted.
[0019] Furthermore, the current loop burst boundary of the PSRAM is suitable for the transmission requirement in the following manner: the starting address of the current transmission request can be used as the address field for accessing the PSRAM, and all data required by the bus can be obtained in a single access process.
[0020] Furthermore, the mapping relationship between the preset transmission requirement and the expected value of the PSRAM loop burst boundary is:
[0021] For different types of INCR type burst transmission requirements, the expected value is uniformly set as Page Size;
[0022] For different types of WRAP type burst transfer requirements, it is assumed that in actual applications, the bus can initiate N types of WRAP type burst transfer requests, and each request corresponds to a PSRAM loop burst boundary parameter that can just meet its requirements. These parameter values together constitute parameter set C; if the bus only supports random initiation of WRAP type burst transfer requests, then the expected values of the PSRAM loop burst boundaries of various types of WRAP type burst transfer requirements are uniformly set to the maximum value in parameter set C; if the bus can relatively concentratedly initiate a certain type of WRAP type burst transfer request, then the expected values of the PSRAM loop burst boundaries of various types of WRAP type burst transfer requirements are respectively set to values that can just meet their respective requirements.
[0023] Furthermore, when the expected value of the PSRAM loop burst boundary is greater than the actual value, the corresponding preset threshold is A; when the expected value of the PSRAM loop burst boundary is less than the actual value, the corresponding preset threshold is B, then A <B。
[0024] Further, if it is considered that the loop burst boundary of the PSRAM needs to be adjusted currently, the adjustment target is its current expected value.
[0025] PSRAM control device, including:
[0026] The bus monitor is responsible for real-time monitoring of the matching degree between the actual value of the PSRAM loop burst boundary and the bus burst transmission demand, and judging whether the PSRAM loop burst boundary needs to be adjusted by analyzing the historical matching between the actual value of the PSRAM loop burst boundary and the expected value;
[0027] If adjustment is required, an adjustment request is made to the adjustment controller and an adjustment target is specified. After receiving a valid adjustment confirmation signal returned by the adjustment controller, the current loop burst boundary of the PSRAM is passed to the access controller. Otherwise, silence is maintained until the bus initiates the next burst transfer request.
[0028] The adjustment controller is responsible for controlling the interface module to adjust the loop burst boundary of the PSRAM to the adjustment target when the bus monitor believes that the loop burst boundary of the PSRAM needs to be adjusted, and returns a valid adjustment confirmation signal to the bus monitor; otherwise, it remains silent;
[0029] The access controller is responsible for analyzing and responding to the bus transmission signal in combination with the actual value of the PSRAM loop burst boundary when the adjustment controller does not adjust the PSRAM loop burst boundary, and realizing the data access to the PSRAM through the control interface module; otherwise, it remains silent until the adjustment process is completed;
[0030] Interface module: responsible for the operation of the routing adjustment controller and the access controller to the PSRAM.
[0031] An electronic device comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor can implement a PSRAM control method when executing the computer program.
[0032] Compared with the prior art, the present invention has the following beneficial effects:
[0033] When the bus initiates a new burst transfer request, based on the historical matching of the PSRAM loop burst boundary and the bus burst transfer demand, it is evaluated whether the PSRAM loop burst boundary needs to be adjusted. If adjustment is required, the operation of modifying the loop burst boundary is first initiated to the PSRAM, and then the transmission demand is processed and the data access operation is initiated to the PSRAM; if no adjustment is required, the transmission demand is directly processed and the data access operation is initiated to the PSRAM.
[0034] In the specific implementation process, the PSRAM controller of the present invention can autonomously adjust the loop burst boundary of the PSRAM according to the regularity of the bus behavior. Starting from the hardware level, it realizes that the parameter is highly consistent with the bus transmission requirements within a specific time period, which not only gives full play to the hardware performance of the PSRAM, but also improves the efficiency of bus access to the PSRAM, and retains the transparency of the hardware interface to the software application level, that is, avoiding the CPU's polling and configuration of its internal loop burst boundary each time the PSRAM is accessed, which is of great value for products with multiple Master concurrent access scenarios. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] Figure 1 It is the flow chart of PSRAM control method;
[0036] Figure 2 A flow chart of a method for evaluating whether to adjust the PSRAM loop burst boundary;
[0037] Figure 3 Schematic diagram of the PSRAM device structure. DETAILED DESCRIPTION
[0038] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.
[0039] like Figure 1 As shown, the PSRAM control method includes:
[0040] When the bus initiates a new transfer request, the bus signal is analyzed to determine the transfer requirements, including but not limited to the access address, access order, and access quantity of the target storage unit. Based on the historical matching of the PSRAM loop burst boundary and the bus burst transfer requirements, it is evaluated whether the PSRAM loop burst boundary needs to be adjusted.
[0041] If the loop burst boundary of the PSRAM needs to be adjusted, the operation of modifying the loop burst boundary is first initiated to the PSRAM, and then the transmission demand is processed and the data access operation is initiated to the PSRAM;
[0042] If there is no need to adjust the loop burst boundary of the PSRAM, the transmission requirement is directly processed and a data access operation is initiated to the PSRAM.
[0043] like Figure 2 As shown in the figure, the evaluation process of whether to adjust the PSRAM loop burst boundary mainly involves the following three key judgments:
[0044] First judgment: judge whether the current loop burst boundary of PSRAM is applicable to the current transmission requirement, that is, whether the starting address of the current transmission request can be used as the address field to access PSRAM and obtain all the data required by the bus in a single access process. If applicable, it is considered that there is no need to adjust the loop burst boundary of PSRAM at present; otherwise, the expected value of the PSRAM loop burst boundary is determined according to the mapping relationship between the preset transmission requirement and the expected value of the PSRAM loop burst boundary, and a second judgment is performed.
[0045] The mapping relationship between the preset transmission requirement and the expected value of the PSRAM loop burst boundary is:
[0046] In order to meet the transmission requirements of address misalignment, for different types of INCR type burst transmission requirements, the expected values of the PSRAM loop burst boundaries are uniformly set to Page Size.
[0047] In order to prevent the bus access efficiency to PSRAM from being reduced due to frequent adjustment of the PSRAM loop burst boundary, the setting of the expected value of the PSRAM loop burst boundary is related to the actual capacity of the bus for different types of WRAP burst transmission requirements, as follows:
[0048] Assume that in actual applications, the bus can initiate N types of WRAP-type burst transfer requests, and each request corresponds to a PSRAM loop burst boundary parameter that can just meet its needs, and these parameter values together constitute parameter set C; if the bus only supports random initiation of WRAP-type burst transfer requests, then the expected values of the PSRAM loop burst boundaries of various WRAP-type burst transfer requirements are uniformly set to the maximum value in parameter set C; if the bus can relatively concentratedly initiate a certain type of WRAP-type burst transfer request, then the expected values of the PSRAM loop burst boundaries of various WRAP-type burst transfer requirements are respectively set to values that can just meet their respective specific needs.
[0049] Second judgment: judge whether the expected value is consistent with the actual value. If they are consistent, it is considered that there is no need to adjust the loop burst boundary of the PSRAM at present; if they are inconsistent, the number of consecutive appearances of the expected value in the historical data is counted, and the statistical result reflects the historical matching of the PSRAM loop burst boundary and the bus transmission demand, and a third judgment is performed.
[0050] The third judgment: judge whether the statistical result has reached the corresponding preset threshold. If it has reached the preset threshold, it is considered that the loop burst boundary of the PSRAM needs to be adjusted, and the adjustment target is the expected value; if it has not reached the preset threshold, it is considered that there is no need to adjust the loop burst boundary of the PSRAM.
[0051] It should be noted that, since there are multiple combinations of expected values and actual values of the PSRAM loop burst boundary, a corresponding preset threshold needs to be set for each different combination.
[0052] When the expected value of the PSRAM loop burst boundary is greater than the actual value, the preset threshold value A should be lower than the preset threshold value B set when the expected value of the PSRAM loop burst boundary is less than the actual value. This can not only reduce the frequent adjustment of the PSRAM loop burst boundary, but also try to ensure that the parameter can match the bus transmission requirements. This is because, compared with a relatively large loop burst boundary, a relatively small loop burst boundary will have a more significant negative impact on the efficiency of bus access to PSRAM. When the loop burst boundary is relatively small, the system needs to frequently activate the PSRAM to complete the entire data transmission process. On the contrary, a relatively large loop burst boundary allows the system to obtain all the required data in one access through data caching, address splicing, etc.
[0053] The following is an example of a specific SoC system to illustrate the above process. In the SoC system, the bus can initiate the following types of burst transfer requests to the PSRAM: INCR, INCR4, INCR8, WRAP4, WRAP8. Depending on the actual application scenario, the expected values of the above five types of transfer requests are set as follows:
[0054] Actual application scenarios INCR INCR4 INCR8 WRAP4 WRAP8 The bus can only randomly initiate WRAP type transfer requests Page Size Page Size Page Size 32Bytes 32Bytes The bus can initiate a certain type of WRAP transfer request more centrally Page Size Page Size Page Size 16Bytes 32Bytes
[0055] If the bus can only randomly initiate WRAP type transfer requests, according to different combinations of actual and expected values of the PSRAM loopback burst boundary, the corresponding preset thresholds are as follows, where X and Y are both positive integers and X > Y:
[0056] Actual value Expected value Preset Threshold Actual value Expected value Preset Threshold Page Size 32Bytes X 32Bytes Page Size Y
[0057] When the actual value of the PSRAM loop burst boundary is Page Size, if a WRAP4 / WRAP8 transfer request is received, that is, the expected value is 32Bytes, and before this request, the expected value has appeared X-1 times in a row, the system will consider it necessary to adjust the PSRAM loop burst boundary to the expected value, that is, 32Bytes; conversely, if the above conditions are not met, the system considers that there is no need to adjust the PSRAM loop burst boundary. When the actual value of the PSRAM loop burst boundary is 32Bytes, the system's processing logic is the same, and it will not be repeated here.
[0058] Figure 3 This is a structural diagram of the PSRAM control device, which mainly includes four core components: bus monitor, adjustment controller, access controller, and interface module.
[0059] The bus monitor is responsible for real-time monitoring of the matching degree between the actual value of the PSRAM loop burst boundary and the bus burst transmission demand, and judging whether the PSRAM loop burst boundary needs to be adjusted at present by analyzing the historical matching between the actual value of the PSRAM loop burst boundary and the expected value. The specific implementation method of the judgment process can be referred to the embodiment of the PSRAM control method mentioned above, which will not be repeated here.
[0060] If adjustment is required, an adjustment request is made to the adjustment controller and the adjustment target is specified. After receiving the valid adjustment confirmation signal returned by the adjustment controller, the current loop burst boundary of the PSRAM is passed to the access controller; otherwise, it remains silent until the bus initiates the next burst transfer request.
[0061] The adjustment controller is responsible for controlling the interface module to adjust the loop burst boundary of the PSRAM to the adjustment target when the bus monitor believes that the loop burst boundary of the PSRAM needs to be adjusted to ensure that the adjustment process meets the timing requirements specified in the manual. Subsequently, the adjustment controller will return a valid adjustment confirmation signal to the bus monitor; otherwise, it will remain silent.
[0062] The access controller is responsible for parsing and responding to the bus transmission signal in combination with the actual value of the PSRAM loop burst boundary when the adjustment controller does not adjust the PSRAM loop burst boundary, and realizing data access to the PSRAM through the control interface module to ensure that the access process can strictly follow the timing requirements specified in the manual; otherwise, it remains silent until the adjustment process is completed.
[0063] The interface module is responsible for the operation of the routing adjustment controller and the access controller to the PSRAM.
[0064] An electronic device comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor can implement a PSRAM control method when executing the computer program.
Claims
1. A PSRAM control method, characterized in that: include: When the bus initiates a new transmission request, the bus signal is parsed to determine the current transmission requirements, and combined with the historical matching of the PSRAM loop burst boundary and the bus burst transmission requirements, it is evaluated whether the PSRAM loop burst boundary needs to be adjusted at present; If the loop burst boundary of the PSRAM needs to be adjusted, the operation of modifying the loop burst boundary is first initiated to the PSRAM, and then the transmission demand is processed and the data access operation is initiated to the PSRAM; If there is no need to adjust the loop burst boundary of the PSRAM, the transmission requirement is directly processed and a data access operation is initiated to the PSRAM.
2. The PSRAM control method according to claim 1, characterized in that: The transmission requirements include: the access address, access sequence and access quantity of the target storage unit.
3. The PSRAM control method according to claim 1, characterized in that: Combined with the historical matching of the PSRAM loop burst boundary and the bus burst transmission requirements, the evaluation of whether the PSRAM loop burst boundary needs to be adjusted involves the following three judgments: First judgment: judge whether the current loop burst boundary of PSRAM is applicable to the current transmission demand; if applicable, it is considered that there is no need to adjust the loop burst boundary of PSRAM at present; otherwise, according to the mapping relationship between the preset transmission demand and the expected value of the PSRAM loop burst boundary, determine the expected value of the PSRAM loop burst boundary, and make a second judgment; Second judgment: judge whether the current loop burst boundary of PSRAM is consistent with the determined expected value; if it is consistent, it is considered that there is no need to adjust the loop burst boundary of PSRAM at present; otherwise, count the number of consecutive appearances of the expected value in the historical data and make a third judgment; The third judgment: judge whether the statistical result has reached the corresponding preset threshold; if it has reached the preset threshold, it is considered that the loop burst boundary of the PSRAM needs to be adjusted; otherwise, it is considered that the loop burst boundary of the PSRAM does not need to be adjusted.
4. The PSRAM control method according to claim 3, characterized in that: The current loop burst boundary of the PSRAM is suitable for the transmission demand in the following manner: the starting address of the current transmission request can be used as the address field for accessing the PSRAM, and all the data required by the bus can be obtained during a single access.
5. The PSRAM control method according to claim 3, characterized in that: The mapping relationship between the preset transmission requirements and the expected value of the PSRAM loop burst boundary is: For different types of INCR type burst transmission requirements, the expected value is uniformly set as Page Size; For different types of WRAP type burst transfer requirements, it is assumed that in actual applications, the bus can initiate N types of WRAP type burst transfer requests, and each request corresponds to a PSRAM loop burst boundary parameter that can just meet its requirements. These parameter values together constitute parameter set C; if the bus only supports random initiation of WRAP type burst transfer requests, then the expected values of the PSRAM loop burst boundaries of various types of WRAP type burst transfer requirements are uniformly set to the maximum value in parameter set C; if the bus can relatively concentratedly initiate a certain type of WRAP type burst transfer request, then the expected values of the PSRAM loop burst boundaries of various types of WRAP type burst transfer requirements are respectively set to values that can just meet their respective requirements.
6. The PSRAM control method according to claim 3, characterized in that: Suppose that when the expected value of the PSRAM loop burst boundary is greater than the actual value, the corresponding preset threshold is A; when the expected value of the PSRAM loop burst boundary is less than the actual value, the corresponding preset threshold is B, then A <B。 7. The PSRAM control method according to claim 3, characterized in that: If it is considered that the loop burst boundary of the PSRAM needs to be adjusted currently, the adjustment target is its current expected value.
8. A PSRAM control device, characterized in that: include: The bus monitor is responsible for real-time monitoring of the matching degree between the actual value of the PSRAM loop burst boundary and the bus burst transmission demand, and judging whether the PSRAM loop burst boundary needs to be adjusted by analyzing the historical matching between the actual value of the PSRAM loop burst boundary and the expected value; If adjustment is required, an adjustment request is made to the adjustment controller and an adjustment target is specified. After receiving a valid adjustment confirmation signal returned by the adjustment controller, the current loop burst boundary of the PSRAM is passed to the access controller. Otherwise, silence is maintained until the bus initiates the next burst transfer request. The adjustment controller is responsible for controlling the interface module to adjust the loop burst boundary of the PSRAM to the adjustment target when the bus monitor believes that the loop burst boundary of the PSRAM needs to be adjusted, and returns a valid adjustment confirmation signal to the bus monitor; otherwise, it remains silent; The access controller is responsible for analyzing and responding to the bus transmission signal in combination with the actual value of the PSRAM loop burst boundary when the adjustment controller does not adjust the PSRAM loop burst boundary, and realizing the data access to the PSRAM through the control interface module; otherwise, it remains silent until the adjustment process is completed; Interface module: responsible for the operation of the routing adjustment controller and the access controller to the PSRAM.
9. An electronic device, characterized in that The invention comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor can implement the PSRAM control method as claimed in any one of claims 1 to 7 when executing the computer program.