Data transmission circuit and method based on data disassembly

Abstract

The invention discloses a data transmission circuit and method based on data disassembly, the data transmission circuit comprises a data splitter, a data memory, a data transmitter and a data receiving controller, the data splitter is used for splitting received data to form a plurality of data units; the data memory is connected with the data splitter, receives and stores the data unit sent by the data splitter, and generates a corresponding first pointer signal at the same time; the data transmitter is connected with the data memory, reads data from the data memory and generates a corresponding second pointer signal at the same time; and the data receiving controller is connected with the data memory and the data transmitter respectively, receives the first pointer signal and the second pointer signal and judges whether data can be received according to the first pointer signal and the second pointer signal. According to the invention, the multi-bit data is disassembled into a plurality of data units, and whether to receive new data is selected according to the dynamic change of the actual demand, so that the data access speed and the data transmission efficiency are improved, the bus competition is reduced, and the energy consumption is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of data transmission, and in particular relates to a data transmission circuit and method based on data disassembly. Background Art

[0002] In a multi-core processor system, if the data transmission between processors is too slow, it may increase the bus contention between processors, resulting in a decrease in the overall throughput and response speed of the multi-core processor system. There are often problems with multi-bit high-speed data cache and low-speed data output in digital logic circuits. To solve this problem, the prior art proposes to use dual-port RAM or specific FIFO buffers to achieve data caching and transmission, but the solutions of the prior art generally have the following problems: (1) Direct access to multi-bit parallel data may cause delays when retrieving data from distant memory addresses; (2) Frequent storage and retrieval of data leads to increased overall power consumption; (3) The storage of data cannot be controlled according to the specific status. Summary of the invention

[0003] In response to the above problems, the present invention proposes a data transmission circuit and method based on data decomposition, which decomposes multi-bit data into multiple data units, and then chooses whether to receive new data according to the dynamic changes in actual needs, thereby improving data access speed, reducing bus contention, improving data transmission efficiency and reducing energy consumption.

[0004] In order to achieve the above technical objectives and the above technical effects, the present invention is implemented through the following technical solutions: In a first aspect, the present invention provides a data transmission circuit based on data disassembly, comprising: A data splitter, used to split the received data into several data units; A data storage device, connected to the data splitter, receives and stores the data units sent by the data splitter, and generates a corresponding first pointer signal; A data transmitter, connected to the data storage device, reads data from the data storage device and generates a corresponding second pointer signal; The data receiving controller is connected to the data storage device and the data transmission device respectively, receives and determines whether the data storage device can receive data according to the first pointer signal and the second pointer signal.

[0005] In combination with the first aspect, optionally, the lengths of the data units are equal.

[0006] In combination with the first aspect, optionally, the depth of the data storage is set to a multiple of the size of the disassembled data unit, and the first pointer signal is incremented by 1 each time a data unit is stored.

[0007] In combination with the first aspect, optionally, each time a data unit is read out from the data transmitter, the second pointer signal is incremented by 1.

[0008] In combination with the first aspect, optionally, when the numerical relationship between the first pointer signal and the second pointer signal satisfies any of the following conditions, the data receiving controller sends a signal to an external device to notify the external device to send data to the data splitter: Condition (1): the value of the first pointer signal is within the depth range of the data memory, and the value of the second pointer signal is smaller than the value of the first pointer signal; Condition (2): The value of the second pointer signal is within the depth range of the data memory, and the value of the first pointer signal is smaller than the value of the second pointer signal.

[0009] In a second aspect, the present invention provides a data transmission method based on data disassembly, comprising: Using a data splitter to split the received data into several data units; Using a data storage device connected to the data splitter, receiving and storing the data unit sent by the data splitter, and generating a corresponding first pointer signal; Using a data transmitter connected to the data storage device, reading data from the data storage device and generating a corresponding second pointer signal; A data receiving controller connected to the data storage device and the data transmission device is used to receive and determine whether data can be received according to the first pointer signal and the second pointer signal.

[0010] In combination with the second aspect, optionally, the lengths of the data units are equal.

[0011] In combination with the second aspect, optionally, the depth of the data storage is set to a multiple of the size of the disassembled data unit, and the first pointer signal is incremented by 1 each time a data unit is stored.

[0012] In combination with the second aspect, optionally, each time a data unit is read out from the data transmitter, the second pointer signal is incremented by 1.

[0013] In combination with the second aspect, optionally, when the numerical relationship between the first pointer signal and the second pointer signal satisfies any of the following conditions, the data receiving controller sends a signal to an external device to notify the external device to send data to the data splitter: Condition (1): the value of the first pointer signal is within the depth range of the data memory, and the value of the second pointer signal is smaller than the value of the first pointer signal; Condition (2): The value of the second pointer signal is within the depth range of the data memory, and the value of the first pointer signal is smaller than the value of the second pointer signal.

[0014] Compared with the prior art, the present invention has the following beneficial effects: The present invention first needs to split the multi-bit data to form a number of data units. Secondly, the processed data units are stored in a data storage device. While storing the data units, the data storage device will generate a first pointer signal (i.e., the storage pointer of the data storage device increases as required); when the data units in the data storage device are read out by the data transmission device, the data transmission device will generate a second pointer signal (i.e., the read pointer of the data transmission device increases as required). Finally, the relationship between the first pointer signal and the second pointer signal is calculated by the data receiving controller to control whether the data storage device accepts new data, thereby improving data access speed, reducing bus competition, improving data transmission efficiency and reducing energy consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative labor, among which: Figure 1 A circuit diagram of a data transmission circuit based on data disassembly according to an embodiment of the present invention; Figure 2 The present invention is a flowchart of a data transmission method based on data disassembly according to an embodiment of the present invention. DETAILED DESCRIPTION

[0016] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0017] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or suggesting their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention. Example

[0018] The present invention provides a data transmission circuit based on data disassembly, such as Figure 1 As shown, it includes: a data splitter, a data storage device, a data transmitter and a data receiving controller; The data splitter is used to split the received data into several data units; The data storage device is connected to the data splitter, receives and stores the data unit sent by the data splitter, and generates a corresponding first pointer signal; The data transmitter is connected to the data storage device, reads data from the data storage device, and generates a corresponding second pointer signal; The data receiving controller is connected to the data storage device and the data transmission device respectively, receives and determines whether the data storage device can receive data according to the first pointer signal and the second pointer signal.

[0019] The data transmission circuit based on data disassembly in the embodiment of the present invention first needs to split the multi-bit data to form a number of data units. Secondly, the processed data unit is stored in the data storage device. While storing the data unit, the data storage device will generate a first pointer signal (that is, the storage pointer of the data storage device increases as required); when the data unit in the data storage device is read out by the data transmission device, the data transmission device will generate a second pointer signal (that is, the read pointer of the data transmission device increases as required). Finally, the relationship between the first pointer signal and the second pointer signal is calculated by the data receiving controller to control whether the data storage device accepts new data, thereby improving data access speed, reducing bus contention, improving data transmission efficiency and reducing energy consumption.

[0020] In a specific implementation of an embodiment of the present invention, in order to facilitate the operation of the data splitter, the lengths of the data units are equal.

[0021] In a specific implementation of the embodiment of the present invention, the depth of the data storage is set to a multiple of the size of the disassembled data unit, and the first pointer signal increases by 1 each time a data unit is stored.

[0022] In a specific implementation manner of the embodiment of the present invention, the second pointer signal is incremented by 1 each time a data unit is read out from the data transmitter.

[0023] In a specific implementation of the embodiment of the present invention, when the numerical relationship between the first pointer signal and the second pointer signal satisfies any of the following conditions, the data receiving controller sends a signal to the external device to notify the external device to send data to the data splitter, so as to realize the dynamic change of selecting whether to receive new data according to actual needs: Condition (1): the value of the first pointer signal is within the depth range of the data memory, and the value of the second pointer signal is smaller than the value of the first pointer signal; Condition (2): the value of the second pointer signal is within the depth range of the data memory, and the value of the first pointer signal is smaller than the value of the second pointer signal; This operation can prevent the unoutput data in the data storage module from being overwritten or lost by mistake. It can also prevent the output data in the data storage module from not being overwritten and the module data from being received untimely.

[0024] The following is based on Figure 1 The working principle of a data transmission circuit based on data disassembly in an embodiment of the present invention is described in detail in conjunction with a specific implementation manner.

[0025] Figure 1 vld: represents a pulse signal. A pulse signal is generated every time a data is received.

[0026] Figure 1 rdy: Indicates that high level is valid. It is high level when ready to receive data, otherwise it is low level.

[0027] 1) Get a data through the handshake process with the data output module.

[0028] For example, the data transmission between the SRAM controller (i.e., data storage) and the SPI module (i.e., data transmitter) is performed through a handshake process to obtain a 32-bit data.

[0029] The handshake process is formed by the dynamic changes of 4 signals: spi_rdy: The SRAM controller is ready to transmit data outward, and the high level is valid.

[0030] sram_vld: The flag of the SRAM controller transmitting data outward. A pulse signal is generated every time a data is transmitted.

[0031] spi_vld: The SPI module needs the SRAM controller to transfer data. Each time a pulse signal is generated, an address is output.

[0032] sram_rdy: The SPI module can receive external data, and high level is valid.

[0033] According to actual needs, the data output in step 1) is split into several parts, that is, into several data units.

[0034] For example, the data splitter splits the 32-bit data in step 1) into four 8-bit data (ie, splits the 32-bit data into four data units of 8 bits each).

[0035] The data units obtained after the splitting are stored in a data storage device (in the specific implementation process, a register, i.e., an SRAM controller, can be selected), and the depth of the register is set to a multiple of the size of the data unit after the splitting. Each time a data unit is stored, the register pointer is incremented.

[0036] For example, the 8-bit data unit in step 2) is stored in the data memory, and the data memory depth is set to 8. Each time an 8-bit data unit is stored, the register pointer [7:0] sram_rd_data_ptr is incremented.

[0037] Each time the data transmitter (ie, SPI module) reads a data unit from the data memory, the read pointer increments.

[0038] For example: the data transmitter reads out the 8-bit data units in the data memory in sequence, and each time an 8-bit data unit is read out, the read pointer [7:0] spi_rd_data_ptr increases.

[0039] The data receiving controller controls whether to receive new data by judging the relationship between the register pointer and the read pointer.

[0040] For example: the pointer signals of sram_rd_data_ptr and spi_rd_data_ptr both start increasing from 0. Since 8-bit data are stored 8 at a time and the read data are read out sequentially, the storage rate is much higher than the read rate.

[0041] Determine the numerical relationship between the register pointer and the read pointer based on specific needs to control whether to receive new data: The data receiving controller notifies the external device data memory whether it receives data through the two signals wr_addr_rdy and wr_data_vld. Example

[0042] The embodiment of the present invention provides a data transmission method based on data disassembly, such as Figure 2 As shown, the following steps are included: (1) Use a data splitter to split the received data into several data units; (2) using a data storage device connected to the data splitter to receive and store the data unit sent by the data splitter, and generating a corresponding first pointer signal; (3) reading data from the data storage device using a data transmitter connected to the data storage device, and generating a corresponding second pointer signal; (4) Using a data receiving controller connected to the data storage device and the data transmission device respectively, receiving and judging whether data can be received according to the first pointer signal and the second pointer signal.

[0043] The data transmission method based on data disassembly in the embodiment of the present invention first needs to split the multi-bit data to form a number of data units. Secondly, the processed data unit is stored in the data storage device. While storing the data unit, the data storage device will generate a first pointer signal (that is, the storage pointer of the data storage device increases as required); when the data unit in the data storage device is read out by the data transmission device, the data transmission device will generate a second pointer signal (that is, the read pointer of the data transmission device increases as required). Finally, the relationship between the first pointer signal and the second pointer signal is calculated by the data receiving controller to control whether the data storage device accepts new data, thereby improving data access speed, reducing bus contention, improving data transmission efficiency and reducing energy consumption.

[0044] In a specific implementation of an embodiment of the present invention, in order to facilitate the operation of the data splitter, the lengths of the data units are equal.

[0045] In a specific implementation of the embodiment of the present invention, the depth of the data storage is set to a multiple of the size of the disassembled data unit, and the first pointer signal increases by 1 each time a data unit is stored.

[0046] In a specific implementation manner of the embodiment of the present invention, the second pointer signal is incremented by 1 each time a data unit is read out from the data transmitter.

[0047] In a specific implementation of the embodiment of the present invention, when the numerical relationship between the first pointer signal and the second pointer signal satisfies any of the following conditions, the data receiving controller sends a signal to the external device to notify the external device to send data to the data splitter, so as to realize the dynamic change of selecting whether to receive new data according to actual needs: Condition (1): the value of the first pointer signal is within the depth range of the data memory, and the value of the second pointer signal is smaller than the value of the first pointer signal; Condition (2): the value of the second pointer signal is within the depth range of the data memory, and the value of the first pointer signal is smaller than the value of the second pointer signal; This operation can prevent the unoutput data in the data storage module from being overwritten or lost by mistake. It can also prevent the output data in the data storage module from not being overwritten and the module data from being received untimely.

[0048] The following is based on Figure 1 The working principle of a data transmission circuit based on data disassembly in an embodiment of the present invention is described in detail in conjunction with a specific implementation manner.

[0049] Figure 1 vld: represents a pulse signal. A pulse signal is generated every time a data is received.

[0050] Figure 1 rdy: Indicates that high level is valid. It is high level when ready to receive data, otherwise it is low level.

[0051] 1) Get a data through the handshake process with the data output module.

[0052] For example, the data transmission between the SRAM controller (i.e., data storage) and the SPI module (i.e., data transmitter) is performed through a handshake process to obtain a 32-bit data.

[0053] The handshake process is formed by the dynamic changes of 4 signals: spi_rdy: The SRAM controller is ready to transmit data outward, and the high level is valid.

[0054] sram_vld: The flag of the SRAM controller transmitting data outward. A pulse signal is generated every time a data is transmitted.

[0055] spi_vld: The SPI module needs the SRAM controller to transfer data. Each time a pulse signal is generated, an address is output.

[0056] sram_rdy: The SPI module can receive external data, and high level is valid.

[0057] According to actual needs, the data output in step 1) is split into several parts, that is, into several data units.

[0058] For example, the data splitter splits the 32-bit data in step 1) into four 8-bit data (ie, splits the 32-bit data into four data units of 8 bits each).

[0059] The data units obtained after the splitting are stored in a data storage device (in the specific implementation process, a register, i.e., an SRAM controller, can be selected), and the depth of the register is set to a multiple of the size of the data unit after the splitting. Each time a data unit is stored, the register pointer is incremented.

[0060] For example, the 8-bit data unit in step 2) is stored in the data memory, and the data memory depth is set to 8. Each time an 8-bit data unit is stored, the register pointer [7:0] sram_rd_data_ptr is incremented.

[0061] Each time the data transmitter (ie, SPI module) reads a data unit from the data memory, the read pointer increments.

[0062] For example: the data transmitter reads out the 8-bit data units in the data memory in sequence, and each time an 8-bit data unit is read out, the read pointer [7:0] spi_rd_data_ptr increases.

[0063] The data receiving controller controls whether to receive new data by judging the relationship between the register pointer and the read pointer.

[0064] For example: the sram_rd_data_ptr and spi_rd_data_ptr pointer signals both start increasing from 0. Since 8-bit data is stored 8 at a time and the read data is read out sequentially, the storage rate is much higher than the read rate.

[0065] Determine the numerical relationship between the register pointer and the read pointer based on specific needs to control whether to receive new data: The data receiving controller notifies the external device data memory whether it receives data through the two signals wr_addr_rdy and wr_data_vld.

[0066] In summary, the data transmission circuit and method based on data disassembly in the present invention have the following advantages: (1) Speed ​​and performance optimization: In the context of existing digital logic circuit design, directly accessing multi-bit parallel data may cause delays when obtaining data from a distant memory address.

[0067] The present invention is specially designed to store and transmit data or states pre-calculated by specific other modules. These data can be used immediately when needed without further calculation or combinational logic operations, thereby improving the response speed and performance of the overall circuit.

[0068] (2) Circuit simplification and power consumption optimization: Compared to frequently storing and retrieving data, the present invention can generally provide faster data access with lower power consumption, which is particularly important for devices that rely on battery power or need to reduce energy consumption.

[0069] The present invention can reduce the number and complexity of complex combinational logic required in the circuit by utilizing the data receiving controller to output a handshake signal to achieve the purpose of controlling the reception and storage of data. This not only reduces the complexity of the circuit, but also reduces power consumption, because accessing pre-stored data is usually more efficient than recalculating.

[0070] (3) Flexibility and control: In the existing common storage transmission logic circuit design, the storage of data cannot be controlled according to the specific state.

[0071] The present invention can detect the data relationship between the first pointer and the second pointer through the data receiving module to determine whether it is currently necessary to store the control signal, status information or other data that needs to be used periodically input by the external module. By cooperating with the handshake signal or other tools of other modules, more flexible and precise control can be achieved.

[0072] (4) Data reuse and reliability: In some applications, there is data that needs to be processed repeatedly in the digital logic circuit design, but the existing digital design may not be able to store this data.

[0073] The present invention can determine whether the first pointer signal and the second pointer signal meet any of the following relationships through a data receiving controller: ① The value of the first pointer signal is within the depth range of the data storage device, and the value of the second pointer signal is less than the value of the first pointer signal. ② The value of the second pointer signal is within the depth range of the data storage device, and the value of the first pointer signal is less than the value of the second pointer signal. If the conditions are met, commonly used data or processed data fragments can be stored for reuse when needed, which improves the reliability and stability of the system because it can ensure that repeated operations obtain the same results.

[0074] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0075] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0076] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0077] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0078] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the enlightenment of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the purpose of the present invention and the claims, which all fall within the protection of the present invention.

[0079] The above shows and describes the basic principles and main features of the present invention and the advantages of the present invention. It should be understood by those skilled in the art that the present invention is not limited to the above embodiments. The above embodiments and descriptions are only for explaining the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, which fall within the scope of the present invention to be protected. The scope of protection of the present invention is defined by the attached claims and their equivalents.

Claims

1. A data transmission circuit based on data disassembly, characterized in that: include: A data splitter, used to split the received data into several data units; A data storage device, connected to the data splitter, receives and stores the data units sent by the data splitter, and generates a corresponding first pointer signal; A data transmitter, connected to the data storage device, reads data from the data storage device and generates a corresponding second pointer signal; The data receiving controller is connected to the data storage device and the data transmission device respectively, receives and determines whether the data storage device can receive data according to the first pointer signal and the second pointer signal.

2. A data transmission circuit based on data disassembly according to claim 1, characterized in that: The length of each data unit is equal.

3. A data transmission circuit based on data disassembly according to claim 1 or 2, characterized in that: The depth of the data storage device is set to a multiple of the size of the disassembled data unit, and the first pointer signal increases by 1 each time a data unit is stored.

4. A data transmission circuit based on data disassembly according to claim 1 or 2, characterized in that: Each time a data unit is read out from the data transmitter, the second pointer signal increases by 1.

5. The data transmission circuit based on data disassembly according to claim 1, characterized in that: When the numerical relationship between the first pointer signal and the second pointer signal satisfies any of the following conditions, the data receiving controller sends a signal to the external device to notify the external device to send data to the data splitter: Condition (1): the value of the first pointer signal is within the depth range of the data memory, and the value of the second pointer signal is smaller than the value of the first pointer signal; Condition (2): The value of the second pointer signal is within the depth range of the data memory, and the value of the first pointer signal is smaller than the value of the second pointer signal.

6. A data transmission method based on data disassembly, characterized in that: include: Using a data splitter to split the received data into several data units; Using a data storage device connected to the data splitter, receiving and storing the data unit sent by the data splitter, and generating a corresponding first pointer signal; Using a data transmitter connected to the data storage device, reading data from the data storage device and generating a corresponding second pointer signal; A data receiving controller connected to the data storage device and the data transmission device is used to receive and determine whether data can be received according to the first pointer signal and the second pointer signal.

7. A data transmission method based on data disassembly according to claim 6, characterized in that: The length of each data unit is equal.

8. A data transmission method based on data disassembly according to claim 6 or 7, characterized in that: The depth of the data storage device is set to a multiple of the size of the disassembled data unit, and the first pointer signal increases by 1 each time a data unit is stored.

9. A data transmission method based on data disassembly according to claim 6 or 7, characterized in that: Each time a data unit is read out from the data transmitter, the second pointer signal increases by 1.

10. The data transmission method based on data disassembly according to claim 6, characterized in that: When the numerical relationship between the first pointer signal and the second pointer signal satisfies any of the following conditions, the data receiving controller sends a signal to the external device to notify the external device to send data to the data splitter: Condition (1): the value of the first pointer signal is within the depth range of the data memory, and the value of the second pointer signal is smaller than the value of the first pointer signal; Condition (2): The value of the second pointer signal is within the depth range of the data memory, and the value of the first pointer signal is smaller than the value of the second pointer signal.

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