State machine verification method, device and system, storage medium and electronic equipment

Abstract

The invention provides a state machine verification method, device and system, a storage medium and electronic equipment, and is applied to the technical field of chip design and verification. The method comprises the steps that a state machine model of the digital chip is obtained, a verification set containing a plurality of signal combination sequences is obtained, and the signal combination sequences are generated by conducting cross combination on input signals of the state machine model. And in the target state jump link, traversing all signal combination sequences of the verification set, and recording a static traversal verification result and a test excitation record result. And when a static traversal verification result shows that all link function coverage points are hit, inputting a signal combination sequence which hits the link function coverage points in a test excitation record result into a state machine model and a tested state machine for dynamic simulation verification, and finally obtaining a state machine verification result of the digital chip. And all possible effective links of the state machine are ensured to be correctly covered, so that the comprehensiveness and integrity of verification of the state machine are improved.

Description

Technical Field

[0001] The present invention relates to the field of chip design and verification technology, and in particular to a state machine verification method, device, system, storage medium and electronic device. Background Art

[0002] In modern digital chip design, state machine logic design is one of the most commonly used logics in the chip and is usually the core part of the logic in chip design. Therefore, the design and verification quality of the state machine often directly affects the quality of the entire chip.

[0003] Existing methods usually use random simulation tests and state machine code coverage to ensure verification quality. However, although this conventional verification method can show whether there are jumps between states, it cannot ensure that all possible valid links are correctly covered. This means that although there may be jumps between two states in the state machine, it is impossible to verify whether these jumps cover all possible paths and scenarios.

[0004] Therefore, how to ensure that all possible valid links are correctly covered in state machine verification has become a technical problem that technical personnel in this field need to solve urgently. Summary of the invention

[0005] In view of the above problems, the present invention provides a state machine verification method, device, system, storage medium and electronic device that overcome the above problems or at least partially solve the above problems. The technical solution is as follows:

[0006] A state machine verification method, comprising:

[0007] Obtaining a state machine model of a digital chip, wherein the state machine model is used to simulate the behavior logic of the state machine under test of the digital chip;

[0008] Obtaining a signal combination sequence verification set of the state machine model, wherein the signal combination sequence verification set includes a plurality of signal combination sequences obtained by cross-combining signal values ​​of a plurality of input signals of the state machine model;

[0009] In the target state jump link of the state machine model, traverse each of the signal combination sequences in the signal sequence verification set to obtain a static traversal verification result and a test stimulus record result of the target state jump link, wherein the test stimulus record result records the signal combination sequence that hits any link function coverage point in the target state jump link;

[0010] When the static traversal verification result shows that all the link function coverage points in the target state jump link have been hit, the signal combination sequence in the test stimulus record result is respectively input into the state machine model and its corresponding state machine under test for dynamic simulation verification to obtain the state machine verification result of the digital chip.

[0011] Optionally, the step of inputting the signal combination sequence in the test stimulus record result into the state machine model and its corresponding state machine under test for dynamic simulation verification to obtain the state machine verification result of the digital chip includes:

[0012] In the test stimulus recording result, each of the signal combination sequences is selected in turn and simultaneously input into the state machine model and its corresponding state machine under test, and the state machine model and the state machine under test are run in a simulation environment, the link function coverage of the state machine model is recorded, and the first state transition behavior information of the state machine model and the second state transition behavior information of the state machine under test are obtained;

[0013] Using the first state transition behavior information and the second state transition behavior information, compare whether the state machine model and the state machine under test have consistent state transition behaviors, and obtain a function verification result of the state machine under test;

[0014] The link function coverage and the function verification result are summarized, and the state machine verification result of the digital chip is output.

[0015] Optionally, the test stimulus recording result records only one hit signal combination sequence for each link function coverage point.

[0016] Optionally, the method further includes:

[0017] When the static traversal verification result is that there is a link function coverage point in the target state jump link that has not been hit, outputting first deadlock risk prompt information, wherein the first deadlock risk prompt information is used to prompt that there is a cyclic deadlock and / or conditional deadlock in the target state jump link;

[0018] Obtain the target state jump link modified according to the first deadlock risk warning information, return to execute the step of traversing each of the signal combination sequences in the signal sequence verification set in the target state jump link of the state machine model, and obtain the static traversal verification result and test stimulus record result of the target state jump link.

[0019] Optionally, in the target state jump link of the state machine model, before traversing each of the signal combination sequences in the signal sequence verification set and obtaining a static traversal verification result and a test stimulus recording result of the target state jump link, the method further includes:

[0020] Obtaining an initial state jump link of the state machine model;

[0021] Detect whether the end condition of each link function coverage point in the initial state jump link is an initial state or an end state; if yes, use the initial state jump link as the target state jump link, and integrate the target state jump link into the state machine model; if no, output second deadlock risk prompt information, wherein the second deadlock risk prompt information is used to prompt that there is an end condition error deadlock in the initial state jump link;

[0022] When the second deadlock risk warning information is output, the initial state jump link modified according to the second deadlock risk warning information is obtained, and the step of detecting whether the end condition of each link function coverage point in the initial state jump link is the initial state or the end state is returned to be executed.

[0023] Optionally, the state machine model is a simulation model that uses a high-level programming language to describe the functional logic of the digital chip.

[0024] A state machine verification device comprises: a state machine model acquisition unit, a signal combination sequence verification set acquisition unit, a static traversal unit and a dynamic verification unit.

[0025] The state machine model obtaining unit is used to obtain a state machine model of a digital chip, wherein the state machine model is used to simulate the behavior logic of the state machine under test of the digital chip;

[0026] The signal combination sequence verification set obtaining unit is used to obtain the signal combination sequence verification set of the state machine model, wherein the signal combination sequence verification set includes a plurality of signal combination sequences obtained by cross-combining signal values ​​of a plurality of input signals of the state machine model;

[0027] The static traversal unit is used to traverse each of the signal combination sequences in the signal sequence verification set in the target state jump link of the state machine model, and obtain the static traversal verification result and test stimulus record result of the target state jump link, wherein the test stimulus record result records the signal combination sequence that hits any link function coverage point in the target state jump link;

[0028] The dynamic verification unit is used to input the signal combination sequence in the test stimulus record result into the state machine model and its corresponding state machine under test for dynamic simulation verification when the static traversal verification result shows that all the link function coverage points in the target state jump link have been hit, so as to obtain the state machine verification result of the digital chip.

[0029] A state machine verification system includes: an interface traversal module, a state machine model, a test stimulus library, a test stimulus player, a test driver, a state machine under test and a test scoreboard.

[0030] The interface traversal module is used to traverse the cross combinations of the state machine input interface in all value spaces to obtain multiple signal combination sequences;

[0031] The state machine model is used to simulate the behavior logic of the state machine under test and integrate the state jump link; according to the signal combination sequence sent by the test driver, the link function coverage of the state machine model in the simulation environment is recorded, and the first state transition behavior information of the state machine model in the simulation environment is sent to the test scoreboard module;

[0032] The test stimulus library is used to store a signal combination sequence that hits any link function coverage point in a state jump link;

[0033] The test stimulus player is used to read the signal combination sequence in the test stimulus library in sequence, and send the read signal combination sequence to the test driver;

[0034] The test driver is used to send the signal combination sequence sent by the test stimulus player to the state machine model, and convert the signal combination sequence sent by the test stimulus player into the signal value of the state machine under test, so as to drive the state machine under test;

[0035] The state machine under test is used to output the second state transition behavior information of the state machine under test in the simulation environment and send it to the test scoreboard according to the value of the signal transmitted by the test driver;

[0036] The test scoreboard is used to compare whether the state transition behaviors of the state machine model and the state machine under test are consistent based on the first state transition behavior information and the second state transition behavior information.

[0037] A computer-readable storage medium stores a program, wherein the program, when executed by a processor, implements any of the state machine verification methods described above.

[0038] An electronic device, comprising at least one processor, and at least one memory and a bus connected to the processor; wherein the processor and the memory communicate with each other via the bus; and the processor is used to call program instructions in the memory to execute any of the state machine verification methods described above.

[0039] By means of the above technical scheme, the present invention provides a state machine verification method, device, system, storage medium and electronic device, the method comprising: obtaining a state machine model of a digital chip, wherein the state machine model is used to simulate the behavioral logic of a state machine under test of the digital chip; obtaining a signal combination sequence verification set of the state machine model, wherein the signal combination sequence verification set includes multiple signal combination sequences obtained by cross-combining the signal values ​​of multiple input signals of the state machine model; in a target state jump link of the state machine model, traversing each signal combination sequence in the signal sequence verification set to obtain a static traversal verification result and a test stimulus recording result of the target state jump link, wherein the test stimulus recording result records a signal combination sequence that hits any link function coverage point in the target state jump link; when the static traversal verification result is that all link function coverage points in the target state jump link have been hit, the signal combination sequence in the test stimulus recording result is respectively input into the state machine model and its corresponding state machine under test for dynamic simulation verification to obtain the state machine verification result of the digital chip. The present invention automatically generates all test stimuli required for dynamic simulation during the static traversal process, and can correctly cover all possible valid links of the state machine, thereby effectively improving the comprehensiveness and integrity of the state machine verification.

[0040] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Moreover, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0042] Figure 1 A schematic diagram showing a flow chart of an implementation of a state machine verification method provided by an embodiment of the present invention;

[0043] Figure 2 A schematic diagram of a state machine under test design provided by an embodiment of the present invention is shown;

[0044] Figure 3 A schematic diagram of a link structure of a target state jump link provided by an embodiment of the present invention is shown;

[0045] Figure 4 A schematic diagram showing the structure of a state machine verification device provided by an embodiment of the present invention is shown;

[0046] Figure 5 A schematic diagram of the structure of a state machine verification system provided by an embodiment of the present invention is shown;

[0047] Figure 6 A verification logic block diagram of a state machine verification system provided by an embodiment of the present invention is shown;

[0048] Figure 7 A schematic structural diagram of an electronic device provided by an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0049] The exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present invention and to enable the scope of the present invention to be fully communicated to those skilled in the art.

[0050] In modern digital chip design, state machine logic design is one of the most commonly used and core parts, so the design and verification quality of the state machine directly affects the performance and reliability of the entire chip. However, the current traditional chip verification methods are not comprehensive and effective enough. Existing methods usually rely on random simulation tests and use the code coverage of the state machine to ensure the verification quality. Although these conventional methods can show the mutual jumps between states, they have significant limitations.

[0051] First, existing verification methods cannot ensure that all possible valid links are correctly covered. This means that although the jumps between two states in the state machine can be verified, there is no guarantee that these jumps have covered all possible paths and scenarios. Second, these methods cannot fully verify all deadlock situations in the state machine. The deadlock problem is critical in state machine design because once the state machine enters a deadlock state, the system may stop responding or exhibit unpredictable behavior.

[0052] Due to these limitations, existing verification methods cannot guarantee the comprehensiveness and integrity of state machine verification, thus affecting the quality of state machine design. Therefore, there is an urgent need for a more comprehensive state machine verification system and method that can not only ensure that all possible valid links are correctly covered, but also detect and prevent deadlocks in the state machine, thereby ensuring the comprehensiveness and integrity of state machine verification, and thus providing higher reliability and performance guarantees for digital chip design.

[0053] Based on this, in an embodiment of the present invention, a state machine verification method is provided, which checks the state machine input signal through a static traversal system and evaluates the functional coverage of the state machine model to determine whether there is a deadlock risk. At the same time, it generates a valid test sequence and stores it in a test stimulus library for testing the dynamic simulation system. Static traversal uses scripts or high-level languages ​​to quickly cover all input signals, and can detect deadlock risks even without dynamic simulation. In addition, it can quickly generate test stimuli for dynamic simulation, saving time, and all possible links can be covered by playing these stimuli. The dynamic simulation system is used to verify the correctness of the state machine. The test stimulus sequence has been fully generated during the static check and only needs to be played, ensuring the correctness of the design and the integrity of the verification.

[0054] like Figure 1 As shown, a flow chart of an implementation of a state machine verification method provided by an embodiment of the present invention is provided, and the method may include:

[0055] S100: Obtain a state machine model of a digital chip, wherein the state machine model is used to simulate the behavior logic of a state machine under test of the digital chip.

[0056] Among them, a digital chip is an electronic component that uses digital signals to process and store information. Digital chips mainly include microprocessors, memories, digital signal processors (DSPs) and field-programmable gate arrays (FPGAs).

[0057] Among them, the state machine model is an abstract mathematical model or logic design used to describe the state, input, output and state transition rules of the state machine under test of the digital chip. The main purpose of the state machine model is to provide a clear and systematic description of the system behavior for design, analysis and verification. Optionally, the state machine model is a simulation model that uses a high-level programming language to describe the functional logic of the digital chip.

[0058] Among them, the state machine under test refers to the actual hardware or software design of the digital chip that is in a state of being checked, verified or tested during the actual testing or verification process.

[0059] Specifically, the embodiment of the present invention can extract the state, transition conditions, and input / output signal information of the state machine based on the chip design document of the digital chip, and then use the hardware description language (such as VHDL or Verilog) to define the state machine model, and then use a special modeling tool (such as MATLAB / Simulink) to perform high-level modeling and simulation to abstract the complex digital chip design into a state machine model. The state machine model uses a state diagram or a state transition table to represent the state and transition logic.

[0060] S110. Obtain a signal combination sequence verification set of a state machine model, wherein the signal combination sequence verification set includes a plurality of signal combination sequences obtained by cross-combining signal values ​​of a plurality of input signals of the state machine model.

[0061] The signal combination sequence verification set includes different input signal combinations of the state machine of the digital chip, and the purpose is to comprehensively test the behavior of the state machine through multiple combinations. The embodiment of the present invention can make different combinations of multiple input signals to form multiple signal combination sequences, and construct a signal combination sequence verification set of the state machine model, which includes multiple signal combination sequences that can cover all possible input conditions of the state machine.

[0062] like Figure 2 The schematic diagram of the state machine under test design shown in the figure assumes that there are four input signals a, b, c and d, each of which has two states: 0 or 1. There are a total of 16 signal combination sequences in the signal combination sequence verification set.

[0063] S120. In the target state jump link of the state machine model, traverse each signal combination sequence in the signal sequence verification set to obtain the static traversal verification result and test stimulus recording result of the target state jump link, wherein the test stimulus recording result records the signal combination sequence that hits any link function coverage point in the target state jump link.

[0064] Among them, the target state jump link represents the different states of the state machine model and the conversion relationship between them. The target state jump link can be used by a graphical tool to intuitively show how the state machine transitions from one state to another under various input conditions in the form of nodes and directed edges. The target state jump link is a complete jump relationship composed of all possible multiple state machine jump links of the state machine model. Each individual state machine jump link in the target state jump link corresponds to a link function coverage point. For example: based on Figure 3The target state jump link shown, the state machine jump link included in the target state jump link can be: "initial state->specific state 1->specific state 4", "initial state->specific state 1->specific state 2->initial state", "initial state->specific state 1->specific substate 1->specific substate 2->specific substate 3->specific state 2->initial state" and "initial state->specific state 1->specific state 2->specific state 3->initial state".

[0065] Among them, the initial state (Idle) usually means that the state machine is in an idle state, without any activities or tasks, waiting for external events or input signals to trigger state transition.

[0066] A specific state represents a specific condition or position of a state machine at a certain moment. A state may represent that the state machine performs a specific function or is at a specific stage.

[0067] Among them, a specific sub-state (sub_state) is also called a nested state, which refers to a state that is further subdivided inside another state, indicating a more specific situation or behavior. For example: "sub_state1" means loading data, "sub_state 2" means processing data, and "sub_state 3" means saving results.

[0068] Among them, the static traversal verification result checks whether all state transitions in the target state jump link are covered by traversing each signal combination sequence in the signal sequence verification set to ensure that all possible state transitions in theory are taken into account, that is, to confirm that each functional coverage point of the state machine can be accessed by the actual signal sequence, ensuring the integrity and coverage of the state machine model.

[0069] The test stimulus record result records the signal combination sequence that hits any link function coverage point in the target state jump link. The test stimulus record result indicates which signal combination sequences can make the state machine jump from one state to another in the actual test, providing specific test cases for subsequent dynamic simulation verification, ensuring that the actual test can cover all functional points.

[0070] Among them, the link function coverage point is the location of each possible state transition in the state machine model. Each link function coverage point represents a transition between a pair of source state and target state, triggered by a specific signal.

[0071] Specifically, the embodiment of the present invention can input each signal combination sequence in the signal sequence verification set into the state machine model one by one, simulate the state jump process of the state machine under the signal combination sequence, and record whether each signal combination sequence hits any link function coverage point of the state machine. The signal combination sequence that hits the link function coverage point is recorded to form a test stimulus record result. At the same time, it is counted whether each function coverage point of the state machine model is hit by at least one signal combination sequence. If each link function coverage point is hit, the static traversal verification result can be "verification passed", otherwise it is "verification failed".

[0072] S130. When the static traversal verification result shows that all link function coverage points in the target state jump link have been hit, the signal combination sequence in the test stimulus record result is respectively input into the state machine model and its corresponding state machine under test for dynamic simulation verification to obtain the state machine verification result of the digital chip.

[0073] Specifically, in an embodiment of the present invention, when it is determined that the static traversal verification result is "verification passed", each signal combination sequence in the test stimulus recording result can be input one by one into the state machine model and the state machine under test for dynamic simulation, and the jump behavior and state transition of the state machine can be recorded. The output of the state machine model is compared with the actual output of the state machine under test, and the aforementioned jump behavior information, state transition information and output comparison information are recorded to determine whether the behavior of the state machine under test meets expectations, and generate a state machine verification result for the digital chip.

[0074] The present invention provides a state machine verification method, which includes: obtaining a state machine model of a digital chip, wherein the state machine model is used to simulate the behavior logic of a state machine under test of the digital chip; obtaining a signal combination sequence verification set of the state machine model, wherein the signal combination sequence verification set includes multiple signal combination sequences obtained by cross-combining the signal values ​​of multiple input signals of the state machine model; in the target state jump link of the state machine model, traversing each signal combination sequence in the signal sequence verification set, obtaining a static traversal verification result and a test stimulus recording result of the target state jump link, wherein the test stimulus recording result records a signal combination sequence that hits any link function coverage point in the target state jump link; when the static traversal verification result is that all link function coverage points in the target state jump link have been hit, the signal combination sequence in the test stimulus recording result is respectively input into the state machine model and its corresponding state machine under test for dynamic simulation verification, and the state machine verification result of the digital chip is obtained. The present invention automatically generates all test stimuli required for dynamic simulation during the static traversal process, and can correctly cover all possible valid links of the state machine, thereby effectively improving the comprehensiveness and integrity of the state machine verification.

[0075] Optional, in the above Figure 1 On the basis of one or more corresponding embodiments, another optional embodiment provided by the embodiment of the present invention is to input the signal combination sequence in the test stimulus recording result into the state machine model and its corresponding state machine under test for dynamic simulation verification, and obtain the state machine verification result of the digital chip, which may specifically include:

[0076] In the test stimulus recording results, each signal combination sequence is selected in turn and input into the state machine model and its corresponding state machine under test at the same time, and the state machine model and the state machine under test are run in a simulation environment, and the link function coverage of the state machine model is recorded to obtain the first state transition behavior information of the state machine model and the second state transition behavior information of the state machine under test; using the first state transition behavior information and the second state transition behavior information, compare whether the state transition behaviors of the state machine model and the state machine under test are consistent, and obtain the functional verification result of the state machine under test; summarize the link function coverage and function verification results, and output the state machine verification result of the digital chip.

[0077] The simulation environment is a virtual environment for running and testing the state machine model and its corresponding state machine under test. The embodiment of the present invention can simulate the actual working conditions of the digital chip through the test platform, observe and record the behavior and output of the state machine. The link function coverage refers to the proportion of state transitions in the state machine model that have been triggered by the signal combination sequence to all possible transitions, which is used to indicate how many functions in the state machine model have been tested.

[0078] The state transition behavior information may include the state change and output of the state machine under a specific signal combination sequence.

[0079] Among them, the functional verification result is the result of verifying whether the state machine under test implements the relevant functions as expected by comparing the state machine model and the state transition behavior information of the state machine under test.

[0080] Specifically, the embodiment of the present invention can simultaneously run the state machine model and the state machine under test in a simulation environment, input a signal combination sequence, record the state changes and outputs of the state machine model and the state machine under test, and form first state transfer behavior information and second state transfer behavior information. The first state transfer behavior information and the second state transfer behavior information are compared item by item to determine whether the behaviors of the two are consistent under the corresponding input signals of all signal combination sequences, record the comparison results, and obtain the function verification results. At the same time, the proportion of all state transitions that have been triggered is counted to calculate the link function coverage as an indicator to measure the integrity of the test. Finally, the link function coverage and function verification results are summarized to generate a comprehensive state machine verification result to confirm whether the relevant functions of the digital chip meet the design requirements.

[0081] The embodiment of the present invention uses the signal combination sequence in the test stimulus record results after static traversal screening to perform dynamic simulation. While reducing the amount of data verification in the dynamic simulation, it can ensure that every possible state transition of the state machine model is tested, and by comparing the state transfer behavior information of the state machine model and the state machine under test, it can accurately detect any functional differences between the two, ensuring that the actual behavior of the state machine under test is consistent with the design expectations, thereby improving the comprehensiveness and accuracy of state machine verification.

[0082] Optional, in the above Figure 1 On the basis of one or more corresponding embodiments, in another optional embodiment provided by the embodiment of the present invention, only one hit signal combination sequence is recorded for each link function coverage point in the test stimulus recording result.

[0083] Specifically, an embodiment of the present invention can check whether each signal combination sequence in the signal sequence verification set hits a link function coverage point in the target state jump link. When a signal combination sequence hits a link function coverage point, check whether the link function coverage point has been recorded. If the link function coverage point has not been hit, record the current signal combination sequence as the hit signal combination sequence of the link function coverage point. If the link function coverage point has already been recorded, no new signal combination sequence is recorded, and continue to traverse the next signal combination sequence. Continue the above process until all signal combination sequences in the signal sequence verification set have been traversed or all link function coverage points have been recorded.

[0084] It is understandable that, when it is detected that the link function coverage point already has a record, the current signal combination sequence may overwrite the original signal combination sequence, and the latest hit signal combination sequence is recorded for the link function coverage point.

[0085] The embodiment of the present invention only records one hitting signal combination sequence for each link function coverage point in the test stimulus recording results, which can further reduce the number of signal combination sequences in the test stimulus recording results, thereby reducing the amount of data verification in subsequent dynamic simulation verification, thereby improving the verification efficiency of dynamic simulation verification.

[0086] Optional, in the above Figure 1 On the basis of one or more corresponding embodiments, in another optional embodiment provided by the embodiment of the present invention, the method may further include:

[0087] When the static traversal verification result is that there are link function coverage points that have not been hit in the target state jump link, the first deadlock risk warning information is output, wherein the first deadlock risk warning information is used to prompt the existence of a cyclic deadlock and / or a conditional deadlock in the target state jump link; the target state jump link modified according to the first deadlock risk warning information is obtained, and the target state jump link executed in the state machine model is returned to traverse each signal combination sequence in the signal sequence verification set to obtain the static traversal verification result of the target state jump link and the test stimulus recording result.

[0088] Among them, cyclic deadlock refers to a state machine in which a set of states and transitions form a closed loop path, causing the state machine to repeat in this loop and unable to jump out, thus failing to complete the transition to the target state. For example: suppose the state machine has states and transitions: state A->state B->state C->state A. In this case, the state machine may fall into an endless loop (A->B->C->A), unable to reach other states or complete other functions.

[0089] Among them, conditional deadlock refers to the situation that some states or state transitions in a state machine are restricted by specific conditions. When these conditions are not met, the state machine cannot perform state transitions and thus stagnates in a certain state. For example, suppose a state machine has states and transitions: state A->(condition x is met)->state B, state A->(condition y is met)->state C. In this case, if condition x and condition y cannot be met at the same time, the state machine will always stay in state A and cannot be transferred to state B or state C.

[0090] In the static traversal verification results, if it is found that there are unhit link function coverage points in the target state jump link, it means that certain states or transitions have not been effectively tested and verified, and the state machine may be at risk of cyclic deadlock and / or conditional deadlock. The embodiment of the present invention can output the first deadlock risk prompt information to prompt that there are unhit link function coverage points in the target state jump link, which may cause cyclic deadlock and / or conditional deadlock, thereby reminding the developer to check and modify the target state jump link to eliminate potential deadlock risks. For example: Figure 3 As shown in the figure, if after traversing all the inputs of the state machine, jump condition 0 and jump condition 1 are still not met, then the jumps of "specific state 3-> initial state" and "specific substate 3-> specific state 2" cannot occur, and the corresponding link function coverage points must not be hit. If the function coverage points of all links have been hit, execute the next step.

[0091] The embodiment of the present invention can identify whether there is a cyclic deadlock and / or conditional deadlock problem in the target state jump link through static traversal, thereby helping developers to specifically solve potential design defects in the digital chip design process, thereby ensuring the comprehensiveness and completeness of the state machine verification and enhancing the reliability of the digital chip.

[0092] Optional, in the above Figure 1 On the basis of one or more corresponding embodiments, in another optional embodiment provided by an embodiment of the present invention, in a target state jump link of a state machine model, before traversing each signal combination sequence in a signal sequence verification set and obtaining a static traversal verification result and a test stimulus recording result of the target state jump link, the method may further include:

[0093] Obtain an initial state jump link of the state machine model; detect whether the end condition of each link function coverage point in the initial state jump link is the initial state or the end state; if so, use the initial state jump link as the target state jump link, and integrate the target state jump link into the state machine model; if not, output a second deadlock risk warning information, wherein the second deadlock risk warning information is used to prompt that there is an end condition error deadlock in the initial state jump link; when the second deadlock risk warning information is output, obtain the initial state jump link modified according to the second deadlock risk warning information, and return to execute the step of detecting whether the end condition of each link function coverage point in the initial state jump link is the initial state or the end state.

[0094] The end condition may include the link jumping back to the initial state, the link reaching the end state, or a certain state in the link (except the initial state and the end state) appearing for the second time.

[0095] Specifically, the embodiment of the present invention can extract all possible state change paths starting from the initial state in the initial state jump link, and check whether the end condition of each link function coverage point in the initial state jump link is the initial state or the end state. When the end condition is correct, the initial state jump link is used as the target state jump link and integrated into the state machine model. When the end condition is wrong, the second deadlock risk prompt information is output, indicating that there is a risk of deadlock due to an end condition error.

[0096] The embodiment of the present invention can output the second deadlock risk prompt information to prompt that there is an end condition error problem in the initial state jump link, which may cause the end condition error deadlock, thereby reminding the developer to check and modify the initial state jump link to eliminate the potential deadlock risk.

[0097] The embodiment of the present invention can detect the end condition of the initial state jump link in advance, and can timely discover the deadlock problem of the end condition error of the initial state jump link, thereby helping developers to solve potential design defects in the digital chip design process in a targeted manner, thereby ensuring the comprehensiveness and completeness of the state machine verification and enhancing the reliability of the digital chip.

[0098] Although operations are depicted in a particular order, this should not be understood as requiring that the operations be performed in the particular order shown or in a sequential order.Multitasking and parallel processing may be advantageous under certain circumstances.

[0099] It should be understood that the various steps described in the method embodiments of the present invention may be performed in different orders and / or in parallel. In addition, the method embodiments may include additional steps and / or omit the steps shown. The scope of the present invention is not limited in this respect.

[0100] Corresponding to the above method embodiment, the embodiment of the present invention also provides a state machine verification device, whose structure is as follows: Figure 4 As shown, it may include: a state machine model obtaining unit 10, a signal combination sequence verification set obtaining unit 20, a static traversal unit 30 and a dynamic verification unit 40.

[0101] The state machine model obtaining unit 10 is used to obtain a state machine model of a digital chip, wherein the state machine model is used to simulate the behavior logic of the state machine under test of the digital chip.

[0102] The signal combination sequence verification set obtaining unit 20 is used to obtain a signal combination sequence verification set of a state machine model, wherein the signal combination sequence verification set includes a plurality of signal combination sequences obtained by cross-combining signal values ​​of a plurality of input signals of the state machine model.

[0103] The static traversal unit 30 is used to traverse each signal combination sequence in the signal sequence verification set in the target state jump link of the state machine model, and obtain the static traversal verification result and test stimulus recording result of the target state jump link, wherein the test stimulus recording result records the signal combination sequence that hits any link function coverage point in the target state jump link.

[0104] The dynamic verification unit 40 is used to input the signal combination sequence in the test stimulus record result into the state machine model and its corresponding state machine under test for dynamic simulation verification when the static traversal verification result shows that all link function coverage points in the target state jump link have been hit, so as to obtain the state machine verification result of the digital chip.

[0105] Optionally, the dynamic verification unit 40 can be specifically used to select each signal combination sequence in the test stimulus recording result in turn and input them into the state machine model and its corresponding state machine under test at the same time, and run the state machine model and the state machine under test in a simulation environment, record the link function coverage of the state machine model, obtain the first state transition behavior information of the state machine model and the second state transition behavior information of the state machine under test; use the first state transition behavior information and the second state transition behavior information to compare whether the state transition behavior of the state machine model and the state machine under test are consistent, and obtain the functional verification result of the state machine under test; summarize the link function coverage and functional verification results, and output the state machine verification result of the digital chip.

[0106] Optionally, only one hit signal combination sequence is recorded for each link function coverage point in the test stimulus recording result.

[0107] Optionally, the state machine verification device may further include: a first deadlock risk prompting unit.

[0108] The first deadlock risk warning unit is used to output the first deadlock risk warning information when the static traversal verification result is that there are link function coverage points that have not been hit in the target state jump link, wherein the first deadlock risk warning information is used to prompt the existence of a circular deadlock and / or a conditional deadlock in the target state jump link; obtain the target state jump link modified according to the first deadlock risk warning information, and trigger the static traversal unit 30.

[0109] Optionally, the state machine verification device may further include: an initial state jump link acquisition unit, a link end condition detection unit, a model integration unit and a second deadlock risk prompting unit.

[0110] The initial state jump link acquisition unit is used to traverse each signal combination sequence in the signal sequence verification set in the target state jump link of the state machine model, and obtain the initial state jump link of the state machine model before obtaining the static traversal verification result and test stimulus recording result of the target state jump link.

[0111] The link end condition detection unit is used to detect whether the end condition of each link function coverage point in the initial state jump link is the initial state or the end state. If yes, the model integration unit is triggered; if not, the second deadlock risk warning unit is triggered.

[0112] The model integration unit is used to use the initial state jump link as the target state jump link and integrate the target state jump link into the state machine model.

[0113] A second deadlock risk warning unit is used to output second deadlock risk warning information, wherein the second deadlock risk warning information is used to prompt that there is an end condition error deadlock in the initial state jump link. When the second deadlock risk warning information is output, the initial state jump link modified according to the second deadlock risk warning information is obtained to trigger the link end condition detection unit.

[0114] Optionally, the state machine model is a simulation model that uses a high-level programming language to describe the functional logic of a digital chip.

[0115] The present invention provides a state machine verification device, which is used to: obtain a state machine model of a digital chip, wherein the state machine model is used to simulate the behavior logic of the state machine under test of the digital chip; obtain a signal combination sequence verification set of the state machine model, wherein the signal combination sequence verification set includes multiple signal combination sequences obtained by cross-combining the signal values ​​of multiple input signals of the state machine model; in the target state jump link of the state machine model, traverse each signal combination sequence in the signal sequence verification set, and obtain the static traversal verification result and test stimulus recording result of the target state jump link, wherein the test stimulus recording result records the signal combination sequence that hits any link function coverage point in the target state jump link; when the static traversal verification result is that all link function coverage points in the target state jump link have been hit, the signal combination sequence in the test stimulus recording result is respectively input into the state machine model and its corresponding state machine under test for dynamic simulation verification, and obtain the state machine verification result of the digital chip. The present invention automatically generates all test stimuli required for dynamic simulation during the static traversal process, and can correctly cover all possible valid links of the state machine, thereby effectively improving the comprehensiveness and integrity of the state machine verification.

[0116] Regarding the device in the above embodiment, the specific manner in which each unit performs the operation has been described in detail in the embodiment of the method, and will not be elaborated here.

[0117] The processor includes a kernel, which retrieves the corresponding program unit from the memory. One or more kernels can be set, and the state machine model of the digital chip can be obtained by adjusting the kernel parameters, and a verification set containing multiple signal combination sequences is obtained, wherein the signal combination sequence is generated by cross-combining the input signals of the state machine model. In the target state jump link, all signal combination sequences of the verification set are traversed, and the static traversal verification results and the test stimulus recording results are recorded. When the static traversal verification results show that all link function coverage points are hit, the signal combination sequence that hits the link function coverage points in the test stimulus recording results is input into the state machine model and the state machine under test for dynamic simulation verification, and finally the state machine verification result of the digital chip is obtained, ensuring that all possible valid links of the state machine are correctly covered, thereby improving the comprehensiveness and completeness of the state machine verification.

[0118] An embodiment of the present invention provides a computer-readable storage medium on which a program is stored. When the program is executed by a processor, the state machine verification method is implemented.

[0119] An embodiment of the present invention provides a processor, which is used to run a program, wherein the state machine verification method is executed when the program is running.

[0120] The state machine verification device includes a processor and a memory. The above-mentioned state machine model acquisition unit 10, signal combination sequence verification set acquisition unit 20, static traversal unit 30 and dynamic verification unit 40 are all stored in the memory as program units, and the processor executes the above-mentioned program units stored in the memory to realize corresponding functions.

[0121] like Figure 5 As shown, an embodiment of the present invention further provides a state machine verification system, including: an interface traversal module, a state machine model, a test stimulus library, a test stimulus player, a test driver, a state machine under test, and a test scoreboard.

[0122] Among them, the state machine static traversal system is composed of the interface traversal module, state machine model and test stimulus library, and the state machine dynamic simulation verification system is composed of the test stimulus library, test stimulus player, test driver, tested state machine and test scoreboard.

[0123] The interface traversal module is used to traverse the cross-combinations of the state machine input interface in all value spaces to obtain multiple signal combination sequences.

[0124] Interface traversal module: responsible for traversing all possible values ​​of the state machine input interface. For example, for the state machine input interfaces input_a, input_b, input_c and input_d, the static traversal system needs to traverse all possible value combinations of these inputs to ensure that all input spaces of the state machine can be quickly covered during static traversal. Compared with traditional dynamic simulation verification, the efficiency of input traversal is greatly improved and verification time is saved.

[0125] The state machine model is used to simulate the behavior logic of the state machine under test and integrate the state jump link; based on the signal combination sequence sent by the test driver, the link function coverage of the state machine model in the simulation environment is recorded, and the first state transfer behavior information of the state machine model in the simulation environment is sent to the test scoreboard module.

[0126] The state machine model module is responsible for simulating the state machine behavior of the design under test. It integrates the state machine link functional coverage to evaluate the coverage of the state machine.

[0127] The test stimulus library is used to store a signal combination sequence that hits any link function coverage point in a state jump link.

[0128] The test stimulus library module stores valid inputs that can cover the functional coverage of the state machine link. These valid inputs can be directly used in the state machine dynamic simulation verification system.

[0129] The test stimulus player is used to read the signal combination sequence in the test stimulus library in sequence and send the read signal combination sequence to the test driver.

[0130] The test driver is used to send the signal combination sequence sent by the test stimulus player to the state machine model, and convert the signal combination sequence sent by the test stimulus player into signal values ​​of the state machine under test to drive the state machine under test.

[0131] The state machine under test is used to take values ​​according to the signals transmitted by the test driver, output the second state transition behavior information of the state machine under test in the simulation environment and send it to the test scoreboard.

[0132] The test scoreboard is used to compare whether the state transition behaviors of the state machine model and the state machine under test are consistent based on the first state transition behavior information and the second state transition behavior information.

[0133] The test scoreboard receives the state change information of the state machine model and compares the state machine changes of the design under test to ensure the functional correctness of the state machine under test.

[0134] The state machine verification system provided by the embodiment of the present invention, through the above modules, the state machine static traversal system and the dynamic simulation verification system work together, which are responsible for traversing all input spaces and dynamically verifying the state machine functions, respectively, to ensure the integrity and correctness of the state machine design.

[0135] In order to facilitate the understanding of the overall logic of the state machine verification provided by this solution, Figure 6 To explain: Figure 6 The verification logic block diagram of the state machine verification system provided by the embodiment of the present invention is shown. First, the jump diagram of the state machine is analyzed, and all state jump links are arranged. Starting from the initial state idle, the end state is reached when the state jumps back to the initial state idle, or when a state in the link (except the initial state and the end state) appears again for the second time, the link ends. Secondly, check whether the end state of each link is the initial state or the end state. If the end state of a link does not meet the above conditions, it is considered that the link has a deadlock risk. Designers are required to modify the state machine to repair the deadlock risk. After repair, return to reanalyze and list all state jump links, so as to effectively detect the deadlock problem on the state machine topology. Then, all state jump links are implemented as functional coverage points, and the functional coverage points are integrated into the state machine model. Next, traverse the combined values ​​of all input signals. When a certain input combination sequence hits the functional coverage point of a link, the sequence is output and recorded in the test stimulus library. The functional coverage point of each link only needs to record a set of input sequences. After the static traversal is completed, check whether the functional coverage points of all links are fully covered. If one or several links are not covered, it is considered that these links are deadlocked and feedback is given to the designer for modification. If all the functional coverage points of all links are covered, the next step is executed. Finally, the test stimulus stored by the static traversal system is played. The functional coverage of the state machine link during the collection process is collected. Compare the consistency of the state jumps of the state machine model and the design under test to ensure the functional correctness and verification completeness of the state machine design under test, so that the state machine verification system can systematically analyze, verify and ensure the correctness of the state machine design, avoid potential deadlock problems, and improve the efficiency of testing and verification.

[0136] like Figure 7 As shown, an embodiment of the present invention provides an electronic device 1000, which includes at least one processor 1001, at least one memory 1002 connected to the processor 1001, and a bus 1003; wherein the processor 1001 and the memory 1002 communicate with each other through the bus 1003; the processor 1001 is used to call the program instructions in the memory 1002 to execute the above-mentioned state machine verification method. The electronic device in this article can be a server, a PC, a PAD, a mobile phone, etc.

[0137] The present invention also provides a computer program product, which, when executed on an electronic device, is suitable for executing the program of initializing the steps of the stateful machine verification method.

[0138] The present invention is described with reference to flowcharts and / or block diagrams of methods, apparatuses, electronic devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable device to generate a machine, so that the instructions executed by the processor of the computer or other programmable device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0139] In a typical configuration, an electronic device includes one or more processors (CPU), a memory, and a bus. The electronic device may also include an input / output interface, a network interface, and the like.

[0140] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM, and the memory includes at least one memory chip. The memory is an example of a computer-readable medium.

[0141] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0142] It is understandable that before using the technical solutions disclosed in the embodiments of the present disclosure, the types, scope of use, usage scenarios, etc. of the personal information involved in the present disclosure should be informed to the user and the user's authorization should be obtained in an appropriate manner in accordance with relevant laws and regulations.

[0143] In the description of the present invention, it should be understood that the terms "up", "down", "front", "back", "left" and "right" etc. indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description. They do not indicate or imply that the positions or elements referred to must have specific directions, be constructed and operate in specific directions. Therefore, they should not be understood as limitations of the present invention.

[0144] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. It should also be noted that the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0145] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0146] The above are only embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent substitution, improvement, etc. made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.

Claims

1. A state machine verification method, characterized in that: include: Obtaining a state machine model of a digital chip, wherein the state machine model is used to simulate the behavior logic of the state machine under test of the digital chip; Obtaining a signal combination sequence verification set of the state machine model, wherein the signal combination sequence verification set includes a plurality of signal combination sequences obtained by cross-combining signal values ​​of a plurality of input signals of the state machine model; In the target state jump link of the state machine model, traverse each of the signal combination sequences in the signal sequence verification set to obtain a static traversal verification result and a test stimulus record result of the target state jump link, wherein the test stimulus record result records the signal combination sequence that hits any link function coverage point in the target state jump link; When the static traversal verification result shows that all the link function coverage points in the target state jump link have been hit, the signal combination sequence in the test stimulus record result is respectively input into the state machine model and its corresponding state machine under test for dynamic simulation verification to obtain the state machine verification result of the digital chip.

2. The method according to claim 1, characterized in that The step of inputting the signal combination sequence in the test stimulus record result into the state machine model and its corresponding state machine under test for dynamic simulation verification to obtain the state machine verification result of the digital chip includes: In the test stimulus recording result, each of the signal combination sequences is selected in turn and simultaneously input into the state machine model and its corresponding state machine under test, and the state machine model and the state machine under test are run in a simulation environment, the link function coverage of the state machine model is recorded, and the first state transition behavior information of the state machine model and the second state transition behavior information of the state machine under test are obtained; Using the first state transition behavior information and the second state transition behavior information, compare whether the state machine model and the state machine under test have consistent state transition behaviors, and obtain a function verification result of the state machine under test; The link function coverage and the function verification result are summarized, and the state machine verification result of the digital chip is output.

3. The method according to claim 1, characterized in that: In the test stimulus recording result, only one hit signal combination sequence is recorded for each link function coverage point.

4. The method according to claim 1, characterized in that Also includes: When the static traversal verification result is that there is a link function coverage point in the target state jump link that has not been hit, outputting first deadlock risk prompt information, wherein the first deadlock risk prompt information is used to prompt that there is a cyclic deadlock and / or conditional deadlock in the target state jump link; Obtain the target state jump link modified according to the first deadlock risk warning information, return to execute the step of traversing each of the signal combination sequences in the signal sequence verification set in the target state jump link of the state machine model, and obtain the static traversal verification result and test stimulus record result of the target state jump link.

5. The method according to claim 1, characterized in that In the target state jump link of the state machine model, before traversing each of the signal combination sequences in the signal sequence verification set and obtaining a static traversal verification result and a test stimulus recording result of the target state jump link, the method further includes: Obtaining an initial state jump link of the state machine model; Detect whether the end condition of each link function coverage point in the initial state jump link is an initial state or an end state; if yes, use the initial state jump link as the target state jump link, and integrate the target state jump link into the state machine model; if no, output second deadlock risk prompt information, wherein the second deadlock risk prompt information is used to prompt that there is an end condition error deadlock in the initial state jump link; When the second deadlock risk warning information is output, the initial state jump link modified according to the second deadlock risk warning information is obtained, and the step of detecting whether the end condition of each link function coverage point in the initial state jump link is the initial state or the end state is returned to be executed.

6. The method according to any one of claims 1 to 5, characterized in that The state machine model is a simulation model that uses a high-level programming language to describe the functional logic of the digital chip.

7. A state machine verification device, characterized in that: include: State machine model acquisition unit, signal combination sequence verification set acquisition unit, static traversal unit and dynamic verification unit, The state machine model obtaining unit is used to obtain a state machine model of a digital chip, wherein the state machine model is used to simulate the behavior logic of the state machine under test of the digital chip; The signal combination sequence verification set obtaining unit is used to obtain the signal combination sequence verification set of the state machine model, wherein the signal combination sequence verification set includes a plurality of signal combination sequences obtained by cross-combining signal values ​​of a plurality of input signals of the state machine model; The static traversal unit is used to traverse each of the signal combination sequences in the signal sequence verification set in the target state jump link of the state machine model, and obtain the static traversal verification result and test stimulus record result of the target state jump link, wherein the test stimulus record result records the signal combination sequence that hits any link function coverage point in the target state jump link; The dynamic verification unit is used to input the signal combination sequence in the test stimulus record result into the state machine model and its corresponding state machine under test for dynamic simulation verification when the static traversal verification result shows that all the link function coverage points in the target state jump link have been hit, so as to obtain the state machine verification result of the digital chip.

8. A state machine verification system, characterized in that: include: Interface traversal module, state machine model, test stimulus library, test stimulus player, test driver, state machine under test and test scoreboard, The interface traversal module is used to traverse the cross combinations of the state machine input interface in all value spaces to obtain multiple signal combination sequences; The state machine model is used to simulate the behavior logic of the state machine under test and integrate the state jump link; According to the signal combination sequence sent by the test driver, the link function coverage of the state machine model in the simulation environment is recorded, and the first state transition behavior information of the state machine model in the simulation environment is sent to the test scoreboard module; The test stimulus library is used to store a signal combination sequence that hits any link function coverage point in a state jump link; The test stimulus player is used to read the signal combination sequence in the test stimulus library in sequence, and send the read signal combination sequence to the test driver; The test driver is used to send the signal combination sequence sent by the test stimulus player to the state machine model, and convert the signal combination sequence sent by the test stimulus player into the signal value of the state machine under test, so as to drive the state machine under test; The state machine under test is used to output the second state transition behavior information of the state machine under test in the simulation environment and send it to the test scoreboard according to the value of the signal transmitted by the test driver; The test scoreboard is used to compare whether the state transition behaviors of the state machine model and the state machine under test are consistent based on the first state transition behavior information and the second state transition behavior information.

9. A computer-readable storage medium having a program stored thereon, characterized in that: When the program is executed by a processor, the state machine verification method according to any one of claims 1 to 6 is implemented.

10. An electronic device, characterized in that: The electronic device includes at least one processor, and at least one memory and a bus connected to the processor; wherein the processor and the memory communicate with each other through the bus; the processor is used to call program instructions in the memory to execute the state machine verification method as described in any one of claims 1 to 6.

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