Method for generating parameterized hardware acceleration circuit for prime field elliptic curve encryption

Abstract

The invention discloses a parameterized hardware acceleration circuit generation method for prime field elliptic curve encryption, which comprises the following steps of: 1, extracting parameters in an elliptic curve parameter group according to a prime field elliptic curve required to be supported in a design requirement; 2, generating the parameterized hardware acceleration circuit according to the parameters in the extracted elliptic curve parameter group and the speed and area requirements of the parameterized hardware acceleration circuit; and step 3, generating a driving program of the parameterized hardware acceleration circuit according to the extracted parameters in the elliptic curve parameter group, wherein the driving program is used for controlling the parameterized hardware acceleration circuit. According to the method, the hardware acceleration circuit design requirements in different application scenes can be met with less workload, the design efficiency is effectively improved, and the hardware development speed is increased.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit design, and in particular relates to a parameterized hardware acceleration circuit generation method for prime number field elliptic curve encryption. Background Art

[0002] Elliptic curve cryptography calculations and related algorithms are widely used in the fields of communications, metering, and the Internet of Things. Their high encryption strength can effectively ensure that data transmission is not tampered with during transmission, thus improving the security of the system. For security reasons, they often use longer key lengths, and the encryption algorithms on elliptic curves are relatively complex. For low-cost on-chip systems, the use of processors for software calculations of elliptic curve cryptography calculations often greatly affects processor performance and may not meet relevant real-time requirements. Therefore, hardware acceleration circuits are often required to implement elliptic curve cryptography calculations. However, for systems on chips with different requirements, the elliptic curves they need to support are different, and the corresponding hardware acceleration circuits are also different. Designs that support higher-bit key lengths can be backward compatible with calculations with lower bits, but when there is no corresponding demand, it will bring additional area and increase costs. If they are all redesigned according to requirements, they need to be designed and verified again, which is a large workload.

[0003] Terminology explanation:

[0004] Interleaved Modular Multiplication: Interleaved Modular Multiplication is a special modular multiplication method. By improving the doubling-addition multiplication calculation method, the addition is replaced by the modular addition to ensure that the intermediate result of each step in the multiplication is in the prime number domain (that is, the result after taking the modularity), and then modular multiplication is performed. The specific algorithm is as follows:

[0005]

[0006] Prime Field: A prime field is a mathematical structure that contains a prime number of elements. It is a field with addition and multiplication operations where each element is a non-negative integer less than a given prime number (called the characteristic or modulus of the field). In a prime field, addition and multiplication are defined similarly to regular integer addition and multiplication, but after performing these operations, the result needs to be modulo a prime number to ensure that the result is still in the field.

[0007] Elliptic Curve: In mathematics, an elliptic curve is a curve on a plane whose equation is y2=x 3 +ax+b, where a and b are the parameters of the curve. In cryptography, elliptic curves are used as the basis of public key cryptography, which has high security and efficiency.

[0008] ECC (Elliptic Curve Cryptography): Elliptic Curve Cryptography. It uses point operations on elliptic curves to achieve encryption and decryption. The advantage of ECC is that it provides considerable security compared to traditional encryption algorithms such as RSA, and uses a shorter key length, thereby improving the efficiency of encryption and decryption.

[0009] ECDSA (Elliptic Curve Digital Signature Algorithm): Elliptic Curve Digital Signature Algorithm. It uses the mathematical properties of elliptic curves to allow users to generate digital signatures with security comparable to RSA digital signatures, but uses a shorter key length, thus providing higher performance.

[0010] ECDH (Elliptic Curve Diffie-Hellman): Elliptic Curve Diffie-Hellman key exchange. Allows two communicating parties to negotiate a shared key through public information without directly exchanging keys. ECDH uses point operations on elliptic curves and discrete logarithm problems to ensure the security of key negotiation.

[0011] Hardware Description Language: Hardware Description Language is a language used to describe the functions and behaviors of electronic circuits. It can describe digital circuit systems at the register transfer level, behavioral level, logic gate level, etc. With the development of automated logic synthesis tools, hardware description languages ​​can be recognized by these tools and automatically converted to logic gate-level netlists, so that hardware description languages ​​can be used for circuit system design and circuit functions can be verified through logic simulation. Summary of the invention

[0012] Purpose of the invention: The technical problem to be solved by the present invention is to provide a parameterized hardware acceleration circuit generation method for prime field elliptic curve encryption in view of the shortcomings of the prior art.

[0013] In order to solve the above technical problems, in a first aspect, a method for generating a parameterized hardware acceleration circuit for prime field elliptic curve encryption is disclosed, comprising the following steps:

[0014] Step 1, extracting parameters in the elliptic curve parameter group according to the prime field elliptic curve that needs to be supported in the design requirements;

[0015] Step 2, generating the parameterized hardware acceleration circuit according to the parameters in the extracted elliptic curve parameter group and the speed and area requirements of the parameterized hardware acceleration circuit;

[0016] Step 3: Generate a driver program for the parameterized hardware acceleration circuit according to the parameters in the extracted elliptic curve parameter group, wherein the driver program is used to control the parameterized hardware acceleration circuit.

[0017] Furthermore, the parameters in the elliptic curve parameter group extracted in step 1 include a characteristic prime number of the prime field elliptic curve, a base point of the prime field elliptic curve, and an order of the base point of the prime field elliptic curve.

[0018] Furthermore, generating the parameterized hardware acceleration circuit in step 2 includes generating a parameterized operation circuit, generating a parameterized prime number lookup table circuit, and generating a parameterized algorithm execution circuit.

[0019] The parameterized operation circuit is used to implement modular operations including modular addition, modular subtraction and interleaved modular multiplication;

[0020] The parameterized prime number lookup table circuit is used to select prime numbers for the parameterized operation circuit to perform modular operations according to design requirements;

[0021] The parameterized algorithm execution circuit is used to control the parameterized prime number lookup table circuit and the parameterized operation circuit to execute the encryption algorithm according to external instructions and configurations.

[0022] Further, the parameterized operation circuit includes a basic calculation circuit and a calculation control circuit, the basic calculation circuit is used to implement modular operations including modular addition, modular subtraction and shift operations, and the calculation cycle and the selection of adders and / or subtractors are determined according to the speed requirements of the parameterized hardware acceleration circuit;

[0023] The calculation control circuit is used to control the basic calculation circuit to perform iterations of modular operations, including: when calculating modular addition and modular subtraction, data iteration is performed according to the results of the basic calculation circuit; when calculating interleaved modular multiplication, according to the input, the basic calculation circuit is controlled to calculate multiple rounds of modular addition, wherein the number of rounds of modular addition is determined by the maximum width of the characteristic prime number of the prime field elliptic curve.

[0024] Furthermore, the content in the lookup table in the parameterized prime number lookup table circuit is determined according to the characteristic prime number of the input prime number field elliptic curve, and the sign bit is filled according to different characteristic prime numbers and the maximum characteristic prime number bit width.

[0025] Furthermore, the parameterized algorithm execution circuit includes a bus slave interface, an instruction storage unit, a calculation control unit, a bus host interface, a data storage unit, a data controller, a prime number storage unit and a prime number controller.

[0026] The bus slave interface is used to receive configuration information from the system bus, wherein the configuration information includes enable, interrupt control, calculation instructions and prime number parameter configuration, and the read calculation instructions are stored in the instruction storage unit for subsequent calculation control;

[0027] The bus host interface is used to read data from the memory on the system bus, wherein the data includes data and calculation instructions for calculation, the calculation instructions are sent to the instruction storage unit, and the calculation data are sent to the data storage unit or the prime number storage unit;

[0028] The calculation control unit obtains the calculation instruction from the instruction storage unit and sends it to the parameterized operation circuit; the data controller obtains the calculation data from the data storage unit according to the executed calculation instruction and sends it to the parameterized operation circuit; the prime number controller obtains the prime number data from the prime number storage unit according to the executed calculation instruction and sends it to the parameterized operation circuit;

[0029] The calculation control unit controls the parameterized operation circuit generated according to the calculation instructions in the instruction storage unit to perform calculations of various elliptic curve encryption algorithms.

[0030] Furthermore, the driver described in step 3 includes curve parameter initialization configuration, basic operation implementation and algorithm operation implementation. The curve parameter initialization configuration writes the parameters in the extracted elliptic curve parameter group into the data storage unit and the prime number storage unit through the system bus; the basic operation implementation writes the instructions into the instruction storage unit according to the instruction format designed for the acceleration circuit, and controls the parameterized operation circuit to perform corresponding operations; the algorithm operation implementation realizes the existing encryption algorithm by combining basic operations; the user initializes the accelerator by calling the driver, and then completes the encryption algorithm according to user needs using the algorithm operation implementation provided by the driver or through the basic operation implementation.

[0031] In a second aspect, a parameterized hardware acceleration circuit for prime number field elliptic curve encryption is disclosed, which is generated using any of the above-mentioned parameterized hardware acceleration circuit generation methods for prime number field elliptic curve encryption.

[0032] In a third aspect, a system on a chip is disclosed, comprising the parameterized hardware acceleration circuit for prime field elliptic curve encryption.

[0033] In a fourth aspect, an accelerator circuit is disclosed, including the parameterized hardware acceleration circuit for prime field elliptic curve encryption.

[0034] Beneficial effects:

[0035] 1. The highly scalable interleaved modular multiplication architecture is adopted to improve the scalability of the design and the consistency of different designs, so that the overall hardware circuit design can be parameterized and adapted according to the input elliptic curve, so as to maximize the speed and reduce the area while meeting the requirements.

[0036] 2. For the parameterized generated circuit, the characteristics of the prime field elliptic curve are utilized to automatically generate the corresponding driver program to reduce the workload.

[0037] 3. Parameterized circuit generation and automated driver generation reduce the workload of corresponding design and reduce the complexity of migration between different platforms. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments, and the above and / or other advantages of the present invention will become more clear.

[0039] Figure 1 A flowchart of a method for generating a parameterized hardware acceleration circuit for prime field elliptic curve encryption provided in an embodiment of the present application.

[0040] Figure 2 A structural schematic diagram of a basic computing circuit in a parameterized hardware acceleration circuit for prime number field elliptic curve encryption provided in an embodiment of the present application.

[0041] Figure 3 Another structural schematic diagram of a basic computing circuit in a parameterized hardware acceleration circuit for prime field elliptic curve encryption provided in an embodiment of the present application.

[0042] Figure 4 A schematic diagram of a modular addition process implemented by a calculation control circuit in a parameterized hardware acceleration circuit for prime field elliptic curve encryption provided in an embodiment of the present application.

[0043] Figure 5 A schematic diagram of a modular reduction process implemented by a calculation control circuit in a parameterized hardware acceleration circuit for prime field elliptic curve encryption provided in an embodiment of the present application.

[0044] Figure 6 A schematic diagram of a modular multiplication process implemented by a calculation control circuit in a parameterized hardware acceleration circuit for prime field elliptic curve encryption provided in an embodiment of the present application.

[0045] Figure 7 A schematic diagram of filling prime sign bits in a parameterized prime lookup table circuit in a parameterized hardware acceleration circuit generation method for prime field elliptic curve encryption provided in an embodiment of the present application.

[0046] Figure 8 A schematic diagram of the structure of a parameterized algorithm execution circuit in a parameterized hardware acceleration circuit for prime number field elliptic curve encryption provided in an embodiment of the present application. DETAILED DESCRIPTION

[0047] The embodiments of the present invention will be described below in conjunction with the accompanying drawings.

[0048] ECC and its related algorithms such as ECDSA and ECDH are widely used in communications, metering, the Internet of Things and other fields. Most related hardware integrates corresponding hardware acceleration circuits to meet the real-time requirements of applications.

[0049] ECC uses many elliptic curve standards, which vary greatly in different application scenarios and result in high costs for repeated design and verification.

[0050] In the prior art, the design of modular multiplication using the improved Montgomery modular reduction method depends on specific elliptic curves and their coefficients (such as the P-256, P-384 and other curves provided by the National Institute of Standards and Technology of the United States), and cannot be used for general elliptic curves (such as brainpool256r1), and is not universal. At the same time, the modular reduction methods between special curves are also different, making it difficult to perform adaptive parameterized expansion. Therefore, the present invention adopts an easily scalable interleaved modular multiplication hardware design to ensure applicability to various types of different elliptic curves.

[0051] In the prior art, hardware circuit design is often only performed for a specific elliptic curve. The designed hardware can only be used for specific applications and is difficult to use in a system-on-chip design that needs to support different elliptic curves. Redesign also requires re-verification, which will introduce a large additional workload. The present invention proposes a method for automatically generating corresponding hardware circuits and driver writing according to input curve parameters (groups). When the elliptic curve support requirements are changed, there is no need to re-design and verify the hardware circuit, which greatly reduces the workload.

[0052] The present invention proposes a parameterized hardware acceleration circuit generation method for prime field elliptic curve encryption, which is used to generate a corresponding elliptic curve hardware acceleration circuit according to the prime field elliptic curve parameters that need to be supported in the design requirements and the speed and area configuration parameters of the hardware acceleration circuit, as well as the driving code corresponding to each prime field elliptic curve to control the acceleration circuit; finally, the generated hardware acceleration circuit is used in the system-on-chip design or a separate accelerator circuit. The present application can meet the hardware acceleration circuit design requirements in different application scenarios with less workload.

[0053] The first embodiment of the present application discloses a method for generating a parameterized hardware acceleration circuit for prime field elliptic curve encryption, such as Figure 1 As shown, the following steps are included:

[0054] Step 1: Extract the relevant parameters in the elliptic curve parameter group to be supported according to the prime domain elliptic curve that needs to be supported in the design requirements. The main parameters include three: the characteristic prime number of the prime domain elliptic curve, the base point of the prime domain elliptic curve, and the base point order of the prime domain elliptic curve. These three parameters, together with the speed and area configuration parameters of the hardware acceleration circuit, affect the generated hardware acceleration circuit.

[0055] Step 2, generating the parameterized hardware acceleration circuit according to the parameters in the extracted elliptic curve parameter group and the speed and area requirements of the parameterized hardware acceleration circuit;

[0056] Generating the parameterized hardware acceleration circuit includes generating a parameterized operation circuit, generating a parameterized prime number lookup table circuit, and generating a parameterized algorithm execution circuit.

[0057] The parameterized operation circuit is used to implement modular operations including modular addition, modular subtraction and interleaved modular multiplication;

[0058] The parameterized prime number lookup table circuit is used to select prime numbers for the parameterized operation circuit to perform modular operations according to design requirements;

[0059] The parameterized algorithm execution circuit is used to control the parameterized prime number lookup table circuit and the parameterized operation circuit to execute the encryption algorithm according to external instructions and configurations.

[0060] Among them, the characteristic prime number of the prime field elliptic curve determines the maximum width that the hardware acceleration circuit needs to support. This width and the speed and area configuration parameters of the hardware acceleration circuit affect the generation of the parameterized operation circuit. The parameterized operation circuit includes two parts, a basic calculation circuit for realizing modular addition, modular subtraction, and shift operations, and a calculation control circuit for controlling the basic calculation circuit to perform operations to further realize interleaved modular multiplication. The basic calculation circuit determines the calculation cycle and selects the adder and / or subtractor according to the speed requirements of the hardware acceleration circuit. Specifically, three optional speed configurations can be supported. When the speed is low, a single adder-subtractor can be used to implement it. Modular addition and modular subtraction are realized by adding first and then subtracting or subtracting first and then adding in two cycles, such as Figure 2 As shown; at higher speeds, a carry-save adder can be used to implement modular addition and modular subtraction in one cycle, but the area is relatively large, such as Figure 3 As shown; when there is a higher speed requirement, the calculation frequency can be further increased by inserting a register in the carry-save adder to realize a pipeline structure. The addition width that can be calculated by the basic calculation circuit is determined by the maximum width of the characteristic prime number of the prime field elliptic curve. Because its structure is relatively simple, it is easy to perform parameterized construction. This basic calculation circuit can also be replaced by a circuit with better performance according to process improvements and design improvements.

[0061] The calculation control circuit controls the basic calculation circuit to realize more complex functions such as interleaved modular multiplication according to the architecture of the basic calculation circuit, including: performing data iteration according to the results of the basic calculation circuit to calculate modular addition and modular subtraction, such as Figure 4 and Figure 5 As shown; according to the input, the basic calculation circuit is controlled to calculate multiple rounds of modular addition to perform interleaved modular multiplication calculations, wherein the number of rounds of modular addition is also determined by the maximum width of the characteristic prime number of the prime field elliptic curve, such as Figure 6 As shown, Figure 6 Where N represents the maximum width of the characteristic prime of the prime field elliptic curve, and R represents the register value in the modular operation.

[0062] The parameterized prime number lookup table circuit selects appropriate prime numbers for the parameterized operation circuit to perform modular operations according to different situations. The content in the lookup table is determined by the characteristic prime number of the input prime field elliptic curve, and the sign bit is filled according to the different characteristic prime numbers and the maximum characteristic prime number bit width to ensure that the data bit width received by the parameterized operation circuit is constant, such as Figure 7 shown.

[0063] The parameterized algorithm execution circuit controls the prime number lookup table circuit and the parameterized operation circuit, and performs higher-level encryption-related algorithms, such as point multiplication, point addition, and doubling operations, according to external instructions and configurations.

[0064] like Figure 8 As shown, the bus slave interface is used to receive configuration information from the system bus, such as enable, interrupt control, calculation instructions, prime number parameter configuration, etc. The read calculation instructions are stored in the instruction storage unit for subsequent calculation control.

[0065] The bus host interface is used to read data from the memory on the system bus. The data can be a number for calculation or a calculation instruction. The calculation instruction is sent to the instruction storage unit, and the calculation data is sent to the data storage unit or the prime number storage unit.

[0066] The numbers used for calculation are stored in the data storage unit, and the maximum bit width supported by the unit is determined by the maximum characteristic prime bit width. The calculation control unit obtains the calculation instruction from the instruction storage unit and sends it to the parameterized operation circuit; the data controller obtains the calculation data from the data storage unit according to the executed calculation instruction and sends it to the parameterized operation circuit.

[0067] In addition to storing the read prime number data, the prime number storage unit can also be used in conjunction with the generated lookup table, providing flexibility in the prime number domain being operated. The prime number controller obtains the prime number data from the prime number storage unit according to the executed calculation instruction and sends it to the parameterized operation circuit.

[0068] By writing different instructions into the instruction storage unit, the calculation control unit can control the generated parameterized operation circuit to perform calculations of various elliptic curve encryption algorithms.

[0069] The encryption algorithms related to prime field elliptic curves are consistent on different curves, and only the corresponding parameters need to be modified.

[0070] Step 3: Generate a driver program for the parameterized hardware acceleration circuit according to the parameters in the extracted elliptic curve parameter group, wherein the driver program is used to control the parameterized hardware acceleration circuit.

[0071] By extracting the relevant parameters in the prime field elliptic curve, a directly available driver can be generated for calling in different applications. Specifically, the driver consists of three parts, namely curve parameter initialization configuration, basic operation implementation and algorithm operation implementation. The curve parameter initialization configuration writes the required curve parameters, such as base point, characteristic prime number, base point order, etc., into the accelerator internal storage or system storage through the system bus as required. The basic operation implementation writes the instructions into the accelerator instruction storage unit according to the instruction format designed by the acceleration circuit, and controls the parameterized operation circuit to perform the corresponding operation. The algorithm operation implementation realizes the existing encryption algorithms, such as elliptic curve cryptography digital signature and elliptic curve Diffie-Hellman key exchange, by combining basic operations. Finally, the user initializes the accelerator by calling the driver, and then uses the algorithm operation implementation provided by the driver or completes his own encryption algorithm through the basic operation implementation according to the user's needs to use the accelerator circuit.

[0072] The present invention designs a parameterized hardware acceleration circuit generation method for prime field elliptic curve encryption, which can automatically generate corresponding hardware description language (HDL) for design and synthesis according to the input elliptic curve parameters that need to be supported. The generated hardware acceleration circuit adopts an interleaved modular multiplication structure to adapt to different parameter curves, and does not need special curves like Montgomery fast modular reduction, which is conducive to adaptive and parameterized generation. This method can effectively improve design efficiency and development speed when designing for different elliptic curve support requirements without reducing design quality.

[0073] The second embodiment of the present application discloses a parameterized hardware acceleration circuit for prime number field elliptic curve encryption, which is generated using the parameterized hardware acceleration circuit generation method for prime number field elliptic curve encryption.

[0074] The third embodiment of the present application discloses a system on a chip, including the parameterized hardware acceleration circuit for prime field elliptic curve encryption.

[0075] The fourth embodiment of the present application discloses an accelerator circuit, including the parameterized hardware acceleration circuit for prime field elliptic curve encryption.

[0076] In a specific implementation, the present application provides a computer storage medium and a corresponding data processing unit, wherein the computer storage medium can store a computer program, and when the computer program is executed by the data processing unit, the invention content of a parameterized hardware acceleration circuit generation method for prime field elliptic curve encryption provided by the present invention and some or all steps in each embodiment can be run. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0077] Those skilled in the art can clearly understand that the technical solutions in the embodiments of the present invention can be implemented by means of computer programs and their corresponding general hardware platforms. Based on this understanding, the technical solutions in the embodiments of the present invention are essentially or partly contributed to the prior art can be embodied in the form of a computer program, i.e., a software product, which can be stored in a storage medium and includes several instructions for enabling a device including a data processing unit (which can be a personal computer, a server, a single-chip microcomputer, a MUU or a network device, etc.) to execute the methods described in various embodiments of the present invention or certain parts of the embodiments.

[0078] The present invention provides a parameterized hardware acceleration circuit generation method for prime field elliptic curve encryption. There are many methods and ways to implement the technical solution. The above is only a preferred implementation of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the protection scope of the present invention. All components not specified in this embodiment can be implemented by existing technologies.

Claims

1. A method for generating a parameterized hardware acceleration circuit for prime field elliptic curve encryption, characterized in that: The following steps are involved: Step 1, extracting parameters in the elliptic curve parameter group according to the prime field elliptic curve that needs to be supported in the design requirements; Step 2, generating the parameterized hardware acceleration circuit according to the parameters in the extracted elliptic curve parameter group and the speed and area requirements of the parameterized hardware acceleration circuit; Step 3: Generate a driver program for the parameterized hardware acceleration circuit according to the parameters in the extracted elliptic curve parameter group, wherein the driver program is used to control the parameterized hardware acceleration circuit.

2. The method for generating a parameterized hardware acceleration circuit for prime field elliptic curve encryption according to claim 1, characterized in that: The parameters in the elliptic curve parameter group extracted in step 1 include the characteristic prime number of the prime field elliptic curve, the base point of the prime field elliptic curve, and the base point order of the prime field elliptic curve.

3. The method for generating a parameterized hardware acceleration circuit for prime field elliptic curve encryption according to claim 2, characterized in that: Generating the parameterized hardware acceleration circuit in step 2 includes generating a parameterized operation circuit, generating a parameterized prime number lookup table circuit, and generating a parameterized algorithm execution circuit. The parameterized operation circuit is used to implement modular operations including modular addition, modular subtraction and interleaved modular multiplication; The parameterized prime number lookup table circuit is used to select prime numbers for the parameterized operation circuit to perform modular operations according to design requirements; The parameterized algorithm execution circuit is used to control the parameterized prime number lookup table circuit and the parameterized operation circuit to execute the encryption algorithm according to external instructions and configurations.

4. The method for generating a parameterized hardware acceleration circuit for prime field elliptic curve encryption according to claim 3, characterized in that: The parameterized operation circuit includes a basic calculation circuit and a calculation control circuit, wherein the basic calculation circuit is used to implement modular operations including modular addition, modular subtraction and shift operations, and the calculation cycle and the adder and / or subtractor are selected according to the speed requirement of the parameterized hardware acceleration circuit; The calculation control circuit is used to control the iteration of the basic calculation circuit to perform modular operations, including: when calculating modular addition and modular subtraction, performing data iteration according to the result of the basic calculation circuit; When calculating the interleaved modular multiplication, the basic calculation circuit is controlled to calculate multiple rounds of modular addition according to the input, wherein the number of rounds of modular addition is determined by the maximum width of the characteristic prime number of the prime field elliptic curve.

5. The method for generating a parameterized hardware acceleration circuit for prime field elliptic curve encryption according to claim 4, characterized in that: The content in the lookup table in the parameterized prime number lookup table circuit is determined according to the characteristic prime number of the input prime number field elliptic curve, and the sign bit is filled according to different characteristic prime numbers and the maximum characteristic prime number bit width.

6. A method for generating a parameterized hardware acceleration circuit for prime field elliptic curve encryption according to claim 5, characterized in that: The parameterized algorithm execution circuit includes a bus slave interface, an instruction storage unit, a calculation control unit, a bus host interface, a data storage unit, a data controller, a prime number storage unit and a prime number controller. The bus slave interface is used to receive configuration information from the system bus, wherein the configuration information includes enable, interrupt control, calculation instructions and prime number parameter configuration, and the read calculation instructions are stored in the instruction storage unit for subsequent calculation control; The bus host interface is used to read data from the memory on the system bus, wherein the data includes data and calculation instructions for calculation, the calculation instructions are sent to the instruction storage unit, and the calculation data are sent to the data storage unit or the prime number storage unit; The calculation control unit obtains the calculation instruction from the instruction storage unit and sends it to the parameterized operation circuit; the data controller obtains the calculation data from the data storage unit according to the executed calculation instruction and sends it to the parameterized operation circuit; the prime number controller obtains the prime number data from the prime number storage unit according to the executed calculation instruction and sends it to the parameterized operation circuit; The calculation control unit controls the parameterized operation circuit generated according to the calculation instructions in the instruction storage unit to perform calculations of various elliptic curve encryption algorithms.

7. A method for generating a parameterized hardware acceleration circuit for prime field elliptic curve encryption according to claim 6, characterized in that: The driver described in step 3 includes curve parameter initialization configuration, basic operation implementation and algorithm operation implementation. The curve parameter initialization configuration writes the parameters in the extracted elliptic curve parameter group into the data storage unit and the prime number storage unit through the system bus; the basic operation implementation writes the instructions into the instruction storage unit according to the instruction format designed for the acceleration circuit, and controls the parameterized operation circuit to perform corresponding operations; the algorithm operation implementation realizes the existing encryption algorithm by combining basic operations; the user initializes the accelerator by calling the driver, and then completes the encryption algorithm according to user needs using the algorithm operation implementation provided by the driver or through the basic operation implementation.

8. A parameterized hardware acceleration circuit for prime field elliptic curve encryption, characterized in that: The method for generating a parameterized hardware acceleration circuit for prime field elliptic curve encryption according to any one of claims 1 to 7 is used for generation.

9. A system on chip, characterized in that: It includes the parameterized hardware acceleration circuit for prime number field elliptic curve encryption as described in claim 8.

10. An accelerator circuit, characterized in that: It includes the parameterized hardware acceleration circuit for prime number field elliptic curve encryption as described in claim 8.

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