A high-speed Ethernet interface conversion circuit based on FPGA

Abstract

The present application provides a high-speed Ethernet interface conversion circuit based on FPGA, which is used for data conversion between the internal user side of FPGA and the MAC layer of high-speed Ethernet. The circuit includes a bridge module and an asynchronous FIFO module; the bridge module is used to transmit data packets and read-write clocks with the MAC layer, and convert the data bit width of the data packet by N times according to the frequency of the read-write clock; the asynchronous FIFO module transmits the converted data packets with the bridge module according to the read-write clock on the bridge module side, and the asynchronous FIFO module transmits the converted data packets with the internal user side of FPGA according to the clock on the internal user side of FPGA; wherein the read-write clock of the asynchronous FIFO module is an asynchronous clock, and the clock frequency of the internal user side of FPGA is one Nth of the clock frequency on the bridge module side. The present application can reduce the internal main frequency of the FPGA chip while keeping the bandwidth of high-speed Ethernet unchanged.

Description

Technical Field

[0001] The present application belongs to the technical field of integrated circuit design, and in particular, relates to a high-speed Ethernet interface conversion circuit based on FPGA. Background Art

[0002] Field Programmable Gate Array (FPGA) is a large-scale programmable device that solves the problem of customized circuits. Users can describe the required functions through hardware description language, and then compile the description language into a bit stream file through software to finally configure the FPGA. The advantages of programmability, reconfigurability, and ease of use make FPGA widely used in various fields.

[0003] With the advancement of chip manufacturing technology and the large-scale application of high-speed Ethernet, some high-performance FPGA chips will integrate 10G / 40G / 50G / 100G Ethernet IP. This IP can further improve the status of FPGA chips in Ethernet applications and significantly increase the bandwidth of Ethernet information interaction.

[0004] The general idea of ​​custom circuit design is to integrate the 10G / 40G / 50G / 100G Ethernet MAC (Media Access Control) IP (Internet Protocol) circuit directly into the chip, so that the user side directly receives the data of the MAC layer. Since the frequency of the data sent by the MAC is relatively high, the custom circuit can be realized through chip design software. However, for FPGA chips, due to their flexible programmable characteristics, if the data sent by the MAC is directly sent to the inside of the FPGA chip, the main frequency of the data to be received inside the FPGA chip is as high as 312.5MHz. Such a high main frequency is more challenging for FPGA chips, and the challenges of FPGA software in layout and routing are also very large, which is basically difficult to achieve.

[0005] Therefore, it is necessary to provide a high-speed Ethernet interface for the FPGA chip to solve the problem of too high main frequency inside the FPGA chip. Summary of the invention

[0006] The present application discloses a high-speed Ethernet interface conversion circuit based on FPGA, which can reduce the internal main frequency of the FPGA chip while keeping the high-speed Ethernet bandwidth unchanged.

[0007] Other purposes and advantages of the present application can be further understood from the technical features disclosed in the present application.

[0008] To achieve one or part or all of the above purposes or other purposes, the present application provides a high-speed Ethernet interface conversion circuit based on FPGA, characterized in that the circuit is used for data conversion between the internal user side of FPGA and the MAC layer of high-speed Ethernet, and the circuit includes a bridge module connected to the MAC layer and an asynchronous FIFO module connected between the bridge module and the internal user side of the FPGA; the bridge module is used to transmit data packets and read-write clocks with the MAC layer, and convert the data bit width of the data packet by N times according to the frequency of the read-write clock, wherein each data packet at least includes data of set bits and corresponding status indication bits; the asynchronous FIFO module transmits the converted data packets with the bridge module according to the read-write clock on the bridge module side, and the asynchronous FIFO module transmits the converted data packets with the internal user side of the FPGA according to the clock on the internal user side of the FPGA; wherein the read-write clock of the asynchronous FIFO module is an asynchronous clock, and the clock frequency of the internal user side of the FPGA is one Nth of the clock frequency of the bridge module side.

[0009] In one implementation, the bridge module at least includes a bridge receiving unit, the asynchronous FIFO module at least includes an asynchronous FIFO receiving unit, and the circuit is used for data conversion between the internal user side of the FPGA and the MAC layer receiving end of the high-speed Ethernet; the bridge receiving unit receives a first received data packet and a first write clock from the MAC layer receiving end, the bridge receiving unit expands the data bit width of the first received data packet by N times, and combines the relevant status indication bit to generate a second received data packet, the bridge receiving unit writes the second received data packet into the asynchronous FIFO receiving unit according to the first write clock; the internal user side of the FPGA reads the second received data packet from the asynchronous FIFO receiving unit according to the first read clock transmission.

[0010] In one implementation, the bridge receiving unit splices N first received data packets to expand the data bit width by N times.

[0011] In one implementation, the bridge receiving unit writes the second received data packet into the asynchronous FIFO receiving unit according to a write enable instruction at every N clock cycles of the first write clock of the asynchronous FIFO receiving unit; wherein the frequency ratio of the first read clock to the first write clock is one-N.

[0012] In one implementation, the asynchronous FIFO receiving unit is used to provide a status signal of the asynchronous FIFO receiving unit to the bridge receiving unit and the FPGA internal user side respectively according to a second received data packet written from the bridge receiving unit side; if the asynchronous FIFO receiving unit is in a non-full state, the bridge receiving unit writes the second received data packet into the asynchronous FIFO receiving unit; if the asynchronous FIFO receiving unit is in a non-empty state, the FPGA internal user side reads the second received data packet from the asynchronous FIFO receiving unit.

[0013] In one implementation, the bridge module at least includes a bridge sending unit, the asynchronous FIFO module includes an asynchronous FIFO sending unit, and the circuit is used for data conversion between the internal user side of the FPGA and the MAC layer sending end of the high-speed Ethernet; the internal user side of the FPGA writes a first sending data packet into the asynchronous FIFO sending unit according to a second write clock input by the internal user side of the FPGA; wherein the read and write clocks of the asynchronous FIFO sending unit are asynchronous clocks; the bridge sending unit reads the first sending data packet from the asynchronous FIFO sending unit according to the second read clock and converts it into a second sending data packet, and the bridge sending unit also sends the second sending data packet to the MAC layer sending end; wherein the bit width of the second sending data packet is lower than the bit width of the first sending data packet, and the frequency of the second write clock is one Nth of the frequency of the second read clock.

[0014] In one implementation, the bridge sending unit monitors the state of the asynchronous FIFO sending unit. If the asynchronous FIFO sending unit is in a non-empty state, the bridge sending unit reads a first sending data packet from the asynchronous FIFO sending unit once every N clock cycles of the second read clock.

[0015] In an implementation manner, the bridge sending unit splits the first sending data packet into N second sending data packets, and cyclically sends the second sending data packets to the MAC layer sending end in sequence.

[0016] In one implementation, the asynchronous FIFO sending unit is used to output a status signal of the asynchronous FIFO sending unit to the bridge sending unit and the FPGA internal user side respectively according to the first sending data packet written by the FPGA internal user side; if the asynchronous FIFO sending unit is in a non-full state, the FPGA internal user side writes the first sending data packet into the asynchronous FIFO sending unit; if the asynchronous FIFO sending unit is in a non-empty state, the bridge sending unit reads the first sending data packet from the asynchronous FIFO sending unit.

[0017] In one implementation, the maximum value of N is 4.

[0018] The above-mentioned FPGA-based high-speed Ethernet interface conversion circuit expands the data bit width of the data packet by N times through the bridge module while keeping the high-speed Ethernet bandwidth unchanged, and reduces the clock frequency of the user side inside the FPGA to one-Nth of the clock frequency on the bridge module side, thereby reducing the internal main frequency of the FPGA and meeting the usage requirements of the user side inside the FPGA.

[0019] In order to make the above and other purposes, features and advantages of the present application more obvious and understandable, preferred embodiments are specifically listed below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the specific embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1 This is a schematic diagram of a high-speed Ethernet interface conversion circuit based on FPGA in this application.

[0022] Figure 2 This is a schematic diagram of another FPGA-based high-speed Ethernet interface conversion circuit of the present application. DETAILED DESCRIPTION

[0023] The aforementioned and other technical contents, features and effects of the present application will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances. This is just a way of distinguishing objects with the same attributes when describing the embodiments of the present application.

[0024] During the research, the inventors of the present application found that for FPGA chips, if the data sent by MAC is sent directly to the inside of the FPGA chip, the main frequency of the data to be received inside the FPGA chip is as high as 312.5MHz, and the data bit width is also relatively wide. The user's interface main frequency and interface bit width are consistent with MAC. Such a high main frequency is more challenging for FPGA chips, and the challenges of FPGA software during layout and routing are also very great, which is basically difficult to achieve.

[0025] Therefore, the present application provides a high-speed Ethernet interface conversion circuit based on FPGA, which is used to solve the problem of interaction between the high-speed MAC IP in the FPGA chip and the internal part of the FPGA chip, thereby satisfying the high bandwidth of the high-speed MAC IP on the one hand, and satisfying the problem that the main frequency of the user circuit of the FPGA chip should not be too high on the other hand.

[0026] The present application provides a high-speed Ethernet interface conversion circuit based on FPGA (hereinafter referred to as "interface conversion circuit"), such as Figure 1 As shown, the bridge module and the asynchronous FIFO (First Input First Output) module are sequentially connected between the MAC layer of the high-speed Ethernet and the internal user side of the FPGA to exchange information. The bridge module is used to transmit data packets and read-write clocks with the MAC layer, and convert the data bit width of the data packet by N times according to the frequency of the read-write clock, wherein each data packet at least includes data of the set bit and the corresponding status indication bit; the asynchronous FIFO module transmits the converted data packet with the bridge module according to the read-write clock on the bridge module side, and the asynchronous FIFO module transmits the converted data packet with the internal user side of the FPGA according to the clock on the internal user side of the FPGA; wherein the read-write clock of the asynchronous FIFO module is an asynchronous clock, and the clock frequency of the internal user side of the FPGA is one-Nth of the clock frequency on the bridge module side. The present application expands the data packet to be transmitted by N times through the bridge module, and configures the clock on the internal user side of the FPGA to be one-Nth of the clock on the bridge module side, thereby realizing data synchronization between different clock domains, and realizing that the clock frequency of the internal user side of the FPGA receiving data through the high-speed Ethernet is reduced by converting the data bit width while the bandwidth of the high-speed Ethernet remains unchanged. Moreover, the circuit helps reduce electromagnetic interference and signal integrity problems caused by high-frequency signals, and improves the stability and reliability of data transmission.

[0027] Among them, the high-speed Ethernet interface conversion circuit of the present application is suitable for high-speed Ethernet with bandwidth 10G / 40G / 50G / 100G, and the MAC layer data interface frequency (MHz: megahertz) and data interface bit width (bit: bit) of 10G / 40G / 50G / 100G Ethernet IP are as follows: 10G (32bit*312.5MHz), 25G (128bit*195.3125MHz), 50G (128bit*2lane*195.3125MHz), 100G (128bit*4lane*195.3125MHz).

[0028] The FPGA-based high-speed Ethernet interface conversion circuit of the present application is described in detail below with reference to the accompanying drawings.

[0029] like Figure 2As shown, between the internal user side of the FPGA and the MAC layer receiving end, data conversion is performed through the bridge receiving unit and the asynchronous FIFO receiving unit to process high-speed signals. Among them, the first received data packet data0_rx includes 128-bit data, 96-bit status indication bits, etc., the first write clock clock0_rx is a 195.3125Mhz clock, the second received data packet data1_rx is 512-bit data, 96-bit status indication bits, etc., and the first read clock clock1_rx frequency is at least one-fourth of the first write clock clock0_rx frequency, that is, the internal user side clock frequency of the FPGA can be reduced by up to 4 times. It should be noted that if the data bit width is widened by 4 times, the first read clock clock1_rx frequency is one-fourth of the first write clock clock0_rx frequency; if the data bit width is widened by 2 times, the first read clock clock1_rx frequency is one-half of the first write clock clock0_rx frequency. It can be seen that the present application provides more clock options for the FPGA user side, and the appropriate clock frequency can be selected according to actual needs to adapt to different application scenarios.

[0030] When the user side inside the FPGA receives data through high-speed Ethernet, the bridge receiving unit receives the 128-bit data and related status indication bits of the first received data packet data0_rx sent by the MAC layer receiving end, and splices the 128-bit data of the first received data packet data0_rx of 4 cycles into 512 bits, widens the 128-bit data into 512-bit data, and simultaneously forms a new data packet, namely, the second received data packet data1_rx, with the related status indication bits sop (start of packet), eop (end of packet) and 512-bit data. It can be seen that the present application combines multiple data with lower bit widths into wider data bits for transmission by widening or splicing, and also reduces the number of data transmissions and improves data transmission efficiency.

[0031] The bridge receiving unit monitors the state of the asynchronous FIFO receiving unit at the same time. When the asynchronous FIFO receiving unit is not full, data is written into the asynchronous FIFO receiving unit every 4 cycles of the first write clock clock0_rx, and the second received data packet data1_rx is written into the asynchronous FIFO receiving unit through the write enable signal wr_en. When the asynchronous FIFO receiving unit receives the data written by the bridge receiving unit, it outputs empty and full state indication signals to the internal user side of the FPGA and the bridge receiving unit respectively. The read and write clocks of the asynchronous FIFO receiving unit are asynchronous clocks. Here, the frequency of the first read clock clock1_rx on the internal user side of the FPGA is one-fourth of the frequency of the first write clock clock0_rx on the bridge receiving unit side. Thus, under the condition that the bandwidth of the high-speed Ethernet remains unchanged, the purpose of reducing the main frequency of the internal user side of the FPGA is achieved by widening the bit width and correspondingly reducing the clock frequency. After the second received data packet is written into the asynchronous FIFO receiving unit, the empty signal of the asynchronous FIFO receiving unit will be pulled low, that is, the asynchronous FIFO receiving unit is in a non-empty state, thereby instructing the internal user side of the FPGA to perform a read operation, and the internal user side of the FPGA then performs the next specific data parsing operation.

[0032] When the user side inside the FPGA sends data via high-speed Ethernet, data conversion is performed between the user side inside the FPGA and the MAC layer transmitter through a bridge transmission unit and an asynchronous FIFO transmission unit to process high-speed signals. Among them, the first transmission data packet data1_tx includes 512-bit data, 96-bit status indication bits, etc., the second transmission data packet data1_rx is 128-bit data, 96-bit status indication bits, etc., the second read clock clock0_tx is a 195.3125Mhz clock, and the second write clock clock1_tx frequency is at least one-fourth of the second read clock clock0_tx frequency. It should be noted that the clock frequency ratio here can also be one-half, which can be flexibly adjusted according to actual needs.

[0033] The user side inside the FPGA initiates a write operation, and when the asynchronous FIFO sending unit is detected to be not full, the first sending data packet data1_tx containing 512-bit data is written into the asynchronous FIFO sending unit. The asynchronous FIFO sending unit receives the first sending data packet data1_tx written by the user side inside the FPGA, and outputs the empty and full status indication bits to the user side inside the FPGA and the bridge sending unit respectively. The read and write clocks of the asynchronous FIFO sending unit are asynchronous clocks, and the frequency of the second write clock clock1_tx on the user side inside the FPGA is one-fourth the frequency of the second read clock clock0_tx on the bridge sending unit side.

[0034] The bridge transmission unit monitors the output of the empty and full status indication signals of the asynchronous FIFO transmission unit. When it detects that there is data in the asynchronous FIFO transmission unit, that is, when it is not empty, it actively reads the first transmission data packet data1_tx from the asynchronous FIFO transmission unit, and reads the data once every 4 cycles of the second read clock clock0_tx. After reading the data, the bridge transmission unit splits the 512-bit data of the first transmission data packet data1_tx into 4 128-bit data, and composes the 128-bit data and related status indication bits into the second transmission data packet data0_tx, and sequentially sends the second transmission data packet data0_tx to the MAC layer transmission end. It can be seen that, under the condition that the high-speed Ethernet bandwidth remains unchanged, by reducing the clock frequency and widening the data bit width, the purpose of reducing the internal main frequency of the FPGA is achieved, and the data reception and transmission of the MAC layer transmission end are not affected.

[0035] It should be noted that the high-speed Ethernet interface conversion circuit of the present application can independently realize the demand for processing high-speed signals when the user side inside the FPGA receives data, and can also independently realize the demand for processing high-speed signals when the user side inside the FPGA sends data. The specific processing flow is as above and will not be repeated here.

[0036] It should be noted that the interface conversion circuit of the present application is also applicable to artificial intelligence SOC chips, large network processing NP chips, etc. The chip can realize the processing of high-speed signals by integrating the interface conversion circuit of the present application.

[0037] In summary, through the above-mentioned FPGA-based high-speed Ethernet interface conversion circuit, the data is spliced ​​or split while the bandwidth of the high-speed Ethernet remains unchanged to reduce the clock frequency of the user side inside the FPGA, thereby realizing flexible regulation of the high-speed Ethernet circuit on the user side inside the FPGA, and also meeting the realization of the layout and wiring of the user side inside the FPGA. At the same time, the present application can also adapt to the needs of different bandwidths by adjusting the ratio of data bit width and clock frequency, and has strong scalability.

[0038] It should be noted that, for those of ordinary skill in the art, several improvements and modifications may be made to the present application without departing from the principles of the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application. It should be understood that certain features of the present disclosure described in the context of a separate embodiment for the sake of clarity may also be provided in a single embodiment by combination. Conversely, various features of the present disclosure described in the context of a single embodiment for the sake of clarity may also be provided individually or in any suitable combination or as any other described embodiment of the present disclosure.

Claims

1. A high-speed Ethernet interface conversion circuit based on FPGA, characterized in that: The circuit is used for data conversion between the internal user side of the FPGA and the MAC layer receiving end of the high-speed Ethernet, and the circuit includes a bridge module connected to the MAC layer, and an asynchronous FIFO module connected between the bridge module and the internal user side of the FPGA; The bridge module is used to transmit data packets and read / write clocks with the MAC layer, and convert the data bit width of the data packet by N times according to the frequency of the read / write clock, wherein each data packet at least includes data of a set bit and a corresponding status indication bit, and the bridge module at least includes a bridge receiving unit, which receives a first received data packet and a first write clock from a receiving end of the MAC layer, and the bridge receiving unit expands the data bit width of the first received data packet by N times, and generates a second received data packet in combination with the relevant status indication bit; The asynchronous FIFO module transmits the converted data packet with the bridge module according to the read and write clock of the bridge module side, and the asynchronous FIFO module transmits the converted data packet with the internal user side of the FPGA according to the clock of the internal user side of the FPGA; wherein the read and write clock of the asynchronous FIFO module is an asynchronous clock, and the clock frequency of the internal user side of the FPGA is one-Nth of the clock frequency of the bridge module side; the asynchronous FIFO module at least includes an asynchronous FIFO receiving unit, and the bridge receiving unit writes the second received data packet into the asynchronous FIFO receiving unit according to the first write clock; the internal user side of the FPGA reads the second received data packet from the asynchronous FIFO receiving unit according to the first read clock transmission, and the frequency ratio of the first read clock to the first write clock is one-Nth.

2. The FPGA-based high-speed Ethernet interface conversion circuit according to claim 1, characterized in that: The bridge receiving unit splices N first received data packets to expand the data bit width by N times.

3. The FPGA-based high-speed Ethernet interface conversion circuit according to claim 1, characterized in that: At intervals of N clock cycles of the first write clock of the asynchronous FIFO receiving unit, the bridge receiving unit writes the second received data packet into the asynchronous FIFO receiving unit according to the write enable instruction.

4. The FPGA-based high-speed Ethernet interface conversion circuit according to claim 3, characterized in that: The asynchronous FIFO receiving unit is used to provide a state signal of the asynchronous FIFO receiving unit to the bridge receiving unit and the internal user side of the FPGA respectively according to the second received data packet written from the bridge receiving unit side; If the asynchronous FIFO receiving unit is in a non-full state, the bridge receiving unit writes the second received data packet into the asynchronous FIFO receiving unit; If the asynchronous FIFO receiving unit is in a non-empty state, the user side inside the FPGA reads the second received data packet from the asynchronous FIFO receiving unit.

5. A high-speed Ethernet interface conversion circuit based on FPGA according to any one of claims 1 to 4, characterized in that: The bridge module at least includes a bridge transmission unit, the asynchronous FIFO module includes an asynchronous FIFO transmission unit, and the circuit is used for data conversion between the user side inside the FPGA and the MAC layer transmission end of the high-speed Ethernet; The FPGA internal user side writes the first transmission data packet into the asynchronous FIFO transmission unit according to the second write clock input by the FPGA internal user side; wherein the read and write clock of the asynchronous FIFO transmission unit is an asynchronous clock; The bridge sending unit reads a first sending data packet from the asynchronous FIFO sending unit according to a second read clock and converts it into a second sending data packet. The bridge sending unit also sends the second sending data packet to the MAC layer sending end; wherein the bit width of the second sending data packet is lower than the bit width of the first sending data packet, and the frequency of the second write clock is one Nth of the frequency of the second read clock.

6. The FPGA-based high-speed Ethernet interface conversion circuit according to claim 5, characterized in that: The bridge sending unit monitors the state of the asynchronous FIFO sending unit. If the asynchronous FIFO sending unit is in a non-empty state, the bridge sending unit reads a first sending data packet from the asynchronous FIFO sending unit once every N clock cycles of the second read clock.

7. The FPGA-based high-speed Ethernet interface conversion circuit according to claim 6, characterized in that: The bridge sending unit splits the first sending data packet into N second sending data packets, and cyclically sends the second sending data packets to the MAC layer sending end in sequence.

8. The FPGA-based high-speed Ethernet interface conversion circuit according to claim 5, characterized in that: The asynchronous FIFO sending unit is used to output a state signal of the asynchronous FIFO sending unit to the bridge sending unit and the FPGA internal user side respectively according to the first sending data packet written by the FPGA internal user side; If the asynchronous FIFO sending unit is in a non-full state, the user side inside the FPGA writes the first sending data packet into the asynchronous FIFO sending unit; If the asynchronous FIFO sending unit is in a non-empty state, the bridge sending unit reads a first sending data packet from the asynchronous FIFO sending unit.

9. The FPGA-based high-speed Ethernet interface conversion circuit according to claim 1, characterized in that: The maximum value of N is 4.

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