Method and device for generating integrated cell library, and digital method, device and chip for integrated cell library

Abstract

The present disclosure relates to the field of chip IP core and EDA technology, and specifically to a method and device for generating an integrated cell library, and a digital method, device and chip for the integrated cell library. The IP core provided by existing IP manufacturers is usually an integral module that can only provide fixed input configuration parameters and cannot be easily changed according to chip requirements. The present disclosure has developed a customized EDA tool, customized the IP core, reconstructed a customized IP core that supports flexible configuration of input configuration parameters, and integrated these customized IP cores into an integrated cell library that is different from the traditional standard cell library. This solves the problems existing in the comprehensiveness and integration of the traditional standard cell library, and also solves the problems existing in the current traditional POC IP core, IO IP core and standard cell, thereby better meeting the needs of modern chip design.

Description

Technical Field

[0001] The present disclosure relates to the field of chip IP core and EDA technology, and in particular to a method and device for generating an integrated cell library, and a digitized method, device and chip for the integrated cell library. Background Art

[0002] In the field of integrated circuit and chip design, standard cell libraries (STDs) are an indispensable foundation for the back-end design process. These libraries typically include layout libraries, symbol libraries, and circuit logic libraries, covering combinational logic, sequential logic, functional units, and special-type units. They provide designers with pre-designed, optimized library cells. These library cells are widely used in automated logic synthesis and layout and routing processes, significantly improving design efficiency and shortening time to market.

[0003] When creating semiconductor integrated circuits, standardized logic elements are typically pre-designed. These logic elements are then combined to create multiple standard cells, which are then pre-registered in a standard cell library. In the design of digital ICs and mixed-analog / digital ICs, designers can utilize these pre-optimized library cells to automate logic synthesis and layout routing, greatly simplifying the design process and significantly shortening product development cycles.

[0004] However, traditional standard cell libraries mainly focus on basic logic circuits such as INV, NAND, NOR, DFF triggers, etc., but often ignore key modules such as power-on control (POC) IP cores and input / output (IO) IP cores. Although the standard cell libraries provided by most processes contain a series of pre-designed basic standard cells, these libraries are not comprehensive enough and lack comprehensive consideration of analog characteristics in the actual physical world. In fact, every chip needs to have functions such as power-on control and input / output interfaces in real application scenarios to ensure its stable and reliable operation. Therefore, for modern chip design, a more comprehensive and highly integrated standard cell library is particularly important.

[0005] How to solve the shortcomings of traditional standard cell libraries in terms of comprehensiveness and integration, so as to better meet the needs of modern chip design and provide more efficient and reliable design tools for modern chip design, is an urgent problem to be solved. Summary of the Invention

[0006] In order to solve the problems in the related art, the embodiments of the present disclosure provide a method and device for generating an integrated cell library, and a method, device and chip for digitizing the integrated cell library.

[0007] In a first aspect, an embodiment of the present disclosure provides a method for generating an integrated cell library. The method is implemented based on a customized EDA tool. The customized EDA tool provides a GUI interface. The GUI interface includes multiple customized input boxes. The customized input boxes are used to obtain configuration parameters input by a user. The method includes:

[0008] Generate a layout of a customized IP core according to the configuration parameters input by the user; the customized IP core includes one or more of the following items: a customized POC IP core, a customized IO IP core, an IO IP core with power-on control, and a customized unit with power-on control;

[0009] Generate an integrated cell library based on the layout of the customized IP core;

[0010] Generating a layout of a customized POC IP core according to the configuration parameters input by the user includes: generating the customized POC IP core according to a configurable POC IP core and a first configuration parameter input by the user; generating a layout of the customized POC IP core based on the customized POC IP core; the first configuration parameter includes: a POC input threshold voltage;

[0011] Generating a layout of a customized IO IP core according to the configuration parameters input by the user, comprising: generating the customized IO IP core according to the configurable IO IP core and second configuration parameters input by the user; generating a layout of the customized IO IP core based on the customized IO IP core, wherein the second configuration parameters include one or more of the following items: input high-level threshold voltage, input low-level threshold voltage, high-level output source current, low-level output sink current, and electrostatic discharge protection level;

[0012] Generating a layout of an IO IP core with power-on control according to the configuration parameters input by the user, comprising: generating the IO IP core with power-on control according to the IO IP core and the configurable POC IP core and a third configuration parameter input by the user; generating a layout of the IO IP core with power-on control based on the IO IP core with power-on control; the third configuration parameter comprising one or more of the following items: a POC input threshold voltage, an input high-level threshold voltage, an input low-level threshold voltage, a high-level output source current, a low-level output sink current, and an electrostatic discharge protection level;

[0013] Generating a layout of a custom unit with power-on control according to the configuration parameters input by the user includes: generating the custom unit with power-on control according to the POC IP core and the standard cell module; generating a layout of the custom unit with power-on control based on the custom unit with power-on control; when the POC IP core is a customized POC IP core, generating the custom unit with power-on control according to the POC IP core and the standard cell module includes: generating the custom unit with power-on control according to the customized POC IP core and the standard cell module and the first configuration parameters.

[0014] According to an embodiment of the present disclosure, generating an integrated cell library based on the layout of the customized IP core includes:

[0015] Verify the layout of the customized IP core, including design rule checking (DRC) and layout and schematic comparison (LVS);

[0016] Generating post-simulation netlist data of the layout of the customized IP core; the post-simulation netlist data is used to describe the circuit structure and connection relationship of the layout of the customized IP core;

[0017] Verify the post-simulation netlist data to ensure that it is consistent with the version of the custom IP core. Figure 1 To;

[0018] Inputting the post-simulation netlist data into a pre-provided Tcl script file, and adding attribute parameters related to the customized IP core in the Tcl script file, wherein the attribute parameters include one or more of the following items: function description, area, pin information, delay, and power consumption;

[0019] Generate a model file according to the Tcl script file, and verify the model file to ensure that the model file can correctly simulate the behavior of the customized IP core, the model file including: a Verilog model file or a VHDL model file;

[0020] Perform post-simulation verification using the model file;

[0021] An integrated unit library is generated based on the model file using a library file generation tool.

[0022] According to an embodiment of the present disclosure, the method further includes: verifying the integrated cell library.

[0023] According to an embodiment of the present disclosure, generating post-simulation netlist data of the layout of the customized IP core includes:

[0024] Extracting parasitic parameters from the layout of the custom IP core using a layout extraction tool; the parasitic parameters include resistance, capacitance, and inductance;

[0025] Obtaining pre-simulation netlist data of the layout of the customized IP core;

[0026] The parasitic parameters are added to the pre-simulation netlist data to generate post-simulation netlist data of the layout of the customized IP core including the parasitic parameters.

[0027] According to an embodiment of the present disclosure, the step of using a library file generation tool and generating an integrated unit library based on the model file includes:

[0028] Select the model file;

[0029] Configuring properties of the integrated unit library, the properties of the integrated unit library including: library name, version, and description;

[0030] Execute the command or operation for generating the library file in the library file generating tool.

[0031] According to an embodiment of the present disclosure, generating the customized POC IP core according to the configurable POC IP core and the first configuration parameter input by the user includes:

[0032] Obtain a configurable POC IP core, wherein the configurable POC IP core includes: a POC core circuit module and a POC input threshold voltage adjustable module;

[0033] Obtaining a POC input threshold voltage input by a user through the plurality of customized input boxes;

[0034] Configuring the POC input threshold voltage adjustable module according to the POC input threshold voltage, the POC input threshold voltage adjustable module including a first MOS module group, configuring the POC input threshold voltage adjustable module according to the POC input threshold voltage includes: selecting a number of MOS modules corresponding to the POC input threshold voltage from the first MOS module group and connecting the selected MOS modules to generate a configured POC input threshold voltage adjustable module, the configured POC input threshold voltage adjustable module being used to generate a POC first control signal of the POC core circuit module;

[0035] Connecting the POC core circuit module and the configured POC input threshold voltage adjustable module to generate a customized POC IP core, wherein the customized POC IP core is used to generate a POC control signal;

[0036] The POC core circuit module includes: a POC first control signal input port and a POC control signal output port; the configured POC input threshold voltage adjustable module includes: a POC first control signal output port; the POC core circuit module and the configured POC input threshold voltage adjustable module also include: a power supply voltage port and a ground port;

[0037] The power supply voltage ports of the POC core circuit module and the configured POC input threshold voltage adjustable module are both connected to the first power supply and the second power supply, and the ground ports of the POC core circuit module and the configured POC input threshold voltage adjustable module are both grounded;

[0038] The POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to the POC first control signal input port of the POC core circuit module, for providing the POC first control signal to the POC core circuit module; the POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to a MOS module selected from the first MOS module group.

[0039] According to an embodiment of the present disclosure, the POC input threshold voltage adjustable module further includes: a resistance module group;

[0040] Configuring the POC input threshold voltage adjustable module according to the POC input threshold voltage further includes: selecting resistor modules with a number and resistance value corresponding to the POC input threshold voltage from the resistor module group and connecting the selected MOS modules and resistor modules to generate the configured POC input threshold voltage adjustable module.

[0041] According to an embodiment of the present disclosure, the method further includes: performing resistance subdivision adjustment on the configured POC input threshold voltage adjustable module, including: adjusting the resistance value or connection mode of the resistors in the configured POC input threshold voltage adjustable module, or adjusting the number of resistors in the configured POC input threshold voltage adjustable module, so as to achieve resistance subdivision adjustment of the configured POC input threshold voltage adjustable module; wherein the connection mode includes: series connection, parallel connection, or a series-parallel mixed mode.

[0042] According to an embodiment of the present disclosure, generating the customized IO IP core according to the configurable IO IP core and the second configuration parameter input by the user includes:

[0043] Obtain a configurable IO IP core, the configurable IO IP core including an IO core circuit module, an input threshold adjustable module, and an output current and electrostatic discharge protection level adjustable module, the input threshold adjustable module including a second MOS module group, the output current and electrostatic discharge protection level adjustable module including a plurality of unit output current and electrostatic discharge protection level adjustable modules, and the unit output current and electrostatic discharge protection level adjustable module including a plurality of MOS modules;

[0044] Obtaining, through the multiple custom input boxes, the input threshold high level voltage, input threshold low level voltage, high level output source current, low level output sink current, and electrostatic discharge protection level input by the user for the specified pin module of the customized IO IP core;

[0045] Configuring the input threshold adjustable module according to the input threshold high level voltage and the input threshold low level voltage, including: selecting a MOS module from the second MOS module group according to the input threshold high level voltage and the input threshold low level voltage and connecting the selected MOS module to generate a configured input threshold adjustable module, wherein the configured input threshold adjustable module is used to generate an IO first control signal of the IO core circuit module;

[0046] Configuring the output current and electrostatic release protection level adjustable module according to the high-level output source current, the low-level output sink current, and the electrostatic release protection level, including: selecting one or more unit output current and electrostatic release protection level adjustable modules from the output current and electrostatic release protection level adjustable modules according to the electrostatic release protection level, and connecting the selected one or more unit output current and electrostatic release protection level adjustable modules to generate a primary configured output current and electrostatic release protection level adjustable module, wherein the primary configured output current and electrostatic release protection level adjustable module includes a third MOS module group; selecting a MOS module from the third MOS module group according to the high-level output source current and the low-level output sink current, and connecting the selected MOS modules to generate a configured output current and electrostatic release protection level adjustable module, wherein the configured output current and electrostatic release protection level adjustable module is used to provide a specified electrostatic release protection capability corresponding to the electrostatic release protection level and provide a specified output current capability under the control of an IO second control signal of the IO core circuit module;

[0047] Connecting the IO core circuit module, the configured input threshold adjustable module, and the configured output current and electrostatic discharge protection level adjustable module to generate a designated pin module of the customized IO IP core;

[0048] The IO core circuit module includes: a power supply voltage port, a ground port, an IO first control signal input port, and an IO second control signal output port; the configured input threshold adjustable module includes: a power supply voltage port, a ground port, and an IO first control signal output port; the configured output current and electrostatic discharge protection level adjustable module includes: a power supply voltage port, a ground port, and an IO second control signal input port;

[0049] The power supply voltage ports of the IO core circuit module, the configured input threshold adjustable module, and the configured output current and electrostatic discharge protection level adjustable module are all connected to the power supply voltage, and the ground ports are all grounded;

[0050] The IO first control signal output port of the configured input threshold adjustable module is connected to the MOS module selected from the second MOS module group, and the IO first control signal output port of the configured input threshold adjustable module is connected to the IO first control signal input port of the IO core circuit module, for providing the IO first control signal to the IO core circuit module;

[0051] The IO second control signal output port of the IO core circuit module is connected to the IO second control signal input port of the configured output current and electrostatic discharge protection level adjustable module, and is used to output the IO second control signal to the configured output current and electrostatic discharge protection level adjustable module based on the IO first control signal and the IO input signal;

[0052] The second control signal input port of the IO of the configured output current and electrostatic discharge protection level adjustable module is connected to a MOS module selected from the third MOS module group; wherein, in the third MOS module group, the selected MOS module provides a first electrostatic discharge protection capability and the specified output current capability, and the remaining MOS modules provide a second electrostatic discharge protection capability, and the first electrostatic discharge protection capability and the second electrostatic discharge protection capability together constitute the specified electrostatic discharge protection capability;

[0053] Based on the designated pin module of the customized IO IP core, a first designated pin circuit layout of the customized IO IP core is generated.

[0054] According to an embodiment of the present disclosure, the IO second control signal input port of the configured output current and electrostatic discharge protection level adjustable module is connected to a MOS module selected from the second MOS module group, including: in any unit output current and electrostatic discharge protection level adjustable module of the configured output current and electrostatic discharge protection level adjustable module:

[0055] All MOS modules in any unit electrostatic discharge protection module are connected to the second control signal input port of the IO of any unit electrostatic discharge protection module, and all connected MOS modules provide unit electrostatic discharge protection capability and unit output current capability at the same time;

[0056] Alternatively, some MOS modules in any one of the unit electrostatic discharge protection modules are connected to the IO second control signal input port of any one of the unit electrostatic discharge protection modules, and the connected part of the MOS modules simultaneously provide corresponding electrostatic discharge protection capabilities and output current capabilities, and the remaining MOS modules provide corresponding electrostatic discharge protection capabilities;

[0057] Alternatively, all MOS modules in any unit electrostatic release protection module are disconnected from the IO second control signal input port of any unit electrostatic release protection module, and all disconnected MOS modules provide unit electrostatic release protection capability.

[0058] According to an embodiment of the present disclosure, when some MOS modules in any unit electrostatic release protection module are connected to the IO second control signal input port of any unit electrostatic release protection module, among the remaining MOS modules in any unit electrostatic release protection module: the gates of some MOS modules are connected to the power supply voltage through the power supply voltage port, and the gates of other MOS modules are grounded through the ground port;

[0059] When all MOS modules in any unit electrostatic release protection module are disconnected from the IO second control signal input port of any unit electrostatic release protection module, among all MOS modules in any unit electrostatic release protection module: the gates of some MOS modules are connected to the power supply voltage through the power supply voltage port, and the gates of other MOS modules are grounded through the ground port.

[0060] According to an embodiment of the present disclosure, the gates of a portion of the MOS modules are connected to a power supply voltage through a power supply voltage port, and the gates of another portion of the MOS modules are grounded through a ground port, including:

[0061] The gates and sources of a part of the MOS modules are short-circuited and then connected to the power supply voltage through the power supply voltage port, and the gates and sources of another part of the MOS modules are short-circuited and then grounded through the ground port.

[0062] According to an embodiment of the present disclosure, when some MOS modules in any unit electrostatic discharge protection module are connected to the IO second control signal input port of any unit electrostatic discharge protection module, in the remaining MOS modules of any unit electrostatic discharge protection module: the gates of some MOS modules are connected to the power supply voltage through the resistor module and the power supply voltage port, and the gates of other MOS modules are grounded through the resistor module and the ground port;

[0063] When all the MOS modules in any one of the unit electrostatic release protection modules are disconnected from the IO second control signal input port of any one of the unit electrostatic release protection modules, among all the MOS modules in any one of the unit electrostatic release protection modules: the gates of some of the MOS modules are connected to the power supply voltage through the resistance module and the power supply voltage port, and the gates of other part of the MOS modules are grounded through the resistance module and the ground port.

[0064] According to an embodiment of the present disclosure, the gates of a portion of the MOS modules are connected to a power supply voltage through a resistor module and a power supply voltage port, and the gates of another portion of the MOS modules are grounded through a resistor module and a ground port, including:

[0065] The gates and sources of a part of the MOS modules are short-circuited and connected to the power supply voltage through the resistance module and the power supply voltage port, and the gates and sources of the other part of the MOS modules are short-circuited and grounded through the resistance module and the ground port.

[0066] According to an embodiment of the present disclosure, generating the IO IP core with power-on control according to the IO IP core, the configurable POC IP core, and the third configuration parameter input by the user includes:

[0067] Obtain a configurable POC IP core, wherein the configurable POC IP core includes: a POC core circuit module and a POC input threshold voltage adjustable module;

[0068] Get IO IP core;

[0069] Obtaining a POC input threshold voltage input by a user through the plurality of customized input boxes;

[0070] Configuring the POC input threshold voltage adjustable module according to the POC input threshold voltage, the POC input threshold voltage adjustable module including a first MOS module group, configuring the POC input threshold voltage adjustable module according to the POC input threshold voltage includes: selecting a number of MOS modules corresponding to the POC input threshold voltage from the first MOS module group and connecting the selected MOS modules to generate a configured POC input threshold voltage adjustable module, the configured POC input threshold voltage adjustable module being used to generate a POC first control signal of the POC core circuit module;

[0071] Connecting the POC core circuit module and the configured POC input threshold voltage adjustable module to generate a customized POC IP core, wherein the customized POC IP core is used to generate a POC control signal;

[0072] Connecting the customized POC IP core and the IO IP core to generate an IO IP core with power-on control; wherein the POC core circuit module includes: a POC first control signal input port and a POC control signal output port; the configured POC input threshold voltage adjustable module includes: a POC first control signal output port; the IO IP core includes: a POC control signal input port; the IO IP core, the POC core circuit module and the configured POC input threshold voltage adjustable module also include: a power supply voltage port and a ground port;

[0073] The power supply voltage ports of the IO IP core, the POC core circuit module, and the configured POC input threshold voltage adjustable module are all connected to a first power supply and a second power supply, and the ground ports of the IO IP core, the POC core circuit module, and the configured POC input threshold voltage adjustable module are all grounded;

[0074] The POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to the POC first control signal input port of the POC core circuit module, for providing the POC first control signal to the POC core circuit module; the POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to a MOS module selected from the first MOS module group;

[0075] The POC control signal output port of the POC core circuit module is connected to the POC control signal input port of the IO IP core, so that the IO IP core controls the output of its own current through the POC control signal output by the customized POC IP core.

[0076] According to an embodiment of the present disclosure, the IO IP core controls the output of its own current through the POC control signal output by the customized POC IP core, including:

[0077] When either the first power supply or the second power supply is powered off, the POC control signal output by the customized POC IP core is at a low level; when the POC control signal is at a low level, the IO IP core controls itself to not output current and enters a high-impedance state;

[0078] When the first power supply and the second power supply are fully powered on, the POC control signal output by the customized POC IP core is at a high level; when the POC control signal is at a high level, the IO IP core controls its own normal output current.

[0079] According to an embodiment of the present disclosure, the IO IP core is a customized IO IP core, and obtaining the IO IP core includes:

[0080] Obtain a configurable IO IP core, the configurable IO IP core including an IO core circuit module, an input threshold adjustable module, and an output current and electrostatic discharge protection level adjustable module, the input threshold adjustable module including a second MOS module group, the output current and electrostatic discharge protection level adjustable module including a plurality of unit output current and electrostatic discharge protection level adjustable modules, and the unit output current and electrostatic discharge protection level adjustable module including a plurality of MOS modules;

[0081] Obtaining, through the multiple custom input boxes, the input threshold high level voltage, input threshold low level voltage, high level output source current, low level output sink current, and electrostatic discharge protection level input by the user for the specified pin module of the customized IO IP core;

[0082] Configuring the input threshold adjustable module according to the input threshold high level voltage and the input threshold low level voltage, including: selecting a MOS module from the second MOS module group according to the input threshold high level voltage and the input threshold low level voltage and connecting the selected MOS module to generate a configured input threshold adjustable module, wherein the configured input threshold adjustable module is used to generate an IO first control signal of the IO core circuit module;

[0083] Configuring the output current and electrostatic release protection level adjustable module according to the high-level output source current, the low-level output sink current, and the electrostatic release protection level, including: selecting one or more unit output current and electrostatic release protection level adjustable modules from the output current and electrostatic release protection level adjustable modules according to the electrostatic release protection level, and connecting the selected one or more unit output current and electrostatic release protection level adjustable modules to generate a primary configured output current and electrostatic release protection level adjustable module, wherein the primary configured output current and electrostatic release protection level adjustable module includes a third MOS module group; selecting a MOS module from the third MOS module group according to the high-level output source current and the low-level output sink current, and connecting the selected MOS modules to generate a configured output current and electrostatic release protection level adjustable module, wherein the configured output current and electrostatic release protection level adjustable module is used to provide a specified electrostatic release protection capability corresponding to the electrostatic release protection level and provide a specified output current capability under the control of an IO second control signal of the IO core circuit module;

[0084] Connecting the IO core circuit module, the configured input threshold adjustable module, and the configured output current and electrostatic discharge protection level adjustable module to generate a designated pin module of the customized IO IP core;

[0085] The IO core circuit module includes: a power supply voltage port, a ground port, an IO first control signal input port, and an IO second control signal output port; the configured input threshold adjustable module includes: a power supply voltage port, a ground port, and an IO first control signal output port; the configured output current and electrostatic discharge protection level adjustable module includes: a power supply voltage port, a ground port, and an IO second control signal input port;

[0086] The power supply voltage ports of the IO core circuit module, the configured input threshold adjustable module, and the configured output current and electrostatic discharge protection level adjustable module are all connected to the power supply voltage, and the ground ports are all grounded;

[0087] The IO first control signal output port of the configured input threshold adjustable module is connected to the MOS module selected from the second MOS module group, and the IO first control signal output port of the configured input threshold adjustable module is connected to the IO first control signal input port of the IO core circuit module, for providing the IO first control signal to the IO core circuit module;

[0088] The IO second control signal output port of the IO core circuit module is connected to the IO second control signal input port of the configured output current and electrostatic discharge protection level adjustable module, and is used to output the IO second control signal to the configured output current and electrostatic discharge protection level adjustable module based on the IO first control signal and the IO input signal;

[0089] The IO second control signal input port of the configured output current and electrostatic release protection level adjustable module is connected to a MOS module selected from the third MOS module group; wherein, in the third MOS module group, the selected MOS module provides a first electrostatic release protection capability and the specified output current capability, and the remaining MOS modules provide a second electrostatic release protection capability, and the first electrostatic release protection capability and the second electrostatic release protection capability together constitute the specified electrostatic release protection capability.

[0090] According to an embodiment of the present disclosure, the IO IP core controls the output of its own current through the POC control signal output by the customized POC IP core, including:

[0091] The IO core circuit module obtains the POC control signal through the POC control signal input port;

[0092] generating a current control signal according to the POC control signal, and sending the current control signal to the configured output current and electrostatic discharge protection level adjustable module;

[0093] The configured output current and electrostatic discharge protection level adjustable module controls the output current of the IO IP core according to the current control signal.

[0094] According to an embodiment of the present disclosure, generating the customized unit with power-on control based on the POC IP core and the standard unit module includes:

[0095] Obtain a POC IP core; the POC IP core includes: a first power input terminal, a second power input terminal and a control signal output terminal;

[0096] Obtain a standard cell module; the standard cell module includes: a first logic control signal input terminal, a second logic control signal input terminal, a power input terminal and a cell signal output terminal;

[0097] Connecting the POC IP core and the standard cell module to generate a custom cell with power-on control; wherein the first logic control signal input terminal of the standard cell module is connected to a first power circuit module powered by a first power supply, so that the standard cell module obtains a first logic control signal through the first power circuit module; the second logic control signal input terminal of the standard cell module is connected to a second power circuit module powered by a second power supply, so that the standard cell module obtains a second logic control signal through the second power circuit module; and the power input terminal of the standard cell module is connected to a power supply;

[0098] The first power input terminal of the POC IP core is connected to the first power supply, and the second power input terminal of the POC IP core is connected to the second power supply, so that the POC IP core obtains the voltage status of the first power supply and the second power supply, and generates a first control signal according to the voltage status of the first power supply and the second power supply;

[0099] The control signal output terminal of the POC IP core is connected to the standard cell module, so that the POC IP core outputs the first control signal to the standard cell module through the control signal output terminal, so as to control whether the standard cell module outputs normally through the first control signal;

[0100] The obtaining of the voltage status of the first power supply and the second power supply includes:

[0101] Comparing a current voltage value of the first power supply with a preset first power-on threshold voltage, and when the current voltage value of the first power supply is not lower than the preset first power-on threshold voltage, the voltage state of the first power supply is a power-on state;

[0102] comparing a current voltage value of the second power supply with a preset second power-on threshold voltage, and when the current voltage value of the second power supply is not lower than the preset second power-on threshold voltage, determining that the voltage state of the second power supply is a power-on state;

[0103] Generating a first control signal according to voltage states of the first power supply and the second power supply includes:

[0104] When the voltage state of the first power supply and the voltage state of the second power supply are both in the power-on state, the first control signal is at a high level; otherwise, the first control signal is at a low level.

[0105] According to an embodiment of the present disclosure, the method further includes:

[0106] Obtain a first switch control circuit module; wherein the first switch control circuit module includes: a first input terminal, a second input terminal, and an output terminal;

[0107] The power input terminal of the standard cell module is connected to a power supply, and the control signal output terminal of the POC IP core is connected to the standard cell module, including: the power supply is connected to the power input terminal of the standard cell module through the first switch control circuit module, and the control signal output terminal of the POC IP core is connected to the standard cell module through the first switch control circuit module, including: the power supply is connected to the first input terminal of the first switch control circuit module, the control signal output terminal of the POC IP core is connected to the second input terminal of the first switch control circuit module, and the output terminal of the first switch control circuit module is connected to the power input terminal of the standard cell module, so that the first switch control circuit module generates a second control signal according to the first control signal and uses the second control signal to control the connection or disconnection of the power supply, so that when the power supply is disconnected, the standard cell module stops processing the first logic control signal and the second logic control signal, so that the standard cell module has no output; and when the power supply is connected, the standard cell module resumes processing the first logic control signal and the second logic control signal, so that the standard cell module has normal output;

[0108] The step of generating a second control signal according to the first control signal and controlling the power supply to be turned on or off by using the second control signal includes:

[0109] When the first control signal is at a high level, the second control signal is a closing signal, and the closing signal closes the output end of the first switch control circuit module;

[0110] When the first control signal is at a low level, the second control signal is a disconnection signal, and the disconnection signal disconnects the output end of the first switch control circuit module;

[0111] When the output end of the first switch control circuit module is closed, the power supply is turned on;

[0112] When the output end of the first switch control circuit module is disconnected, the power supply is cut off.

[0113] According to an embodiment of the present disclosure, the method further includes:

[0114] Obtain a second switch control circuit module; wherein the second switch control circuit module includes: a signal input terminal and a signal output terminal;

[0115] The control signal output terminal of the POC IP core is connected to the standard cell module, including:

[0116] The control signal output terminal of the POC IP core is connected to the signal input terminal of the second switch control circuit module; the signal output terminal of the second switch control circuit module is connected to the cell signal output terminal of the standard cell module, so that the second switch control circuit module generates a third control signal according to the first control signal, and uses the third control signal to control the connection or disconnection of the output of the standard cell module, so that when the output of the standard cell module is disconnected, the standard cell module has no output; and when the output of the standard cell module is connected, the standard cell module outputs normally;

[0117] The step of generating a third control signal according to the first control signal and using the third control signal to control the connection or disconnection of the output of the standard cell module includes:

[0118] When the first control signal is at a high level, the third control signal is a closing signal, and the closing signal connects the cell signal output terminal of the standard cell module;

[0119] When the first control signal is at a low level, the third control signal is a disconnection signal, and the disconnection signal cuts off the cell signal output end of the standard cell module;

[0120] When the cell signal output terminal of the standard cell module is turned on, the output of the standard cell module is turned on;

[0121] When the cell signal output terminal of the standard cell module is cut off, the output of the standard cell module is cut off.

[0122] According to an embodiment of the present disclosure, the standard cell module further includes: a control signal input terminal;

[0123] The control signal output terminal of the POC IP core is connected to the standard cell module, comprising: connecting the control signal output terminal of the POC IP core to the control signal input terminal of the standard cell module, so that the standard cell module controls whether to output itself according to the first control signal;

[0124] The standard unit module controls whether to output itself according to the first control signal, including:

[0125] When the first control signal is at a high level, the output of the standard cell module is turned on, and the standard cell module outputs normally;

[0126] When the first control signal is at a low level, the output of the standard cell module is cut off, and the standard cell module has no output.

[0127] According to an embodiment of the present disclosure, the POC IP core is a customized POC IP core; the customized POC IP core is configurable, including: the preset first power-on threshold voltage is a first power-on threshold voltage input by a user, the preset second power-on threshold voltage is a second power-on threshold voltage input by a user;

[0128] or,

[0129] The POC IP core is a default POC IP core; the default POC IP core is non-configurable, including: the preset first power-on threshold voltage and the preset second power-on threshold voltage are both preset fixed values;

[0130] The default POC IP core includes: a connected POC IP core circuit module and a default threshold voltage module, wherein the default threshold voltage module includes MOS modules corresponding to the preset first power-on threshold voltage and the preset second power-on threshold voltage.

[0131] In a second aspect, an embodiment of the present disclosure provides a method for digitizing an integrated cell library. The method is implemented based on a customized EDA tool. The customized EDA tool integrates an integrated cell library generated using the method described in any one of the first aspects. The integrated cell library includes basic standard cells and customized IP cells corresponding to customized IP cores. The customized IP cores include one or more of the following: a customized POC IP core, a customized IO IP core, an IO IP core with power-on control, and a customized cell with power-on control. The method includes:

[0132] Obtaining RTL code for calling the basic standard cell and / or the custom IP cell corresponding to the custom IP core, wherein the RTL code includes an instance of a hardware description language module describing the basic standard cell and / or an instance of a hardware description language module describing the custom IP cell;

[0133] converting the RTL code into a gate-level netlist using a synthesizer;

[0134] Importing the synthesized gate-level netlist into a place-and-route tool;

[0135] Performing physical layout and routing based on the gate-level netlist to generate layout and routing data; performing physical layout and routing based on the gate-level netlist includes: selectively placing the custom IP units and the basic standard units, and generating connections between the custom IP units and / or between the basic standard units and / or between the custom IP units and the basic standard units.

[0136] According to an embodiment of the present disclosure, the method further includes:

[0137] The layout and routing data is verified, and the verification includes one or more of the following items: design rule check (DRC), layout and schematic comparison (LVS), and electrical rule check (ERC).

[0138] According to an embodiment of the present disclosure, the method further includes:

[0139] Manufacturing data is generated according to the layout and routing data, and the manufacturing data includes: a GDSII file and a manufacturing mask.

[0140] In a third aspect, an embodiment of the present disclosure provides an apparatus for generating an integrated cell library. The apparatus is implemented based on a customized EDA tool. The customized EDA tool provides a GUI interface. The GUI interface includes multiple customized input boxes. The customized input boxes are used to obtain configuration parameters input by a user. The apparatus includes:

[0141] A customized IP layout generation module is configured to generate a layout of a customized IP core according to the configuration parameters input by the user; the customized IP layout includes one or more of the following items: a layout of a customized POC IP core, a layout of a customized IO IP core, and a layout of an IO IP core with power-on control;

[0142] an integrated cell library generation module, configured to generate an integrated cell library based on the layout of the customized IP core;

[0143] Generating a layout of a customized POC IP core according to the configuration parameters input by the user includes: generating the customized POC IP core according to a configurable POC IP core and a first configuration parameter input by the user; generating a layout of the customized POC IP core based on the customized POC IP core; the first configuration parameter includes: a POC input threshold voltage;

[0144] Generating a layout of a customized IO IP core according to the configuration parameters input by the user, comprising: generating the customized IO IP core according to the configurable IO IP core and second configuration parameters input by the user; generating a layout of the customized IO IP core based on the customized IO IP core, wherein the second configuration parameters include one or more of the following items: input high-level threshold voltage, input low-level threshold voltage, high-level output source current, low-level output sink current, and electrostatic discharge protection level;

[0145] Generating a layout of an IO IP core with power-on control according to the configuration parameters input by the user, comprising: generating the IO IP core with power-on control according to the IO IP core and the configurable POC IP core and a third configuration parameter input by the user; generating a layout of the IO IP core with power-on control based on the IO IP core with power-on control; the third configuration parameter comprising one or more of the following items: a POC input threshold voltage, an input high-level threshold voltage, an input low-level threshold voltage, a high-level output source current, a low-level output sink current, and an electrostatic discharge protection level;

[0146] Generating a layout of a custom unit with power-on control according to the configuration parameters input by the user includes: generating the custom unit with power-on control according to the POC IP core and the standard cell module; generating a layout of the custom unit with power-on control based on the custom unit with power-on control; when the POC IP core is a customized POC IP core, generating the custom unit with power-on control according to the POC IP core and the standard cell module includes: generating the custom unit with power-on control according to the customized POC IP core and the standard cell module and the first configuration parameters.

[0147] In a fourth aspect, an embodiment of the present disclosure provides a digitization device for an integrated cell library, wherein the digitization device is implemented based on a customized EDA tool, wherein the customized EDA tool integrates an integrated cell library generated using the method described in any one of the first aspects, wherein the integrated cell library includes basic standard cells and customized IP cells corresponding to customized IP cores, wherein the customized IP cores include one or more of the following: a customized POC IP core, a customized IO IP core, an IO IP core with power-on control, and a customized cell with power-on control, wherein the digitization device includes:

[0148] an RTL code acquisition module configured to acquire RTL code for calling the basic standard cell and / or the customized IP cell, wherein the RTL code includes an instance of a hardware description language module describing the basic standard cell and / or an instance of a hardware description language module describing the customized IP cell;

[0149] a gate-level netlist generation module configured to convert the RTL code into a gate-level netlist using a synthesizer;

[0150] a gate-level netlist import module configured to import the synthesized gate-level netlist into a place-and-route tool;

[0151] A layout and routing data generation module is configured to perform physical layout and routing based on the gate-level netlist and generate layout and routing data; the physical layout and routing based on the gate-level netlist includes: selectively placing the custom IP units and the basic standard units, and generating connections between the custom IP units and / or between the basic standard units and / or between the custom IP units and the basic standard units.

[0152] According to an embodiment of the present disclosure, the digitizing device further includes:

[0153] The layout and routing data verification module is configured to verify the layout and routing data, wherein the verification includes one or more of the following items: design rule check (DRC), layout and schematic comparison (LVS), and electrical rule check (ERC).

[0154] According to an embodiment of the present disclosure, the digitizing device further includes:

[0155] The manufacturing data generating module is configured to generate manufacturing data according to the layout and routing data, wherein the manufacturing data includes: a GDSII file and a manufacturing mask.

[0156] In a fifth aspect, a chip is provided in an embodiment of the present disclosure, wherein the chip is manufactured using library cells in an integrated cell library generated by the method described in any one of the first aspects, wherein the library cells include basic standard cells and customized IP cells corresponding to customized IP cores, wherein the customized IP cores include one or more of the following items: customized POC IP core, customized IO IP core, IO IP core with power-on control, and customized cells with power-on control.

[0157] In a sixth aspect, an embodiment of the present disclosure provides an electronic device, comprising the chip described in the fifth aspect.

[0158] In a seventh aspect, an embodiment of the present disclosure provides a computer-readable storage medium on which computer instructions are stored. When the computer instructions are executed by a processor, the method described in any one of the first and second aspects is implemented.

[0159] In an eighth aspect, an embodiment of the present disclosure provides a computer program product, comprising a computer program, characterized in that when the computer program is executed by a processor, it implements the method described in any one of the first and second aspects.

[0160] The IP core provided by existing IP manufacturers is usually an integral module that can only provide fixed input configuration parameters and cannot be easily changed according to chip requirements. The present invention discloses the development of a customized EDA tool, and customized the IP core, reconstructing it into a customized IP core including a customized POC IP core, a customized IO IP core, an IO IP core with power-on control, and a customized unit with power-on control, and integrating these customized IP cores into an integrated cell library that is different from the traditional standard cell library, wherein the customized POC IP core and the customized IO IP core support input configuration parameters that can be flexibly configured, and the IO IP core with power-on control and the customized unit with power-on control combine the POC IP core with the existing IO IP core and standard cell. This solves the problems existing in the comprehensiveness and integration of the traditional standard cell library, and also solves the problems existing in the current traditional POC IP core, IO IP core, and standard cell, thereby better meeting the needs of modern chip design.

[0161] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0162] Other features, objectives and advantages of the present disclosure will become more apparent through the following detailed description of non-limiting embodiments in conjunction with the accompanying drawings. In the accompanying drawings:

[0163] Figure 1 A flowchart illustrating a method for generating an integrated cell library according to an embodiment of the present disclosure is shown;

[0164] Figure 2 A flowchart illustrating a method for generating a customized POC IP core based on a configurable POC IP core according to an embodiment of the present disclosure is shown;

[0165] Figure 3 A schematic structural diagram of a customized POC IP core according to an embodiment of the present disclosure is shown;

[0166] Figure 4 A flowchart illustrating a method for generating a customized IO IP core based on a configurable IO IP core with adjustable input threshold voltage, output current capability, and electrostatic discharge protection level according to an embodiment of the present disclosure is shown;

[0167] Figure 5A diagram showing the working principle of a hysteresis voltage provided by a hysteresis circuit module according to an embodiment of the present disclosure is shown;

[0168] Figure 6 A schematic diagram illustrating connecting an IO core circuit module, a configured input voltage adjustable module, and a configured output current and electrostatic discharge protection level adjustable module in a method for generating a customized IO IP core based on a configurable IO IP core according to an embodiment of the present disclosure is shown;

[0169] Figure 7 A flowchart illustrating a method for generating an IOIP core with power-on control based on a configurable POC IP core according to an embodiment of the present disclosure is shown;

[0170] Figure 8 FIG. 1 shows a schematic structural diagram of an IO IP core with power-on control according to an embodiment of the present disclosure;

[0171] Figure 9 A flowchart illustrating a method for generating a customized unit with power-on control according to an embodiment of the present disclosure is shown;

[0172] Figure 10 A structural connection diagram of a customization unit with power-on control according to an embodiment of the present disclosure is shown;

[0173] Figure 11 A structural connection diagram showing another customized unit with power-on control according to an embodiment of the present disclosure is shown;

[0174] Figure 12 FIG2 shows a structural connection diagram of another customized unit with power-on control according to an embodiment of the present disclosure;

[0175] Figure 13 A flow chart showing a method for digitizing an integrated cell library according to an embodiment of the present disclosure is shown;

[0176] Figure 14 A schematic structural diagram of an apparatus for generating an integrated cell library according to an embodiment of the present disclosure is shown;

[0177] Figure 15 A schematic structural diagram of a digitization device for an integrated cell library according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0178] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement them. In addition, for the sake of clarity, parts not related to the description of the exemplary embodiments are omitted in the accompanying drawings.

[0179] In the present disclosure, it should be understood that terms such as "include" or "have" are intended to indicate the presence of features, numbers, steps, actions, components, parts, or combinations thereof disclosed in the present specification, and are not intended to exclude the possibility that one or more other features, numbers, steps, actions, components, parts, or combinations thereof exist or are added.

[0180] It should also be noted that, in the absence of conflict, the embodiments and features of the embodiments of the present disclosure may be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0181] As mentioned above, traditional standard cell libraries mainly focus on the design of basic logic circuits, such as INV, NAND, NOR, DFF triggers, etc., but are somewhat lacking in comprehensiveness, especially when dealing with key modules in modern chip design, such as POC IP cores and IO IP cores.

[0182] How to address the shortcomings of traditional standard cell libraries in terms of comprehensiveness and integration? After repeated demonstration and careful consideration, the inventors of this disclosure proposed a method for designing a more comprehensive and highly integrated integrated cell library using customized EDA tools and based on customized IP cores.

[0183] The integrated cell library involved in this disclosure refers to a new library that integrates traditional standard cells, custom cells, and custom IP cores, such as custom POC IP cores, custom IO IP cores, IO IP cores with power-on control, and custom cells with power-on control. It can be imported into custom EDA tools for users to select and use the required library cells when designing chips.

[0184] Among them, the custom cell is relative to the standard cell in the existing standard cell library. Standard cells refer to pre-designed, verified and optimized circuit modules, which usually have fixed functions and interfaces, including basic logic unit modules such as logic cells, storage cells, and arithmetic cells. Custom cells are cells customized according to the logic design, performance requirements and specific design constraints of a specific circuit. In this disclosure, custom cells include custom cells with power-on control, which are obtained by combining traditional standard cells with POC IP, giving traditional standard cells the power-on control function.

[0185] Customized IP cores are in contrast to standard IP cores in existing technologies. Standard IP cores are pre-designed, general-purpose integrated circuit design modules. They are typically design-verified and adhere to industry standards to ensure compatibility and interoperability across different chip designs. They offer a high degree of versatility, reusability, and standardized support. Integrated circuit design tools (such as EDA tools) often include an integrated IP core library, from which designers select the desired IP core for chip design. Standard IP cores in traditional processes typically have fixed configuration parameters.

[0186] For example, POC IP cores typically have fixed input threshold voltages. For example, for a 5V power supply, the power-on threshold voltage is fixed at 4.7V, and the power-off threshold voltage is fixed at 2.5V. These thresholds cannot be changed after user selection. However, the reality is that even for the same process node and operating voltage, the power-on and power-off threshold voltages can vary between different fabs and different POC IP cores. For example, for a 5V power supply, some require a power-on threshold voltage of 4.7V to indicate a power-on state, while others only require 4.5V. For a 1.8V power supply, some require a power-off threshold voltage of 0.6V to indicate a power-off state, while others require a voltage of 0.4V.

[0187] For another example, IO IP cores, currently provided by most mainstream fabs, have fixed input threshold voltages (input threshold high voltage VIH, input threshold low voltage VIL). Even with the same process node and operating voltage, IO IP cores produced by different fabs may have different input threshold high voltages VIH and input threshold low voltages VIL. For example, the input threshold high voltage VIH may be 0.65*VDD, 0.8*VDD, or an absolute voltage value (e.g., 0.4V), while the input threshold low voltage VIL may be 0.35*VDD, 0.3*VDD, or an absolute voltage value (e.g., 0.8V, 1.2V). For different analog chips and hybrid analog / digital chips, the input threshold voltages may have different defined ranges depending on the application.

[0188] At the same time, the output current capabilities of IO IP cores are also fixed at a few values. For example, Hua Hong HHGRACE only offers three output current capabilities: 4mA, 8mA, and 16mA; TSMC mainly offers four output current capabilities: 2mA, 4mA, 8mA, and 12mA; and SMIC mainly offers six output current capabilities: 2mA, 4mA, 8mA, 12mA, 16mA, and 24mA. However, in actual industrial chip design, the required output current capabilities of IO IP cores vary. Some only require μA-level output current capabilities, such as 100μA or 500μA, while others require output current capabilities greater than 24mA.

[0189] Furthermore, the IO IP provided by most mainstream fabs currently only offers 2kV ESD (electrostatic discharge) protection. However, many industrial chips, such as power drivers, require 4kV and 5kV ESD protection, while some interface chips even require ESD protection exceeding 10kV. Therefore, the ESD protection provided by the specific IO IP provided by current fabs cannot meet the requirements for chip designs designed for complex industrial applications such as those involving electromagnetic heating.

[0190] For example, the IO IP cores provided by existing IO IP libraries still face challenges with power management, particularly in the event of a sudden power outage. Specifically, when one power source in a dual-power circuit suddenly loses power, traditional IO IP designs cannot accurately predict the subsequent circuitry, causing some circuits to function normally while others fail. This can generate erroneous logic signals and severely impact the functionality of the entire chip. Furthermore, if IO circuits continue to output high current when the power source is disconnected, this poses a potential safety risk.

[0191] For example, if a standard cell in a standard cell library uses multiple power supply voltages and one of the power supply voltages suddenly loses power for some reason, the subsequent circuitry cannot detect this situation. This can cause some circuits to continue functioning normally while others cannot. Errors are already generated before these two signals are transmitted to the subsequent standard cell modules. This can cause the standard cell to fail to correctly perform its intended logical function by outputting erroneous logic signals or no signals at all. This logical error can propagate along the circuit chain, ultimately causing the entire circuit system to produce incorrect results or fail to perform its intended function, posing a significant risk to industrial production processes.

[0192] When designing an integrated cell library, the inventors of the present disclosure addressed the problems existing in the prior art POC IP cores, IO IP cores, and standard cells. To enable configuration of the POC IP cores and IO IP cores according to the different configuration parameters required by the actual chip, achieving flexible configurability of the POC IP and IO IP, and to enable traditional standard cells and IO IP cores to monitor and correctly respond to situations where dual power supplies are not fully powered on, they combined customized POC IP cores, customized IO IP cores, IO IP cores with power-on control, and customized cells with power-on control, which can solve the above problems, into a single library to form an integrated cell library. Simultaneously, combined with corresponding modifications to the EDA tool, the modified portions were installed as plug-ins into the existing EDA tool, thereby obtaining a customized EDA tool. In this way, designers select the required custom cells or custom IP cores from the integrated cell library and use customized EDA tools to configure the parameters of the selected custom cells or custom IP cores according to the actual design requirements of the chip. In this way, while solving the problems of insufficient comprehensiveness and integration of traditional standard cell libraries, designers also solve the above problems existing in traditional POC IP cores, IO IP cores and standard cells, thereby better meeting the needs of modern chip design.

[0193] Figure 1 A flow chart of a method for generating an integrated cell library according to an embodiment of the present disclosure is shown. The method is implemented based on a customized EDA tool. The customized EDA tool provides a GUI interface. The GUI interface includes multiple customized input boxes for obtaining configuration parameters input by the user. Figure 1 As shown, the method includes the following steps S110 to S120:

[0194] In step S110, a layout of a customized IP core is generated according to the configuration parameters input by the user; the customized IP includes one or more of the following items: a customized POC IP core, a customized IO IP core, an IO IP core with power-on control, and a customized unit with power-on control.

[0195] In step S120 , an integrated cell library is generated based on the layout of the customized IP core.

[0196] According to an embodiment of the present disclosure, when generating an integrated cell library based on the layout of the customized IP core, the following steps are included:

[0197] First, the layout of the customized IP core is verified, and the verification includes: design rule checking DRC and layout and schematic comparison LVS; generating post-simulation netlist data of the layout of the customized IP core; the post-simulation netlist data is used to describe the circuit structure and connection relationship of the layout of the customized IP core; verifying the post-simulation netlist data to ensure that it is consistent with the layout of the customized IP core. Figure 1 The method comprises the following steps: inputting the post-simulation netlist data into a pre-provided Tcl (Tool Command Language) script file, and adding attribute parameters related to the custom IP core in the Tcl script file, wherein the attribute parameters include one or more of the following items: function description, area, pin information, delay, and power consumption; generating a model file according to the Tcl script file, and verifying the model file to ensure that the model file can correctly simulate the behavior of the custom IP core, wherein the model file includes a Verilog model file or a VHDL model file; performing post-simulation verification using the model file; and using a library file generation tool to generate an integrated unit library based on the model file.

[0198] Then, the layout of the customized IP core is verified, and the verification includes: design rule check (DRC) and layout and schematic comparison (LVS).

[0199] Among them, Design Rule Check (DRC) refers to using layout verification tools to perform DRC checks on the layout to ensure that the layout complies with design rules, such as minimum line width, minimum spacing, etc.

[0200] Layout Versus Schematics (LVS) involves comparing the layout with the schematic using LVS verification tools to ensure logical consistency between the two. LVS verification tools include, but are not limited to, Dracula, which checks the layout and logic diagram for consistency and compares the logical equivalence between the transistor-level SPICE netlist extracted from the layout and the gate-level Verilog netlist generated during the design phase (which must be converted to a SPICE netlist). The LVS verification process helps ensure the correctness and reliability of chip designs.

[0201] After analyzing and processing the verification results of DRC and LVS, if there are errors or inconsistencies, it is necessary to return to step S110 for modification.

[0202] Afterwards, post-simulation netlist data of the layout of the customized IP core is generated; the post-simulation netlist data is used to describe the circuit structure and connection relationship of the layout of the customized IP core.

[0203] When generating post-simulation netlist data of the layout of the custom IP core, extracting parasitic parameters from the layout of the custom IP core using a layout extraction tool (such as FastCap, Q3D, etc.); the parasitic parameters include resistance, capacitance, and inductance;

[0204] Obtaining pre-simulation netlist data of the layout of the customized IP core;

[0205] The parasitic parameters are added to the pre-simulation netlist data to generate post-simulation netlist data of the layout of the customized IP core including the parasitic parameters.

[0206] Next, the post-simulation netlist data is verified to ensure that it is consistent with the version of the custom IP core. Figure 1 To.

[0207] Verification includes, but is not limited to, netlist consistency checking and functional verification. During the netlist consistency check, the post-simulation netlist data is compared with the custom IP core layout to ensure consistency in circuit structure and connectivity. During functional verification, the post-simulation netlist data is simulated using circuit simulation tools to verify that its functionality meets design requirements.

[0208] Thereafter, the post-simulation netlist data is input into a pre-provided Tcl script file, and attribute parameters related to the customized IP core are added to the Tcl script file, wherein the attribute parameters include one or more of the following items: function description, area, pin information, delay, and power consumption.

[0209] Specifically, first prepare a predefined Tcl script file, then input the post-simulation netlist data into the Tcl script file, and finally add relevant attribute parameters in the Tcl script file according to the characteristics of the customized IP core, such as function description, area, pin information, delay, power consumption, etc.

[0210] Next, a model file is generated according to the Tcl script file, and the model file is verified to ensure that the model file can correctly simulate the behavior of the customized IP core, and the model file is used for post-simulation verification. The model file includes: a Verilog model file or a VHDL model file.

[0211] Specifically, the Tcl script file is first parsed to extract the post-simulation netlist data and attribute parameters. Then, based on the extracted data and parameters, a model generation tool (such as ModelSim, VCS, etc.) is used to generate a Verilog model file or a VHDL model file. If necessary, an IBIS model file can also be generated.

[0212] Finally, a library file generation tool is used to generate an integrated unit library based on the model file, where the integrated unit library includes the customized IP unit corresponding to the customized IP core.

[0213] Custom IP units, as used in this disclosure, refer to intellectual property (IP) modules with specific functionality and performance, customized to meet specific user requirements within integrated circuit (IC) designs. These IP modules can be digital, analog, or mixed-signal circuits, designed as reusable components for integration across different IC designs.

[0214] In the present disclosure, for a customized POC IP core, a customized IO IP core, and an IO IP core with power-on control, the corresponding customized IP units are: a customized POC IP unit, a customized IO IP unit, and an IO IP unit with power-on control.

[0215] In general, custom IP units are IP modules with specific functions and performance generated in a customized manner. They can meet the special needs of users in different IC designs and improve the flexibility and efficiency of design.

[0216] The library file generation tool may be a Library Generator.

[0217] According to an embodiment of the present disclosure, the step of using a library file generation tool and generating an integrated unit library based on the model file includes:

[0218] First, select the model file.

[0219] Then, the properties of the integrated unit library are configured. The properties of the integrated unit library include: library name, version and description.

[0220] Afterwards, the command or operation for generating the library file in the library file generating tool is executed.

[0221] Finally, the generated integrated cell library is saved in a standard library file format for use by custom EDA tools.

[0222] After executing step S120 , the method further includes: verifying the integrated cell library.

[0223] The specific implementation of step S110 is described in detail below.

[0224] The customized IP cores involved in step S110 include, but are not limited to: customized POC IP cores, customized IO IP cores, IO IP cores with power-on control, and customized units with power-on control.

[0225] When the customized IP core is a customized POC IP core, generating a layout of the customized POC IP core according to the configuration parameters input by the user includes: generating the customized POC IP core according to the configurable POC IP core and the first configuration parameters input by the user; and generating a layout of the customized POC IP core based on the customized POC IP core.

[0226] The first configuration parameter includes: POC input threshold voltage.

[0227] Figure 2 FIG. 1 is a flow chart showing a method for generating a customized POC IP core based on a configurable POC IP core according to an embodiment of the present disclosure. Figure 2 As shown, generating the customized POC IP core according to the configurable POC IP core and the first configuration parameter input by the user specifically includes the following steps S210 to S240:

[0228] In step S210 , a configurable POC IP core is obtained, where the configurable POC IP core includes a POC core circuit module and a POC input threshold voltage adjustable module.

[0229] After research, the inventors of the present disclosure discovered that the reason why the existing POC IP core can only provide a fixed input threshold voltage (including a power-up threshold voltage and a power-down threshold voltage) is that the POC IP core is designed as an integral module, which makes it impossible to easily change it according to chip requirements. As a result, the existing POC IP core can only provide a fixed input threshold voltage, and thus cannot meet the actual requirements of different chips for different input threshold voltages.

[0230] The present disclosure splits the existing overall POC IP core into multiple functional modules and separately configures the input threshold voltage module therein, thereby realizing a configurable POC IP core. In the configurable POC IP core, each internal function can be easily and independently controlled, and then automatically adjusted according to the actual needs of different chips, thereby realizing flexible and configurable POC input threshold voltage.

[0231] In the present disclosure, the configurable POC IP core is no longer an integral module, but includes a POC core circuit module and a POC input threshold voltage adjustable module, wherein the POC input threshold voltage adjustable module can be configured according to the POC input threshold voltage input by the user, so that the customized POC IP core generated based on the configured POC input threshold voltage adjustable module meets the actual demand of supporting the specified POC input threshold voltage.

[0232] The configurable POC IP core is provided by a customized EDA tool.

[0233] In step S220 , the POC input threshold voltage input by the user is obtained through the multiple customized input boxes.

[0234] Typically, the POC IP core connects to two power supplies: a first power supply and a second power supply. For each power supply, the POC can have two input threshold voltages: a power-on threshold voltage and a power-off threshold voltage. These represent specific voltage levels during power-up and power-down, respectively. The power-on threshold voltage refers to the voltage point at which the chip begins normal operation or starts its internal circuitry when the power supply voltage reaches or exceeds a certain value during chip power-up. The power-off threshold voltage refers to the voltage point at which the chip begins to shut down its internal circuitry or enters low-power mode when the power supply voltage drops below a certain value during power-down. The specific values ​​of the power-on and power-off threshold voltages vary depending on the chip design and application requirements. In some cases, both the power-on and power-off threshold voltages are defined as a voltage range to accommodate fluctuations in the power supply voltage.

[0235] In a specific embodiment, four input boxes are provided through the graphical user interface of the customized EDA tool, namely: "Expected first power-on threshold voltage" input box, "Expected second power-on threshold voltage", "Expected first power-down threshold voltage" input box and "Expected second power-down threshold voltage" input box. After the user enters the power-on threshold voltage and power-down threshold voltage expected to be achieved by the first power supply and the second power supply of the POCIP core in the four input boxes, the customized EDA tool can obtain the first power-on threshold voltage, the second power-on threshold voltage, the first power-down threshold voltage and the second power-down threshold voltage input by the user.

[0236] The POC input threshold voltage is a positive integer multiple of the product of a preset minimum scaling factor and the power supply voltage, or a positive integer multiple of a preset minimum unit voltage. For example, when the power-on and power-off threshold voltages are input proportionally, the input voltage value can be set as a positive integer multiple of 0.05*VDD, such as 0.2*VDD. When the power-on and power-off threshold voltages are input as absolute values, the input voltage value can be set as an integer multiple of 0.1V. For example, when the power supply voltage is 5V, the power-on threshold voltage value can be set as 3.8V, 3.9V, 4.0V, ..., 4.5V; when the standard power supply voltage is 1.8V, the power-on threshold voltage value can be set as 1.3V, 1.4V, ..., 1.8V. Those skilled in the art will appreciate that the specific values ​​of the preset minimum scaling factor and the preset minimum unit voltage can be set based on the user's desired layout area for the customized POC IP core and the desired input threshold voltage accuracy, and are not limited thereto.

[0237] In step S230, the POC input threshold voltage adjustable module is configured according to the POC input threshold voltage. The POC input threshold voltage adjustable module includes a first MOS module group. The configuring of the POC input threshold voltage adjustable module according to the POC input threshold voltage includes: selecting a number of MOS modules corresponding to the POC input threshold voltage from the first MOS module group and connecting the selected MOS modules to generate a configured POC input threshold voltage adjustable module. The configured POC input threshold voltage adjustable module is used to generate a POC first control signal of the POC core circuit module.

[0238] As previously mentioned, the POC input threshold voltages include: a first power-up threshold voltage, a second power-up threshold voltage, a first power-down threshold voltage, and a second power-down threshold voltage. The first power-up threshold voltage and the first power-down threshold voltage are configuration parameters for a first power supply connected to the POC IP core, while the second power-up threshold voltage and the second power-down threshold voltage are configuration parameters for a second power supply connected to the POC IP core.

[0239] In the present disclosure, the POC first control signal of the POC core circuit module is a voltage level that provides a reference to the POC core circuit module, so that the POC core circuit module can compare and judge the power supply voltage received from the external power supply with the POC first control signal, thereby obtaining a judgment result of whether the power supply corresponding to the power supply voltage value is in a power-on or power-off state.

[0240] The first MOS module group includes multiple MOS modules, each of which corresponds to a PMOS transistor or NMOS transistor when the customized IO IP core is implemented as an integrated circuit or chip, that is, the first MOS module group corresponds to a MOS transistor group.

[0241] Assume that the first MOS module group includes m PMOS modules and n NMOS modules; when configuring the POC input threshold voltage adjustable module, p PMOS modules and q NMOS modules are selected from the first MOS module group according to the POC input threshold voltage and connected to generate a configured POC input threshold voltage adjustable module to achieve a desired POC input threshold voltage, where p≤m, q≤n.

[0242] In a specific embodiment, the POC input threshold voltage adjustable module may include an inverter module or a Schmitt trigger circuit module. The inverter module or the Schmitt trigger circuit module is connected to the first MOS module group. Based on the POC input threshold voltage, the inverter module or the Schmitt trigger circuit module controls the on and off of different MOS modules in the first MOS module group, thereby selecting a MOS module from the first MOS module group and connecting the selected MOS module to achieve a desired POC input threshold voltage.

[0243] To save user time, the disclosed embodiments allow for pre-configured configurations of the POC input threshold voltage adjustable module. Each configured input threshold voltage adjustable module includes different MOS modules and / or different MOS module connection methods, corresponding to different POC input threshold voltages. When the user enters a desired POC input threshold voltage, the corresponding configured POC input threshold voltage adjustable module can be directly selected.

[0244] In another specific embodiment, a plurality of MOS module groups are pre-set in the first MOS module group of the POC input threshold voltage adjustable module, and each MOS module group corresponds to a different POC input threshold voltage; thus, when the user inputs the required POC input threshold voltage, a corresponding MOS module group is directly selected from the pre-set plurality of MOS module groups.

[0245] In a specific embodiment, the POC input threshold voltage adjustable module includes not only a MOS module group but also a resistor module group.

[0246] Accordingly, configuring the POC input threshold voltage adjustable module based on the POC input threshold voltage further includes: selecting resistor modules of a number and resistance value corresponding to the POC input threshold voltage from the resistor module group, and connecting the selected MOS modules and resistor modules to generate the configured POC input threshold voltage adjustable module. That is, the configured POC input threshold voltage adjustable module is configured by selecting the MOS modules and resistor modules from the MOS module group and the resistor module group based on the POC input threshold voltage.

[0247] To more accurately configure the POC input threshold voltage adjustable module based on the POC input threshold voltage, resistor subdivision adjustment is optional. The EDA tool determines whether resistor subdivision adjustment is necessary based on the design requirements and circuit characteristics. Specifically, the EDA tool first reads the design specification document to understand the design requirements for the accuracy and stability of the POC input threshold voltage. The EDA tool then analyzes the topology and component parameters of the POC input threshold voltage adjustable module and assesses their impact on the threshold voltage. Based on the design requirements and circuit characteristics, the EDA tool configures the POC input threshold voltage adjustable module, including selecting the parameters of components such as resistors. The EDA tool then uses circuit simulation to simulate the operation of the configured POC input threshold voltage adjustable module under different conditions, calculates the actual POC input threshold voltage value, and compares the simulated POC input threshold voltage with the target value specified in the design requirements to calculate the deviation. If the deviation is within the allowable error range, resistor subdivision adjustment is not required. If the deviation exceeds the allowable error range, resistor subdivision adjustment is required.

[0248] When resistance subdivision is required, resistance subdivision adjustment is performed on the configured POC input threshold voltage adjustable module, specifically including: adjusting the resistance value or connection mode of the resistors in the configured POC input threshold voltage adjustable module, or adjusting the number of resistors in the configured POC input threshold voltage adjustable module, so as to achieve resistance subdivision adjustment of the configured POC input threshold voltage adjustable module; wherein the connection mode includes: series connection, parallel connection, or a series-parallel mixed mode.

[0249] In step S240, the POC core circuit module and the configured POC input threshold voltage adjustable module are connected to generate a customized POC IP core.

[0250] The generated custom POC IP core also includes a bottom module and a filling module.

[0251] The present disclosure inserts a bottom module at the bottom of the customized POC IP core to achieve the requirement of closed overall circuit layout and meet the design rule check. In order to ensure the smoothness and integrity of the wiring in the customized POC IP core, the bottom module is used to meet the wiring requirements in the customized POC IP core layout. Figure 3 A schematic structural diagram of a customized POC IP core according to an embodiment of the present disclosure is shown.

[0252] Among them, the POC core circuit module includes: a POC first control signal input port and a POC control signal output port, and the configured POC input threshold voltage adjustable module includes: a POC first control signal output port; the POC core circuit module and the configured POC input threshold voltage adjustable module also include: a power supply voltage port and a ground port.

[0253] The power supply voltage ports of the POC core circuit module and the configured POC input threshold voltage adjustable module are both connected to the first power supply and the second power supply, and the ground ports of the POC core circuit module and the configured POC input threshold voltage adjustable module are both grounded.

[0254] The POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to the POC first control signal input port of the POC core circuit module, for providing a POC first control signal to the POC core circuit module; the POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to a MOS module selected from the first MOS module group, so that when the configured POC input threshold voltage adjustable module is implemented as an integrated circuit or chip, the POC first control signal is implemented through the selected MOS transistor.

[0255] Through the customized POC IP core provided in this disclosure, users can configure the POC IP according to the different threshold voltages required by the actual chip, thereby achieving flexible configuration of the POC input threshold voltage and meeting the design requirements of complex industrial chips.

[0256] When the customized IP core is a customized IO IP core, generating a layout of the customized IO IP core according to the configuration parameters input by the user includes: generating the customized IO IP core according to the configurable IO IP core and the second configuration parameters input by the user; and generating a layout of the customized IO IP core based on the customized IO IP core.

[0257] The second configuration parameter includes one or more of the following items: input threshold high level voltage, input threshold low level voltage, high level output source current, low level output sink current and electrostatic discharge protection level.

[0258] Figure 4 The flowchart of a method for generating a customized IO IP core based on a configurable IO IP core with adjustable input threshold voltage, output current capability and electrostatic discharge protection level according to an embodiment of the present disclosure is shown. Figure 4 As shown, generating the customized IO IP core according to the configurable IO IP core and the second configuration parameter input by the user specifically includes the following steps S410 to S450:

[0259] In step S410, a configurable IO IP core is obtained, where the configurable IO IP core includes an IO core circuit module, an input threshold adjustable module, and an output current and electrostatic discharge protection level adjustable module. The input threshold adjustable module includes a second MOS module group. The output current and electrostatic discharge protection level adjustable module includes multiple unit output current and electrostatic discharge protection level adjustable modules. The unit output current and electrostatic discharge protection level adjustable module includes multiple MOS modules.

[0260] In the present disclosure, the configurable IO IP core is no longer a single integrated module, but rather includes multiple functional modules, such as an IO core circuit module, an input threshold adjustable module, and modules for adjusting multiple unit output currents and electrostatic discharge protection levels. Different functional modules implement corresponding functions, enabling the customized EDA tool to provide more customizable and refined configuration of the input threshold voltage, output current capability, and electrostatic discharge protection capability of the configurable IO IP core.

[0261] The second MOS module group included in the input threshold adjustable module includes multiple MOS modules, each of which corresponds to a PMOS transistor or an NMOS transistor when the customized IO IP core is implemented as an integrated circuit or chip. That is, in this case, the input threshold adjustable module includes multiple PMOS transistors and multiple NMOS transistors.

[0262] Similarly, in the multiple MOS modules included in each unit output current and electrostatic discharge protection level adjustable module, each MOS module corresponds to a PMOS transistor or an NMOS transistor when the customized IO IP core is implemented as an integrated circuit or chip. That is, in this case, each unit output current and electrostatic discharge protection level adjustable module includes multiple PMOS transistors and multiple NMOS transistors.

[0263] In step S420, the input threshold high level voltage, input threshold low level voltage, high level output source current, low level output sink current and electrostatic discharge protection level input by the user for the specified pin module of the customized IO IP core are obtained through the multiple customized input boxes.

[0264] According to an embodiment of the present disclosure, the designated pin module of the customized IO IP core is any pin module to be generated in the customized IO IP core; the input threshold high-level voltage, input threshold low-level voltage, high-level output source current, low-level output sink current, and electrostatic discharge protection level input by the user are the input threshold voltage, output current capability, and electrostatic discharge protection capability that the designated pin module of the customized IO IP core is expected to achieve.

[0265] In a specific embodiment, five input boxes are provided through the graphical user interface of the customized EDA tool, namely: "Expected input threshold high level voltage VIH" input box, "Expected input threshold low level voltage VIL" input box, "Expected high level output source current IOH" input box, "Expected low level output sink current IOL" input box, and "Expected electrostatic discharge protection level" input box. The user enters the input threshold voltage, output current capability and electrostatic discharge protection capability corresponding to the expected electrostatic discharge protection level expected to be implemented for the specified pin module of the customized IO IP core from the five input boxes. The electrostatic discharge protection capability is divided into levels based on the unit electrostatic discharge protection capability. For example, assuming the unit electrostatic discharge protection capability is 1 kV, the electrostatic discharge protection capability corresponding to the first-level electrostatic discharge protection level is 1 kV, the electrostatic discharge protection capability corresponding to the second-level electrostatic discharge protection level is 2 kV, the electrostatic discharge protection capability corresponding to the third-level electrostatic discharge protection level is 3 kV, and so on.

[0266] In the present disclosure, the voltage values ​​of the input threshold high level voltage and the input threshold low level voltage are relative. For example, when the input threshold high level voltage is 0.8*VDD, the input threshold low level voltage may be 0.35*VDD, 0.3*VDD, etc.; when the input threshold high level voltage is 4V, the input threshold low level voltage may be 0.8V, 1.2V, etc. The input threshold high level voltage is less than the power supply voltage, and the input threshold low level voltage is greater than 0.

[0267] In step S430, the input threshold adjustable module is configured according to the input threshold high level voltage and the input threshold low level voltage, including: selecting a MOS module from the second MOS module group according to the input threshold high level voltage and the input threshold low level voltage and connecting the selected MOS module to generate a configured input threshold adjustable module, wherein the configured input threshold adjustable module is used to generate the IO first control signal of the IO core circuit module.

[0268] In the present disclosure, the IO first control signal is a voltage level that provides a reference to the IO core circuit module, so that the IO core circuit module can compare and judge the voltage level of the IO input signal received from the outside with the IO first control signal, thereby obtaining a logical judgment result of the voltage level of the IO input signal.

[0269] According to an embodiment of the present disclosure, configuring the input threshold adjustable module further includes: determining a corresponding hysteresis voltage based on the input threshold high-level voltage and the input threshold low-level voltage; selecting a MOS module from the first MOS module group based on the input threshold high-level voltage, the input threshold low-level voltage and the hysteresis voltage and connecting the selected MOS module to generate a configured input threshold adjustable module, wherein the configured input threshold adjustable module includes a hysteresis circuit module for realizing the hysteresis voltage.

[0270] Figure 5 A diagram showing the working principle of a hysteresis voltage provided by a hysteresis circuit module according to an embodiment of the present disclosure is shown.

[0271] like Figure 5 As shown, when the hysteresis voltage Vhys is provided by the hysteresis circuit module, the IO first control signal (VCH and VCL) is obtained by using the hysteresis voltage Vhys and the input threshold high voltage level VIH and the input threshold low voltage level VIL, VCH=VIH-Vhys, VCL=VIL+Vhys.

[0272] In the present disclosure, after the input threshold high level voltage VIH and the input threshold low level voltage VIL are determined, the corresponding hysteresis voltage Vhys can be determined according to the values ​​of VIH and VIL. For example, the hysteresis voltage Vhys can be determined according to the difference between VIH and VIL and a preset ratio. Specifically, for example, when VIH = 0.8*VDD and VIL = 0.3*VDD, Vhys = (0.8*VDD-0.3*VDD) / 2 = 0.25*VDD. It should be understood by those skilled in the art that the above-mentioned method for calculating the hysteresis voltage is only a specific example and is not intended to be a technical means for limiting the scope of protection of the present disclosure. The hysteresis voltage can also be calculated using other solution methods, for example, Vhys = (0.8*VDD-0.3*VDD) / 3 = 0.2*VDD.

[0273] In a specific embodiment, assuming that VIH = 0.8*VDD, VIL = 0.3*VDD, and Vhys = 0.2*VDD, the IO first control signal can be determined as: VCH = 0.8*VDD-0.2*VDD = 0.6*VDD, VCL = 0.3*VDD+0.2*VDD = 0.5*VDD. Then, when the voltage value of the IO input signal obtained from the IO core circuit module increases from 0 to VCH = 0.6*VDD, the voltage level of the IO input signal is judged to be a logic low level. In the interval in which the voltage value of the IO input signal rises from VCH = 0.6*VDD to VDD, and in the interval in which the voltage value of the IO input signal falls from VDD to VCL = 0.5*VDD, the voltage level of the IO input signal is judged to be a logic high level. In the interval in which the voltage value of the IO input signal falls from VCL = 0.5*VDD to 0, the voltage level of the IO input signal is judged to be a logic low level.

[0274] When the customized IO IP core is implemented as an integrated circuit or chip, an analog voltage is generally obtained from an external device or sensor as an IO input signal. In order to prevent the voltage signal of the obtained analog voltage from jumping back and forth between the input threshold high-level voltage VIH and the input threshold low-level voltage VIL, it is necessary to use the hysteresis voltage Vhys to correct VIH and VIL to obtain the IO first control signal, so that the voltage signal of the analog voltage is judged as a high level when it does not reach but is close to the input threshold high-level voltage VIH, and is judged as a low level when it is higher than but close to the input threshold low-level voltage VIL, thereby improving the stability and reliability of the integrated circuit or chip during operation.

[0275] Assume that the second MOS module group includes m PMOS modules and n NMOS modules; when configuring the input threshold adjustable module, p PMOS modules and q NMOS modules are selected from the second MOS module group according to the input threshold high-level voltage and the input threshold low-level voltage and connected to generate a configured input threshold adjustable module to achieve the desired input threshold voltage and corresponding hysteresis voltage, where p≤m, q≤n.

[0276] The inventors have discovered that in order to save the layout area of ​​the designed custom IO IP core when it is implemented as a circuit layout, while ensuring that the input threshold voltage can achieve the desired input accuracy, the voltage values ​​of the input threshold high voltage VIH and the input threshold low voltage VIL can be set to integer multiples of 0.01*VDD, 0.02*VDD, ..., 0.2*VDD, or the voltage values ​​of the input threshold high voltage VIH and the input threshold low voltage VIL can be set to integer multiples of 0.01V, 0.02V, ..., 0.2V, thereby minimizing the layout area of ​​the designed custom IO IP core while maximizing the number of configurable input threshold voltage values. Those skilled in the art will appreciate that the values ​​of the input threshold high voltage VIH and the input threshold low voltage VIL can be set based on the desired layout area of ​​the custom IO IP core and the desired input threshold voltage accuracy required by the user, and are not limited thereto.

[0277] For example, when the customized EDA tool configures the input threshold adjustable module to obtain the configured input threshold adjustable module, when the configured input threshold adjustable module is implemented as an integrated circuit or chip, under a 0.18μm design process (the minimum distance or feature size between circuits in chip manufacturing reaches 0.18 microns), when VIH=0.8*VDD and VIL=0.2*VDD, the customized EDA tool determines, based on the values ​​of VIH and VIL, that 18 PMOS tubes and 12 NMOS tubes need to be selected from the second MOS tube group for connection, wherein the desired VIH and VIL are achieved using 16 PMOS tubes and 10 NMOS tubes, and the corresponding hysteresis voltage is achieved using 2 PMOS tubes and 2 NMOS tubes.

[0278] In a specific embodiment, the input threshold adjustable module may include an inverter module or a Schmitt trigger circuit module. The inverter module or the Schmitt trigger circuit module is connected to the second MOS module group. According to the input threshold high level voltage VIH and the input threshold low level voltage VIL, the inverter module or the Schmitt trigger circuit module controls the on and off of different MOS modules in the second MOS module group, thereby selecting a MOS module from the second MOS module group and connecting the selected MOS module to achieve a desired input threshold voltage and hysteresis voltage.

[0279] To save user operation time, the disclosed embodiments can pre-configure the input threshold adjustable module in multiple configurations. Each configured input threshold adjustable module includes different MOS modules and / or different MOS module connection methods, thereby corresponding to different input threshold high voltages VIH and input threshold low voltages VIL. When the user enters the desired input threshold high voltage VIH and input threshold low voltage VIL, the corresponding configured input threshold adjustable module can be directly selected.

[0280] In another specific embodiment, a plurality of MOS module groups are pre-set in the second MOS module group of the input threshold adjustable module, and each MOS module group corresponds to a different input threshold high-level voltage VIH and input threshold low-level voltage VIL; thus, when the user inputs the required input threshold high-level voltage VIH and input threshold low-level voltage VIL, a corresponding MOS module group is directly selected from the pre-set plurality of MOS module groups.

[0281] In step S440, the output current and electrostatic release protection level adjustable module is configured according to the high-level output source current, the low-level output sink current and the electrostatic release protection level, including: selecting one or more unit output current and electrostatic release protection level adjustable modules from the output current and electrostatic release protection level adjustable module according to the electrostatic release protection level and connecting the selected one or more unit output current and electrostatic release protection level adjustable modules to generate a single-configuration output current and electrostatic release protection level adjustable module, wherein the single-configuration output current and electrostatic release protection level adjustable module includes a third MOS module group; selecting a MOS module from the third MOS module group according to the high-level output source current and the low-level output sink current and connecting the selected MOS module to generate a configured output current and electrostatic release protection level adjustable module, wherein the configured output current and electrostatic release protection level adjustable module is used to provide a specified electrostatic release protection capability corresponding to the electrostatic release protection level and provide a specified output current capability under the control of the IO second control signal of the IO core circuit module.

[0282] In step S450, the IO core circuit module, the configured input threshold adjustable module, and the configured output current and electrostatic discharge protection level adjustable module are connected to generate a designated pin module of the customized IO IP core.

[0283] The IO core circuit module includes: a power supply voltage port, a ground port, an IO first control signal input port, and an IO second control signal output port; the configured input threshold adjustable module includes: a power supply voltage port, a ground port, and an IO first control signal output port; the configured output current and electrostatic discharge protection level adjustable module includes: a power supply voltage port, a ground port, and an IO second control signal input port;

[0284] The power supply voltage ports of the IO core circuit module, the configured input threshold adjustable module, and the configured output current and electrostatic discharge protection level adjustable module are all connected to the power supply voltage, and the ground ports are all grounded;

[0285] The IO first control signal output port of the configured input threshold adjustable module is connected to the MOS module selected from the second MOS module group, and the IO first control signal output port of the configured input threshold adjustable module is connected to the IO first control signal input port of the IO core circuit module, for providing the IO first control signal to the IO core circuit module;

[0286] The IO second control signal output port of the IO core circuit module is connected to the IO second control signal input port of the configured output current and electrostatic discharge protection level adjustable module, and is used to output the IO second control signal to the configured output current and electrostatic discharge protection level adjustable module based on the IO first control signal and the IO input signal;

[0287] The IO second control signal input port of the configured output current and electrostatic release protection level adjustable module is connected to a MOS module selected from the third MOS module group; wherein, in the third MOS module group, the selected MOS module provides a first electrostatic release protection capability and the specified output current capability, and the remaining MOS modules provide a second electrostatic release protection capability, and the first electrostatic release protection capability and the second electrostatic release protection capability together constitute the specified electrostatic release protection capability.

[0288] Specifically, the output current and electrostatic discharge protection level adjustable module configured once may include one or more unit output current and electrostatic discharge protection level adjustable modules, that is, the number of the selected unit output current and electrostatic discharge protection level adjustable modules may be one or more, wherein each selected output current and electrostatic discharge protection level adjustable module utilizes all the MOS modules it includes to provide unit electrostatic discharge protection capability. For example, if the unit electrostatic discharge protection capability provided by the selected unit output current and electrostatic discharge protection level adjustable module is 0.5kV, if the electrostatic discharge protection capability corresponding to the electrostatic discharge protection capability level input by the user is desired to be 4kV, then it is necessary to select 4kV / 0.5kV=8 unit output current and electrostatic discharge protection level adjustable modules from the output current and electrostatic discharge protection level adjustable modules, and connect the selected 8 unit output current and electrostatic discharge protection level adjustable modules to obtain a single-configuration output current and electrostatic discharge protection level adjustable module to provide 4kV electrostatic discharge protection capability.

[0289] After obtaining the output current and electrostatic release protection level adjustable module of the primary configuration, a MOS module is selected from the third MOS module group included in the output current and electrostatic release protection level adjustable module of the primary configuration and connected to the selected MOS module to generate a configured output current and electrostatic release protection level adjustable module. The IO second control signal input port of the configured output current and electrostatic release protection level adjustable module is connected to the MOS module selected from the third MOS module group, thereby providing a specified output current capability under the control of the IO second control signal of the IO core circuit module.

[0290] Among them, the selected unit output current and electrostatic release protection level adjustable module includes a power supply voltage port, a ground port and an IO second control signal input port. The power supply voltage port of the unit output current and electrostatic release protection level adjustable module is connected to the power supply voltage, and the ground port of the unit output current and electrostatic release protection level adjustable module is grounded. The selected unit output current and electrostatic release protection level adjustable module is used to provide unit electrostatic release protection capability, and if all MOS modules in the selected unit output current and electrostatic release protection level adjustable module are controlled by the IO second control signal of the IO core circuit module, then the unit output current capability is provided.

[0291] In a specific embodiment, all MOS modules in any unit output current and electrostatic discharge protection level adjustable module are connected to the IO second control signal input port of any unit output current and electrostatic discharge protection level adjustable module, and all connected MOS modules simultaneously provide unit electrostatic discharge protection capability and unit output current capability, such as Figure 5 At this time, all MOS modules in any one of the modules with adjustable unit output current and electrostatic discharge protection level provide not only unit electrostatic discharge protection capability but also unit output current capability.

[0292] In specific embodiment 1, some MOS modules in the module with adjustable output current and electrostatic discharge protection level are connected to the second control signal input port of the IO of the module with adjustable output current and electrostatic discharge protection level, and the connected MOS modules simultaneously provide corresponding electrostatic discharge protection capabilities and output current capabilities, while the remaining MOS modules provide corresponding electrostatic discharge protection capabilities. In this case, some MOS modules in the module with adjustable output current and electrostatic discharge protection level have corresponding electrostatic discharge protection capabilities and output current capabilities, while the remaining MOS modules only have corresponding electrostatic discharge protection capabilities. The electrostatic discharge protection capabilities corresponding to the some MOS modules and the electrostatic discharge protection capabilities corresponding to the remaining MOS modules together constitute the unit electrostatic discharge protection capability.

[0293] In the specific embodiment 2, all MOS modules in any unit output current and electrostatic discharge protection level adjustable module are disconnected from the IO second control signal input port of any unit output current and electrostatic discharge protection level adjustable module, and all disconnected MOS modules provide unit electrostatic discharge protection capability, such as Figure 7 At this time, any unit output current and ESD protection level adjustable module can only provide unit ESD protection capability, but cannot provide any output current capability.

[0294] The unit output current and electrostatic discharge protection level adjustable module includes an output PMOS unit and an output NMOS unit. The output PMOS unit includes multiple PMOS modules, and the output NMOS unit includes multiple NMOS modules.

[0295] In a specific embodiment 3, assuming IOH = 3mA, IOL = 5.1mA, and ESD = 12kV, the unit output current capability provided by the unit output current and electrostatic discharge protection level adjustable module is 0.5mA, and the unit electrostatic discharge protection capability provided is 1kV. Therefore, IOH is 3mA / 0.5mA = 6, requiring 6 complete output PMOS cells to provide a high-level output source current. IOL is 5.1mA / 0.5mA = 10.2, requiring 10 complete output NMOS cells and one output NMOS cell with a 20% ratio to provide a low-level output sink current. The 20% ratio of output NMOS cells means that 20% of the multiple NMOS modules included in the output NMOS cells are used. ESD = 12kV / 1kV = 12, requiring 12 complete output NMOS cells and 12 complete output NMOS cells.

[0296] Therefore, to achieve the above-mentioned assumed conditions, it is necessary to connect 12 unit output current and electrostatic discharge protection level adjustable modules to the IO core circuit module to provide 12kV electrostatic discharge protection capability, and select 6 complete output PMOS units from the 12 unit output current and electrostatic discharge protection level adjustable modules to connect to the IO second control signal input port to provide high-level output source current, and select 10 complete output NMOS units and one output NMOS unit accounting for 20% to connect to the IO second control signal input port to provide low-level output sink current. The output NMOS unit accounting for 20% is: 20% of the number of NMOS modules used in the multiple NMOS modules included in the output NMOS unit.

[0297] In the present disclosure, in the unit output current and electrostatic discharge protection level adjustable module, the IO second control signal of the IO core circuit module is received through the IO second control signal input port to control the PMOS module and NMOS module connected to the IO second control signal input port in the output PMOS unit and the output NMOS unit, respectively, to achieve the output current capability expected by the user.

[0298] When the customized IO IP core is implemented as a circuit layout, the layout area of ​​the implemented circuit layout capable of providing electrostatic discharge protection capability needs to be implemented as the layout area of ​​the customized IO IP core.

[0299] After generating the designated pin module of the customized IO IP core, the input threshold voltage, output current capability, and anti-static protection capability of other pins of the customized IO IP core can be configured according to actual configuration requirements. The corresponding pin module of the customized IO IP core is generated through the above steps S410 to 450. Then, all the pin modules are spliced ​​together to finally generate the customized IO IP core.

[0300] The present disclosure divides the output current and electrostatic release protection level adjustable module into multiple unit output current and electrostatic release protection level adjustable modules, which not only improves the setting accuracy of the output current capability and electrostatic release protection capability, but also further increases the flexibility of the configuration of the output current capability and electrostatic release protection capability. Moreover, when the required high-level output source current IOH or low-level output sink current IOL, and the electrostatic release protection capability ESD are large values, multiple unit output current and electrostatic release protection level adjustable modules can be conveniently and directly selected for splicing, which simplifies the design process of the customized IOIP core and improves the user experience.

[0301] Furthermore, in the above-mentioned specific embodiment 2, that is, when some MOS modules in the any unit output current and electrostatic release protection level adjustable module are connected to the IO second control signal input port of the any unit output current and electrostatic release protection level adjustable module, in the remaining MOS modules of the any unit output current and electrostatic release protection level adjustable module: the gates of some MOS modules are connected to the power supply voltage through the power supply voltage port, and the gates of other MOS modules are grounded through the ground port.

[0302] Specifically, in the remaining MOS modules of any unit output current and electrostatic discharge protection level adjustable module: the gate and source of a portion of the MOS modules are short-circuited and connected to the power supply voltage through the power supply voltage port, and the gate and source of another portion of the MOS modules are short-circuited and grounded through the ground port. For example, when the configured output current and electrostatic discharge protection level adjustable module is implemented as a chip or an integrated circuit, the remaining MOS modules correspond to one or more PMOS tubes and one or more NMOS tubes, then it is necessary to short-circuit the gate and source of the one or more PMOS tubes corresponding to the remaining MOS modules and connect the power supply voltage through the power supply voltage port VDD to form a GDPMOS (Gate VDD PMOS) structure, and short-circuit the gate and source of the one or more NMOS tubes corresponding to the remaining MOS modules and connect them to the power supply voltage through the ground port VSS to form a GGNMOS (Gate Ground NMOS) structure.

[0303] Alternatively, in the remaining MOS modules of any one of the unit output current and electrostatic discharge protection level adjustable modules: the gates of some of the MOS modules are connected to the power supply voltage through the resistance module and the power supply voltage port, and the gates of other MOS modules are grounded through the resistance module and the ground port.

[0304] Specifically, in the remaining MOS modules of any unit output current and electrostatic discharge protection level adjustable module: the gate and source of a portion of the MOS modules are short-circuited and then connected to the power supply voltage through the resistor module and the power supply voltage port, and the gate and source of another portion of the MOS modules are short-circuited and then grounded through the resistor module and the ground port. For example, when the configured unit output current and electrostatic discharge protection level adjustable module is implemented as a chip or an integrated circuit, the remaining MOS modules correspond to one or more PMOS tubes and one or more NMOS tubes, then it is necessary to short-circuit the gate and source of the one or more PMOS tubes corresponding to the remaining MOS modules and then connect the power supply voltage through the resistor module and the power supply voltage port VDD to form an RGPMOS (Resistor-Gate PMOS) structure, and short-circuit the gate and source of the one or more NMOS tubes corresponding to the remaining MOS modules and then connect to the power supply voltage through the resistor module and the ground port VSS to form an RGNMOS (Resistor-Gate NMOS) structure.

[0305] In the above-mentioned specific embodiment 2, that is, when all the MOS modules in the selected unit output current and electrostatic discharge protection level adjustable module are disconnected from the IO second control signal input port of the selected unit output current and electrostatic discharge protection level adjustable module, among all the MOS modules in the selected unit output current and electrostatic discharge protection level adjustable module: the gates of some of the MOS modules are connected to the power supply voltage through the power supply voltage port, and the gates of other part of the MOS modules are grounded through the ground port.

[0306] Specifically, among all MOS modules of the selected unit output current and electrostatic discharge protection level adjustable module: among all MOS modules of the selected unit output current and electrostatic discharge protection level adjustable module: the gate and source of some MOS modules are short-circuited and connected to the power supply voltage through the power supply voltage port, and the gate and source of another part of the MOS modules are short-circuited and grounded through the ground port. For example, when the configured unit output current and electrostatic discharge protection level adjustable module is implemented as a chip or an integrated circuit, all the MOS modules correspond to multiple PMOS transistors and multiple NMOS transistors, then it is necessary to short-circuit the gate and source of the multiple PMOS transistors corresponding to all the MOS modules and connect them to the power supply voltage through the power supply voltage port VDD to form a GDPMOS structure, and short-circuit the gate and source of the multiple NMOS transistors corresponding to all the MOS modules and connect them to the ground through the ground port VSS to form a GGNMOS structure.

[0307] Alternatively, among all the MOS modules of the selected unit output current and electrostatic discharge protection level adjustable module: the gates of some MOS modules are connected to the power supply voltage through the resistance module and the power supply voltage port, and the gates of other MOS modules are grounded through the resistance module and the ground port.

[0308] Specifically, among all MOS modules of the selected unit output current and electrostatic discharge protection level adjustable module: the gate and source of some MOS modules are short-circuited and then connected to the power supply voltage through the resistor module and the power supply voltage port, while the gate and source of another part of the MOS modules are short-circuited and then grounded through the resistor module and the ground port. For example, when the configured unit output current and electrostatic discharge protection level adjustable module is implemented as a chip or an integrated circuit, all the MOS modules correspond to multiple PMOS transistors and multiple NMOS transistors. Then, it is necessary to short-circuit the gate and source of the multiple PMOS transistors corresponding to all the MOS modules and then connect them to the power supply voltage through the resistor module and the power supply voltage port VDD to form an RGPMOS structure, and short-circuit the gate and source of the multiple NMOS transistors corresponding to all the MOS modules and then ground them through the resistor module and the ground port VSS to form a GGNMOS structure.

[0309] Figure 6 A schematic diagram illustrating connecting an IO core circuit module, a configured input voltage adjustable module, and a configured output current and electrostatic discharge protection level adjustable module in a method for generating a customized IO IP core based on a configurable IO IP core according to an embodiment of the present disclosure is shown. Figure 6In the example shown, the configured output current and ESD protection level adjustable module includes two different unit output current and ESD protection level adjustable modules. Those skilled in the art should understand that the number and type of the unit output current and ESD protection level adjustable modules are set according to user needs, and the number and type of the unit output current and ESD protection level adjustable modules are not intended to limit the scope of protection of this disclosure.

[0310] like Figure 6 As shown, the customized IO IP core includes: an IO core circuit module, a configured input threshold adjustable module, and a configured unit output current and electrostatic release protection level adjustable module. The IO first control signal output port of the configured input threshold adjustable module is connected to the IO first control signal input port of the IO core circuit module, the IO second control signal output port of the IO core circuit module is connected to the IO second control signal input port of each unit output current and electrostatic release protection level adjustable module in the configured output current and electrostatic release protection level adjustable module, and the IO second control signal input port of the configured unit output current and electrostatic release protection level adjustable module is disconnected from all MOS modules of the configured unit output current and electrostatic release protection level adjustable module.

[0311] Among them, the IO core circuit module includes: a power supply voltage port, a ground port, an IO first control signal input port and an IO second control signal output port; the selected unit electrostatic discharge protection module includes: a power supply voltage port, a ground port and an IO second control signal input port.

[0312] The power supply voltage ports of the IO core circuit module and the selected unit output current and electrostatic release protection level adjustable module are both connected to the power supply voltage, and the ground ports are both grounded. The IO first control signal input port of the IO core circuit module receives the external IO input signal, obtains the IO second control signal after processing and outputs it through the IO second control signal output port, and the selected unit output current and electrostatic release protection level adjustable module obtains the IO second control signal through the IO second control signal input port to control the MOS module connected to the IO second control signal input port of the selected output current and electrostatic release protection level adjustable module to provide corresponding electrostatic release protection capability and output current capability at the same time. Figure 6In the example shown, two modules with adjustable unit output current and electrostatic discharge protection level are included. The control input port of one of them is disconnected from all the MOS modules it includes, and it can only provide unit electrostatic discharge protection capability. The control input port of the other one is connected to all the MOS modules it includes, so that it can provide unit electrostatic discharge protection capability and unit output current capability at the same time.

[0313] For example, when a pin module of a customized IO IP core needs to have a 5kV electrostatic discharge protection capability, when the configured output current and electrostatic discharge protection level adjustable module is implemented as an integrated circuit or chip, assuming that the unit electrostatic discharge protection capability provided by a unit output current and electrostatic discharge protection level adjustable module in the configured output current and electrostatic discharge protection level adjustable module is 0.5kV, then under a 0.18μm design process, 5kV / 0.5kV=10 unit electrostatic discharge protection modules need to be connected to the IO core circuit.

[0314] For another example, a pin module of a customized IO IP core needs to have both a 4kV ESD protection capability and a 4mA output current capability. When the configured output current and ESD protection level adjustable module is implemented as an integrated circuit or chip, assuming that the unit ESD protection capability provided by a unit output current and ESD protection level adjustable module in the configured output current and ESD protection level adjustable module is 0.5kV, then under a 0.18μm design process, when all MOS transistors in the unit output current and ESD protection level adjustable module are used, the unit output current capability that can be provided is 1mA. In this case, 8 unit output current and ESD protection level adjustable modules (4kV / 0.5kV) need to be connected to the IO core circuit, of which 4 unit output current and ESD protection level adjustable modules need to provide both unit ESD protection capability and unit output current capability, and the remaining 4 unit output current and ESD protection level adjustable modules only need to provide unit ESD protection capability.

[0315] The present invention can automatically select the unit output current and electrostatic release level adjustable protection module that needs to be connected and automatically select the MOS module that needs to be connected in the selected unit output current and electrostatic release level adjustable protection module according to the different input threshold voltage, output current capability and electrostatic release protection capability requirements of the actual chip, thereby forming a chip design that meets the requirements of input threshold voltage, output current capability and electrostatic release protection capability, and realizing flexible configuration of input threshold voltage, output current capability and electrostatic release protection capability.

[0316] When the customized IP core is an IO IP core with power-on control, a layout of the IO IP core with power-on control is generated according to the configuration parameters input by the user, including: generating the IO IP core with power-on control according to the IO IP core and the configurable POC IP core and the third configuration parameters input by the user; and generating a layout of the IO IP core with power-on control based on the IO IP core with power-on control.

[0317] The third configuration parameter includes one or more of the following items: POC input threshold voltage, input threshold high level voltage, input threshold low level voltage, high level output source current, low level output sink current and electrostatic discharge protection level.

[0318] Figure 7 FIG. 1 is a flow chart showing a method for generating an IOIP core with power-on control based on a configurable POC IP core according to an embodiment of the present disclosure. Figure 7 As shown, generating the IO IP core with power-on control according to the IO IP core, the configurable POC IP core and the third configuration parameter input by the user specifically includes the following steps S710 to S760:

[0319] In step S710 , a configurable POC IP core is obtained, where the configurable POC IP core includes a POC core circuit module and a POC input threshold voltage adjustable module.

[0320] After research, the inventors of the present disclosure discovered that the reason why existing POC IP cores can only provide fixed input threshold voltages (including power-up threshold voltage and power-down threshold voltage) is that the POC IP core is designed as an integrated module. This makes it impossible to easily and independently configure its various internal functional modules (such as the POC input threshold voltage module). As a result, the IO IP core can only provide a fixed input threshold voltage, which cannot meet the actual requirements of different chips for different input threshold voltages.

[0321] The present disclosure splits the existing overall POC IP core into multiple functional modules and separately configures the input threshold voltage module therein, thereby realizing a configurable POC IP core. In the configurable POC IP core, each internal function can be easily and independently controlled, and then automatically adjusted according to the actual needs of different chips, thereby realizing flexible and configurable POC input threshold voltage.

[0322] In the present disclosure, the configurable POC IP core is no longer an integral module, but includes a POC core circuit module and a POC input threshold voltage adjustable module, wherein the POC input threshold voltage adjustable module can be configured according to the POC input threshold voltage input by the user, so that the customized POC IP core generated based on the configured POC input threshold voltage adjustable module meets the actual demand of supporting the specified POC input threshold voltage.

[0323] The configurable POC IP core is provided by a customized EDA tool.

[0324] In step S720 , the IO IP core is obtained.

[0325] Different from the IO IP core in the existing standard IO IP core library, the IO IP core involved in step S720 includes: a POC control signal input port, so as to receive the POC control signal through the port.

[0326] In addition to this difference, the IO IP cores involved in this disclosure include two types: one is an IO IP core with a fixed input threshold voltage and anti-static protection capability and a limited number of output current capabilities; the other is an IO IP core with a flexibly configurable input threshold voltage, anti-static protection capability, and output current capability.

[0327] For the first type of IO IP core, when obtaining the customized EDA tool, it is necessary to add a POC control signal input port and a corresponding circuit module for processing the received POC control signal on the basis of the existing IO IP core.

[0328] For the second type of IO IP core, which is a customized IO IP core, the customized EDA tool needs to design it based on a configurable IO IP core with adjustable input threshold voltage, adjustable output current capability, and adjustable anti-static protection capability when obtaining the customized IO IP core. The specific method can be found according to Figure 4 The customized IO IP core is designed based on a configurable IO IP core with adjustable input threshold voltage, output current capability, and electrostatic discharge protection level.

[0329] In step S730 , the POC input threshold voltage input by the user is obtained through the multiple customized input boxes.

[0330] In the present disclosure, after combining the POC IP with the IO IP, since the IO IP primarily utilizes the POC control signal to reflect whether the dual power supplies are fully powered on, in a specific embodiment, the user can configure the POC input threshold voltage adjustable module simply by inputting the first power-on threshold voltage and the second power-on threshold voltage.

[0331] In step S740, the POC input threshold voltage adjustable module is configured according to the POC input threshold voltage. The POC input threshold voltage adjustable module includes a first MOS module group. The configuring of the POC input threshold voltage adjustable module according to the POC input threshold voltage includes: selecting a number of MOS modules corresponding to the POC input threshold voltage from the first MOS module group and connecting the selected MOS modules to generate a configured POC input threshold voltage adjustable module. The configured POC input threshold voltage adjustable module is used to generate a POC first control signal of the POC core circuit module.

[0332] In step S750, the POC core circuit module and the configured POC input threshold voltage adjustable module are connected to generate a customized POC IP core, and the customized POC IP core is used to generate a POC control signal.

[0333] In step S760, the customized POC IP core and the IO IP core are connected to generate an IO IP core with power-on control.

[0334] Figure 8 A structural schematic diagram of an IO IP core with power-on control according to an embodiment of the present disclosure is shown, wherein the IO IP core is a customized IO IP core.

[0335] Among them, the POC core circuit module includes: a POC first control signal input port and a POC control signal output port; the configured POC input threshold voltage adjustable module includes: a POC first control signal output port; the IOIP core includes: a POC control signal input port; the IO IP core, the POC core circuit module and the configured POC input threshold voltage adjustable module also include: a power supply voltage port and a ground port.

[0336] The power supply voltage ports of the IO IP core, the POC core circuit module, and the configured POC input threshold voltage adjustable module are all connected to the first power supply and the second power supply, and the ground ports of the IO IP core, the POC core circuit module, and the configured POC input threshold voltage adjustable module are all grounded.

[0337] The POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to the POC first control signal input port of the POC core circuit module, for providing the POC first control signal to the POC core circuit module; the POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to a MOS module selected from the first MOS module group.

[0338] The POC control signal output port of the POC core circuit module is connected to the POC control signal input port of the IO IP core, so that the IO IP core controls the output of its own current through the POC control signal output by the customized POC IP core.

[0339] According to an embodiment of the present disclosure, the IO IP core controls the output of its own current through the POC control signal output by the customized POC IP core, including:

[0340] When either the first power supply or the second power supply is powered off, the POC control signal output by the customized POC IP core is at a low level; when the POC control signal is at a low level, the IO IP core controls itself to not output current and enters a high-impedance state;

[0341] When the first power supply and the second power supply are fully powered on, the POC control signal output by the customized POC IP core is at a high level; when the POC control signal is at a high level, the IO IP core controls its own normal output current.

[0342] In a specific embodiment, if the IO IP core is a customized IO IP core, the IO IP core controls the output of its own current through the POC control signal output by the customized POC IP core, including:

[0343] The IO core circuit module obtains the POC control signal through the POC control signal input port;

[0344] generating a current control signal according to the POC control signal, and sending the current control signal to the configured output current adjustable module;

[0345] The configured output current adjustable module controls the output current of the IO IP core according to the current control signal.

[0346] When the IO IP core specifically implements controlling the output of its own current through the POC control signal output by the customized POC IP core, a corresponding circuit module for processing the received POC control signal can be added to the existing IO IP core. For example, a signal parsing unit is added inside the IO core circuit module. The signal parsing unit can be a hardware logic circuit that can identify and parse the POC control signal, and generate a current control signal based on the POC control signal parsing unit. The current control signal can be an analog signal (such as a voltage signal) or a digital signal (such as a PWM signal) for controlling the output current adjustable module. After generating the current control signal, the IO core circuit module will send this signal to the configured output current adjustable module through an internal signal transmission unit. The signal transmission unit can be a hardware interface (such as SPI, I2C, etc.) or a software communication protocol (such as UART, CAN, etc.), depending on the design and requirements of the system. After receiving the current control signal, the configured output current adjustable module adjusts its internal current regulation circuit according to the current control signal. The current regulating circuit may include some switching tubes, resistors, inductors and other components, and the output current can be adjusted by changing the states or parameters of these components.

[0347] Specifically, when the POC control signal is low, the IO IP core stops outputting current and enters a high-impedance state, effectively preventing current from flowing through it. To achieve this high-impedance state, the IO IP core can employ a specialized circuit design, such as an open-drain structure or similar configuration. When in this high-impedance state, the IO IP core's pins are disconnected from the internal circuitry, creating a high-impedance path that effectively blocks current flow.

[0348] When the first power supply and the second power supply are fully powered on, the POC control signal output by the customized POC IP core is at a high level. At this time, the IO IP core controls its own normal output current.

[0349] The IO IP core with power-on control provided in the embodiment of the present disclosure controls the current output of the IOIP through a flexible and configurable POC IP, so that the generated customized IO IP core with power-on control can meet the design requirements of complex industrial chips.

[0350] When the customized IP core is a customized unit with power-on control, the layout of the customized unit with power-on control is generated according to the configuration parameters input by the user, including: generating the customized unit with power-on control according to the POC IP core and the standard cell module; generating the layout of the customized unit with power-on control based on the customized unit with power-on control; when the POCIP core is a customized POC IP core, generating the customized unit with power-on control according to the POC IP core and the standard cell module includes: generating the customized unit with power-on control according to the customized POC IP core, the standard cell module and the first configuration parameters.

[0351] Figure 9 FIG. 1 is a flow chart showing a method for generating a customized unit with power-on control according to an embodiment of the present disclosure. Figure 9 As shown, generating the customized unit with power-on control according to the POC IP core and the standard unit module specifically includes the following steps S910 to S930:

[0352] In step S910, a POC IP core is obtained; the POC IP core includes: a first power input terminal, a second power input terminal and a control signal output terminal.

[0353] In step S920 , a standard cell module is obtained; the standard cell module includes: a first logic control signal input terminal, a second logic control signal input terminal, a power input terminal, and a cell signal output terminal.

[0354] Specifically, the custom EDA tool provides a POC IP core and a standard cell module for the user to design the custom cell with power-on control.

[0355] The standard cell module may be a library cell in a standard cell library provided by a customized EDA tool, or a library cell designed as needed and stored in a cell library; the POC IP core may be a POC IP core provided by the customized EDA tool.

[0356] In step S930 , the POC IP core and the standard cell module are connected to generate a custom cell with power-on control.

[0357] The first logic control signal input terminal of the standard cell module is connected to a first power supply circuit module powered by a first power supply, so that the standard cell module obtains a first logic control signal through the first power supply circuit module; the second logic control signal input terminal of the standard cell module is connected to a second power supply circuit module powered by a second power supply, so that the standard cell module obtains a second logic control signal through the second power supply circuit module; and the power input terminal of the standard cell module is connected to a power supply;

[0358] The first power input terminal of the POC IP core is connected to the first power supply, and the second power input terminal of the POC IP core is connected to the second power supply, so that the POC IP core obtains the voltage status of the first power supply and the second power supply, and generates a first control signal according to the voltage status of the first power supply and the second power supply;

[0359] The control signal output terminal of the POC IP core is connected to the standard cell module, so that the POC IP core outputs the first control signal to the standard cell module through the control signal output terminal, so as to control whether the standard cell module outputs normally through the first control signal;

[0360] The obtaining of the voltage status of the first power supply and the second power supply includes:

[0361] Comparing a current voltage value of the first power supply with a preset first power-on threshold voltage, and when the current voltage value of the first power supply is not lower than the preset first power-on threshold voltage, the voltage state of the first power supply is a power-on state;

[0362] comparing a current voltage value of the second power supply with a preset second power-on threshold voltage, and when the current voltage value of the second power supply is not lower than the preset second power-on threshold voltage, determining that the voltage state of the second power supply is a power-on state;

[0363] Generating a first control signal according to voltage states of the first power supply and the second power supply includes:

[0364] When the voltage state of the first power supply and the voltage state of the second power supply are both in the power-on state, the first control signal is at a high level; otherwise, the first control signal is at a low level.

[0365] When step S930 is specifically executed, it can be performed in the following three ways:

[0366] The first method uses the first control signal to control the power supply of the standard cell module to be turned on and off. When the first control signal is at a high level, i.e., when the dual power supplies are fully powered on, the power supply of the standard cell module is turned on; when the first control signal is at a low level, i.e., when the dual power supplies are partially powered on, the power supply of the standard cell module is turned off.

[0367] The first method cuts off the power supply of subsequent standard unit modules when the dual power supplies are not fully powered on, thereby avoiding erroneous logic output and preventing the standard unit modules from generating power, thereby reducing the power consumption output of the entire circuit.

[0368] The second method uses the first control signal to control the connection or disconnection of the output of the standard cell module. When the first control signal is at a high level, that is, when the dual power supplies are fully powered on, the output of the standard cell module is controlled to be connected; when the first control signal is at a low level, that is, when the dual power supplies are not fully powered on, the output of the standard cell module is controlled to be disconnected.

[0369] The third method involves directly inputting the first control signal to the standard cell module, which then controls its output based on the first control signal. When the first control signal is high (i.e., when the dual power supplies are fully powered), the standard cell module controls its output to be on. When the first control signal is low (i.e., when the dual power supplies are partially powered), the standard cell module controls its output to be off.

[0370] The first and second methods mentioned above do not require any modification to the standard cell module. In this way, it is easier to customize the standard cells in the standard cell library with power-on control functions, simplifying the design process and making it easier to upgrade and maintain the standard cell module.

[0371] The specific implementation plans of the above three methods are described in detail below.

[0372] For the first method:

[0373] According to an embodiment of the present disclosure, the method further includes: acquiring a first switch control circuit module; wherein the first switch control circuit module includes: a first input terminal, a second input terminal, and an output terminal.

[0374] The power input terminal of the standard cell module is connected to the power supply, and the control signal output terminal of the POC IP core is connected to the standard cell module, including: the power supply is connected to the power input terminal of the standard cell module through the first switch control circuit module, and the control signal output terminal of the POC IP core is connected to the standard cell module through the first switch control circuit module, including: the power supply is connected to the first input terminal of the first switch control circuit module, the POC The control signal output terminal of the IP core is connected to the second input terminal of the first switch control circuit module, and the output terminal of the first switch control circuit module is connected to the power input terminal of the standard cell module, so that the first switch control circuit module generates a second control signal according to the first control signal, and uses the second control signal to control the connection or disconnection of the power supply. When the power supply is disconnected, the standard cell module stops processing the first logic control signal and the second logic control signal, so that the standard cell module has no output; and when the power supply is connected, the standard cell module resumes processing the first logic control signal and the second logic control signal, so that the standard cell module outputs normally. The generating of the second control signal according to the first control signal and using the second control signal to control the connection or disconnection of the power supply include:

[0375] When the first control signal is at a high level, the second control signal is a closing signal, which closes the output end of the first switch control circuit module; when the first control signal is at a low level, the second control signal is a disconnecting signal, which disconnects the output end of the first switch control circuit module; when the output end of the first switch control circuit module is closed, the power supply is turned on; when the output end of the first switch control circuit module is disconnected, the power supply is turned off.

[0376] For example, assuming the first power supply is 5V, the second power supply and the power supply for the standard cell module are 1.8V, and the preset first power-on threshold voltage is 4.5V, when the current voltage of the first power supply is 4.3V, the POC IP core detects that the current voltage is lower than the preset first power-on threshold voltage, and determines that the voltage state of the first power supply is off. The first control signal output to the first switch control circuit module is low. The second control signal generated by the first switch control circuit module based on the first control signal is a disconnect signal. The disconnect signal disconnects the output terminal of the first switch control circuit module, thereby disconnecting the power supply, causing the standard cell module to stop processing the first logic control signal and the second logic control signal, resulting in no output from the standard cell module.

[0377] When the current voltage value of the first power supply is 4.9V, the POC IP core detects that the current voltage value is higher than the preset first power-on threshold voltage, determines that the voltage state of the first power supply is powered on, and outputs a first control signal to the first switch control circuit module at a high level. The first switch control circuit module generates a second control signal as a closing signal based on the first control signal, and the closing signal controls the output terminal of the first switch control circuit module to close. This turns on the power supply, the standard cell module resumes processing the first logic control signal and the second logic control signal, and the standard cell module outputs normally.

[0378] For the second method:

[0379] According to an embodiment of the present disclosure, the method further includes: acquiring a second switch control circuit module; wherein the second switch control circuit module includes: a signal input terminal and a signal output terminal.

[0380] According to an embodiment of the present disclosure, the control signal output terminal of the POC IP core is connected to the standard cell module, including:

[0381] The control signal output terminal of the POC IP core is connected to the signal input terminal of the second switch control circuit module; the signal output terminal of the second switch control circuit module is connected to the cell signal output terminal of the standard cell module, so that the second switch control circuit module generates a third control signal according to the first control signal, and uses the third control signal to control the connection or disconnection of the output of the standard cell module, so that when the output of the standard cell module is disconnected, the standard cell module has no output; and when the output of the standard cell module is connected, the standard cell module outputs normally; wherein, generating the third control signal according to the first control signal and using the third control signal to control the connection or disconnection of the output of the standard cell module includes:

[0382] When the first control signal is at a high level, the third control signal is a closing signal, which connects the unit signal output end of the standard unit module; when the first control signal is at a low level, the third control signal is a disconnecting signal, which cuts off the unit signal output end of the standard unit module; when the unit signal output end of the standard unit module is connected, the output of the standard unit module is connected; when the unit signal output end of the standard unit module is cut off, the output of the standard unit module is cut off.

[0383] For the third method:

[0384] According to an embodiment of the present disclosure, the standard cell module further includes: a control signal input terminal;

[0385] Connecting the control signal output end of the POC IP core to the standard cell module includes: connecting the control signal output end of the POC IP core to the control signal input end of the standard cell module, so that the standard cell module controls whether to output itself according to the first control signal.

[0386] According to an embodiment of the present disclosure, the standard cell module controls whether it has output according to the first control signal, including: when the first control signal is at a high level, the output of the standard cell module is turned on, and the standard cell module outputs normally; when the first control signal is at a low level, the output of the standard cell module is cut off, and the standard cell module has no output.

[0387] The POC IP cores involved in the embodiments of the present disclosure include but are not limited to two types. One type is a default POC IP core provided by a custom EDA tool. The default POC IP core is non-configurable, including: the preset first power-on threshold voltage and the preset second power-on threshold voltage are both preset fixed values. That is, the user can only select an existing POC IP core with a fixed first power-on threshold voltage value and a fixed second power-on threshold voltage value provided by the custom EDA tool, and cannot flexibly set the power-on threshold voltage of the selected POC IP core according to actual application needs.

[0388] According to an embodiment of the present disclosure, the default POC IP core includes: a connected POC IP core circuit module and a default threshold voltage module, wherein the default threshold voltage module includes a number of MOS modules corresponding to the preset first power-on threshold voltage and the preset second power-on threshold voltage.

[0389] That is, in the default POC IP core, the number of MOS modules in the default threshold voltage module corresponds to the preset first power-on threshold voltage and the preset second power-on threshold voltage, and cannot be flexibly adjusted.

[0390] In order to achieve flexible adjustment of the power-on threshold voltage, the generated customized unit with power-on control can meet the design requirements of complex industrial chips such as different power-on threshold voltages. Figure 2 The customized POC IP core shown is designed based on the configurable POC IP core; the customized POC IP core is configurable, including: the preset first power-on threshold voltage is the first power-on threshold voltage input by the user, and the preset second power-on threshold voltage is the second power-on threshold voltage input by the user.

[0391] Directly using the default and custom POC IP cores provided by custom EDA tools can greatly simplify system design complexity and reduce design and maintenance costs. Furthermore, these and other custom POC IP cores are typically designed based on widely accepted and proven standards, which means they offer greater reliability and predictability. In contrast, custom-designed power-on control circuits may contain unknown issues or design flaws, requiring more extensive testing and verification to ensure reliability. Therefore, directly using the default and custom POC IP cores provided by custom EDA tools offers higher reliability, reduced complexity, and improved compatibility.

[0392] Figure 10 FIG. 1 shows a structural connection diagram of a customized unit with power-on control according to an embodiment of the present disclosure. Figure 10 As shown, the customized unit includes: a POC IP core, a first switch control circuit module and a standard unit module.

[0393] Among them, the POC IP core includes: a first power input terminal 110, a second power input terminal 120 and a control signal output terminal 130; the standard cell module includes: a first logic control signal input terminal 210, a second logic control signal input terminal 220, a power input terminal 230, and a cell signal output terminal 240; the first switch control circuit module includes: a first input terminal 310, a second input terminal 320, and an output terminal 330.

[0394] The first logic control signal input terminal 210 of the standard cell module is connected to a first power supply circuit module powered by a first power supply, and the second logic control signal input terminal 220 of the standard cell module is connected to a second power supply circuit module powered by a second power supply. The standard cell module is configured to obtain a first logic control signal through the first power supply circuit module and to obtain a second logic control signal through the second power supply circuit module.

[0395] The first power input terminal 110 of the POC IP core is connected to the first power supply, and the second power input terminal 120 of the POC IP core is connected to the second power supply. The POC IP core is configured to obtain the voltage status of the first power supply and the second power supply, and generate a first control signal according to the voltage status of the first power supply and the second power supply.

[0396] According to an embodiment of the present disclosure, obtaining the voltage status of the first power supply and the second power supply includes:

[0397] Comparing a current voltage value of the first power supply with a preset first power-on threshold voltage, and when the current voltage value of the first power supply is not lower than the preset first power-on threshold voltage, the voltage state of the first power supply is a power-on state;

[0398] The current voltage value of the second power supply is compared with a preset second power-on threshold voltage. When the current voltage value of the second power supply is not lower than the preset second power-on threshold voltage, the voltage state of the second power supply is a power-on state.

[0399] According to an embodiment of the present disclosure, generating a first control signal according to voltage states of the first power supply and the second power supply includes:

[0400] When the voltage state of the first power supply and the voltage state of the second power supply are both in the power-on state, the first control signal is at a high level; otherwise, the first control signal is at a low level.

[0401] The control signal output terminal 130 of the POC IP core is connected to the standard cell module. The POC IP core is also configured to output the first control signal to the standard cell module through the control signal output terminal 130 to control whether the standard cell module outputs normally through the first control signal.

[0402] Specifically, the power input terminal 230 of the standard cell module is connected to the power supply through the first switch control circuit module, and the control signal output terminal 130 of the POC IP core is connected to the standard cell module through the first switch control circuit module, including: the power supply is connected to the first input terminal 310 of the first switch control circuit module, the control signal output terminal 130 of the POC IP core is connected to the second input terminal 320 of the first switch control circuit module, and the output terminal 330 of the first switch control circuit module is connected to the power input terminal 230 of the standard cell module; the first switch control circuit module is configured to generate a second control signal according to the first control signal, and use the second control signal to control the connection or disconnection of the power supply; when the power supply is disconnected, the standard cell module stops processing the first logic control signal and the second logic control signal, so that the standard cell module has no output; when the power supply is connected, the standard cell module resumes processing the first logic control signal and the second logic control signal, so that the standard cell module outputs normally.

[0403] According to an embodiment of the present disclosure, generating a second control signal according to the first control signal, and using the second control signal to control the connection or disconnection of the power supply includes:

[0404] When the first control signal is at a high level, the second control signal is a closing signal, which closes the output end 330 of the first switch control circuit module; when the first control signal is at a low level, the second control signal is a disconnecting signal, which disconnects the output end 330 of the first switch control circuit module; when the output end 330 of the first switch control circuit module is closed, the power supply is turned on; when the output end 330 of the first switch control circuit module is disconnected, the power supply is turned off.

[0405] Figure 11 FIG. 2 shows a structural connection diagram of another customized unit with power-on control according to an embodiment of the present disclosure. Figure 11 As shown, the customized unit includes: a POC IP core, a second switch control circuit module and a standard unit module.

[0406] Among them, the POC IP core includes: a first power input terminal 110, a second power input terminal 120 and a control signal output terminal 130; the standard cell module includes: a first logic control signal input terminal 210, a second logic control signal input terminal 220, a power input terminal 230, and a cell signal output terminal 240; the second switch control circuit module includes: a signal input terminal 410 and a signal output terminal 420.

[0407] The first logic control signal input terminal 210 of the standard cell module is connected to a first power supply circuit module powered by a first power supply, and the second logic control signal input terminal 220 of the standard cell module is connected to a second power supply circuit module powered by a second power supply. The standard cell module is configured to obtain a first logic control signal through the first power supply circuit module and to obtain a second logic control signal through the second power supply circuit module.

[0408] The first power input terminal 110 of the POC IP core is connected to the first power supply, and the second power input terminal 120 of the POC IP core is connected to the second power supply. The POC IP core is configured to obtain the voltage status of the first power supply and the second power supply, and generate a first control signal according to the voltage status of the first power supply and the second power supply.

[0409] According to an embodiment of the present disclosure, obtaining the voltage status of the first power supply and the second power supply includes:

[0410] Comparing a current voltage value of the first power supply with a preset first power-on threshold voltage, and when the current voltage value of the first power supply is not lower than the preset first power-on threshold voltage, the voltage state of the first power supply is a power-on state;

[0411] The current voltage value of the second power supply is compared with a preset second power-on threshold voltage. When the current voltage value of the second power supply is not lower than the preset second power-on threshold voltage, the voltage state of the second power supply is a power-on state.

[0412] According to an embodiment of the present disclosure, generating a first control signal according to voltage states of the first power supply and the second power supply includes:

[0413] When the voltage state of the first power supply and the voltage state of the second power supply are both in the power-on state, the first control signal is at a high level; otherwise, the first control signal is at a low level.

[0414] The control signal output terminal 130 of the POC IP core is connected to the standard cell module. The POC IP core is also configured to output the first control signal to the standard cell module through the control signal output terminal 130 to control whether the standard cell module outputs normally through the first control signal.

[0415] Specifically, the control signal output terminal 130 of the POC IP core is connected to the signal input terminal 410 of the second switch control circuit module; the signal output terminal 420 of the second switch control circuit module is connected to the unit signal output terminal 240 of the standard unit module; the second switch control circuit module is configured to generate a third control signal according to the first control signal, and use the third control signal to control the connection or disconnection of the output of the standard unit module; when the output of the standard unit module is disconnected, the standard unit module has no output; when the output of the standard unit module is connected, the standard unit module outputs normally.

[0416] According to an embodiment of the present disclosure, generating a third control signal according to the first control signal, and using the third control signal to control the on or off of the output of the standard cell module includes:

[0417] When the first control signal is at a high level, the third control signal is a closing signal, which connects the unit signal output terminal 240 of the standard unit module; when the first control signal is at a low level, the third control signal is a disconnecting signal, which disconnects the unit signal output terminal 240 of the standard unit module; when the unit signal output terminal 240 of the standard unit module is connected, the output of the standard unit module is connected; when the unit signal output terminal 240 of the standard unit module is disconnected, the output of the standard unit module is disconnected.

[0418] Figure 12 FIG. 2 shows a structural connection diagram of another customized unit with power-on control according to an embodiment of the present disclosure. Figure 12 As shown, the customized unit includes: a POC IP core, a standard cell module, a threshold voltage adjustable power supply monitoring circuit module and a third switch control circuit module.

[0419] In the embodiment of the present disclosure, the POC IP core is a default POC IP core.

[0420] Among them, the POC IP core includes: the POC IP core includes: a first power input terminal 110, a second power input terminal 120 and a control signal output terminal 130; the standard cell module includes: a first logic control signal input terminal 210, a second logic control signal input terminal 220, a power input terminal 230, a unit signal output terminal 240, and a control signal input terminal 250; the threshold voltage adjustable power supply monitoring circuit module includes: a first power input terminal 510, a second power input terminal 520 and a control signal output terminal 530; the third switch control circuit module includes: a control signal input terminal 610 and a power enable signal output terminal 620.

[0421] Specifically, the first power input terminal 510 of the threshold voltage adjustable power supply monitoring circuit module is connected to the first power supply; the second power input terminal 520 of the threshold voltage adjustable power supply monitoring circuit module is connected to the second power supply; the control signal output terminal 530 of the threshold voltage adjustable power supply monitoring circuit module is connected to the control signal input terminal 610 of the third switch control circuit module; the power enable signal output terminal 620 of the third switch control circuit module is respectively connected to the first power input terminal 110 and the second power input terminal 120 of the POC IP core;

[0422] The threshold voltage adjustable power supply monitoring circuit module includes a first threshold voltage adjustable power supply monitoring circuit module, a second threshold voltage adjustable power supply monitoring circuit module, and a fourth control signal generating module; the first threshold voltage adjustable power supply monitoring circuit module is connected to the first power supply, the second threshold voltage adjustable power supply monitoring circuit module is connected to the second power supply, the first threshold voltage adjustable power supply monitoring circuit module and the second threshold voltage adjustable power supply monitoring circuit module are respectively connected to the fourth control signal generating module, and the fourth control signal generating module is connected to the control signal input terminal 610 of the third switch control circuit module;

[0423] The first threshold voltage adjustable power supply monitoring circuit module is configured to receive a first external control signal and determine a dynamically adjustable first power-on threshold voltage according to the first external control signal;

[0424] The second threshold voltage adjustable power supply monitoring circuit module is configured to receive a second external control signal and determine a dynamically adjustable second power-on threshold voltage according to the second external control signal;

[0425] The first threshold voltage adjustable power supply monitoring circuit module is further configured to compare a current voltage value of the first power supply with the dynamically adjustable first power-on threshold voltage, and when the current voltage value of the first power supply is not lower than the dynamically adjustable first power-on threshold voltage, the voltage state of the first power supply is a power-on state;

[0426] The second threshold voltage adjustable power supply monitoring circuit module is further configured to compare a current voltage value of the second power supply with the dynamically adjustable second power-on threshold voltage, and when the current voltage value of the second power supply is not lower than the dynamically adjustable second power-on threshold voltage, the voltage state of the second power supply is a power-on state;

[0427] The fourth control signal generating module is configured to generate a fourth control signal according to the voltage state of the first power supply and the voltage state of the second power supply, including: when the voltage state of the first power supply and the voltage state of the second power supply are both in the power-on state, the fourth control signal is a high level; otherwise, the fourth control signal is a low level;

[0428] The fourth control signal generating module is further configured to output the fourth control signal to the control signal input terminal 610 of the third switch control circuit module;

[0429] The third switch control circuit module is configured to control the connection or disconnection of the first power supply and the second power supply for supplying power to the POC IP core according to the fourth control signal, including: when the fourth control signal is at a high level, disconnecting the first power supply and the second power supply for supplying power to the POC IP core; when the fourth control signal is at a low level, connecting the first power supply and the second power supply for supplying power to the POC IP core;

[0430] When the first power supply and the second power supply for supplying power to the POC IP core are cut off, the first control signal is at a low level; when the first power supply and the second power supply for supplying power to the POC IP core are connected, the first control signal is at a high level.

[0431] The first logic control signal input terminal 210 of the standard cell module is connected to a first power supply circuit module powered by a first power supply, and the second logic control signal input terminal 220 of the standard cell module is connected to a second power supply circuit module powered by a second power supply. The standard cell module is configured to obtain a first logic control signal through the first power supply circuit module and to obtain a second logic control signal through the second power supply circuit module.

[0432] The first power input terminal 110 of the POC IP core is connected to the first power supply, and the second power input terminal 120 of the POC IP core is connected to the second power supply. The POC IP core is configured to obtain the voltage status of the first power supply and the second power supply, and generate a first control signal according to the voltage status of the first power supply and the second power supply.

[0433] According to an embodiment of the present disclosure, obtaining the voltage status of the first power supply and the second power supply includes:

[0434] Comparing a current voltage value of the first power supply with a preset first power-on threshold voltage, and when the current voltage value of the first power supply is not lower than the preset first power-on threshold voltage, the voltage state of the first power supply is a power-on state;

[0435] The current voltage value of the second power supply is compared with a preset second power-on threshold voltage. When the current voltage value of the second power supply is not lower than the preset second power-on threshold voltage, the voltage state of the second power supply is a power-on state.

[0436] According to an embodiment of the present disclosure, generating a first control signal according to voltage states of the first power supply and the second power supply includes:

[0437] When the voltage state of the first power supply and the voltage state of the second power supply are both in the power-on state, the first control signal is at a high level; otherwise, the first control signal is at a low level.

[0438] The control signal output terminal 130 of the POC IP core is connected to the control signal input terminal 250 of the standard cell module; the standard cell module is further configured to control whether it has output according to the first control signal.

[0439] According to an embodiment of the present disclosure, controlling whether to output according to the first control signal includes:

[0440] When the first control signal is at a high level, the output of the standard cell module is turned on and the standard cell module outputs normally; when the first control signal is at a low level, the output of the standard cell module is turned off and the standard cell module has no output.

[0441] By combining the POC IP core with standard cell modules and utilizing the different control signals output by the POC IP core when both power supplies are partially and fully powered in a dual-power circuit, the system can monitor in real time whether both power supplies are in place. It can also control subsequent standard cell modules to disable output when both power supplies are partially powered. Once both power supplies are fully powered, subsequent standard cell modules can resume normal output, thus avoiding logic output errors. This solves the problem of output logic errors caused by a sudden power outage of one of the power supplies in a dual-power circuit and ensures the stability and reliability of the circuit system in the event of abnormal power supply voltages.

[0442] Figure 13 A flow chart of a method for digitizing an integrated cell library according to an embodiment of the present disclosure is shown. The digitization method is implemented based on a custom EDA tool. The custom EDA tool integrates an integrated cell library generated using the above method described in an embodiment of the present disclosure. The integrated cell library includes standard cells and custom IP cells corresponding to custom IP cores. The custom IP cores include one or more of the following: a custom POC IP core, a custom IO IP core, an IO IP core with power-on control, and a custom cell with power-on control. Figure 13 As shown, the digital method includes the following steps S1310 to S1360:

[0443] In step S1310, the RTL code for calling the basic standard unit and / or the custom IP unit is obtained, wherein the RTL (Register-Transfer Level Code) code includes an instance of a hardware description language module describing the basic standard unit and / or an instance of a hardware description language module describing the custom IP unit.

[0444] In step S1320 , a synthesizer is used to convert the RTL code into a gate-level netlist.

[0445] In step S1330, the synthesized gate-level netlist is imported into a place-and-route tool.

[0446] In step S1340, physical layout and routing are performed based on the gate-level netlist to generate layout and routing data; the physical layout and routing based on the gate-level netlist includes: selectively placing the custom IP units and the basic standard units, and generating connections between the custom IP units and / or between the basic standard units and / or between the custom IP units and the basic standard units.

[0447] In addition to the above steps S1310 to S1340, the digitization method further includes the following steps S1350 to S1360:

[0448] In step S1350 , the layout and routing data is verified, and the verification includes one or more of the following items: design rule check (DRC), layout and schematic comparison (LVS), and electrical rule check (ERC).

[0449] In step S1360, manufacturing data is generated according to the layout and routing data. The manufacturing data includes but is not limited to: a GDSII file and a manufacturing mask.

[0450] Figure 14 The following is a schematic diagram of a device for generating an integrated cell library according to an embodiment of the present disclosure. The device is implemented based on a customized EDA tool. The customized EDA tool provides a GUI interface. The GUI interface includes multiple customized input boxes for obtaining configuration parameters input by the user. Figure 14As shown, the apparatus 1400 includes: a customized IP layout generation module, configured to generate a layout of a customized IP core according to the configuration parameters input by the user; the customized IP core includes one or more of the following items: a customized POC IP core, a customized IO IP core, an IO IP core with power-on control, and a customized unit with power-on control; an integrated unit library generation module, configured to generate an integrated unit library based on the layout of the customized IP core; wherein, generating the layout of the customized POC IP core according to the configuration parameters input by the user includes: generating the customized POC IP core according to a configurable POC IP core and a first configuration parameter input by the user; generating the layout of the customized POC IP core based on the customized POC IP core; the first configuration parameter includes: a POC input threshold voltage; generating the layout of the customized IO IP core according to the configuration parameters input by the user includes: generating the customized IO IP core according to a configurable IO IP core and a second configuration parameter input by the user; generating the customized IO IP core based on the customized IO IP core; the layout of the IP core; the second configuration parameters include one or more of the following items: input threshold high level voltage, input threshold low level voltage, high level output source current, low level output sink current and electrostatic discharge protection level; generating a layout of the IO IP core with power-on control according to the configuration parameters input by the user, including: generating the IO IP core with power-on control according to the IO IP core and the configurable POC IP core and the third configuration parameters input by the user; generating the layout of the IO IP core with power-on control based on the IO IP core with power-on control; the third configuration parameters include one or more of the following items: POC input threshold voltage, input threshold high level voltage, input threshold low level voltage, high level output source current, low level output sink current and electrostatic discharge protection level; generating a layout of the custom unit with power-on control according to the configuration parameters input by the user, including: generating the custom unit with power-on control according to the POC IP core and the standard cell module; generating the layout of the custom unit with power-on control based on the custom unit with power-on control; when the POC IP core is a customized POC IP core, the layout according to the POC The IP core and the standard cell module generate the customized cell with power-on control, including: generating the customized cell with power-on control according to the customized POC IP core, the standard cell module and the first configuration parameters.

[0451] Figure 15A schematic diagram of the structure of a digitization device for an integrated cell library according to an embodiment of the present disclosure is shown. The digitization device is implemented using a custom EDA tool that integrates an integrated cell library generated using the method described in any of the above embodiments of the present disclosure. The integrated cell library includes basic standard cells and custom IP cells corresponding to custom IP cores. The custom IP cores include one or more of the following: a custom POC IP core, a custom IO IP core, an IO IP core with power-on control, and a custom cell with power-on control.

[0452] like Figure 15 As shown, the device 1500 includes: an RTL code acquisition module, configured to acquire RTL code that calls the basic standard cell and / or the customized IP cell corresponding to the customized IP core, wherein the RTL code includes an instance of a hardware description language module that describes the basic standard cell and / or an instance of a hardware description language module that describes the customized IP cell; a gate-level netlist generation module, configured to use a synthesizer to convert the RTL code into a gate-level netlist; a gate-level netlist import module, configured to import the synthesized gate-level netlist into a layout and routing tool; a layout and routing data generation module, configured to perform physical layout and routing based on the gate-level netlist and generate layout and routing data; the physical layout and routing based on the gate-level netlist includes: selectively placing the customized IP cell and the basic standard cell, and generating connections between the customized IP cells and / or between the basic standard cells and / or between the customized IP cell and the basic standard cell.

[0453] According to an embodiment of the present disclosure, the digitization device also includes: a layout and routing data verification module, which is configured to verify the layout and routing data, and the verification includes one or more of the following items: design rule check DRC, layout and schematic comparison LVS and electrical rule check ERC.

[0454] According to an embodiment of the present disclosure, the digitizing device further includes: a manufacturing data generating module configured to generate manufacturing data according to the layout and wiring data, wherein the manufacturing data includes: a GDSII file and a manufacturing mask.

[0455] According to the technical solution provided by the embodiments of the present disclosure, customized POC IP cores, customized IO IP cores, IO IP cores with power-on control, and customized cells with power-on control, generated based on user-entered configuration parameters, are integrated into an integrated cell library that is different from traditional standard cell libraries. The customized POC IP cores and customized IO IP cores support flexible configuration of input configuration parameters, and the IO IP cores with power-on control and customized cells with power-on control combine the POC IP cores with existing IO IP cores and standard cells. This solves the problems of traditional standard cell libraries in terms of comprehensiveness and integration, as well as the problems currently existing in traditional POC IP cores, IO IP cores, and standard cells, thereby better meeting the needs of modern chip design.

[0456] The present disclosure provides a chip, comprising: manufacturing according to library cells in an integrated cell library generated by the method described above, wherein the library cells include basic standard cells and customized IP cells corresponding to customized IP cores, wherein the customized IP cores include one or more of the following items: a customized POC IP core, a customized IO IP core, an IO IP core with power-on control, and a customized cell with power-on control.

[0457] The present disclosure provides an electronic device, including: the chip as described above.

[0458] The present disclosure provides a computer-readable storage medium having computer instructions stored thereon. When the computer instructions are executed by a processor, the method as described in any one of the preceding items is implemented.

[0459] The present disclosure provides a computer program product, comprising computer instructions, which implement any of the above methods when executed by a processor.

[0460] The above description is merely a preferred embodiment of the present disclosure and an illustration of the technical principles employed. Those skilled in the art should understand that the scope of the invention herein is not limited to the technical solutions formed by the specific combination of the above-mentioned technical features, but also encompasses other technical solutions formed by any combination of the above-mentioned technical features or their equivalents without departing from the inventive concept. For example, a technical solution formed by replacing the above-mentioned features with (but not limited to) technical features with similar functions disclosed in this disclosure.

Claims

1. A method for generating an integrated cell library, characterized in that: The method is implemented based on a customized EDA tool, wherein the customized EDA tool provides a GUI interface, wherein the GUI interface includes a plurality of customized input boxes, wherein the customized input boxes are used to obtain configuration parameters input by a user, and the method includes: Generate a layout of a customized IP core according to the configuration parameters input by the user; the customized IP core includes one or more of the following items: a customized POC IP core, a customized IO IP core, an IO IP core with power-on control, and a customized unit with power-on control; Generate an integrated cell library based on the layout of the customized IP core; Generating a layout of a customized POC IP core according to the configuration parameters input by the user includes: generating the customized POC IP core according to the configurable POC IP core and a first configuration parameter input by the user; generating a layout of the customized POC IP core based on the customized POC IP core; the first configuration parameter includes: a POC input threshold voltage; Generating a layout of a customized IO IP core according to the configuration parameters input by the user, comprising: generating the customized IO IP core according to the configurable IO IP core and second configuration parameters input by the user; generating a layout of the customized IO IP core based on the customized IO IP core, wherein the second configuration parameters include one or more of the following items: input high-level threshold voltage, input low-level threshold voltage, high-level output source current, low-level output sink current, and electrostatic discharge protection level; Generating a layout of an IO IP core with power-on control according to the configuration parameters input by the user, comprising: generating the IO IP core with power-on control according to the IO IP core and the configurable POC IP core and a third configuration parameter input by the user; generating a layout of the IO IP core with power-on control based on the IO IP core with power-on control; the third configuration parameter comprising one or more of the following items: a POC input threshold voltage, an input high-level threshold voltage, an input low-level threshold voltage, a high-level output source current, a low-level output sink current, and an electrostatic discharge protection level; Generating a layout of a custom unit with power-on control according to the configuration parameters input by the user includes: generating the custom unit with power-on control according to the POC IP core and the standard cell module; generating a layout of the custom unit with power-on control based on the custom unit with power-on control; when the POC IP core is a customized POC IP core, generating the custom unit with power-on control according to the POC IP core and the standard cell module includes: generating the custom unit with power-on control according to the customized POC IP core and the standard cell module and the first configuration parameters.

2. The method according to claim 1, characterized in that The generating of an integrated cell library based on the layout of the customized IP core includes: Verify the layout of the customized IP core, including: design rule check (DRC) and layout and schematic comparison (LVS); Generating post-simulation netlist data of the layout of the customized IP core; the post-simulation netlist data is used to describe the circuit structure and connection relationship of the layout of the customized IP core; Verifying the post-simulation netlist data to ensure that it is consistent with the layout of the customized IP core; Inputting the post-simulation netlist data into a pre-provided Tcl script file, and adding attribute parameters related to the customized IP core in the Tcl script file, wherein the attribute parameters include one or more of the following items: function description, area, pin information, delay, and power consumption; Generate a model file according to the Tcl script file, and verify the model file to ensure that the model file can correctly simulate the behavior of the customized IP core, the model file including: a Verilog model file or a VHDL model file; Perform post-simulation verification using the model file; An integrated unit library is generated based on the model file using a library file generation tool.

3. The method according to claim 2, characterized in that The method further includes: verifying the integrated cell library.

4. The method according to claim 2, characterized in that The post-simulation netlist data of the layout of the customized IP core is generated, including: Extracting parasitic parameters from the layout of the custom IP core using a layout extraction tool; the parasitic parameters include resistance, capacitance, and inductance; Obtaining pre-simulation netlist data of the layout of the customized IP core; The parasitic parameters are added to the pre-simulation netlist data to generate post-simulation netlist data of the layout of the customized IP core including the parasitic parameters.

5. The method according to claim 2, characterized in that The method of using a library file generation tool to generate an integrated unit library based on the model file includes: Select the model file; Configuring properties of the integrated unit library, the properties of the integrated unit library including: library name, version, and description; Execute the command or operation for generating the library file in the library file generating tool.

6. The method according to claim 1, wherein Generating the customized POC IP core according to the configurable POC IP core and the first configuration parameter input by the user includes: Obtain a configurable POC IP core, wherein the configurable POC IP core includes: a POC core circuit module and a POC input threshold voltage adjustable module; Obtaining a POC input threshold voltage input by a user through the plurality of customized input boxes; Configuring the POC input threshold voltage adjustable module according to the POC input threshold voltage, the POC input threshold voltage adjustable module including a first MOS module group, configuring the POC input threshold voltage adjustable module according to the POC input threshold voltage includes: selecting a number of MOS modules corresponding to the POC input threshold voltage from the first MOS module group and connecting the selected MOS modules to generate a configured POC input threshold voltage adjustable module, the configured POC input threshold voltage adjustable module being used to generate a POC first control signal of the POC core circuit module; Connecting the POC core circuit module and the configured POC input threshold voltage adjustable module to generate a customized POC IP core, wherein the customized POC IP core is used to generate a POC control signal; The POC core circuit module includes: a POC first control signal input port and a POC control signal output port; the configured POC input threshold voltage adjustable module includes: a POC first control signal output port; the POC core circuit module and the configured POC input threshold voltage adjustable module also include: a power supply voltage port and a ground port; The power supply voltage ports of the POC core circuit module and the configured POC input threshold voltage adjustable module are both connected to the first power supply and the second power supply, and the ground ports of the POC core circuit module and the configured POC input threshold voltage adjustable module are both grounded; The POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to the POC first control signal input port of the POC core circuit module, for providing a reference voltage to the POC core circuit module; the POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to a MOS module selected from the first MOS module group.

7. The method according to claim 6, characterized in that The POC input threshold voltage adjustable module further includes: a resistance module group; Configuring the POC input threshold voltage adjustable module according to the POC input threshold voltage further includes: selecting resistor modules with a number and resistance value corresponding to the POC input threshold voltage from the resistor module group and connecting the selected MOS modules and resistor modules to generate the configured POC input threshold voltage adjustable module.

8. The method according to claim 7, characterized in that The method further includes: performing resistance subdivision adjustment on the configured POC input threshold voltage adjustable module, including: adjusting the resistance value or connection mode of the resistors in the configured POC input threshold voltage adjustable module, or adjusting the number of resistors in the configured POC input threshold voltage adjustable module, so as to achieve resistance subdivision adjustment on the configured POC input threshold voltage adjustable module; wherein the connection mode includes: series connection, parallel connection, or a series-parallel mixed mode.

9. The method according to claim 1, characterized in that Generating the customized IO IP core according to the configurable IO IP core and the second configuration parameter input by the user includes: Obtain a configurable IO IP core, the configurable IO IP core including an IO core circuit module, an input threshold adjustable module, and an output current and electrostatic discharge protection level adjustable module, the input threshold adjustable module including a second MOS module group, the output current and electrostatic discharge protection level adjustable module including a plurality of unit output current and electrostatic discharge protection level adjustable modules, and the unit output current and electrostatic discharge protection level adjustable module including a plurality of MOS modules; Obtaining, through the multiple custom input boxes, the input threshold high level voltage, input threshold low level voltage, high level output source current, low level output sink current, and electrostatic discharge protection level input by the user for the specified pin module of the customized IO IP core; Configuring the input threshold adjustable module according to the input threshold high level voltage and the input threshold low level voltage, including: selecting a MOS module from the second MOS module group according to the input threshold high level voltage and the input threshold low level voltage and connecting the selected MOS module to generate a configured input threshold adjustable module, wherein the configured input threshold adjustable module is used to generate an IO first control signal of the IO core circuit module; Configuring the output current and electrostatic release protection level adjustable module according to the high-level output source current, the low-level output sink current, and the electrostatic release protection level, including: selecting one or more unit output current and electrostatic release protection level adjustable modules from the output current and electrostatic release protection level adjustable modules according to the electrostatic release protection level, and connecting the selected one or more unit output current and electrostatic release protection level adjustable modules to generate a primary configured output current and electrostatic release protection level adjustable module, wherein the primary configured output current and electrostatic release protection level adjustable module includes a third MOS module group; selecting a MOS module from the third MOS module group according to the high-level output source current and the low-level output sink current, and connecting the selected MOS modules to generate a configured output current and electrostatic release protection level adjustable module, wherein the configured output current and electrostatic release protection level adjustable module is used to provide a specified electrostatic release protection capability corresponding to the electrostatic release protection level and provide a specified output current capability under the control of an IO second control signal of the IO core circuit module; Connecting the IO core circuit module, the configured input threshold adjustable module, and the configured output current and electrostatic discharge protection level adjustable module to generate a designated pin module of the customized IO IP core; The IO core circuit module includes: a power supply voltage port, a ground port, an IO first control signal input port, and an IO second control signal output port; the configured input threshold adjustable module includes: a power supply voltage port, a ground port, and an IO first control signal output port; the configured output current and electrostatic discharge protection level adjustable module includes: a power supply voltage port, a ground port, and an IO second control signal input port; The power supply voltage ports of the IO core circuit module, the configured input threshold adjustable module, and the configured output current and electrostatic discharge protection level adjustable module are all connected to the power supply voltage, and the ground ports are all grounded; The IO first control signal output port of the configured input threshold adjustable module is connected to the MOS module selected from the second MOS module group, and the IO first control signal output port of the configured input threshold adjustable module is connected to the IO first control signal input port of the IO core circuit module, for providing the IO first control signal to the IO core circuit module; The IO second control signal output port of the IO core circuit module is connected to the IO second control signal input port of the configured output current and electrostatic discharge protection level adjustable module, and is used to output the IO second control signal to the configured output current and electrostatic discharge protection level adjustable module based on the IO first control signal and the IO input signal; The second control signal input port of the IO of the configured output current and electrostatic discharge protection level adjustable module is connected to a MOS module selected from the third MOS module group; wherein, in the third MOS module group, the selected MOS module provides a first electrostatic discharge protection capability and the specified output current capability, and the remaining MOS modules provide a second electrostatic discharge protection capability, and the first electrostatic discharge protection capability and the second electrostatic discharge protection capability together constitute the specified electrostatic discharge protection capability; Based on the designated pin module of the customized IO IP core, a first designated pin circuit layout of the customized IO IP core is generated.

10. The method according to claim 9, characterized in that The IO second control signal input port of the configured output current and electrostatic discharge protection level adjustable module is connected to a MOS module selected from the second MOS module group, including: in any unit output current and electrostatic discharge protection level adjustable module of the configured output current and electrostatic discharge protection level adjustable module: All MOS modules in any unit electrostatic discharge protection module are connected to the second control signal input port of the IO of any unit electrostatic discharge protection module, and all connected MOS modules provide unit electrostatic discharge protection capability and unit output current capability at the same time; Alternatively, some MOS modules in any one of the unit electrostatic discharge protection modules are connected to the IO second control signal input port of any one of the unit electrostatic discharge protection modules, and the connected part of the MOS modules simultaneously provide corresponding electrostatic discharge protection capabilities and output current capabilities, and the remaining MOS modules provide corresponding electrostatic discharge protection capabilities; Alternatively, all MOS modules in any unit electrostatic release protection module are disconnected from the IO second control signal input port of any unit electrostatic release protection module, and all disconnected MOS modules provide unit electrostatic release protection capability.

11. The method according to claim 10, characterized in that When some MOS modules in any one unit electrostatic release protection module are connected to the IO second control signal input port of any one unit electrostatic release protection module, in the remaining MOS modules of any one unit electrostatic release protection module: the gates of some MOS modules are connected to the power supply voltage through the power supply voltage port, and the gates of other MOS modules are grounded through the ground port; When all MOS modules in any unit electrostatic release protection module are disconnected from the IO second control signal input port of any unit electrostatic release protection module, among all MOS modules in any unit electrostatic release protection module: the gates of some MOS modules are connected to the power supply voltage through the power supply voltage port, and the gates of other MOS modules are grounded through the ground port.

12. The method according to claim 11, characterized in that The gates of a part of the MOS modules are connected to the power supply voltage through the power supply voltage port, and the gates of another part of the MOS modules are grounded through the ground port, comprising: The gates and sources of a part of the MOS modules are short-circuited and then connected to the power supply voltage through the power supply voltage port, and the gates and sources of another part of the MOS modules are short-circuited and then grounded through the ground port.

13. The method according to claim 10, characterized in that When some MOS modules in any one unit electrostatic release protection module are connected to the IO second control signal input port of any one unit electrostatic release protection module, in the remaining MOS modules of any one unit electrostatic release protection module: the gates of some MOS modules are connected to the power supply voltage through the resistor module and the power supply voltage port, and the gates of other MOS modules are grounded through the resistor module and the ground port; When all the MOS modules in any one of the unit electrostatic release protection modules are disconnected from the IO second control signal input port of any one of the unit electrostatic release protection modules, among all the MOS modules in any one of the unit electrostatic release protection modules: the gates of some of the MOS modules are connected to the power supply voltage through the resistance module and the power supply voltage port, and the gates of other part of the MOS modules are grounded through the resistance module and the ground port.

14. The method according to claim 13, characterized in that The gates of a part of the MOS modules are connected to the power supply voltage through the resistance module and the power supply voltage port, and the gates of another part of the MOS modules are grounded through the resistance module and the ground port, comprising: The gates and sources of a part of the MOS modules are short-circuited and connected to the power supply voltage through the resistance module and the power supply voltage port, and the gates and sources of the other part of the MOS modules are short-circuited and grounded through the resistance module and the ground port.

15. The method according to claim 1, wherein The step of generating the IO IP core with power-on control according to the IO IP core, the configurable POC IP core, and the third configuration parameter input by the user includes: Obtain a configurable POC IP core, wherein the configurable POC IP core includes: a POC core circuit module and a POC input threshold voltage adjustable module; Get IO IP core; Obtaining a POC input threshold voltage input by a user through the plurality of customized input boxes; Configuring the POC input threshold voltage adjustable module according to the POC input threshold voltage, the POC input threshold voltage adjustable module including a first MOS module group, configuring the POC input threshold voltage adjustable module according to the POC input threshold voltage includes: selecting a number of MOS modules corresponding to the POC input threshold voltage from the first MOS module group and connecting the selected MOS modules to generate a configured POC input threshold voltage adjustable module, the configured POC input threshold voltage adjustable module being used to generate a POC first control signal of the POC core circuit module; Connecting the POC core circuit module and the configured POC input threshold voltage adjustable module to generate a customized POC IP core, wherein the customized POC IP core is used to generate a POC control signal; Connecting the customized POC IP core and the IO IP core to generate an IO IP core with power-on control; wherein the POC core circuit module includes: a POC first control signal input port and a POC control signal output port; the configured POC input threshold voltage adjustable module includes: a POC first control signal output port; the IO IP core includes: a POC control signal input port; the IO IP core, the POC core circuit module and the configured POC input threshold voltage adjustable module also include: a power supply voltage port and a ground port; The power supply voltage ports of the IO IP core, the POC core circuit module, and the configured POC input threshold voltage adjustable module are all connected to a first power supply and a second power supply, and the ground ports of the IO IP core, the POC core circuit module, and the configured POC input threshold voltage adjustable module are all grounded; The POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to the POC first control signal input port of the POC core circuit module, for providing the POC first control signal to the POC core circuit module; the POC first control signal output port of the configured POC input threshold voltage adjustable module is connected to a MOS module selected from the first MOS module group; The POC control signal output port of the POC core circuit module is connected to the POC control signal input port of the IO IP core, so that the IO IP core controls the output of its own current through the POC control signal output by the customized POC IP core.

16. The method according to claim 15, characterized in that The IO IP core controls the output of its own current through the POC control signal output by the customized POC IP core, including: When either the first power supply or the second power supply is powered off, the POC control signal output by the customized POC IP core is at a low level; when the POC control signal is at a low level, the IO IP core controls itself to not output current and enters a high-impedance state; When the first power supply and the second power supply are fully powered on, the POC control signal output by the customized POC IP core is at a high level; when the POC control signal is at a high level, the IO IP core controls its own normal output current.

17. The method according to claim 15, characterized in that The IO IP core is a customized IO IP core, and obtaining the IO IP core includes: Obtain a configurable IO IP core, the configurable IO IP core including an IO core circuit module, an input threshold adjustable module, and an output current and electrostatic discharge protection level adjustable module, the input threshold adjustable module including a second MOS module group, the output current and electrostatic discharge protection level adjustable module including a plurality of unit output current and electrostatic discharge protection level adjustable modules, and the unit output current and electrostatic discharge protection level adjustable module including a plurality of MOS modules; Obtaining, through the multiple custom input boxes, the input threshold high level voltage, input threshold low level voltage, high level output source current, low level output sink current, and electrostatic discharge protection level input by the user for the specified pin module of the customized IO IP core; Configuring the input threshold adjustable module according to the input threshold high level voltage and the input threshold low level voltage, including: selecting a MOS module from the second MOS module group according to the input threshold high level voltage and the input threshold low level voltage and connecting the selected MOS module to generate a configured input threshold adjustable module, wherein the configured input threshold adjustable module is used to generate an IO first control signal of the IO core circuit module; Configuring the output current and electrostatic release protection level adjustable module according to the high-level output source current, the low-level output sink current, and the electrostatic release protection level, including: selecting one or more unit output current and electrostatic release protection level adjustable modules from the output current and electrostatic release protection level adjustable modules according to the electrostatic release protection level, and connecting the selected one or more unit output current and electrostatic release protection level adjustable modules to generate a primary configured output current and electrostatic release protection level adjustable module, wherein the primary configured output current and electrostatic release protection level adjustable module includes a third MOS module group; selecting a MOS module from the third MOS module group according to the high-level output source current and the low-level output sink current, and connecting the selected MOS modules to generate a configured output current and electrostatic release protection level adjustable module, wherein the configured output current and electrostatic release protection level adjustable module is used to provide a specified electrostatic release protection capability corresponding to the electrostatic release protection level and provide a specified output current capability under the control of an IO second control signal of the IO core circuit module; Connecting the IO core circuit module, the configured input threshold adjustable module, and the configured output current and electrostatic discharge protection level adjustable module to generate a designated pin module of the customized IO IP core; The IO core circuit module includes: a power supply voltage port, a ground port, an IO first control signal input port, and an IO second control signal output port; the configured input threshold adjustable module includes: a power supply voltage port, a ground port, and an IO first control signal output port; the configured output current and electrostatic discharge protection level adjustable module includes: a power supply voltage port, a ground port, and an IO second control signal input port; The power supply voltage ports of the IO core circuit module, the configured input threshold adjustable module, and the configured output current and electrostatic discharge protection level adjustable module are all connected to the power supply voltage, and the ground ports are all grounded; The IO first control signal output port of the configured input threshold adjustable module is connected to the MOS module selected from the second MOS module group, and the IO first control signal output port of the configured input threshold adjustable module is connected to the IO first control signal input port of the IO core circuit module, for providing the IO first control signal to the IO core circuit module; The IO second control signal output port of the IO core circuit module is connected to the IO second control signal input port of the configured output current and electrostatic discharge protection level adjustable module, and is used to output the IO second control signal to the configured output current and electrostatic discharge protection level adjustable module based on the IO first control signal and the IO input signal; The IO second control signal input port of the configured output current and electrostatic release protection level adjustable module is connected to a MOS module selected from the third MOS module group; wherein, in the third MOS module group, the selected MOS module provides a first electrostatic release protection capability and the specified output current capability, and the remaining MOS modules provide a second electrostatic release protection capability, and the first electrostatic release protection capability and the second electrostatic release protection capability together constitute the specified electrostatic release protection capability.

18. The method according to claim 17, characterized in that The IO IP core controls the output of its own current through the POC control signal output by the customized POC IP core, including: The IO core circuit module obtains the POC control signal through the POCIO second control signal input port; generating a current control signal according to the POC control signal, and sending the current control signal to the configured output current and electrostatic discharge protection level adjustable module; The configured output current and electrostatic discharge protection level adjustable module controls the output current of the IO IP core according to the current control signal.

19. The method according to claim 1, wherein Generating the customized unit with power-on control according to the POC IP core and the standard unit module includes: Obtain a POC IP core; the POC IP core includes: a first power input terminal, a second power input terminal and a control signal output terminal; Obtain a standard cell module; the standard cell module includes: a first logic control signal input terminal, a second logic control signal input terminal, a power input terminal and a cell signal output terminal; Connecting the POC IP core and the standard cell module to generate a custom cell with power-on control; wherein the first logic control signal input terminal of the standard cell module is connected to a first power circuit module powered by a first power supply, so that the standard cell module obtains a first logic control signal through the first power circuit module; the second logic control signal input terminal of the standard cell module is connected to a second power circuit module powered by a second power supply, so that the standard cell module obtains a second logic control signal through the second power circuit module; and the power input terminal of the standard cell module is connected to a power supply; The first power input terminal of the POC IP core is connected to the first power supply, and the second power input terminal of the POC IP core is connected to the second power supply, so that the POC IP core obtains the voltage status of the first power supply and the second power supply, and generates a first control signal according to the voltage status of the first power supply and the second power supply; The control signal output terminal of the POC IP core is connected to the standard cell module, so that the POC IP core outputs the first control signal to the standard cell module through the control signal output terminal, so as to control whether the standard cell module outputs normally through the first control signal; The obtaining of the voltage status of the first power supply and the second power supply includes: Comparing a current voltage value of the first power supply with a preset first power-on threshold voltage, and when the current voltage value of the first power supply is not lower than the preset first power-on threshold voltage, the voltage state of the first power supply is a power-on state; comparing a current voltage value of the second power supply with a preset second power-on threshold voltage, and when the current voltage value of the second power supply is not lower than the preset second power-on threshold voltage, determining that the voltage state of the second power supply is a power-on state; Generating a first control signal according to voltage states of the first power supply and the second power supply includes: When the voltage state of the first power supply and the voltage state of the second power supply are both in the power-on state, the first control signal is at a high level; otherwise, the first control signal is at a low level.

20. The method according to claim 19, characterized in that The method further comprises: Obtain a first switch control circuit module; wherein the first switch control circuit module includes: a first input terminal, a second input terminal, and an output terminal; The power input terminal of the standard cell module is connected to a power supply, and the control signal output terminal of the POC IP core is connected to the standard cell module, including: the power supply is connected to the power input terminal of the standard cell module through the first switch control circuit module, and the control signal output terminal of the POC IP core is connected to the standard cell module through the first switch control circuit module, including: the power supply is connected to the first input terminal of the first switch control circuit module, the control signal output terminal of the POC IP core is connected to the second input terminal of the first switch control circuit module, and the output terminal of the first switch control circuit module is connected to the power input terminal of the standard cell module, so that the first switch control circuit module generates a second control signal according to the first control signal and uses the second control signal to control the connection or disconnection of the power supply, so that when the power supply is disconnected, the standard cell module stops processing the first logic control signal and the second logic control signal, so that the standard cell module has no output; and when the power supply is connected, the standard cell module resumes processing the first logic control signal and the second logic control signal, so that the standard cell module has normal output; The step of generating a second control signal according to the first control signal and controlling the power supply to be turned on or off by using the second control signal includes: When the first control signal is at a high level, the second control signal is a closing signal, and the closing signal closes the output end of the first switch control circuit module; When the first control signal is at a low level, the second control signal is a disconnection signal, and the disconnection signal disconnects the output end of the first switch control circuit module; When the output end of the first switch control circuit module is closed, the power supply is turned on; When the output end of the first switch control circuit module is disconnected, the power supply is cut off.

21. The method according to claim 19, wherein The method further comprises: Obtain a second switch control circuit module; wherein the second switch control circuit module includes: a signal input terminal and a signal output terminal; The control signal output terminal of the POC IP core is connected to the standard cell module, including: The control signal output terminal of the POC IP core is connected to the signal input terminal of the second switch control circuit module; the signal output terminal of the second switch control circuit module is connected to the cell signal output terminal of the standard cell module, so that the second switch control circuit module generates a third control signal according to the first control signal, and uses the third control signal to control the connection or disconnection of the output of the standard cell module, so that when the output of the standard cell module is disconnected, the standard cell module has no output; and when the output of the standard cell module is connected, the standard cell module outputs normally; The step of generating a third control signal according to the first control signal and using the third control signal to control the connection or disconnection of the output of the standard cell module includes: When the first control signal is at a high level, the third control signal is a closing signal, and the closing signal connects the cell signal output terminal of the standard cell module; When the first control signal is at a low level, the third control signal is a disconnection signal, and the disconnection signal cuts off the cell signal output end of the standard cell module; When the cell signal output terminal of the standard cell module is turned on, the output of the standard cell module is turned on; When the cell signal output terminal of the standard cell module is cut off, the output of the standard cell module is cut off.

22. The method according to claim 19, wherein The standard unit module further includes: a control signal input terminal; The control signal output terminal of the POC IP core is connected to the standard cell module, comprising: connecting the control signal output terminal of the POC IP core to the control signal input terminal of the standard cell module, so that the standard cell module controls whether to output itself according to the first control signal; The standard unit module controls whether to output itself according to the first control signal, including: When the first control signal is at a high level, the output of the standard cell module is turned on, and the standard cell module outputs normally; When the first control signal is at a low level, the output of the standard cell module is cut off, and the standard cell module has no output.

23. The method according to claim 19, wherein The POC IP core is a customized POC IP core; the customized POC IP core is configurable, including: the preset first power-on threshold voltage is a first power-on threshold voltage input by a user, and the preset second power-on threshold voltage is a second power-on threshold voltage input by a user; or, The POC IP core is a default POC IP core; the default POC IP core is non-configurable, including: the preset first power-on threshold voltage and the preset second power-on threshold voltage are both preset fixed values; The default POC IP core includes: a connected POC IP core circuit module and a default threshold voltage module, wherein the default threshold voltage module includes MOS modules corresponding to the preset first power-on threshold voltage and the preset second power-on threshold voltage.

24. A method for digitizing an integrated cell library, characterized in that: The method is implemented based on a customized EDA tool, wherein the customized EDA tool integrates an integrated cell library generated using the method according to any one of claims 1 to 23, wherein the integrated cell library includes basic standard cells and customized IP cells corresponding to customized IP cores, wherein the customized IP cores include one or more of the following: a customized POC IP core, a customized IO IP core, an IO IP core with power-on control, and a customized cell with power-on control, wherein the method includes: Obtaining RTL code for calling the basic standard cell and / or the custom IP cell corresponding to the custom IP core, wherein the RTL code includes an instance of a hardware description language module describing the basic standard cell and / or an instance of a hardware description language module describing the custom IP cell; converting the RTL code into a gate-level netlist using a synthesizer; Importing the synthesized gate-level netlist into a place-and-route tool; Performing physical layout and routing based on the gate-level netlist to generate layout and routing data; performing physical layout and routing based on the gate-level netlist includes: selectively placing the custom IP units and the basic standard units, and generating connections between the custom IP units and / or between the basic standard units and / or between the custom IP units and the basic standard units.

25. The method according to claim 24, characterized in that The method further comprises: The layout and routing data is verified, and the verification includes one or more of the following items: design rule check (DRC), layout and schematic comparison (LVS), and electrical rule check (ERC).

26. The method according to claim 24, characterized in that The method further comprises: Manufacturing data is generated according to the layout and routing data, and the manufacturing data includes: a GDSII file and a manufacturing mask.

27. A device for generating an integrated cell library, characterized in that: The device is implemented based on a customized EDA tool, which provides a GUI interface. The GUI interface includes multiple customized input boxes, which are used to obtain configuration parameters input by a user. The device includes: A customized IP layout generation module is configured to generate a layout of a customized IP core according to the configuration parameters input by the user; the customized IP layout includes one or more of the following items: a layout of a customized POC IP core, a layout of a customized IO IP core, and a layout of an IO IP core with power-on control; an integrated cell library generation module, configured to generate an integrated cell library based on the layout of the customized IP core; Generating a layout of a customized POC IP core according to the configuration parameters input by the user includes: generating the customized POC IP core according to the configurable POC IP core and a first configuration parameter input by the user; generating a layout of the customized POC IP core based on the customized POC IP core; the first configuration parameter includes: a POC input threshold voltage; Generating a layout of a customized IO IP core according to the configuration parameters input by the user, comprising: generating the customized IO IP core according to the configurable IO IP core and second configuration parameters input by the user; generating a layout of the customized IO IP core based on the customized IO IP core, wherein the second configuration parameters include one or more of the following items: input high-level threshold voltage, input low-level threshold voltage, high-level output source current, low-level output sink current, and electrostatic discharge protection level; Generating a layout of an IO IP core with power-on control according to the configuration parameters input by the user, comprising: generating the IO IP core with power-on control according to the IO IP core and the configurable POC IP core and a third configuration parameter input by the user; generating a layout of the IO IP core with power-on control based on the IO IP core with power-on control; the third configuration parameter comprising one or more of the following items: a POC input threshold voltage, an input high-level threshold voltage, an input low-level threshold voltage, a high-level output source current, a low-level output sink current, and an electrostatic discharge protection level; Generating a layout of a custom unit with power-on control according to the configuration parameters input by the user includes: generating the custom unit with power-on control according to the POC IP core and the standard cell module; generating a layout of the custom unit with power-on control based on the custom unit with power-on control; when the POC IP core is a customized POC IP core, generating the custom unit with power-on control according to the POC IP core and the standard cell module includes: generating the custom unit with power-on control according to the customized POC IP core and the standard cell module and the first configuration parameters.

28. A digital device for an integrated cell library, characterized in that: The digitization device is implemented based on a customized EDA tool, wherein the customized EDA tool integrates an integrated cell library generated using the method according to any one of claims 1 to 23, wherein the integrated cell library includes basic standard cells and customized IP cells corresponding to customized IP cores, wherein the customized IP cores include one or more of the following: a customized POC IP core, a customized IO IP core, an IO IP core with power-on control, and a customized cell with power-on control. The digitization device includes: an RTL code acquisition module configured to acquire RTL code for calling the basic standard cell and / or the customized IP cell, wherein the RTL code includes an instance of a hardware description language module describing the basic standard cell and / or an instance of a hardware description language module describing the customized IP cell; a gate-level netlist generation module configured to convert the RTL code into a gate-level netlist using a synthesizer; a gate-level netlist import module configured to import the synthesized gate-level netlist into a place-and-route tool; A layout and routing data generation module is configured to perform physical layout and routing based on the gate-level netlist and generate layout and routing data; the physical layout and routing based on the gate-level netlist includes: selectively placing the custom IP units and the basic standard units, and generating connections between the custom IP units and / or between the basic standard units and / or between the custom IP units and the basic standard units.

29. The digitizing device according to claim 28, characterized in that The digitizing device further comprises: The layout and routing data verification module is configured to verify the layout and routing data, wherein the verification includes one or more of the following items: design rule check (DRC), layout and schematic comparison (LVS), and electrical rule check (ERC).

30. The digitizing device according to claim 28, wherein: The digitizing device further comprises: The manufacturing data generating module is configured to generate manufacturing data according to the layout and routing data, wherein the manufacturing data includes: a GDSII file and a manufacturing mask.

31. A chip, characterized in that: The chip is manufactured using library cells in an integrated cell library generated by the method according to any one of claims 1 to 23, wherein the library cells include basic standard cells and customized IP cells corresponding to customized IP cores, and the customized IP cores include one or more of the following items: a customized POC IP core, a customized IO IP core, an IO IP core with power-on control, and a customized cell with power-on control.

32. An electronic device, characterized in that: Comprising the chip according to claim 31.

33. A computer-readable storage medium having computer instructions stored thereon, characterized in that: When the computer instructions are executed by a processor, the method according to any one of claims 1 to 23 is implemented.

34. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the method according to any one of claims 1 to 23 is implemented.

Images