A neural network training method applicable to the hardware deployment of memristive neuromorphic chips

Abstract

The present invention discloses a neural network training method applicable to the hardware deployment of memristive neuromorphic chips. In the training stage, the present invention extracts the equivalent circuit of the crossbar array by the partial element equivalent circuit method, and integrates the time-domain transient simulation solution process of the equivalent circuit of the crossbar array into the gradient propagation, enabling the network to learn and adapt to the output characteristics of the crossbar array during the training process; further, a weight threshold-based unstructured dynamic pruning method is introduced, effectively reducing the proportion of memristors in the low-resistance state, suppressing sneak paths in the crossbar array while reducing the operating cost of the crossbar array. Compared with traditional training methods, the method provided by the present invention can significantly enhance the stability and accuracy of the neural network during hardware deployment, and has wide applicability, and can be used for the neural network training and deployment optimization of various advanced memory devices.

Description

Technical Field

[0001] The present invention relates to an offline training method in the field of brain-inspired chips, specifically a neural network training method suitable for hardware deployment of memristive brain-inspired chips. Background Art

[0002] The brain-inspired chip is proposed to overcome the "memory wall" bottleneck of the traditional von Neumann circuit architecture and solve the problem that traditional chips cannot meet the requirements of the artificial intelligence industry for chip performance and computing power. The memristive brain-inspired chip is a main circuit architecture of the brain-inspired chip. It uses the emerging electronic device memristor to simulate artificial neural synapses and uses cross-interconnect lines as signal transmission channels to realize the simulation of human brain computing with memory and computing integrated.

[0003] The memristive brain-inspired chip has advantages such as simple structure, high device density, and low manufacturing cost. However, there are signal integrity problems such as sneak paths, resistance voltage drops, and parasitic effects in its hardware implementation, which often lead to poor signal transmission quality. However, traditional neural network training methods ignore such non-ideal characteristics in the hardware implementation process. When deploying traditional training methods to actual memristive brain-inspired chips, the model performance is often greatly reduced due to ignoring these non-ideal factors.

[0004] Currently, some researchers have reduced the impact of these circuit non-ideal characteristics on the performance of neural networks by adjusting the architecture of neural networks or optimizing algorithms, such as by increasing the redundancy of the network or using fault-tolerant training algorithms. However, such methods usually lead to an increase in computational complexity and computational resources, and often require a compromise between the accuracy and efficiency of the model.

[0005] Therefore, there is a need to develop a neural network training method more suitable for hardware deployment of memristive brain-inspired chips. Summary of the Invention

[0006] Aiming at the deficiencies of the existing brain-inspired chip training methods, the present invention provides a neural network training method suitable for hardware deployment of memristive brain-inspired chips. The present invention takes into account the non-ideal circuit factors in the memristor cross array during the training stage, and reduces the performance loss during the deployment process by combining the non-ideal characteristics of the hardware circuit and the dynamic pruning strategy. Compared with the traditional method, the method proposed by the present invention can significantly improve the performance of the neural network when deployed on the hardware of the memristive brain-inspired chip.

[0007] The technical method of the present invention is as follows:

[0008] 1. A neural network training method suitable for hardware deployment of memristive brain-inspired chips

[0009] Step 1: Construct an equivalent circuit of the neuromorphic memristor cross array;

[0010] Step 2: Encode each sample in the training set into a voltage vector and send it into the equivalent circuit of the neuromorphic memristor crossbar array. Then, obtain the voltage and current signals output by the neuromorphic memristor crossbar array through circuit simulation. Calculate the loss function based on the voltage and current signals output by the neuromorphic memristor crossbar array and complete the backpropagation of the gradient.

[0011] Step 3: After the backpropagation of the gradient is completed, use the dynamic pruning method to increase the sparsity of the network weights in the neuromorphic memristor crossbar array, and then update the network weights.

[0012] Step 4: Based on the updated network weights, repeat Step 2 and Step 3, and continuously train the neuromorphic memristor crossbar array using the remaining samples in the training set until the loss function converges, completing the training of the neural network.

[0013] In the above Step 1, use the partial element equivalent circuit method to construct the equivalent circuit of the neuromorphic memristor crossbar array, which specifically includes the following steps:

[0014] First, divide the neuromorphic memristor crossbar array into multiple basic units; then, calculate the equivalent resistance of each basic unit; then, construct an equivalent inductance model; finally, extract the equivalent capacitance of each basic unit to obtain the equivalent circuit of the neuromorphic memristor crossbar array.

[0015] The obtaining of the voltage and current signals output by the neuromorphic memristor crossbar array through circuit simulation includes:

[0016] First, calculate the steady-state value output of the neuromorphic memristor crossbar array, and then jointly determine the steady-state moment of the network output based on the steady-state value output and the dynamic time-domain simulation of the crossbar array. Then, calculate the steady-state output values corresponding to the voltage and current of the neuromorphic memristor crossbar array from the circuit equations of the connection matrix A and the resistance matrix R of the equivalent circuit. The calculation formula is as follows:

[0017]

[0018] where, V s and I s are the solved steady-state node voltage and branch current respectively, V r represents the read voltage applied to the neuromorphic memristor crossbar array, X i represents the input voltage vector, ⊙ represents the Hadamard product, and T represents the transpose;

[0019] Finally, after simulating the time-domain waveform of the circuit through the partial element equivalent circuit method, obtain the transient output values corresponding to the voltage and current of the neuromorphic memristor crossbar array. The formula is as follows:

[0020]

[0021] Among them, V n represents the node voltage at the nth moment, and I n represents the branch current at the nth moment, M U , M L and M P respectively represent the upper triangular matrix, lower triangular matrix, and permutation matrix obtained after the LU decomposition of the circuit structure matrix.

[0022] Calculating the loss function and completing the backpropagation of the gradient based on the voltage and current signals output by the neuromorphic memristor crossbar array includes:

[0023] Based on the voltage and current signals output by the neuromorphic memristor crossbar array, obtaining the true response S xbar of the neuromorphic memristor crossbar array and the ideal response S ideal ; then using the following formula to calculate the modified network response S:

[0024] S = S ideal +(S xbar -S ideal )·(1-β epoch )

[0025] where β is the adjustment factor and epoch is the number of training rounds.

[0026] Increasing the sparsity of the network weights in the neuromorphic memristor crossbar array by using the dynamic pruning method includes:

[0027] By adjusting the pruning ratio to control the high-resistance state ratio of the memristors in the neuromorphic memristor crossbar array, so as to increase the sparsity of the network weights. The formula is as follows:

[0028]

[0029] where W(i,j) and Wpruned(i,j) respectively represent the weight values at position (i,j) in the weight matrix before pruning and the weight matrix after pruning, T r represents the pruning threshold, and || represents taking the absolute value.

[0030] II. A neural network training device suitable for hardware deployment of memristive brain-like chips

[0031] An equivalent circuit generation unit for constructing an equivalent circuit of a neuromorphic memristor crossbar array;

[0032] A circuit simulation unit, configured to encode each sample in a training set into a voltage vector and input it into an equivalent circuit of a neuromorphic memristor crossbar array, and obtain voltage and current signals output by the neuromorphic memristor crossbar array through circuit simulation;

[0033] A first training unit, configured to calculate a loss function and perform backpropagation of gradients according to the voltage and current signals output by the neuromorphic memristor crossbar array;

[0034] A second training unit, configured to increase the sparsity of network weights in the neuromorphic memristor crossbar array and update the network weights by using a dynamic pruning method.

[0035] III. A computer device

[0036] The device includes a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, the steps of the neural network training method applicable to hardware deployment of a memristive brain-like chip are implemented.

[0037] IV. A computer-readable storage medium

[0038] The medium stores a computer program, and when the computer program is executed by a processor, the steps of the neural network training method applicable to hardware deployment of a memristive brain-like chip are implemented.

[0039] V. A computer program product

[0040] The product includes a computer program / instructions, and when the computer program / instructions are executed by a processor, the steps of the neural network training method applicable to hardware deployment of a memristive brain-like chip are implemented.

[0041] The present invention models the crossbar array by using a partial element equivalent circuit method, trains the network by combining the ideal response and the actual response of the circuit, and suppresses the sneak paths in the crossbar array by using an unstructured dynamic pruning method. The training results can be imported and verified on a memristive brain-like chip.

[0042] Compared with the traditional brain-like chip training method, the method proposed by the present invention has the following beneficial effects:

[0043] 1. The dynamic pruning method of the present invention optimizes the structure of the neural network by adaptively adjusting the weight connections of the memristor network, reduces the proportion of low-resistance-state memristors in the inference process, and thus reduces the network operation cost.

[0044] 2. The present invention trains and optimizes by integrating the non-ideal circuit factors of the memristive brain-like chip during the neural network training process, and can significantly improve the stability and accuracy of the network during actual hardware deployment. Description of the Drawings

[0045] Figure 1 Schematic diagram of a neural network structure based on sparse pruning in an embodiment of the present invention;

[0046] Figure 2 Schematic diagram of a memristive brain-inspired chip used in an embodiment of the present invention;

[0047] Figure 3 Schematic diagram of the information embedding process of a crossbar array circuit in an embodiment of the present invention;

[0048] Figure 4 Diagram of an ideal test process and a simulation test flow based on an actual memristor;

[0049] Figure 5 3D schematic diagram of modeling the equivalent circuit of a crossbar array in the implementation of the present invention;

[0050] Figure 6 Comparison chart of recognition accuracy rates when the present invention and traditional training methods are deployed on an actual crossbar array. Specific implementation manners

[0051] To enable those skilled in the art to better understand the method of the present invention and to make the above-mentioned objects, features, and advantages of the present invention more clearly understandable, the present invention will be further described in detail below with reference to embodiments.

[0052] According to the inventive concept of the present invention, the complete implementation of the embodiment is as follows:

[0053] The task targeted in this example is handwritten digit recognition, and the dataset used is the large handwritten digit database (MNIST) collected and collated by the National Institute of Standards and Technology of the United States. Through computer preprocessing, there are 10,000 training set pictures in this dataset, and each picture consists of 28×28 binary pixels. Based on this dataset, the neural network training method applicable to memristive brain-inspired chips proposed in this example is implemented, and the effectiveness of the present invention is verified by comparing with the traditional training method that does not consider the non-ideal characteristics of the circuit. The three-layer network used is as Figure 1 shown, including an input layer, an output layer, and a classification layer of softmax respectively. The corresponding memristor-based brain-inspired chip is as Figure 2 shown, realizing the mapping from the input layer to the output layer in Figure 1 , that is, the core inference part of the network.

[0054] The training method proposed in the present invention, which combines an unstructured dynamic pruning strategy and integrates the non-ideal characteristics of the hardware circuit, is as Figure 3As shown in the figure. During the network training process, the present invention dynamically adjusts the connection weights according to the importance and activity of each neuron, that is, discards the smaller values in the weight matrix based on the set pruning ratio, and prunes the unimportant connections, thereby improving the sparsity and operation efficiency of the network. Further, the present invention corrects the gradient descent and backpropagation algorithms by combining the non-ideal circuit factors of the memristive brain-inspired chip during the training process, so that the neural network can adapt to the circuit characteristics during the learning process to adapt to and compensate for the non-ideal matrix multiplication characteristics of the memristive brain-inspired chip, and further improve the performance of the neural network deployed in the crossbar array.

[0055] The specific process of the method proposed by the present invention is as follows:

[0056] Step 1: The neuromorphic memristor crossbar array is composed of multiple memristors arranged in a row-column neural network chip architecture. Construct the equivalent circuit of the neuromorphic memristor crossbar array;

[0057] The partial element equivalent circuit method is an electromagnetic field numerical calculation technology based on circuit theory. It simplifies the model and significantly reduces the calculation time by discretizing the conductor into a series of discrete units and assigning circuit elements such as resistors, inductors, and capacitors to these discrete units to simulate electromagnetic effects. The partial element equivalent circuit method does not require discretization of the spatial medium, so it is particularly suitable for analyzing large-scale circuit systems with complex structures.

[0058] Construct the equivalent circuit of the neuromorphic memristor crossbar array by using the partial element equivalent circuit method, which specifically includes the following steps:

[0059] First, divide the dense but periodic neuromorphic memristor crossbar array into multiple basic units, as Figure 5 shown, which can significantly reduce the workload of extracting parasitic circuits;

[0060] Next, calculate the equivalent resistance of each basic unit. The calculation formula is:

[0061]

[0062] where R is the equivalent resistance value, ρ is the resistivity of the material, l is the conductor length, S is the conductor cross-sectional area.

[0063] Then, construct an equivalent inductance model; specifically, extract the self-inductance of the word line and bit line and the mutual inductance between adjacent word lines and bit lines respectively through the inductance analytical calculation formula. These inductance values reflect the induced voltage generated due to the magnetic field interaction when the current flows.

[0064] Finally, the equivalent capacitance of each basic unit is extracted to obtain the equivalent circuit of the neuromorphic memristor crossbar array. The extraction process of the equivalent capacitance of each basic unit is as follows:

[0065] The self-capacitances of the word line and the bit line, the mutual capacitances between adjacent word lines and bit lines, and the capacitance between the word line and the bit line are extracted respectively. The short-circuit capacitance matrix is quickly extracted by calculating the potential coefficient matrix, and then the capacitance values of each basic unit are obtained.

[0066] In the simulation, the modified nodal analysis method can be combined to perform transient simulation to verify the effectiveness of the proposed circuit model.

[0067] Step 2: Encode each sample in the training set into a voltage vector and send it into the equivalent circuit of the neuromorphic memristor crossbar array, and then perform time-domain simulation and steady-state value simulation through circuit simulation to obtain the voltage and current signals output by the neuromorphic memristor crossbar array. In the present invention, through circuit simulation, non-ideal factors such as sneak paths and resistance voltage drops in the memristor are integrated into the normal training and reverse gradient propagation processes of the network in the active training mode, allowing the network to adapt to and learn the output characteristics of the crossbar array during the training process; the loss function is calculated and the gradient is backpropagated based on the voltage and current signals output by the neuromorphic memristor crossbar array, and the cross-entropy loss function is used as the loss function;

[0068] Among them, performing time-domain simulation and steady-state value simulation through circuit simulation to obtain the voltage and current signals output by the neuromorphic memristor crossbar array includes:

[0069] First, calculate the steady-state value output of the neuromorphic memristor crossbar array, and then jointly determine the steady-state moment of the network output by combining the steady-state value output and the dynamic time-domain simulation of the crossbar array, in order to help the peripheral circuit read the moment n. The expression for determining the read moment of the memristor crossbar array through dynamic time-domain simulation and circuit steady-state value is:

[0070]

[0071] where I n and I s respectively represent the transient current value and the steady-state current value at the nth moment in the transient simulation of the crossbar array, ε represents the allowable error, and k is the number of sampling points required to determine convergence;

[0072] Then, the steady-state output values corresponding to the voltage and current of the neuromorphic memristor crossbar array are calculated from the circuit equations of the connection matrix A and the resistance matrix R of the equivalent circuit, and the calculation formula is as follows:

[0073]

[0074] Among them, V s and I s are respectively the steady-state node voltage and branch current to be solved, V r represents the read voltage applied to the neuromorphic memristor crossbar array, X i represents the input voltage vector, ⊙ represents the Hadamard product, and T represents the transpose.

[0075] Finally, the transient output values corresponding to the voltage and current of the neuromorphic memristor crossbar array are obtained after simulating the time-domain waveform of the circuit by the partial element equivalent circuit method, and the formula is as follows:

[0076]

[0077] Among them, V n represents the node voltage at the nth moment, I n represents the branch current at the nth moment, M U , M L and M P respectively represent the upper triangular matrix, lower triangular matrix, and permutation matrix obtained after LU decomposition of the circuit structure matrix. The circuit structure matrix is composed of the connection matrix A, resistance matrix R, inductance matrix L, and capacitance matrix C corresponding to the equivalent circuit, which respectively store the connection relationships between various nodes in the circuit, the resistance values of each resistor element, the inductance values of each inductor element, and the capacitance values of each capacitor element.

[0078] Based on the voltage and current signals output by the neuromorphic memristor crossbar array, the calculation of the loss function and the backpropagation of the gradient are carried out, including:

[0079] Based on the voltage and current signals output by the neuromorphic memristor crossbar array, the true response S of the neuromorphic memristor crossbar array is solved xbar (that is, the true crossbar simulation result obtained by circuit simulation) and the ideal response S ideal (that is, the ideal matrix multiplication result); then the corrected network response S (that is, the corrected matrix multiplication result) is calculated using the following formula:

[0080] S = f(S ideal， S xbar ) = S ideal + (S xbar - S ideal ), (1 - β epoch )

[0081] Among them, β is a regulation factor used to control the correction ratio; f(S ideal , S xbar ) is a correction function, and epoch is the number of training rounds.

[0082] Among them, the true response S of the neuromorphic memristor crossbar array xbar is obtained by performing a range reflection mapping on the matrix multiplication of the memristors for use in correcting the ideal matrix multiplication, and the formula is as follows:

[0083]

[0084] where G on and G o f f are the conductance values corresponding to the low-resistance state and high-resistance state of the memristor respectively, V r represents the read voltage, and I s is the steady-state current value.

[0085] The calculation method of the ideal response S ideal is as follows:

[0086] S ideal = W·X i

[0087] where W is the weight trained in the current batch, and X i represents the input voltage vector.

[0088] Step 3: After the backpropagation of the gradient is completed, use the dynamic pruning method to increase the sparsity of the network weights in the neuromorphic memristor crossbar array, and then update the network weights;

[0089] Among them, using the dynamic pruning method to increase the sparsity of the network weights in the neuromorphic memristor crossbar array includes:

[0090] By adjusting the pruning ratio to control the high-resistance state ratio of the memristors in the neuromorphic memristor crossbar array, that is, adjusting the weight distribution and restricting the weights to positive values, so as to increase the sparsity of the network weights, and the formula is as follows:

[0091]

[0092] where W(i,j) and Wpruned(i,j) represent the weight values at position (i,j) in the weight matrix before pruning and the weight matrix after pruning respectively, and || represents taking the absolute value.

[0093] Among them, by setting a fixed pruning ratio P to determine the number of weights to be deleted, and dynamically adjusting the pruning threshold T r , so as to adapt to the change of the weight distribution during the training process. For example, after each backpropagation, all the weight values W will be updated, and their distribution will also change accordingly. Then, according to the set pruning ratio P, a threshold T r is found such that it is less than T rThe proportion of the number of weights in the total number of weights is equal to the specified P. Since the weight distribution changes continuously during the training process, T r also needs to be adjusted dynamically accordingly to ensure that the correct number of weights is always deleted.

[0094] Step Four: Based on the updated network weights, repeat Step Two and Step Three, and continuously train the neuromorphic memristor crossbar array using the remaining samples in the training set until the loss function converges, completing the training of the neural network.

[0095] Figure 4 shows the flowcharts of the ideal performance test in a computer and the simulation test in a crossbar array. The difference between the two test methods is that matrix multiplication is performed in the ideal performance test in a computer, while in the performance test in a crossbar array, the training weights need to be mapped to the memristor conductance range first, and then the test is carried out according to its circuit structure. According to the circuit architecture of the memristive brain-like chip, the present invention adopts the equivalent circuit model test as Figure 5 shown. As Figure 6 shown, when the unit interconnection resistance is 0.1Ω, 0.5Ω, 0.7Ω, and 1.0Ω based on the training method of the present invention, the recognition rates are 97.1%, 97.3%, 96.6%, and 95.0% respectively, which are 4.5%, 26.3%, 32.5%, and 38.5% higher than those after deploying the traditional training method to the memristor array respectively, which proves the effectiveness of the present invention.

[0096] The above embodiments are the implementation manners of the present invention, but the implementation manners of the present invention are not limited by the above embodiments. Any other changes, modifications, substitutions, combinations, and simplifications made without departing from the spirit and principle of the present invention shall be equivalent substitution methods and are all included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope defined by the claims.

Claims

1. A neural network training method suitable for hardware deployment of memristive brain-like chips, characterized in that: include: Step 1: Construct the equivalent circuit of the neuromorphic memristor crossbar array; Step 2: Encode each sample in the training set into a voltage vector and send it to the equivalent circuit of the neuromorphic memristor cross array, and then obtain the voltage and current signals output by the neuromorphic memristor cross array through circuit simulation; calculate the loss function based on the voltage and current signals output by the neuromorphic memristor cross array and complete the back propagation of the gradient; Step 3: After the back propagation of the gradient is completed, the dynamic pruning method is used to increase the sparsity of the network weights in the neuromorphic memristor crossbar array, thereby updating the network weights; Step 4: Based on the updated network weights, repeat steps 2 and 3, and use the remaining samples in the training set to continuously train the neuromorphic memristor cross array until the loss function converges, completing the training of the neural network.

2. A neural network training method suitable for hardware deployment of memristive brain-like chips according to claim 1, characterized in that: In the step 1, the equivalent circuit of the neuromorphic memristor crossbar array is constructed using a partial element equivalent circuit method, which specifically includes the following steps: First, the neuromorphic memristor crossbar array is divided into multiple basic units. Then, the equivalent resistance of each basic unit is calculated. Then, an equivalent inductance model is constructed. Finally, the equivalent capacitance of each basic unit is extracted to obtain the equivalent circuit of the neuromorphic memristor crossbar array.

3. A neural network training method suitable for hardware deployment of memristive brain-like chips according to claim 1, characterized in that: The method of obtaining the voltage and current signals output by the neuromorphic memristor crossbar array by means of circuit simulation includes: First, the steady-state value output of the neuromorphic memristor cross array is calculated, and then the steady-state value output and the dynamic time domain simulation of the cross array are combined to determine the steady-state moment of the network output; then the steady-state output values ​​corresponding to the voltage and current of the neuromorphic memristor cross array are calculated by the circuit equation of the connection matrix A and the resistance matrix R of the equivalent circuit. The calculation formula is as follows: Among them, V s and I s are the steady-state node voltage and branch current to be solved, V r represents the read voltage applied in the neuromorphic memristor crossbar array, X i represents the input voltage vector, ⊙ represents the Hadamard product, T represents the transpose; Finally, the transient output values ​​of the voltage and current of the neuromorphic memristor cross array are obtained by simulating the time domain waveform of the circuit through the partial element equivalent circuit method. The formula is as follows: Among them, V n represents the node voltage at the nth moment, I n represents the branch current at the nth moment, M U , M L and M P They respectively represent the upper triangular matrix, lower triangular matrix and permutation matrix obtained after the circuit structure matrix is ​​decomposed by LU.

4. A neural network training method suitable for hardware deployment of memristive brain-like chips according to claim 1, characterized in that: The method of calculating the loss function based on the voltage and current signals output by the neuromorphic memristor crossbar array and completing the back propagation of the gradient includes: Based on the voltage and current signals output by the neuromorphic memristor crossbar array, the real response S of the neuromorphic memristor crossbar array is obtained. xbar and the ideal response S ideal ; Then use the following formula to calculate the modified network response S: S=S ideal +(S xbar -S ideal )·(1-β epoch ) Among them, β is the adjustment factor and epoch is the round of training.

5. A neural network training method suitable for hardware deployment of memristive brain-like chips according to claim 1, characterized in that: The method of increasing the sparsity of network weights in a neuromorphic memristor crossbar array by using a dynamic pruning method includes: By adjusting the pruning ratio, the proportion of high-resistance states of memristors in the neuromorphic memristor cross array is controlled, so that the sparsity of network weights is increased. The formula is as follows: Among them, W(i, j) and W prumed (i, j) represents the weight value at position (i, j) in the weight matrix before pruning and the weight matrix after pruning, respectively. r represents the pruning threshold, and || represents the absolute value.

6. A neural network training device suitable for hardware deployment of memristive brain-like chips, characterized in that: include: An equivalent circuit generation unit for constructing an equivalent circuit of a neuromorphic memristor crossbar array; A circuit simulation unit, used to encode each sample in the training set into a voltage vector and send it into the equivalent circuit of the neuromorphic memristor crossbar array, and obtain the voltage and current signals output by the neuromorphic memristor crossbar array by means of circuit simulation; A first training unit, for calculating a loss function and back-propagating a gradient according to voltage and current signals output by the neuromorphic memristor crossbar array; The second training unit is used to increase the sparsity of network weights in the neuromorphic memristor crossbar array and update the network weights by using a dynamic pruning method.

7. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that: When the processor executes the computer program, the steps of a neural network training method suitable for hardware deployment of a memristive brain-like chip as described in any one of claims 1 to 5 are implemented.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of a neural network training method suitable for hardware deployment of a memristive brain-like chip as described in any one of claims 1 to 5 are implemented.

9. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instruction is executed by a processor, the steps of a neural network training method suitable for hardware deployment of a memristive brain-like chip as described in any one of claims 1 to 5 are implemented.

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