Liquid crystal driving system

Abstract

The invention provides a liquid crystal driving system. The liquid crystal driving system comprises a CPU and a liquid crystal connected with the CPU. The CPU has the maximum drivable resolution Wmax * Hmax, and the driving layer is configured to drive the liquid crystal according to the maximum drivable resolution, and the resolution of the liquid crystal is W * H; a horizontal synchronizing signal port and a field synchronizing signal port of the CPU are vacant, and an original horizontal synchronizing signal output by the horizontal synchronizing signal port and an original field synchronizing signal output by the field synchronizing signal port are fed back to the application layer; the CPU is respectively connected with a line driving signal pin and a field driving signal pin of the liquid crystal through the first configurable IO port and the second configurable IO port, and is configured in an application layer, so that an implementation synchronizing signal and a real field synchronizing signal output by the first configurable IO port and the second configurable IO port are matched with the resolution ratio of the liquid crystal. According to the invention, adaptation can be easily realized through configuration on the application layer.

Description

Technical Field

[0001] The present invention relates to the technical field of communication within an embedded system, and in particular to a liquid crystal driving system. Background Art

[0002] In the field of embedded systems, the existing LCD driver system is generally designed based on the resolution of the selected LCD and the size of the video memory, so it can only drive a single LCD. If the system is upgraded to use an LCD with another resolution, it is necessary to rewrite the bottom layer (driver layer) and update the driver, which brings certain troubles to the system upgrade and maintenance and is inefficient. Summary of the invention

[0003] The object of the present invention is to provide a liquid crystal driving system, which does not need to rewrite the driving layer when changing to liquid crystals with different resolutions, and can be easily adapted by directly configuring at the application layer, with high efficiency.

[0004] To achieve the above object, the present invention provides the following technical solutions:

[0005] The present invention provides a liquid crystal driving system, the liquid crystal driving system comprising a CPU and a liquid crystal connected to the CPU; the CPU has a maximum drivable resolution W max ×H max , and the driving layer is configured to drive the liquid crystal at a maximum drivable resolution, the resolution of the liquid crystal is W×H, W max , H max , W, and H are all integers greater than 0, and W is less than or equal to W max , H is less than or equal to H max ; The CPU has a horizontal synchronization signal port, a field synchronization signal port, a first configurable IO port, and a second configurable IO port, and the liquid crystal has a horizontal drive signal pin and a field drive signal pin; the horizontal synchronization signal port and the field synchronization signal port of the CPU are vacant, and the original horizontal synchronization signal output by the horizontal synchronization signal port and the original field synchronization signal output by the field synchronization signal port are fed back to the application layer; the CPU is connected to the horizontal drive signal pin and the field drive signal pin of the liquid crystal through the first configurable IO port and the second configurable IO port, respectively, and is configured at the application layer so that the execution synchronization signal and the real field synchronization signal output by the first configurable IO port and the second configurable IO port are adapted to the resolution of the liquid crystal.

[0006] In one embodiment, the CPU is configured with the starting position (x0, y0) of the display area of ​​the liquid crystal in the display area driven by the CPU, the row counter Count_H, and the field counter Count_V at the application layer, x0 and y0 can be set arbitrarily as needed, and x0 is less than H. max, y0 is less than W max ;

[0007] When the original vertical synchronization signal received by the line counter Count_H becomes valid, it is reset, and when the original horizontal synchronization signal received becomes valid, it is incremented: Count_H = Count_H + 1;

[0008] When the original vertical synchronization signal received by the field counter Count_V becomes valid, it is reset, and when the original horizontal synchronization signal received becomes valid, it is also reset. It is incremented every time a pixel data is output: Count_V = Count_V + 1;

[0009] When Count_H > y0 and Count_H < y0 + H, the real vertical synchronization signal of the liquid crystal is configured to be in an active state, and in other cases it is configured to be in an inactive state;

[0010] When Count_H > y0 and Count_H0 < y0 + H, and at the same time Count_V > x0 and Count_V < x0 + W, the real horizontal synchronization signal of the liquid crystal is configured to be in an active state, and in other cases it is configured to be in an invalid state.

[0011] In an embodiment, the liquid crystal driving system further includes a video memory connected to the CPU, and the size of the video memory is also W max ×H max .

[0012] In an embodiment, the liquid crystal driving system further includes a parallel data bus. The CPU is connected to the liquid crystal via the parallel data bus and sends the data to be displayed to the liquid crystal.

[0013] The present invention also provides a liquid crystal driving system, which includes a CPU and a first liquid crystal and a second liquid crystal respectively connected to the CPU; the CPU has a maximum drivable resolution of W max ×H max , and the driving layer is configured to drive the first liquid crystal and the second liquid crystal at the maximum drivable resolution. The resolution of the first liquid crystal is W1×H1, and the resolution of the second liquid crystal is W2×H2. W max , H max , W1, H1, W2, H2 are all integers greater than 0, and both W1 and W2 are less than W max , and both H1 and H2 are less than H max; The CPU has a line synchronization signal port, a field synchronization signal port, a first configurable IO port, a second configurable IO port, a third configurable IO port, and a fourth configurable IO port; the first liquid crystal has a first line drive signal pin and a first field drive signal pin; the second liquid crystal has a second line drive signal pin and a second field drive signal pin; the line synchronization signal port and the field synchronization signal port of the CPU are vacant, and the original line synchronization signal output by the line synchronization signal port and the original field synchronization signal output by the field synchronization signal port are fed back to the application layer; the CPU communicates with the first configurable IO port and the second configurable IO port respectively The first row drive signal pin and the first field drive signal pin of the first liquid crystal are connected, and are respectively connected to the second row drive signal pin and the second field drive signal pin of the second liquid crystal through the third configurable IO port and the fourth configurable IO port, and are configured at the application layer so that the first execution synchronization signal and the first real field synchronization signal output by the first configurable IO port and the second configurable IO port are adapted to the resolution of the first liquid crystal, and the second execution synchronization signal and the second real field synchronization signal output by the third configurable IO port and the fourth configurable IO port are adapted to the resolution of the second liquid crystal.

[0014] In one embodiment, the CPU is configured at the application layer with a first starting position (x1, y1) of the display area of ​​the first liquid crystal in the display area driven by the CPU, a second starting position (x2, y2) of the display area of ​​the second liquid crystal in the display area driven by the CPU, a first row counter Count_H1, a first field counter Count_V1, a second row counter Count_H2, and a second field counter Count_V2, x1, y1, x2, and y2 can be arbitrarily set as needed, and x1 and x2 are both less than H max , y1 and y2 are both less than W max ;

[0015] The first row counter Count_H1 and the second row counter Count_H2 are reset when the original field synchronization signal is switched to be valid, and are accumulated when the original row synchronization signal is switched to be valid: Count_H1=Count_H1+1, Count_H2=Count_H2+1;

[0016] The first field counter Count_V1 and the second field counter Count_V2 are reset when the original field synchronization signal is switched to valid, and are also reset when the original line synchronization signal is switched to valid. Each time a pixel data is output, the counters are accumulated: Count_V1=Count_V1+1, Count_V2=Count_V2+1;

[0017] When Count_H1 > y1 and Count_H1 < y1 + H1, the first real field synchronization signal of the first liquid crystal is configured to be in an effective state, and in other cases it is configured to be in an invalid state;

[0018] When Count_H1 > y1 and Count_H1 < y1 + H1, and at the same time Count_V1 > x1 and Count_V1 < x1 + W1, the first real-time synchronization signal of the first liquid crystal is configured to be in an effective state, and in other cases it is configured to be in an invalid state;

[0019] When Count_H2 > y2 and Count_H2 < y2 + H2, the second real field synchronization signal of the second liquid crystal is configured to be in an effective state, and in other cases it is configured to be in an invalid state;

[0020] When Count_H2 > y2 and Count_H2 < y2 + H2, and at the same time Count_V2 > x2 and Count_V2 < x2 + W2, the second real-time synchronization signal of the second liquid crystal is configured to be in an effective state, and in other cases it is configured to be in an invalid state.

[0021] In one embodiment, x1 + W1 < x2.

[0022] In one embodiment, x1 = x2, y1 = y2, W1 = W2, H1 = H2.

[0023] In one embodiment, x1 + W1 = x2, y1 = y2, W1 = W2, H1 = H2.

[0024] In one embodiment, the liquid crystal driving system further includes a video memory connected to the CPU, and the size of the video memory is also W max ×H max .

[0025] In one embodiment, the liquid crystal driving system further includes a parallel data bus, and the CPU is respectively connected to the first liquid crystal and the second liquid crystal via the parallel data bus to send the data to be displayed to the first liquid crystal and the second liquid crystal.

[0026] In one embodiment, a signal buffer is further provided in the parallel data bus to improve the driving ability.

[0027] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0028] In the liquid crystal drive system of the present invention, the drive layer drives the liquid crystal according to the maximum drivable resolution of the CPU, but the line synchronization signal port and the field synchronization signal port of the CPU are vacant, and the original line synchronization signal output by the line synchronization signal port and the original field synchronization signal output by the field synchronization signal port are fed back to the application layer; and the CPU is connected to the line drive signal pin and the field drive signal pin of the liquid crystal through the first configurable IO port and the second configurable IO port respectively, and the application layer is configured so that the execution synchronization signal and the real field synchronization signal output by the first configurable IO port and the second configurable IO port are adapted to the resolution of the liquid crystal. In this way, when it is necessary to replace the liquid crystal with another resolution at any time, it is only necessary to configure in the application layer to easily achieve adaptation, and there is no need to rewrite the drive layer, thereby improving efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0030] Figure 1 A schematic structural diagram of a liquid crystal driving system provided in a first embodiment of the present invention;

[0031] Figure 2 for Figure 1 A schematic diagram showing the relationship between a display area driven by a CPU and a display area of ​​a liquid crystal in the liquid crystal drive system;

[0032] Figure 3 A schematic structural diagram of a liquid crystal driving system provided in a second embodiment of the present invention;

[0033] Figure 4 The three parts (a), (b) and (c) are Figure 2 A schematic diagram of the relationship between the display area driven by the CPU and the display area of ​​the liquid crystal in the liquid crystal driving system is shown. DETAILED DESCRIPTION

[0034] The technical solutions in the embodiments of the present invention will be described clearly and completely below. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those skilled in the art without creative work belong to the scope of protection of the present invention. It should be noted that the description order of the following embodiments is not used as a limitation on the preferred order of the embodiments of the present invention. In the following embodiments, the description of each embodiment has its own emphasis. For the parts that are not described in detail in a certain embodiment, please refer to the relevant description of other embodiments.

[0035] See also Figure 1 As shown, the first embodiment of the present invention provides a liquid crystal driving system, the liquid crystal driving system includes a CPU and a liquid crystal connected to the CPU; the CPU has a maximum drivable resolution W max ×H max , and the driving layer is configured to drive the liquid crystal at the maximum drivable resolution (for example, the maximum drivable resolution of Freescale's iMX6 is 2048*2048, and the driving timing of the liquid crystal is directly configured to drive it to 2080*2048), and the resolution of the liquid crystal is W×H, W max , H max , W, and H are all integers greater than 0, and W is less than or equal to W max , H is less than or equal to H max ; The CPU has a horizontal synchronization signal port, a field synchronization signal port, a first configurable IO port, and a second configurable IO port, and the liquid crystal has a horizontal drive signal pin and a field drive signal pin; the horizontal synchronization signal port and the field synchronization signal port of the CPU are vacant, and the original horizontal synchronization signal output by the horizontal synchronization signal port and the original field synchronization signal output by the field synchronization signal port are fed back to the application layer; the CPU is connected to the horizontal drive signal pin and the field drive signal pin of the liquid crystal through the first configurable IO port and the second configurable IO port, respectively, and is configured at the application layer so that the execution synchronization signal and the real field synchronization signal output by the first configurable IO port and the second configurable IO port are adapted to the resolution of the liquid crystal.

[0036] In the liquid crystal drive system of the present invention, the driving layer drives the liquid crystal according to the maximum drivable resolution of the CPU, but the line synchronization signal port and the field synchronization signal port of the CPU (the line synchronization signal port and the field synchronization signal port are defaulted when the CPU leaves the factory) are vacant, and the original line synchronization signal output by the line synchronization signal port and the original field synchronization signal output by the field synchronization signal port are fed back to the application layer; and the CPU is connected to the line drive signal pin and the field drive signal pin of the liquid crystal through the first configurable IO port and the second configurable IO port respectively, and the configuration is performed at the application layer so that the execution synchronization signal and the real field synchronization signal output by the first configurable IO port and the second configurable IO port are adapted to the resolution of the liquid crystal. In this way, when it is necessary to replace the liquid crystal with another resolution at any time, it is only necessary to configure at the application layer to easily achieve adaptation, and there is no need to rewrite the driving layer, thereby improving efficiency.

[0037] For details, please refer to Figure 2As shown, in one embodiment, the CPU is configured in the application layer with the starting position (x0, y0) of the display area of the liquid crystal in the display area driven by the CPU, a line counter Count_H, and a field counter Count_V. x0 and y0 can be set arbitrarily according to needs, and x0 is less than H max , y0 is less than W max ;

[0038] When the original field synchronization signal received by the line counter Count_H switches to valid, it is reset, and when the original line synchronization signal received switches to valid, it is incremented: Count_H = Count_H + 1; that is, the line counter Count_H is used to record the row where the currently scanned pixel data is located;

[0039] When the original field synchronization signal received by the field counter Count_V switches to valid, it is reset, and when the original line synchronization signal received switches to valid, it is also reset, and it is incremented every time a pixel data is output: Count_V = Count_V + 1; that is, the field counter Count_V is used to record the column where the currently scanned pixel data is located;

[0040] When Count_H > y0 and Count_H < y0 + H, the real field synchronization signal of the liquid crystal is configured to be in an effective state (e.g., high level), and in other cases it is configured to be in an invalid state (e.g., low level);

[0041] When Count_H > y0 and Count_H0 < y0 + H, and at the same time Count_V > x0 and Count_V < x0 + W, the real line synchronization signal of the liquid crystal is configured to be in an effective state (e.g., high level), and in other cases it is configured to be in an invalid state (e.g., low level).

[0042] In this way, only by configuring the starting position (x0, y0) of the display area of the actually used liquid crystal in the display area driven by the CPU and the size (resolution) W×H of the liquid crystal in the application layer, it can be adapted to the actually used liquid crystal.

[0043] Moreover, in the display area (W_max×H_max) driven by the CPU, the area outside the display area (W×H) corresponding to the actually used liquid crystal is called the off-screen area. Since the liquid crystal driving system of the present invention drives at the maximum resolution of W_max×H_max in the driving layer, the entire continuous area of W_max×H_max can be operated in the application layer, that is, off-screen rendering can also be performed on the off-screen area outside the liquid crystal screen, and then the display area of the liquid crystal can be adjusted by adjusting the coordinates of the starting position (x0, y0) of the display area of the liquid crystal. This off-screen rendering method directly controlled by hardware for the display area is much more efficient and smoother in sliding than the off-screen rendering method implemented by software.

[0044] In addition, it can also be easily expanded to multi-screen display, for which please refer to the description of the second embodiment of the present invention below.

[0045] In one embodiment, the liquid crystal drive system further includes a video memory (not shown) connected to the CPU, and the size of the video memory is also W. max ×H max That is, the size of the video memory is also configured according to the maximum driveable resolution of the CPU.

[0046] Please refer to Figure 1 As shown, in one embodiment, the liquid crystal driving system of the present invention further includes a parallel data bus, and the CPU is connected to the liquid crystal via the parallel data bus to send data to be displayed to the liquid crystal.

[0047] See also Figure 3 As shown, the second embodiment of the present invention provides a liquid crystal driving system, the liquid crystal driving system includes a CPU and a first liquid crystal and a second liquid crystal respectively connected to the CPU; the CPU has a maximum drivable resolution W max ×H max , and the driving layer is configured to drive the first liquid crystal and the second liquid crystal according to the maximum drivable resolution, the resolution of the first liquid crystal is W1×H1, the resolution of the second liquid crystal is W2×H2, W max , H max W1, H1, W2, H2 are all integers greater than 0, and W1 and W2 are both less than W max , H1 and H2 are both smaller than H max; The CPU has a line synchronization signal port, a field synchronization signal port, a first configurable IO port, a second configurable IO port, a third configurable IO port, and a fourth configurable IO port; the first liquid crystal has a first line drive signal pin and a first field drive signal pin; the second liquid crystal has a second line drive signal pin and a second field drive signal pin; the line synchronization signal port and the field synchronization signal port of the CPU are vacant, and the original line synchronization signal output by the line synchronization signal port and the original field synchronization signal output by the field synchronization signal port are fed back to the application layer; the CPU communicates with the first configurable IO port and the second configurable IO port respectively The first row drive signal pin and the first field drive signal pin of the first liquid crystal are connected, and are respectively connected to the second row drive signal pin and the second field drive signal pin of the second liquid crystal through the third configurable IO port and the fourth configurable IO port, and are configured at the application layer so that the first execution synchronization signal and the first real field synchronization signal output by the first configurable IO port and the second configurable IO port are adapted to the resolution of the first liquid crystal, and the second execution synchronization signal and the second real field synchronization signal output by the third configurable IO port and the fourth configurable IO port are adapted to the resolution of the second liquid crystal.

[0048] The difference between the second embodiment and the first embodiment is that the second embodiment is to connect two liquid crystals at the same time. Of course, three or even more liquid crystals can be connected at the same time as needed, which should be included in the protection scope of the present invention, because the core idea of ​​the second embodiment is exactly the same as that of the first embodiment, both of which drive the liquid crystal at the driver layer according to the maximum drivable resolution of the CPU. The configuration at the application layer can easily achieve the adaptation of each liquid crystal, and there is no need to rewrite the driver layer, which improves efficiency. The second embodiment uses two liquid crystals just for illustration. Through the second embodiment, it can be easily understood that through expansion, a single port (original row and field synchronization signal port) can be easily realized for multi-screen display, and a liquid crystal drive port (original row and field synchronization signal port) can be realized on a CPU with limited resources to drive multiple liquid crystal screens, and a highly synchronized display can be maintained, without having to deal with the synchronous refresh problem of multiple screens separately.

[0049] For details, please refer to Figure 4 As shown in part (a), in one embodiment, the CPU is configured at the application layer with a first starting position (x1, y1) of the display area of ​​the first liquid crystal in the display area driven by the CPU, a second starting position (x2, y2) of the display area of ​​the second liquid crystal in the display area driven by the CPU, a first row counter Count_H1, a first field counter Count_V1, a second row counter Count_H2, and a second field counter Count_V2, x1, y1, x2, and y2 can be arbitrarily set as needed, and x1 and x2 are both less than Hmax where both y1 and y2 are less than W max ;

[0050] The first line counter Count_H1 and the second line counter Count_H2 are reset when the original field sync signal switches to valid, and are incremented when the original line sync signal switches to valid: Count_H1 = Count_H1 + 1, Count_H2 = Count_H2 + 1;

[0051] The first field counter Count_V1 and the second field counter Count_V2 are reset when the original field sync signal switches to valid, and are also reset when the original line sync signal switches to valid, and are incremented every time a pixel data is output: Count_V1 = Count_V1 + 1, Count_V2 = Count_V2 + 1;

[0052] When Count_H1 > y1 and Count_H1 < y1 + H1, the first real field sync signal of the first liquid crystal is configured to be in an active state, and in other cases it is configured to be in an inactive state;

[0053] When Count_H1 > y1 and Count_H1 < y1 + H1, and at the same time Count_V1 > x1 and Count_V1 < x1 + W1, the first real line sync signal of the first liquid crystal is configured to be in an active state, and in other cases it is configured to be in an invalid state;

[0054] When Count_H2 > y2 and Count_H2 < y2 + H2, the second real field sync signal of the second liquid crystal is configured to be in an active state, and in other cases it is configured to be in an inactive state;

[0055] When Count_H2 > y2 and Count_H2 < y2 + H2, and at the same time Count_V2 > x2 and Count_V2 < x2 + W2, the second real line sync signal of the second liquid crystal is configured to be in an active state, and in other cases it is configured to be in an invalid state.

[0056] Similarly, only by configuring the starting position (x1, y1) of the display area of the first liquid crystal actually used in the application layer in the display area driven by the CPU and the size (resolution) W1×H1 of the first liquid crystal, and the starting position (x2, y2) of the display area of the second liquid crystal in the display area driven by the CPU and the size (resolution) W2×H2 of the second liquid crystal, it can be adapted to both the first liquid crystal and the second liquid crystal actually used.

[0057] Moreover, Figure 4In the embodiment shown in part (a), the display areas of the first liquid crystal and the second liquid crystal are completely separated, that is, each liquid crystal selects a different display area for driving and displaying. At this time, only x1 + W1 < x2 needs to be noted. As for the relationships among y1, y2, W1, H1, W2, and H2, they can be appropriately configured according to the actual needs. For example, y1 > y2 can be set, or y1 < y2 can be set. W1 = W2 can be set, or W1 ≠ W2 can be set. H1 = H2 can be set, or H1 ≠ H2 can be set. That is, the first liquid crystal and the second liquid crystal can have the same resolution or different resolutions.

[0058] Please refer to Figure 4 As shown in part (b), in one embodiment, the display areas of the first liquid crystal and the second liquid crystal completely overlap, that is, the two liquid crystals have the same resolution and select the same display area for driving and displaying. At this time, x1 = x2, y1 = y2, W1 = W2, and H1 = H2.

[0059] Please refer to Figure 4 As shown in part (c), in one embodiment, the display areas of the first liquid crystal and the second liquid crystal exactly form a seamless splicing, that is, the two liquid crystals have the same resolution and select different display areas for driving and displaying. At this time, x1 + W1 = x2, y1 = y2, W1 = W2, and H1 = H2.

[0060] Similarly, in one embodiment, the liquid crystal driving system further includes a video memory (not shown) connected to the CPU, and the size of the video memory is also W max ×H max . That is, the size of the video memory is also configured according to the maximum resolvable resolution of the CPU.

[0061] Please refer to again Figure 3 As shown, similarly, in one embodiment, the liquid crystal driving system further includes a parallel data bus, and the CPU is connected to the first liquid crystal and the second liquid crystal via the parallel data bus respectively, and sends the data to be displayed to the first liquid crystal and the second liquid crystal.

[0062] Moreover, in one embodiment, a signal buffer is further provided in the parallel data bus to improve the driving ability.

[0063] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0064] In the liquid crystal drive system of the present invention, the drive layer drives the liquid crystal according to the maximum drivable resolution of the CPU, but the line synchronization signal port and the field synchronization signal port of the CPU are vacant, and the original line synchronization signal output by the line synchronization signal port and the original field synchronization signal output by the field synchronization signal port are fed back to the application layer; and the CPU is connected to the line drive signal pin and the field drive signal pin of the liquid crystal through the first configurable IO port and the second configurable IO port respectively, and the application layer is configured so that the execution synchronization signal and the real field synchronization signal output by the first configurable IO port and the second configurable IO port are adapted to the resolution of the liquid crystal. In this way, when it is necessary to replace the liquid crystal with another resolution at any time, it is only necessary to configure in the application layer to easily achieve adaptation, and there is no need to rewrite the drive layer, thereby improving efficiency.

[0065] The above is only a specific implementation of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims. In addition, the specification uses specific examples to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. The content of this specification should not be understood as a limitation on the present invention.

Claims

1. A liquid crystal driving system, characterized in that: The liquid crystal driving system includes a CPU and a liquid crystal connected to the CPU; the CPU has a maximum drivable resolution W max ×H max , and the driving layer is configured to drive the liquid crystal at a maximum drivable resolution, the resolution of the liquid crystal is W×H, W max , H max , W, and H are all integers greater than 0, and W is less than or equal to W max , H is less than or equal to H max ; The CPU has a horizontal synchronization signal port, a field synchronization signal port, a first configurable IO port, and a second configurable IO port, and the liquid crystal has a horizontal drive signal pin and a field drive signal pin; the horizontal synchronization signal port and the field synchronization signal port of the CPU are vacant, and the original horizontal synchronization signal output by the horizontal synchronization signal port and the original field synchronization signal output by the field synchronization signal port are fed back to the application layer; the CPU is connected to the horizontal drive signal pin and the field drive signal pin of the liquid crystal through the first configurable IO port and the second configurable IO port, respectively, and is configured at the application layer so that the execution synchronization signal and the real field synchronization signal output by the first configurable IO port and the second configurable IO port are adapted to the resolution of the liquid crystal.

2. The liquid crystal driving system according to claim 1, characterized in that: The CPU is configured with the starting position (x0, y0) of the display area of ​​the liquid crystal in the display area driven by the CPU, the row counter Count_H, and the field counter Count_V at the application layer. x0 and y0 can be set arbitrarily according to needs, and x0 is less than H. max , y0 is less than W max ; The line counter Count_H is reset when the original vertical synchronization signal switches to valid, and is incremented when the original horizontal synchronization signal switches to valid: Count_H = Count_H + 1; The field counter Count_V is reset when the original vertical synchronization signal switches to valid, and is also reset when the original horizontal synchronization signal switches to valid, and is incremented every time a pixel data is output: Count_V = Count_V + 1; When Count_H > y0 and Count_H < y0 + H, the real vertical synchronization signal of the liquid crystal is configured to be in a valid state, and in other cases it is configured to be in an invalid state; When Count_H > y0 and Count_H0 < y0 + H, and at the same time Count_V > x0 and Count_V < x0 + W, the real horizontal synchronization signal of the liquid crystal is configured to be in a valid state, and in other cases it is configured to be in an invalid state.

3. The liquid crystal driving system according to claim 1, characterized in that: The liquid crystal drive system also includes a video memory connected to the CPU, and the size of the video memory is also W max ×H max .

4. The liquid crystal driving system according to claim 1, characterized in that: The liquid crystal driving system further includes a parallel data bus, and the CPU is connected to the liquid crystal via the parallel data bus to send the data to be displayed to the liquid crystal.

5. A liquid crystal driving system, characterized in that: The liquid crystal driving system includes a CPU and a first liquid crystal and a second liquid crystal respectively connected to the CPU; the CPU has a maximum drivable resolution W max ×H max , and the driving layer is configured to drive the first liquid crystal and the second liquid crystal according to the maximum drivable resolution, the resolution of the first liquid crystal is W1×H1, the resolution of the second liquid crystal is W2×H2, W max , H max W1, H1, W2, H2 are all integers greater than 0, and W1 and W2 are both less than W max , H1 and H2 are both smaller than H max ; The CPU has a line synchronization signal port, a field synchronization signal port, a first configurable IO port, a second configurable IO port, a third configurable IO port, and a fourth configurable IO port; the first liquid crystal has a first line drive signal pin and a first field drive signal pin; the second liquid crystal has a second line drive signal pin and a second field drive signal pin; the line synchronization signal port and the field synchronization signal port of the CPU are vacant, and the original line synchronization signal output by the line synchronization signal port and the original field synchronization signal output by the field synchronization signal port are fed back to the application layer; the CPU communicates with the first configurable IO port and the second configurable IO port respectively The first row drive signal pin and the first field drive signal pin of the first liquid crystal are connected, and are respectively connected to the second row drive signal pin and the second field drive signal pin of the second liquid crystal through the third configurable IO port and the fourth configurable IO port, and are configured at the application layer so that the first execution synchronization signal and the first real field synchronization signal output by the first configurable IO port and the second configurable IO port are adapted to the resolution of the first liquid crystal, and the second execution synchronization signal and the second real field synchronization signal output by the third configurable IO port and the fourth configurable IO port are adapted to the resolution of the second liquid crystal.

6. The liquid crystal driving system according to claim 5, characterized in that: The CPU is configured at the application layer with a first starting position (x1, y1) of the display area of ​​the first liquid crystal in the display area driven by the CPU, a second starting position (x2, y2) of the display area of ​​the second liquid crystal in the display area driven by the CPU, a first row counter Count_H1, a first field counter Count_V1, a second row counter Count_H2, and a second field counter Count_V2, x1, y1, x2, and y2 can be set arbitrarily according to needs, and x1 and x2 are both less than H max , y1 and y2 are both less than W max ; The first line counter Count_H1 and the second line counter Count_H2 are reset when the original vertical synchronization signal switches to valid, and are incremented when the original horizontal synchronization signal switches to valid: Count_H1 = Count_H1 + 1, Count_H2 = Count_H2 + 1; The first field counter Count_V1 and the second field counter Count_V2 are reset when the original vertical synchronization signal switches to valid, and are also reset when the original horizontal synchronization signal switches to valid, and are incremented every time a pixel data is output: Count_V1 = Count_V1 + 1, Count_V2 = Count_V2 + 1; When Count_H1 > y1 and Count_H1 < y1 + H1, the first real vertical synchronization signal of the first liquid crystal is configured to be in a valid state, and in other cases it is configured to be in an invalid state; When Count_H1 > y1 and Count_H1 < y1 + H1, and at the same time Count_V1 > x1 and Count_V1 < x1 + W1, the first real horizontal synchronization signal of the first liquid crystal is configured to be in a valid state, and in other cases it is configured to be in an invalid state; When Count_H2 > y2 and Count_H2 < y2 + H2, the second real vertical synchronization signal of the second liquid crystal is configured to be in a valid state, and in other cases it is configured to be in an invalid state; When Count_H2 > y2 and Count_H2 < y2 + H2, and at the same time Count_V2 > x2 and Count_V2 < x2 + W2, the second real horizontal synchronization signal of the second liquid crystal is configured to be in a valid state, and in other cases it is configured to be in an invalid state.

7. The liquid crystal driving system according to claim 6, characterized in that: x1 + W1 < x2.

8. The liquid crystal driving system according to claim 6, characterized in that: x1 = x2, y1 = y2, W1 = W2, H1 = H2.

9. The liquid crystal driving system according to claim 6, characterized in that: x1 + W1 = x2, y1 = y2, W1 = W2, H1 = H2.

10. The liquid crystal driving system according to claim 5, characterized in that: The liquid crystal drive system also includes a video memory connected to the CPU, and the size of the video memory is also W max ×H max ; The liquid crystal driving system also includes a parallel data bus, and the CPU is connected to the first liquid crystal and the second liquid crystal respectively via the parallel data bus to send data to be displayed to the first liquid crystal and the second liquid crystal; a signal buffer is also provided in the parallel data bus to enhance the driving capability.

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