Memory and testing method

Abstract

The invention provides a memory and a test method, the memory comprises a plurality of memory arrays, and each memory array comprises a plurality of memory areas; the memory further comprises a plurality of reading circuits and a first output circuit; each storage area is connected with the corresponding reading circuit through a data line, at least one storage area in the memory is activated, and the reading circuit corresponding to the activated storage area reads data from the activated storage area and then outputs the data at the output end; the output end of the reading circuit is connected with the input end of the first output circuit, and the first output circuit sequentially outputs data output by the output end of at least one reading circuit to a data receiving and transmitting port of the memory; wherein the bit of the data output by each reading circuit is an integral multiple of the burst length, and the bit of the data output by the data receiving and transmitting port is an integral multiple of the burst length.

Description

Technical Field

[0001] The present application relates to but is not limited to a memory and a testing method. Background Art

[0002] With the development of memory technology, memories are widely used in various fields. For example, dynamic random access memory (DRAM) is widely used.

[0003] As we all know, memory has to go through a series of tests after tape-out before it can be finally put on the market. How to improve the testing efficiency of memory is an important direction for improvement. Summary of the invention

[0004] The present application provides a memory, comprising: a plurality of storage areas, a plurality of readout circuits and a first output circuit;

[0005] Each storage area is connected to a corresponding readout circuit via a data line, at least one storage area in the memory is activated, and the readout circuit corresponding to the activated storage area reads data from the activated storage area and outputs it at the output end;

[0006] The output end of the readout circuit is connected to the input end of the first output circuit, and the first output circuit sequentially outputs the output data of at least one of the output ends of the readout circuit to a data transceiver port of the memory;

[0007] The bit position of the data output by each readout circuit is an integer multiple of the burst length, and the bit position of the data output by the data transceiver port is an integer multiple of the burst length.

[0008] In some embodiments, there are multiple first output circuits, each of which corresponds to a data transceiver port, and each of which is connected to output terminals of multiple readout circuits;

[0009] The readout circuit corresponding to the activated storage area outputs data of a burst length to each first output circuit, and the data received by each first output circuit is at a different position in the storage area; each first output circuit performs parallel-to-serial conversion on the data of at least one storage area and outputs it to the corresponding data transceiver port.

[0010] In some embodiments, the first output circuit includes a plurality of first latch circuits and a first parallel-to-serial conversion circuit;

[0011] The input end of the first latch circuit is connected to the corresponding readout circuit, and the first latch circuit latches the data output by the readout circuit at the output end;

[0012] The output end of each first latch circuit is connected to the input end of the first parallel-to-serial conversion circuit. The control end of the first parallel-to-serial conversion circuit also receives a mode signal, which is used to characterize the number of activated storage areas. The first parallel-to-serial conversion circuit sequentially outputs the data of the output end of at least one first latch circuit to a data transceiver port of the memory.

[0013] In some embodiments, the mode signal includes a first mode sub-signal and a second mode sub-signal; the first parallel-to-serial conversion circuit includes a first input circuit, a second parallel-to-serial conversion circuit, and a second output circuit;

[0014] The input end of the first input circuit is connected to the output end of each first latch circuit, and the control end of the first input circuit receives a first mode sub-signal, the first mode sub-signal represents activation of one storage area or activation of multiple storage areas; when the first mode sub-signal represents activation of one storage area, the first input circuit outputs data to the second output circuit; when the first mode sub-signal represents activation of multiple storage areas, the first input circuit outputs data to the second parallel-to-serial conversion circuit;

[0015] The input end of the second parallel-to-serial conversion circuit is connected to the first output end of the first input circuit, and the control end of the second parallel-to-serial conversion circuit receives a second mode sub-signal, the second mode sub-signal indicates activation of the first number of storage areas or activation of the second number of storage areas; the second parallel-to-serial conversion circuit performs parallel-to-serial conversion on the input end data based on the second mode sub-signal and outputs the result to the second output circuit;

[0016] The first input end of the second output circuit is connected to the second output end of the first input circuit, the second input end of the second output circuit is connected to the output end of the second parallel-to-serial conversion circuit, and the control end of the second output circuit receives the first mode sub-signal and the logical address of the activated storage area; the second output circuit outputs the data of the first input end to the data transceiver port or outputs the data of the second input end to the data transceiver port at the output end based on the first mode sub-signal and the logical address of the activated storage area.

[0017] In some embodiments, the first input circuit includes a plurality of first selectors;

[0018] An input end of a first selector is connected to an output end of a first latch circuit, a control end of each first selector receives a first mode sub-signal, a first output end of each first selector is connected to an input end of a second parallel-to-serial conversion circuit, and a second output end of each first selector is connected to an input end of a second output circuit.

[0019] In some embodiments, the second parallel-to-serial conversion circuit includes a second input circuit and a third parallel-to-serial conversion circuit;

[0020] The input end of the second input circuit is connected to the output end of the first input circuit, the control end of the second input circuit receives the second mode sub-signal, and when the second mode sub-signal indicates activation of the first number of storage areas, the second input circuit outputs data to the first input end of the third parallel-to-serial conversion circuit; when the second mode sub-signal indicates activation of the second number of storage areas, the second input circuit outputs data to the second input end of the third parallel-to-serial conversion circuit;

[0021] The first input end of the third parallel-to-serial conversion circuit is connected to the first output end of the second input circuit, and the second input end of the third parallel-to-serial conversion circuit is connected to the second output end of the second input circuit. The third parallel-to-serial conversion circuit performs parallel-to-serial conversion on the data at the first input end and outputs it to the first output circuit, or performs parallel-to-serial conversion on the data at the second input end and outputs it to the first output circuit.

[0022] In some embodiments, the first input circuit includes four first selectors, and the second input circuit includes three second selectors;

[0023] The input end of the first second selector is connected to the first output end of the first first selector, the second output end of the first second selector is connected to the first input end of the third parallel-to-serial conversion circuit, and the first output end of the first second selector is connected to the first output end of the second second selector;

[0024] The input end of the second second selector is connected to the first output end of the second first selector, the second output end of the second second selector is connected to the first input end of the third parallel-to-serial conversion circuit, and the first output end of the second second selector is connected to the second input end of the third parallel-to-serial conversion circuit;

[0025] The input end of the third second selector is connected to the first output end of the third first selector, the second output end of the third second selector is connected to the first input end of the third parallel-to-serial conversion circuit, the first output end of the third second selector is connected to the first output end of the fourth first selector, and the first output end of the third second selector is connected to the second input end of the third parallel-to-serial conversion circuit.

[0026] In some embodiments, the third parallel-to-serial conversion circuit includes four second latch circuits;

[0027] The input end of the first second latch circuit is connected to the second output end of the first second selector, and the output end of the first second latch circuit is connected to the input end of the second second latch circuit;

[0028] The input end of the second second latch circuit is connected to the second output end of the second second selector, and the output end of the second second latch circuit is connected to the input end of the third second latch circuit;

[0029] The input end of the third second latch circuit is connected to the second output end of the third second selector, the input end of the third second latch circuit is connected to the first output end of the second second selector, and the output end of the third second latch is connected to the input end of the fourth second latch circuit;

[0030] The input end of the fourth second latch circuit is connected to the first output end of the third second selector, and the output end of the fourth second latch circuit is the output end of the third parallel-to-serial conversion circuit.

[0031] In some embodiments, the second output circuit includes a third selector and a fourth selector;

[0032] The input end of the third selector is connected to the output end of the first input circuit, the output end of the third selector is connected to the first input end of the fourth selector, the control end of the third selector receives the first mode sub-signal and the logical address of the activated storage area, and the third selector outputs the data in the activated storage area based on the first mode sub-signal and the logical address of the activated storage area;

[0033] The second input end of the fourth selector is connected to the output end of the second parallel-to-serial conversion circuit, the control end of the fourth selector receives the first mode sub-signal, and the fourth selector outputs the data of the first input end or the second input end to a data transceiver port of the memory based on the first mode sub-signal.

[0034] In some embodiments, the third selector includes four input terminals;

[0035] The first input end of the third selector is connected to the second output end of the first first selector, the second input end of the third selector is connected to the second output end of the second first selector, the third input end of the third selector is connected to the second output end of the third first selector, and the fourth input end of the third selector is connected to the second output end of the fourth first selector.

[0036] In some embodiments, each storage region includes a plurality of storage columns;

[0037] Each storage column corresponds to a row address, and the third number of bit addresses in the row address from high to low is called a high-order row address, and the third number is less than the total number of row address bits in the row address;

[0038] The high-order row addresses of storage columns in the same storage area are the same, and the high-order row addresses of the storage columns are the logical addresses of the storage area.

[0039] In some embodiments, the memory further comprises a plurality of groups of data lines, each group of data lines comprising a global data line and a local data line;

[0040] Each readout circuit is connected to a group of data lines. The readout circuit reads data stored in a corresponding storage area through the corresponding data line. Each readout circuit also outputs data to the first output circuit through the data line.

[0041] In some embodiments, the memory further comprises a plurality of drive circuits;

[0042] Each driving circuit input terminal is connected to an output terminal of a readout circuit through a data line, and the output terminal of the driving circuit is connected to an input terminal of a first latch circuit.

[0043] Some embodiments of the present application also provide a method for testing a memory, wherein the memory includes a plurality of memory arrays, each memory array includes a plurality of storage areas; the method includes:

[0044] Writing background data into each storage array of the memory and reading data from each storage array in turn;

[0045] Comparing the background data written in each storage array with the data read out of each storage array to obtain a test result;

[0046] Wherein, reading data from a storage array specifically includes:

[0047] Activating at least one storage area at the same time, reading data from the at least one activated storage area, and performing parallel-to-serial conversion on the data read from the at least one activated storage area and outputting the data to a data transceiver port;

[0048] The bit positions of the data read from each storage area are integer multiples of the burst length, and the bit positions of the data output by the data transceiver port are integer multiples of the burst length.

[0049] In some embodiments, the data read from at least one activated storage area is converted from parallel to serial and then output to a data transceiver port, specifically including:

[0050] Acquire a burst length of data from the data read from each activated storage area;

[0051] Data of a burst length in the read data of all activated storage areas are converted from parallel to serial and then output to a data transceiver port.

[0052] The memory and test method provided by the present application, the memory includes multiple storage areas, multiple readout circuits and a first output circuit. Each storage area is connected to the corresponding readout circuit through a data line, at least one storage area in the memory is activated, and the readout circuit corresponding to the activated storage area reads data from the activated storage area and outputs it at the output end, the output end of the readout circuit is connected to the input end of the first output circuit, and the first output circuit sequentially outputs the output end output data of at least one readout circuit to a data transceiver port of the memory. By setting it in this way, data in at least one storage area can be read out each time, and the time for reading data in all storage areas in the memory can be reduced. Especially when the memory is tested, the test efficiency can be improved. In addition, the data in at least one storage area is converted by the first output circuit and output through a data transceiver port, occupying fewer data transceiver ports. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0054] Figure 1 A diagram showing an example of a memory architecture;

[0055] Figure 2 for Figure 1 A schematic diagram of the architecture of a data input / output circuit in a memory shown;

[0056] Figure 3 A schematic diagram of the architecture of a memory provided for some embodiments of the present application;

[0057] Figure 4 is a specific circuit diagram of a first parallel-to-serial conversion circuit;

[0058] Figure 5 A schematic diagram for activating a storage area in a storage array;

[0059] Figure 6 The data flow diagram for activating one storage area in the storage area;

[0060] Figure 7 This is a timing diagram for activating a storage area in a storage array;

[0061] Figure 8 A schematic diagram of activating four storage areas in a storage array;

[0062] Fig. 9 The data flow diagram for activating 4 storage areas in the storage area;

[0063] Fig.10 The timing diagram for activating four storage areas in the storage array;

[0064] Fig.11 A schematic diagram of activating two storage areas in a storage array;

[0065] Fig.12 The data flow diagram for activating 2 storage areas in the storage area;

[0066] Fig.13 It is a timing diagram for activating two storage areas in the storage array;

[0067] Fig.14 A schematic diagram of the architecture of a memory provided for some embodiments of the present application.

[0068] Reference numerals:

[0069] 10. A first parallel-to-serial conversion circuit; 20. A first input circuit; 30. A second parallel-to-serial conversion circuit; 40. A second output circuit; 31. A second input circuit; 32. A third parallel-to-serial conversion circuit. 100, the first output circuit; 101, the first first latch circuit; 102, the second first latch circuit; 103, the third first latch circuit; 104, the fourth first latch circuit; 301, the first first selector; 302, the second first selector; 303, the third first selector; 304, the fourth first selector; 305, the first second selector; 306, the second second selector; 307, the third second selector; 201, the first second latch circuit; 202, the second second latch circuit; 203, the third second latch circuit; 204, the fourth second latch circuit; 401, the third selector; 402, the fourth selector; CK_t, the first clock signal; DQSCK, the second clock signal; MS1, the first mode sub-signal; MS2, the second mode sub-signal. 50. A third input circuit; 60. A fourth parallel-to-serial conversion circuit; 70. A third output circuit.

[0070] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0071] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0072] At present, memory technology is developing rapidly. Taking DRAM as an example, the main applications include synchronous dynamic random access memory (Synchronous Dynamic Random-Access Memory, referred to as: SDRAM), various generations of double data rate (Double Data Rate, referred to as: DDR) SDRAM, various generations of low power double data rate (Low Power Double Data Rate, referred to as: LPDDR) SDRAM and other types.

[0073] Figure 1 A sample diagram of a memory architecture is shown below. Figure 1 As shown, taking DRAM as an example, it includes an address processing circuit 210, a command decoding circuit 220, a data input / output circuit 230, a row decoder 240, a column decoder 250, a sense amplifier 260 and a storage array. Among them, the address processing circuit 210, the command decoding circuit 220 and the data input / output circuit 230 belong to the peripheral area circuit, and the row decoder 240, the column decoder 250, the sense amplifier 260 and the storage array belong to the array area circuit. The storage array is mainly composed of a storage cell 270, a bit line BL and a word line WL. The word line WL in the storage array extends in the row direction, and the bit line BL in the storage array extends in the column direction. The intersection of the word line WL and the bit line BL is the storage cell 270 of the storage array.

[0074] Figure 2 for Figure 1 The schematic diagram of the data input / output circuit in the memory shown in FIG. Figure 2 As shown, the data input / output circuit includes an amplifier circuit, a conversion circuit and a timing circuit. The timing circuit provides a clock signal to the storage array and the conversion circuit. The amplifier circuit receives data through the local data line and the global data line. The amplifier circuit performs signal enhancement on the data and outputs it to the conversion circuit. The conversion circuit performs parallel-to-serial conversion on the data and outputs it to the data transceiver port of the memory.

[0075] When testing a memory, test data is usually written into the memory, then read out from the memory, the written test data is compared with the read test data, and whether the performance of the memory is good is determined based on the comparison result.

[0076] Generally, when reading out the test data in the memory, a full read method is used. That is, the data is read in the order of the structure of the storage array in the memory. More specifically, the memory includes multiple storage arrays, and the test data in one storage array is read first, and then the test data in the next storage array is read. For each storage array, the storage array includes multiple storage areas, each storage area includes multiple word lines, and the number of word lines in each storage area is the same. When reading the test data in a storage array, the data in the first storage area is read first, and then the data in the second storage area is read, and so on, until the data in all storage areas are read out.

[0077] For example, a memory includes 8 data transceiver ports (DQ) and the burst length of data is 8 bits. Each time a storage area is activated, 64 bits of data are read from the storage area, and the 64 bits of data are output through 8 data transceiver ports, and each data transceiver port outputs 8 bits of data. If the data of one storage area is read at a time, it takes a long time to read the test data when the data of all storage areas of the storage array are read out.

[0078] Some aspects of the embodiments of the present disclosure relate to the above considerations. The following is an example introduction of the solution in combination with some embodiments of the present disclosure.

[0079] Figure 3 The following is a schematic diagram of the memory architecture provided by some embodiments of the present application. Figure 3 As shown, some embodiments of the present application provide a memory, which includes multiple storage areas, multiple readout circuits (not shown) and a first output circuit 100.

[0080] Wherein, each storage area is connected to the corresponding readout circuit through a data line, at least one storage area in the memory is activated, and the readout circuit corresponding to the activated storage area reads data from the activated storage area and outputs it at the output end, and the output end of the readout circuit is connected to the input end of the first output circuit 100, and the first output circuit 100 sequentially outputs the output data of at least one readout circuit to a data transceiver port of the memory. The bit position of the data output by each readout circuit is an integer multiple of the burst length, and the bit position of the data output by the data transceiver port is an integer multiple of the burst length. By setting it in this way, data in at least one storage area can be read out each time, and the time for reading data in all storage areas in the memory can be reduced. The number of instructions can also be reduced. In particular, when the memory is tested, the test efficiency can be improved. In addition, the data in at least one storage area is converted by the first output circuit 100 and then output through a data transceiver port, occupying fewer data transceiver ports.

[0081] There are multiple first output circuits 100, each of which corresponds to a data transceiver port, and each of which is connected to the output ends of multiple readout circuits. When the storage area is activated, the corresponding readout circuit is used to output a burst length of data to each first output circuit, and the data received by any two first output circuits are located in different positions in the storage area. Each first output circuit performs parallel-to-serial conversion on the data of at least one storage area and outputs it to the corresponding data transceiver port. By setting it in this way, data concurrent output can be achieved, data readout efficiency can be improved, and test efficiency can be improved.

[0082] Continuing with the example that the memory includes 8 data transceiver ports and the burst length of the data is 8 bits.

[0083] Each time a storage area is activated, 64 bits of data are read from the storage area. Accordingly, there are also 8 first output circuits, each of which reads 64 bits of data from the storage area, outputs 8 bits of data to the first first output circuit, outputs 8 bits of data to the second first output circuit, outputs 8 bits of data to the third first output circuit, and so on, and the 8 bits of data received by any two first output circuits are stored in different storage units.

[0084] When two storage areas are activated at the same time, each first output circuit can receive 16 bits of concurrent data, and after parallel-to-serial conversion, output 16 bits of serial data through a data transceiver port. The eight data transceiver ports can output 128 bits of data, which doubles the data output at one time compared to the original 64 bits of data output at one time.

[0085] When four storage areas are activated at the same time, each first output circuit can receive 32 bits of concurrent data, and after parallel-to-serial conversion, output 32 bits of serial data through a data transceiver port. The eight data transceiver ports can output 256 bits of data. Compared with the original 64 bits of data output at a time, the data output volume is increased four times.

[0086] Continue to refer Figure 3 The memory also includes a plurality of groups of data lines, one group of data lines corresponds to one storage area, each group of data lines includes a global data line GIO and a local data line YIO, each readout circuit is connected to a group of data lines, the readout circuit reads the data stored in the corresponding storage area through the corresponding data line, and each readout circuit also outputs data to the first output circuit 100 through the data line. By configuring a group of data lines for each storage area, that is, the storage areas do not share data lines, multiple storage areas can be activated at the same time, so that the data of each storage area is output to the corresponding data line through the readout circuit, and the data will not be interfered.

[0087] Continue to refer Figure 3 The first output circuit 100 includes a plurality of first latch circuits and a first parallel-to-serial conversion circuit 10. The input ends of the plurality of first latch circuits serve as the input ends of the first output circuit 100. The input ends of the first latch circuits are connected to corresponding readout circuits (not shown in the figure). The first latch circuit latches the data output by the readout circuit at the output end.

[0088] The output end of each first latch circuit is connected to the input end of the first parallel-to-serial conversion circuit 10. The control end of the first parallel-to-serial conversion circuit 10 also receives a mode signal, which is used to characterize the number of activated storage areas. The first parallel-to-serial conversion circuit 10 sequentially outputs the data of the output end of at least one first latch circuit to a data transceiver port of the memory. The number of first latch circuits is the same as the number of readout circuits, and one first latch circuit corresponds to one readout circuit. By setting a corresponding first latch circuit for each readout circuit, multiple first latch circuits latch the data outputted simultaneously by multiple readout circuits, thereby realizing the storage and latching of concurrent data, and allowing the first parallel-to-serial conversion circuit 10 to have sufficient data conversion time.

[0089] More specifically, when the mode signal indicates activation of a storage area, the first parallel-to-serial conversion circuit 10 outputs the data read from the activated storage area under the control of the mode signal. When the mode signal indicates activation of multiple storage areas, the first parallel-to-serial conversion circuit 10 outputs the data read from the multiple activated storage areas after parallel-to-serial conversion under the control of the mode signal. Since a corresponding first latch circuit is provided for each readout circuit, the first latch circuit latches the data output by the readout circuit, so that the first parallel-to-serial conversion circuit 10 has sufficient time to perform parallel-to-serial conversion, and realizes that the data read from the multiple activated storage areas are sequentially output from a data transceiver port.

[0090] Continue to refer Figure 3 The memory also includes a plurality of driving circuits, each of which has an input end connected to an output end of a readout circuit via a data line, and an output end of the driving circuit connected to an input end of the first output circuit. The driving circuit is used to enhance the signal strength of the data so that the data can be accurately transmitted from the data line through the first output circuit 100 to the data transceiver port.

[0091] Figure 4 FIG. 1 is a specific circuit diagram of a first parallel-to-serial conversion circuit 10. Figure 4 As shown, the mode signal includes a first mode sub-signal MS1 and a second mode sub-signal MS2. The first parallel-to-serial conversion circuit 10 includes a first input circuit 20, a second parallel-to-serial conversion circuit 30 and a second output circuit 40.

[0092] The input end of the first input circuit 20 is connected to the output end of each first latch circuit, and the control end of the first input circuit 20 receives the first mode sub-signal MS1, and the first mode sub-signal MS1 indicates activation of one storage area or activation of multiple storage areas. When the first mode sub-signal MS1 indicates activation of one storage area, the first input circuit 20 outputs data to the second output circuit 40. When the first mode sub-signal MS1 indicates activation of multiple storage areas, the first input circuit 20 outputs data to the second parallel-to-serial conversion circuit 30.

[0093] The input end of the second parallel-to-serial conversion circuit 30 is connected to the first output end of the first input circuit 20. The control end of the second parallel-to-serial conversion circuit 30 receives the second mode sub-signal MS2, and the second mode sub-signal MS2 indicates activation of the first number of storage areas or activation of the second number of storage areas. The second parallel-to-serial conversion circuit 30 performs parallel-to-serial conversion on the input end data based on the second mode sub-signal MS2 and outputs the result to the second output circuit 40.

[0094] The first input end of the second output circuit 40 is connected to the second output end of the first input circuit 20, and the second input end of the second output circuit 40 is connected to the output end of the second parallel-to-serial conversion circuit 30. The control end of the second output circuit 40 receives the first mode sub-signal MS1 and the logical address of the activated storage area. The second output circuit 40 outputs the data of the first input end to the data transceiver port or outputs the data of the second input end to the data transceiver port at the output end based on the first mode sub-signal MS1 and the logical address of the activated storage area.

[0095] More specifically, the first mode sub-signal MS1 represents activation of one storage region, and the second mode sub-signal MS2 represents activation of a first number of storage regions or activation of a second number of storage regions.

[0096] When the first mode sub-signal MS1 indicates activation of a storage area, the first input circuit 20 transmits the data read from the activated storage area to the first input terminal of the second output circuit 40, and the second output circuit 40 outputs the data at the first input terminal to the data transceiver port according to the logical address of the activated storage area.

[0097] When the first mode sub-signal MS1 represents the activation of multiple storage areas and the second mode sub-signal MS2 represents the activation of a first number of storage areas, the first input circuit 20 transmits the data read from the activated storage area to the input end of the second parallel-to-serial conversion circuit 30, the second parallel-to-serial conversion circuit 30 performs parallel-to-serial conversion on the data of the first number of activated storage areas and outputs it to the second output circuit 40, and then outputs it to the data transceiver port through the second output circuit 40.

[0098] When the first mode sub-signal MS1 represents the activation of multiple storage areas and the second mode sub-signal MS2 represents the activation of a second number of storage areas, the first input circuit 20 transmits the data read from the activated storage area to the input end of the second parallel-to-serial conversion circuit 30, and the second parallel-to-serial conversion circuit 30 performs parallel-to-serial conversion on the data of the second number of activated storage areas and outputs it to the second output circuit 40, and then outputs it to the data transceiver port through the second output circuit 40.

[0099] In the above technical solution, the first input circuit 20 determines the transmission path of the data of the first latch circuit based on the first mode sub-signal MS1, and if only one storage area is activated, the data is transmitted to the second output circuit 40. If multiple storage areas are activated, the data is transmitted to the second parallel-to-serial conversion circuit 30 for parallel-to-serial conversion and then output by the second output circuit 40. By setting in this way, both the case of activating one storage area and multiple storage areas can be output to the data transceiver port, and when multiple storage areas are activated, two numbers of storage areas can be activated.

[0100] In some embodiments, each storage area includes a plurality of storage columns, and each storage column includes a plurality of storage cells that share the same column selection line. Each storage column corresponds to a row address, and the third number of bit addresses in the row address from high to low is called a high-order row address, and the third number is less than the total number of row address bits in the row address. The high-order row addresses of the storage columns in the same storage area are the same, and the high-order row addresses of the storage columns are the logical addresses of the storage area. By using the high-order row address in the original row address of the memory to determine the logical address of the storage area, it can be applied to the original memory design and simplify the design.

[0101] For example: the row address of each storage column is 15 bits, and X1 to X15 represent the 1st to 15th bit addresses respectively. The 2 bits from high to low are used as the logical address, that is, X15 and X14 are used as the logical address of the storage area where the storage column is located. Accordingly, the storage array is divided into 4 storage areas. When X15 and X14 are both 0, it means the first storage area is activated. When X15 is 0 and X14 is 1, it means the second storage area is activated. When X15 is 1 and X14 is 0, it means the third storage area is activated. When X15 and X14 are both 1, it means the fourth storage area is activated.

[0102] Continue to refer Figure 4 The first input circuit 20 includes multiple first selectors, the input end of a first selector is connected to the output end of a first latch circuit, the control end of each first selector receives the first mode sub-signal MS1, the first output end of each first selector is connected to the input end of the second parallel-to-serial conversion circuit 30, and the second output end of each first selector is connected to the input end of the second output circuit 40.

[0103] More specifically, when the first mode sub-signal MS1 indicates activation of a storage area, for the activated storage area, the first selector corresponding to the storage area outputs the data latched by the first latch circuit corresponding to the storage area through the second output terminal of the first selector, so as to transmit the data latched by the first latch circuit to the second output circuit 40. When the first mode sub-signal MS1 indicates activation of multiple activated storage areas, for each activated storage area, the first selector corresponding to the activated storage area outputs the data latched by the first latch circuit corresponding to the storage area through the first output terminal of the first selector. By such a setting, if only one storage area is activated, the data is transmitted to the second output circuit 40. If multiple storage areas are activated, the data is transmitted to the second parallel-to-serial conversion circuit 30 for parallel-to-serial conversion and then output by the second output circuit 40.

[0104] Continue to refer Figure 4 The second parallel-to-serial conversion circuit 30 includes a second input circuit 31 and a third parallel-to-serial conversion circuit 32. The input end of the second input circuit 31 is connected to the output end of the first input circuit 20, the first input end of the third parallel-to-serial conversion circuit 32 is connected to the first output end of the second input circuit 31, and the second input end of the third parallel-to-serial conversion circuit 32 is connected to the second output end of the second input circuit 31.

[0105] The control end of the second input circuit 31 receives the second mode sub-signal MS2. When the second mode sub-signal MS2 indicates activation of the first number of storage areas, the second input circuit 31 outputs data to the first input end of the third parallel-to-serial conversion circuit 32. When the second mode sub-signal MS2 indicates activation of the second number of storage areas, the second input circuit 31 outputs data to the second input end of the third parallel-to-serial conversion circuit 32.

[0106] The third parallel-to-serial conversion circuit 32 performs parallel-to-serial conversion on the data at the first input end and outputs the result to the first output circuit 100 , or performs parallel-to-serial conversion on the data at the second input end and outputs the result to the first output circuit 100 .

[0107] More specifically, when the second mode sub-signal MS2 indicates activation of the first number of storage areas, the second input circuit 31 outputs data to the first input terminal of the third parallel-to-serial conversion circuit 32. The third parallel-to-serial conversion circuit 32 performs parallel-to-serial conversion on the data at the first input terminal and outputs the data to the first output circuit 100.

[0108] When the second mode sub-signal MS2 indicates activation of the second number of storage areas, the second input circuit 31 outputs data to the second input terminal of the third parallel-to-serial conversion circuit 32. The third parallel-to-serial conversion circuit 32 performs parallel-to-serial conversion on the data at the second input terminal and outputs the data to the first output circuit 100.

[0109] In the above technical solution, the second parallel-to-serial conversion circuit 30 includes a second input circuit 31 and a third parallel-to-serial conversion circuit 32. The second input circuit 31 determines the data transmission path based on the second mode sub-signal MS2, thereby realizing parallel-to-serial conversion of data in the first number or the second number of storage areas.

[0110] Continue to refer Figure 4 The second output circuit 40 includes a third selector 401 and a fourth selector 402. The input end of the third selector 401 is connected to the output end of the first input circuit 20, the output end of the third selector 401 is connected to the first input end of the fourth selector 402, the second input end of the fourth selector 402 is connected to the output end of the second parallel-to-serial conversion circuit 30, and the control end of the fourth selector 402 receives the first mode sub-signal MS1.

[0111] The control end of the third selector 401 receives the first mode sub-signal MS1 and the logical address of the activated storage area, and the third selector 401 outputs the data in the activated storage area based on the first mode sub-signal MS1 and the logical address of the activated storage area. The fourth selector 402 outputs the data of the first input end or the second input end to a data transceiver port based on the first mode sub-signal MS1.

[0112] More specifically, when the first mode sub-signal MS1 indicates activation of one storage area, the third selector 401 is enabled, and the logic address of the activated storage area is used as the selection signal of the third selector 401 to select the data in the activated storage area to be transmitted to the first input end of the fourth selector 402. When the first mode sub-signal MS1 indicates activation of multiple storage areas, the data in the multiple activated storage areas are output to the second input end of the fourth selector 402 after being converted from parallel to serial by the second parallel-to-serial conversion circuit 30. The first mode sub-signal MS1 is used as the selection signal of the fourth selector 402. When the first mode sub-signal MS1 indicates activation of one storage area, the data at the first input end of the fourth selector 402 is selected to be output, that is, the data in one activated storage area is output. When the first mode sub-signal MS1 indicates activation of multiple storage areas, the data at the second input end of the fourth selector 402 is selected to be output, that is, the data in multiple activated storage areas is output.

[0113] In the above technical solution, when only one storage area is activated, the activated storage area is output to the fourth selector 402 through the third selector 401, and transmitted to the data transceiver port by the fourth selector 402. When multiple storage areas are activated, the data is output to the data transceiver port through the fourth selector 402. In this way, the same data transceiver port can be used to output data when one storage area or multiple storage areas are activated.

[0114] The specific structure of the first parallel-to-serial conversion circuit 10 is described below by taking each storage array including four storage areas as an example, and the specific structure of the first parallel-to-serial conversion circuit 10 is not limited here. The first mode sub-signal MS1 represents the activation of one storage area or multiple storage areas. The second mode sub-signal MS2 represents the activation of two storage areas or the activation of four storage areas.

[0115] Continue to refer Figure 4 Each storage array includes 4 storage areas. Accordingly, 4 groups of data lines, 4 readout circuits and 4 first latch circuits are configured for the 4 storage areas. The first storage area is connected to the first readout circuit through the first group of data lines. The second storage area is connected to the second readout circuit through the second group of data lines. The third storage area is connected to the third readout circuit through the third group of data lines. The fourth storage area is connected to the fourth readout circuit through the fourth group of data lines.

[0116] Correspondingly, the first output circuit 100 includes four first latch circuits, the input end of the first first latch circuit 101 is connected to the output end of the first read-out circuit through the first group of data lines, the input end of the second first latch circuit 102 is connected to the output end of the second read-out circuit through the second group of data lines, the input end of the third first latch circuit 103 is connected to the output end of the third read-out circuit through the third group of data lines, and the input end of the fourth first latch circuit 104 is connected to the output end of the fourth read-out circuit through the fourth group of data lines.

[0117] When data is activated in the first storage area, the first first latch circuit 101 latches the data read from the first storage area. When data is activated in the second storage area, the second first latch circuit 102 latches the data read from the second storage area. When data is activated in the third storage area, the third first latch circuit 103 latches the data read from the third storage area. When data is activated in the fourth storage area, the fourth first latch circuit 104 latches the data read from the fourth storage area.

[0118] Accordingly, the first input circuit 20 includes four first selectors, and the second input circuit 31 includes three second selectors.

[0119] The input end of the first first selector 301 is connected to the output end of the first first latch circuit 101, the input end of the second first selector 302 is connected to the output end of the second first latch circuit 102, the input end of the third first selector 303 is connected to the output end of the third first latch circuit 103, and the input end of the fourth first selector 304 is connected to the output end of the fourth first latch circuit 104.

[0120] The input end of the first second selector 305 is connected to the first output end of the first first selector 301, the second output end of the first second selector 305 is connected to the first input end of the third parallel-to-serial conversion circuit 32, and the first output end of the first second selector 305 is connected to the first output end of the second second selector 306.

[0121] The input end of the second second selector 306 is connected to the first output end of the second first selector 302, the second output end of the second second selector 306 is connected to the first input end of the third parallel-to-serial conversion circuit 32, and the first output end of the second second selector 306 is connected to the second input end of the third parallel-to-serial conversion circuit 32.

[0122] The input end of the third second selector 307 is connected to the first output end of the third first selector 303, the second output end of the third second selector 307 is connected to the first input end of the third parallel-to-serial conversion circuit 32, the first output end of the third second selector is connected to the first output end of the fourth first selector 304, and the first output end of the third second selector is connected to the second input end of the third parallel-to-serial conversion circuit 32.

[0123] Correspondingly, the first output end of the second input circuit includes the second output end of the first second selector 305 , the second output end of the second second selector 306 , the second output end of the third second selector 307 and the second output end of the fourth first selector 304 .

[0124] The second output end of the second input circuit includes the first output end of the second second selector 306 and the first output end of the third second selector 307 .

[0125] The third parallel-to-serial conversion circuit 32 includes four second latch circuits. The input end of the first second latch circuit 201 is connected to the second output end of the first second selector 305 , and the output end of the first second latch circuit 201 is connected to the input end of the second second latch circuit 202 .

[0126] An input end of the second second latch circuit 202 is connected to a second output end of the second second selector 306 , and an output end of the second second latch circuit 202 is connected to an input end of the third second latch circuit 203 .

[0127] The input end of the third second latch circuit 203 is connected to the second output end of the third second selector 307, the input end of the third second latch circuit 203 is connected to the first output end of the second second selector 306, and the output end of the third second latch is connected to the input end of the fourth second latch circuit 204.

[0128] An input end of the fourth second latch circuit 204 is connected to a first output end of the third second selector 307 , and an output end of the fourth second latch circuit 204 is an output end of the third parallel-to-serial conversion circuit 32 .

[0129] Correspondingly, the first input end of the third parallel-to-serial conversion circuit includes the input end of the first second latch circuit 201, the input end of the second second latch circuit 202, the input end of the third second latch circuit 203, and the input end of the fourth second latch circuit 204. The second input end of the third parallel-to-serial conversion circuit includes the input end of the third second latch circuit 203 and the input end of the fourth second latch circuit 204.

[0130] Among them, the third selector 401 includes four input terminals, the first input terminal of the third selector 401 is connected to the second output terminal of the first first selector 301, the second input terminal of the third selector 401 is connected to the second output terminal of the second first selector 302, the third input terminal of the third selector 401 is connected to the second output terminal of the third first selector 303, and the fourth input terminal of the third selector 401 is connected to the second output terminal of the fourth first selector 304.

[0131] The control end of the second latch circuit receives the second clock signal DQSCK, the control end of the first latch circuit receives the first clock signal CK_t, and the frequency of the second clock signal DQSCK is an integer multiple of the frequency of the first clock signal CK_t. The specific multiple is determined by the number of activated storage areas. When the number of activated storage areas is 2, the frequency of the second clock signal DQSCK is twice the frequency of the first clock signal CK_t. When the number of activated storage areas is 4, the frequency of the second clock signal DQSCK is 4 times the frequency of the first clock signal CK_t.

[0132] When the first mode sub-signal MS1 indicates activation of one storage area, any one of the first storage area to the fourth storage area may be activated.

[0133] If the first storage area is activated, the first first selector 301 outputs the data read from the first storage area to the second output end of the first first selector 301 , and then outputs the data to the data transceiver port through the second output circuit 40 .

[0134] If the second storage area is activated, the second first selector 302 outputs the data read from the second storage area to the second output end of the second first selector 302 , and then outputs the data to the data transceiver port through the second output circuit 40 .

[0135] If the third storage area is activated, the third first selector 303 outputs the data read from the third storage area to the second output end of the third first selector 303 , and then outputs the data to the data transceiver port through the second output circuit 40 .

[0136] If the fourth storage area is activated, the fourth first selector 304 outputs the data read from the fourth storage area to the second output end of the fourth first selector 304 , and then outputs the data to the data transceiver port through the second output circuit 40 .

[0137] Figure 5 This is a schematic diagram of activating a storage area in a storage array, such as Figure 5 As shown, each storage region includes m storage sub-arrays. One storage sub-array in a storage region is activated each time. Figure 5 , the first storage subarray in the first storage area is activated, and the activated storage subarray is indicated by dot filling. After reading the data of the first storage subarray in the first storage area, the second storage subarray in the first storage area can be activated. After reading the data of the second storage subarray in the first storage area, the third storage subarray in the first storage area can be activated. And so on, until all storage subarrays in the first storage area are activated, each storage subarray in the second storage area can be activated.

[0138] It should be noted here that the subsequent description of reading data from a storage area refers to reading data from a storage sub-array in a storage area.

[0139] Figure 6 This is the data flow diagram for activating one storage area in the storage area. Figure 6 As shown, when the first storage area is activated, the first first latch circuit 101 latches the data of the first storage area at the output end. The output ends of the second first latch circuit 102 to the fourth first latch circuit 104 maintain the default level. Under the control of the first mode sub-signal MS1, the first first selector 301 outputs the data of the first storage area to the second output end of the first first selector 301. Under the control of the first mode sub-signal MS1, the second first selector 302 outputs the default level to the second output end of the second first selector 302. Under the control of the first mode sub-signal MS1, the third first selector 303 outputs the default level to the second output end of the third first selector 303. Under the control of the first mode sub-signal MS1, the fourth first selector 304 outputs the default level to the second output end of the fourth first selector 304. That is, the data path from the first first selector 301 to the fourth first selector 304 is shown as a solid line.

[0140] The third selector 401 includes 4 input terminals, the first input terminal of the third selector 401 receives the data of the first storage area, and the second to fourth input terminals of the third selector 401 receive the default level. The control terminal of the third selector 401 receives the logical address of the first storage area, and the data output of the first input terminal is selected by the logical address of the first storage area. Through such a setting, the data of the first storage area is output to a data transceiver port.

[0141] Figure 7 This is a timing diagram for activating a storage area in the storage array. Figure 7 As shown, under the control of the clock signal CLK, the command CMD and the address BA of the storage array are received, for example, the received command is the read command signal RAED and the column selection signal CAS, and the received address is the address BA<2:0> of the storage array. The activated storage area is processed by the first output circuit 100 and then output to a data transceiver port DQ. For example, it can be output to any one of the data transceiver ports DQ0 to DQ7.

[0142] Here, it is taken that the data read out from a storage area is 64 bits and there are 8 data transceiver ports as an example. Accordingly, there are 8 first output circuits, each of which receives 8 bits of serial data, which are marked as D0-D7 (represented by 0-7 in the figure). The 8 bits of serial data pass through the output end of the first first latch circuit 101, the input end of the first first selector 301, the second output end of the first first selector 301, the first input end of the third selector 401, the output end of the third selector 401, the first input end of the fourth selector 402 to the output end of the fourth selector 402, and are finally output through one data transceiver port.

[0143] When the first mode sub-signal MS1 indicates that a plurality of storage regions are activated, the second mode sub-signal MS2 indicates that four storage regions are activated. Figure 8 Schematic diagram of activating 4 storage areas in the storage array, and Figure 5The difference is that the data of the first storage subarray in the first storage area, the data of the first storage subarray in the second storage area, the data of the first storage subarray in the third storage area, and the first storage subarray in the fourth storage area are read simultaneously first, and then the data of the second storage subarray in the first storage area, the data of the second storage subarray in the second storage area, the data of the second storage subarray in the third storage area, and the second storage subarray in the fourth storage area are read simultaneously, and then the data of the third storage subarray in the first storage area, the data of the third storage subarray in the second storage area, the data of the third storage subarray in the third storage area, and the third storage subarray in the fourth storage area are read simultaneously. And so on, until all storage subarrays in each storage area are read.

[0144] Fig. 9 This is the data flow diagram for activating the four storage areas in the storage area. Fig. 9 As shown, when the first storage area, the second storage area, the third storage area and the fourth storage area are activated, the first first selector 301 outputs the data read from the first storage area to the first output end of the first first selector 301, and the input end of the first second selector 305 is connected to the first output end of the first first selector 301, the first second selector 305 outputs the data read from the first storage area to the second output end of the first second selector 305, and the second output end of the first second selector 305 is connected to the input end of the first second latch circuit 201, so that the first second latch circuit 201 receives the data in the first storage area.

[0145] The second first selector 302 outputs the data read from the second storage area to the first output end of the second first selector 302, and the input end of the second second selector 306 is connected to the first output end of the second first selector 302, and the second second selector 306 outputs the data read from the second storage area to the second output end of the second second selector 306, and the second output end of the second second selector 306 is connected to the input end of the second second latch circuit 202, so that the second second latch circuit 202 receives the data read from the second storage area.

[0146] The third first selector 303 outputs the data read from the third storage area to the first output end of the third first selector 303, and the input end of the third second selector 307 is connected to the first output end of the third first selector 303, and the third second selector 307 outputs the data read from the third storage area to the second output end of the third second selector 307, and the second output end of the third second selector 307 is connected to the input end of the third second latch circuit 203, so that the third second latch circuit 203 receives the data read from the third storage area.

[0147] The fourth first selector 304 outputs the data read from the fourth storage area to the first output terminal of the fourth first selector 304. The first output terminal of the fourth first selector 304 is connected to the input terminal of the fourth second latch circuit 204, so that the fourth second latch circuit 204 receives the data read from the fourth storage area. Under the control of the clock signal, the four latch circuits convert the data of the four storage areas into parallel and serial data and then output them.

[0148] Here, the data read out from a storage area is 64 bits, and there are 8 data transceiver ports as an example. Accordingly, there are 8 first output circuits, and each first output circuit receives 8 bits of serial data from a storage area, which are marked as D0-D7 (shown as 0, 1, ..., 7 in the attached figure). When 4 storage areas are activated, the first storage area transmits 8 bits of data to each first output circuit, the second storage area transmits 8 bits of data to each first output circuit, the third storage area transmits 8 bits of data to each first output circuit, and the fourth storage area transmits 8 bits of data to each first output circuit, that is, each first output circuit receives 32 bits of data.

[0149] Continue to refer Fig. 9 , the solid line represents the data transmission path. The 8-bit serial data of the first storage area passes through the output end of the first first latch circuit 101, the input end of the first first selector 301, the first output end of the first first selector 301, the input end of the first second selector 305, the second output end of the first second selector 305, and enters the input end of the first second latch circuit 201.

[0150] The 8-bit serial data of the second storage area passes through the output end of the second first latch circuit 102, the input end of the second first selector 302, the first output end of the second first selector 302, the input end of the second second selector 306, the second output end of the second second selector 306, and enters the input end of the second second latch circuit 202.

[0151] The 8-bit serial data of the third storage area passes through the output end of the third first latch circuit 103, the input end of the third first selector 303, the first output end of the third first selector 303, the input end of the third second selector 307, the second output end of the third second selector 307, and enters the input end of the third second latch circuit 203.

[0152] The 8-bit serial data of the 4th storage area is output through the output end of the 4th first latch circuit 104 , the input end of the 4th first selector 304 , and the first output end of the 4th first selector 304 , and enters the input end of the 4th second latch circuit 204 .

[0153] Considering that increasing the number of concurrent data will cause data interference, a first latch circuit is added to buffer the concurrent data. At the same time, a parallel-to-serial conversion circuit needs to be designed so that the data can be output according to the preset timing requirements. More specifically, the format of converting parallel data to serial data is determined according to the number of parallel data.

[0154] Since the frequency of the second clock signal DQSCK is 4 times the frequency of the first clock signal CK_t. Four second clock signals DQSCK are received within a cycle of the first clock signal CK_t. After four cycles of the first clock signal CK_t, the input end of the first second latch circuit 201 receives 8-bit data of the first storage area. The input end of the second second latch circuit 202 receives 8-bit data of the first storage area. The input end of the third second latch circuit 203 receives 8-bit data of the first storage area. The input end of the fourth second latch circuit 204 receives 8-bit data of the first storage area. Within the first half cycle of the first clock signal CK_t, the input end of the first second latch circuit 201 receives 1-bit data of the first storage area. The input end of the second second latch circuit 202 receives 1-bit data of the first storage area. The input end of the third second latch circuit 203 receives 1-bit data of the first storage area. The input terminal of the fourth second latch circuit 204 receives the 1-bit data of the first storage area.

[0155] Here, taking the upper half cycle of the first first clock signal CK_t as an example, when the rising edge of the first first clock signal CK_t is received, the input end of the first second latch circuit 201 receives D0 of the first storage area, the input end of the second second latch circuit 202 receives D0 of the second storage area, the input end of the third second latch circuit 203 receives D0 of the third storage area, and the input end of the fourth second latch circuit 204 receives D0 of the fourth storage area.

[0156] At the rising edge of the first second clock signal DQSCK, the output end of the fourth second latch circuit 204 latches D0 of the fourth storage area, the output end of the third second latch circuit 203 latches D0 of the third storage area, the output end of the second second latch circuit 202 latches D0 of the second storage area, and the output end of the first second latch circuit 201 latches D0 of the first storage area.

[0157] At the falling edge of the first second clock signal DQSCK, the output end of the fourth second latch circuit 204 latches D0 of the third storage area, the output end of the third second latch circuit 203 latches D0 of the second storage area, and the output end of the second second latch circuit 202 latches D0 of the first storage area.

[0158] At the rising edge of the second second clock signal DQSCK, the output end of the fourth second latch circuit 204 latches D0 of the second storage area, and the output end of the third second latch circuit 203 latches D0 of the second storage area.

[0159] At the falling edge of the second second clock signal DQSCK, the output end of the fourth second latch circuit 204 latches D0 of the first storage area.

[0160] Fig.10 This is a timing diagram for activating four storage areas in the storage array. Fig.10 As shown, in the first half cycle of the first clock signal CK_t, D0 of the four storage areas is converted from parallel to serial and then output to the second input end of the fourth selector 402, and then output to the data transceiver port from the output end of the fourth selector 402.

[0161] The working process of the four second latch circuits under the second first clock signal CK_t to the fourth first clock signal CK_t is similar to the working process of the first first clock signal CK_t, which will not be repeated here.

[0162] In the above technical solution, each storage array is divided into four storage areas, each storage area uses an independent data line and read circuit, and the storage columns at the same position in the four storage areas are activated. The data of the four storage areas can be output simultaneously, and the data output is increased from the original 8 bits to 32 bits. It only takes 1 / 4 of the original time to read out all the data of the entire storage array, and the number of read commands is also 1 / 4 of the original.

[0163] When the first mode sub-signal MS1 indicates activation of multiple storage areas and the second mode sub-signal MS2 indicates activation of two storage areas, for example, the first storage area and the third storage area are activated, or the second storage area and the fourth storage area are activated.

[0164] Fig.11 Schematic diagram of activating two storage areas in the storage array, and Figure 8 The difference is that the data of the first storage area and the data of the third storage area are read simultaneously first, then the data of the second storage subarray in the first storage area and the data of the second storage subarray in the third storage area are read simultaneously, then the data of the third storage subarray in the first storage area and the data of the third storage subarray in the third storage area are read simultaneously. And so on, until all the storage subarrays in the first storage area and the third storage area are read simultaneously. Then the data of the first storage subarray in the second storage area and the data of the first storage subarray in the fourth storage area are read simultaneously, then the data of the second storage subarray in the second storage area and the data of the second storage subarray in the fourth storage area are read simultaneously, then the data of the third storage subarray in the second storage area and the data of the third storage subarray in the fourth storage area are read simultaneously. And so on, until all the storage subarrays in the second storage area and the fourth storage area are read simultaneously.

[0165] Fig.12 This is the data flow diagram for activating two storage areas in the storage area. Fig.12 As shown, when the first storage area and the third storage area are activated, the first first selector 301 outputs the data read from the first storage area to the first output terminal of the first first selector 301, and the input terminal of the first second selector 305 is connected to the first output terminal of the first first selector 301, and the first second selector 305 outputs the data read from the first storage area to the first output terminal of the first second selector 305, and the first output terminal of the first second selector 305 is connected to the input terminal of the third second latch circuit 203, and the input terminal of the third second latch circuit 203 receives the data read from the first storage area.

[0166] The third first selector 303 outputs the data read from the third storage area to the first output end of the third first selector 303, and the input end of the third second selector 307 is connected to the first output end of the third first selector 303. The third second selector 307 outputs the data read from the first storage area to the first output end of the third second selector 307. The first output end of the third second selector 307 is connected to the input end of the fourth second latch circuit 204, and the input end of the fourth second latch circuit 204 receives the data read from the third storage area. Under the control of the clock signal, the two latch circuits perform parallel-to-serial conversion on the data of the two storage areas and output them.

[0167] Here, the data read from a storage area is 64 bits, and there are 8 data transceiver ports. Correspondingly, there are 8 first output circuits, and each first output circuit receives 8 bits of serial data from a storage area, which are marked as D0-D7 (shown as 0, 1, ..., 7 in the attached figure). When 2 storage areas are activated, the first storage area transmits 8 bits of data to each first output circuit, and the third storage area transmits 8 bits of data to each first output circuit. That is, each first output circuit receives 16 bits of data.

[0168] Continue to refer Fig.12 , the solid line represents the data transmission path. When the first storage area and the third storage area are activated, the 8-bit serial data of the first storage area passes through the output end of the first first latch circuit 101, the input end of the first first selector 301, the first output end of the first first selector 301, the input end of the first second selector 305, the first output end of the first second selector 305, and enters the input end of the third second latch circuit 203.

[0169] The 8-bit serial data of the third storage area passes through the output end of the third first latch circuit 103, the input end of the third first selector 303, the first output end of the third first selector 303, the input end of the third second selector 307, the first output end of the third second selector 307, and enters the input end of the fourth second latch circuit 204.

[0170] When the second storage area and the fourth storage area are activated, the second first selector 302 outputs the data read from the second storage area to the first output end of the second first selector 302, and the input end of the second second selector 306 is connected to the first output end of the second first selector 302, and the second second selector 306 outputs the data read from the second storage area to the first output end of the second second selector 306, and the first output end of the second second selector 306 is connected to the input end of the third second latch circuit 203, and the input end of the third second latch circuit 203 receives the data read from the second storage area.

[0171] The fourth first selector 304 outputs the data read from the fourth storage area to the first output terminal of the fourth first selector 304. The input terminal of the fourth second latch circuit 204 is connected to the first output terminal of the fourth first selector 304. The input terminal of the fourth second latch circuit 204 receives the data read from the fourth storage area. Under the control of the clock signal, the two latch circuits perform parallel-to-serial conversion on the data of the two storage areas and output them.

[0172] Here, it is taken that the data read out from a storage area is 64 bits, and there are 8 data transceiver ports. Correspondingly, there are 8 first output circuits, and each first output circuit receives 8 bits of serial data from a storage area, which are marked as D0-D7 (shown as 0, 1, ..., 7 in the attached figure). When 2 storage areas are activated, the second storage area transmits 8 bits of data to each first output circuit, and the fourth storage area transmits 8 bits of data to each first output circuit. That is, each first output circuit receives 16 bits of data. Continue to refer to Fig.12 The solid line represents the data transmission path.

[0173] The 8-bit serial data of the second storage area passes through the output end of the second first latch circuit 102, the output end of the second first selector 302, the first output end of the second first selector 302, the input end of the second second selector 306, the first output end of the second second selector 306, and enters the input end of the third second latch circuit 203.

[0174] The 8-bit serial data of the 4th storage area is output through the output end of the 4th first latch circuit 104 , the output end of the 4th first selector 304 , and the first output end of the 4th first selector 304 , and enters the input end of the 4th second latch circuit 204 .

[0175] Since the frequency of the second clock signal DQSCK is twice the frequency of the first clock signal CK_t, two second clock signals DQSCK are received within a cycle of the first clock signal CK_t. After four cycles of the first clock signal CK_t, the input end of the first second latch circuit 201 receives 8-bit data from the first storage area. The input end of the third second latch circuit 203 receives 8-bit data from the third storage area. Within the first half cycle of the first clock signal CK_t, the input end of the first second latch circuit 201 receives 1-bit data from the first storage area. The input end of the third second latch circuit 203 receives 1-bit data from the first storage area.

[0176] Taking the first first clock signal CK_t as an example, when the first second clock signal DQSCK is received, the input end of the third second latch circuit 203 receives D0 of the first storage area, and the input end of the fourth second latch circuit 204 receives D0 of the third storage area.

[0177] At the rising edge of the first second clock signal DQSCK, the output end of the fourth second latch circuit 204 latches D0 of the third storage area, and the output end of the third second latch circuit 203 latches D0 of the first storage area. At the falling edge of the first second clock signal DQSCK, the output end of the fourth second latch circuit 204 latches D0 of the first storage area.

[0178] Fig.13 This is a timing diagram for activating two storage areas in the storage array. Fig.13 As shown, in the first half cycle of the first clock signal, the data of the first storage sub-array of the two storage areas are converted from parallel to serial and then output to the input end of the fourth selector 402.

[0179] In the above technical solution, each storage array is divided into four storage areas, each storage area uses an independent data line and read circuit, and the storage columns at the same position in two storage areas are activated. The data of the two storage areas can be output simultaneously, and the data output is increased from the original 8 bits to 16 bits. It only takes 1 / 2 of the original time to read out all the data of the entire storage array, and the number of read commands is also 1 / 2 of the original.

[0180] like Fig.14 As shown, some embodiments of the present application further provide a memory, wherein the first parallel-to-serial conversion circuit 10 includes a third input circuit 50 , a fourth parallel-to-serial conversion circuit 60 and a third output circuit 70 .

[0181] The input end of the third input circuit 50 is connected to the output end of each first latch circuit, and the control end of the third input circuit 50 receives the first mode signal MS1, and the first mode signal MS1 indicates activation of one storage area or activation of multiple storage areas. When the first mode signal MS1 indicates activation of one storage area, the third input circuit 50 outputs data to the third output circuit 70. When the first mode signal MS1 indicates activation of multiple storage areas, the third input circuit 50 outputs data to the fourth parallel-to-serial conversion circuit 60.

[0182] The input end of the fourth parallel-to-serial conversion circuit 60 is connected to the first output end of the third input circuit 50. The fourth parallel-to-serial conversion circuit 60 performs parallel-to-serial conversion on the input end data and outputs it to the third output circuit 70. The first input end of the third output circuit 70 is connected to the second output end of the third input circuit 50. The second input end of the third output circuit 70 is connected to the output end of the fourth parallel-to-serial conversion circuit 60. The control end of the third output circuit 70 receives the first mode signal MS1 and the logical address of the activated storage area. The third output circuit 70 outputs the data of the first input end to the data transceiver port or the data of the second input end to the data transceiver port at the output end based on the first mode signal MS1 and the logical address of the activated storage area. With such a configuration, both the activation of one storage area and multiple storage areas can be output to the data transceiver port, which is the same as Figure 4 The structural memory shown differs in that, when activating a plurality of memory areas, only one number of memory areas can be activated.

[0183] In some embodiments, the third input circuit 50 includes multiple fifth selectors, the input end of a fifth selector is connected to the output end of a first latch circuit, the control end of each fifth selector receives the first mode signal MS1, the first output end of each fifth selector is connected to the input end of the fourth parallel-to-serial conversion circuit 60, and the second output end of each fifth selector is connected to the input end of the third output circuit 70.

[0184] Continuing to take the example that each storage array includes 4 storage areas, the input end of the first fifth selector 501 is connected to the output end of the first first latch circuit to receive data in the first storage area. When the mode signal indicates activation of one storage area, the first fifth selector 501 transmits the data in the first storage area to the second output end of the first fifth selector 501. When the mode signal indicates activation of multiple storage areas, the first fifth selector 501 transmits the data in the first storage area to the first output end of the first fifth selector 501. The data transmission paths of the second fifth selector 502, the second fifth selector 503 and the fourth fifth selector 504 are similar and will not be described in detail here.

[0185] Correspondingly, the fourth parallel-to-serial conversion circuit 60 includes four third latch circuits, the input end of the first third latch circuit 601 is connected to the first output end of the first fifth selector, and the output end of the first third latch circuit 601 is connected to the input end of the second third latch circuit 602. The input end of the second third latch circuit 602 is connected to the first output end of the second fifth selector 502, and the output end of the second third latch circuit 602 is connected to the input end of the third third latch circuit 603. The input end of the third third latch circuit 603 is connected to the first output end of the third fifth selector 503, and the output end of the third second latch 603 is connected to the input end of the fourth third latch circuit 604. The input end of the fourth third latch circuit 604 is connected to the first output end of the fourth fifth selector 504, and the output end of the fourth third latch circuit 604 is the output end of the fourth parallel-to-serial conversion circuit 60. When the first mode signal MS1 indicates that four storage areas are activated, the four third latch circuits are used to convert the data in the four storage areas into serial and parallel data and then output the data. Fig. 9 and Fig.10 The description is not repeated here.

[0186] The third output circuit 70 includes a fifth selector 701 and a sixth selector 702. The input end of the fifth selector 701 is connected to the output end of the third input circuit 50, the output end of the fifth selector 701 is connected to the first input end of the sixth selector 702, the second input end of the sixth selector 702 is connected to the output end of the fourth parallel-to-serial conversion circuit 60, and the control end of the sixth selector 702 receives the first mode sub-signal MS1. The third output circuit 70 is similar to the second output circuit 40 in principle, and will not be described in detail here.

[0187] Some embodiments of the present application further provide a memory testing method, wherein the memory includes a plurality of memory arrays, each memory array includes a plurality of storage areas, and the testing method specifically includes the following steps:

[0188] S101, writing background data into each storage array of a memory, and reading data from each storage array in turn.

[0189] Wherein, reading data from a storage array specifically includes:

[0190] At the same time, at least one storage area is activated, data is read from the at least one activated storage area, and the data read from the at least one activated storage area is converted from parallel to serial and then output to a data transceiver port.

[0191] The bit positions of the data read from each storage area are integer multiples of the burst length, and the bit positions of the data output by the data transceiver port are integer multiples of the burst length.

[0192] S102, obtaining a test result after comparing the background data written into each storage array with the data read out of each storage array.

[0193] If the background data written is the same as the read data, it means that the storage array has good performance. If the background data written is different from the read data, it means that the storage array has poor performance.

[0194] In the above technical solution, by activating at least one storage area and converting the data read from the at least one activated storage area into parallel and serial data and then outputting it to a data transceiver port, the data read time can be reduced, the number of read instructions can be reduced, and the test efficiency can be improved.

[0195] In some embodiments, the data read from at least one activated storage area is converted from parallel to serial and then output to a data transceiver port, specifically including:

[0196] Data of one burst length is obtained from the data read from each activated storage area.

[0197] Data of a burst length in the read data of all activated storage areas are converted from parallel to serial and then output to a data transceiver port.

[0198] When a storage area is activated, the bits of the data read out from the storage area are integer multiples of the burst length. Data of a burst length is taken out from the data read out from the storage area, and data of a burst length taken out from each activated storage area is converted from parallel to serial and then output to a data transceiver port, which can make full use of the existing data transceiver port of the memory to output concurrent data and simplify the structure of the memory.

[0199] Some embodiments of the present application also provide a memory testing method, the testing method comprising the following steps:

[0200] S201, initialize the memory and complete the basic configuration of the memory.

[0201] S202: Write background data into the memory.

[0202] S203, executing a read instruction, after activating a word line of one storage sub-array in a storage area, the word lines of the storage sub-arrays at the same position in other storage areas can be turned on to activate multiple storage areas, and data can be read from each activated storage area.

[0203] S204, converting the data in a storage column in each activated storage area into serial data and outputting the converted data to a data transceiver port.

[0204] Among them, a storage column includes multiple storage units using the same column selection line, and the bit of data in a storage column is a burst length. By opening multiple storage columns, data of an integer multiple of the burst length can be output. The data in a storage column in each activated storage area is converted from parallel to serial and then output to a data transceiver port.

[0205] For example: 2 storage areas are activated at the same time, 8 storage columns are activated in each storage area, 8 bits of data are read out from a storage column, and 64 bits of data can be read out from each storage area. The 8 bits of data in the first storage column of the first activated storage area and the 8 bits of data in the first storage column of the second activated storage area are converted into 16 bits of data after being parallel-to-serial converted, and the 16 bits of serial data are output through the first data transceiver port. The 8 bits of data in the second storage column of the first activated storage area and the 8 bits of data in the second storage column of the second activated storage area are converted into 16 bits of data after being parallel-to-serial converted, and the 16 bits of serial data are output through the second data transceiver port. And so on, 128 bits of data can be output through 8 data transceiver ports.

[0206] S205. After reading the data of all columns on the current word line, if all word lines have been read, the process can be stopped. If not all word lines have been read, the next word line can be opened and the process returns to S203.

[0207] In the above technical solution, by activating at least one storage area at a time, the amount of concurrent data can be increased, the number of instructions can be reduced, the data read efficiency can be improved, the test time can be reduced, and the test cost can be reduced.

[0208] It should be noted that the high level and low level referred to in the above embodiments are relative concepts (i.e., the voltage value of the high level is higher than the voltage value of the corresponding low level), and the specific voltage value of the high level is not limited, nor is the specific voltage value of the low level. In addition, it is not limited that the high levels applied to different signal lines in this specific embodiment are equal, for example, the high level on the bit line and the high level on the word line can be different voltages, nor is it limited that the high levels of a specific signal line at different stages are equal, for example, the high level applied to the bit line when writing 1 and when reading can be different voltage values. Those skilled in the art should understand that the corresponding high level and low level values ​​can be set according to the process node, speed requirements, reliability requirements, etc.

[0209] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0210] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A memory, characterized in that: include: A plurality of storage arrays, each storage array comprising a plurality of storage areas; The memory further includes a plurality of readout circuits and a first output circuit; Each of the storage areas is connected to the corresponding readout circuit via a data line, at least one storage area in the memory is activated, and the readout circuit corresponding to the activated storage area reads data from the activated storage area and outputs it at the output end; The output end of the readout circuit is connected to the input end of the first output circuit, and the first output circuit sequentially outputs the output data of at least one output end of the readout circuit to a data transceiver port of the memory; The bit position of the data output by each of the readout circuits is an integer multiple of the burst length, and the bit position of the data output by the data transceiver port is an integer multiple of the burst length.

2. The memory according to claim 1, characterized in that: There are a plurality of the first output circuits, each of which corresponds to one of the data transceiver ports, and each of which is connected to output ends of a plurality of readout circuits; The readout circuit corresponding to the activated storage area outputs data of a burst length to each of the first output circuits, and the data received by each first output circuit is located at a different position in the storage area; each first output circuit performs parallel-to-serial conversion on the data of at least one storage area and outputs it to the corresponding data transceiver port.

3. The memory according to claim 1 or 2, characterized in that: The first output circuit includes a plurality of first latch circuits and a first parallel-to-serial conversion circuit; The input end of the first latch circuit is connected to the corresponding readout circuit, and the first latch circuit latches the data output by the readout circuit at the output end; The output end of each of the first latch circuits is connected to the input end of the first parallel-to-serial conversion circuit. The control end of the first parallel-to-serial conversion circuit also receives a mode signal, and the mode signal is used to characterize the number of activated storage areas. The first parallel-to-serial conversion circuit sequentially outputs the data of the output end of at least one of the first latch circuits to a data transceiver port of the memory.

4. The memory according to claim 3, characterized in that: The mode signal includes a first mode sub-signal and a second mode sub-signal; the first parallel-to-serial conversion circuit includes a first input circuit, a second parallel-to-serial conversion circuit and a second output circuit; The input end of the first input circuit is connected to the output end of each of the first latch circuits, and the control end of the first input circuit receives a first mode sub-signal, wherein the first mode sub-signal indicates activation of one of the storage areas or activation of multiple storage areas; When the first mode sub-signal indicates activation of one storage area, the first input circuit outputs data to the second output circuit; when the first mode sub-signal indicates activation of multiple storage areas, the first input circuit outputs data to the second parallel-to-serial conversion circuit; The input end of the second parallel-to-serial conversion circuit is connected to the first output end of the first input circuit, the control end of the second parallel-to-serial conversion circuit receives a second mode sub-signal, and the second mode sub-signal indicates activation of the first number of storage areas or activation of the second number of storage areas; the second parallel-to-serial conversion circuit performs parallel-to-serial conversion on the input end data based on the second mode sub-signal and outputs the result to the second output circuit; The first input end of the second output circuit is connected to the second output end of the first input circuit, the second input end of the second output circuit is connected to the output end of the second parallel-to-serial conversion circuit, and the control end of the second output circuit receives the first mode sub-signal and the logical address of the activated storage area; the second output circuit outputs the data of the first input end to the data transceiver port or outputs the data of the second input end to the data transceiver port at the output end based on the first mode sub-signal and the logical address of the activated storage area.

5. The memory according to claim 4, characterized in that: The first input circuit includes a plurality of first selectors; An input end of one of the first selectors is connected to an output end of one of the first latch circuits, a control end of each of the first selectors receives the first mode sub-signal, a first output end of each of the first selectors is connected to an input end of the second parallel-to-serial conversion circuit, and a second output end of each of the first selectors is connected to an input end of the second output circuit.

6. The memory according to claim 4, characterized in that: The second parallel-to-serial conversion circuit includes a second input circuit and a third parallel-to-serial conversion circuit; The input end of the second input circuit is connected to the output end of the first input circuit, the control end of the second input circuit receives a second mode sub-signal, and when the second mode sub-signal indicates activation of the first number of the storage areas, the second input circuit outputs data to the first input end of the third parallel-to-serial conversion circuit; when the second mode sub-signal indicates activation of the second number of the storage areas, the second input circuit outputs data to the second input end of the third parallel-to-serial conversion circuit; The first input end of the third parallel-to-serial conversion circuit is connected to the first output end of the second input circuit, and the second input end of the third parallel-to-serial conversion circuit is connected to the second output end of the second input circuit. The third parallel-to-serial conversion circuit performs parallel-to-serial conversion on the data at the first input end and outputs it to the first output circuit, or performs parallel-to-serial conversion on the data at the second input end and outputs it to the first output circuit.

7. The memory according to claim 6, characterized in that: The first input circuit includes four first selectors, and the second input circuit includes three second selectors; The input end of the first second selector is connected to the first output end of the first first selector, the second output end of the first second selector is connected to the first input end of the third parallel-to-serial conversion circuit, and the first output end of the first second selector is connected to the first output end of the second second selector; The input end of the second second selector is connected to the first output end of the second first selector, the second output end of the second second selector is connected to the first input end of the third parallel-to-serial conversion circuit, and the first output end of the second second selector is connected to the second input end of the third parallel-to-serial conversion circuit; The input end of the third second selector is connected to the first output end of the third first selector, the second output end of the third second selector is connected to the first input end of the third parallel-to-serial conversion circuit, the first output end of the third second selector is connected to the first output end of the fourth first selector, and the first output end of the third second selector is connected to the second input end of the third parallel-to-serial conversion circuit.

8. The memory according to claim 7, characterized in that: The third parallel-to-serial conversion circuit includes four second latch circuits; An input end of the first second latch circuit is connected to the second output end of the first second selector, and an output end of the first second latch circuit is connected to an input end of the second second latch circuit; The input end of the second second latch circuit is connected to the second output end of the second second selector, and the output end of the second second latch circuit is connected to the input end of the third second latch circuit; The input end of the third second latch circuit is connected to the second output end of the third second selector, the input end of the third second latch circuit is connected to the first output end of the second second selector, and the output end of the third second latch is connected to the input end of the fourth second latch circuit; The input end of the fourth second latch circuit is connected to the first output end of the third second selector, and the output end of the fourth second latch circuit is the output end of the third parallel-to-serial conversion circuit.

9. The memory according to claim 4, characterized in that: The second output circuit includes a third selector and a fourth selector; The input end of the third selector is connected to the output end of the first input circuit, the output end of the third selector is connected to the first input end of the fourth selector, the control end of the third selector receives the first mode sub-signal and the logical address of the activated storage area, and the third selector outputs the data in the activated storage area based on the first mode sub-signal and the logical address of the activated storage area; The second input end of the fourth selector is connected to the output end of the second parallel-to-serial conversion circuit, the control end of the fourth selector receives the first mode sub-signal, and the fourth selector outputs the data of the first input end or the second input end to a data transceiver port of the memory based on the first mode sub-signal.

10. The memory according to claim 9, characterized in that: The third selector includes four input terminals; The first input end of the third selector is connected to the second output end of the first first selector, the second input end of the third selector is connected to the second output end of the second first selector, the third input end of the third selector is connected to the second output end of the third first selector, and the fourth input end of the third selector is connected to the second output end of the fourth first selector.

11. The memory according to claim 4, characterized in that: Each storage area includes a plurality of storage columns; Each of the storage columns corresponds to a row address, and the third number of bit addresses in the row address from high to low is called a high-order row address, and the third number is less than the total number of row address bits in the row address; The high-order row addresses of the storage columns in the same storage area are the same, and the high-order row addresses of the storage columns are the logical addresses of the storage area.

12. The memory according to claim 1 or 2, characterized in that: The memory further comprises a plurality of groups of data lines, each group of data lines comprising a global data line and a local data line; Each of the readout circuits is connected to a group of data lines. The readout circuit reads the data stored in the corresponding storage area through the corresponding data line. Each of the readout circuits also outputs data to the first output circuit through the data line.

13. The memory according to claim 3, characterized in that: The memory also includes a plurality of driving circuits; Each driving circuit input terminal is connected to an output terminal of the readout circuit through a data line, and the output terminal of the driving circuit is connected to an input terminal of the first latch circuit.

14. A memory testing method, characterized in that: The memory includes a plurality of storage arrays, each storage array includes a plurality of storage areas; the method includes: Writing background data into each storage array of the memory and reading data from each storage array in turn; Comparing the background data written in each storage array with the data read out of each storage array to obtain a test result; Wherein, reading data from one of the storage arrays specifically includes: Activating at least one storage area at the same time, reading data from the at least one activated storage area, and performing parallel-to-serial conversion on the data read from the at least one activated storage area and outputting the data to a data transceiver port; The bit positions of the data read from each storage area are integer multiples of the burst length, and the bit positions of the data output by the data transceiver port are integer multiples of the burst length.

15. The testing method according to claim 14, characterized in that: The data read from at least one activated storage area is converted into serial data and then output to a data transceiver port, specifically including: Acquire a burst length of data from the data read from each activated storage area; Data of a burst length in the read data of all activated storage areas are converted from parallel to serial and then output to a data transceiver port.

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