A write protection test method and test system for storage chip

Abstract

The present invention provides a write protection test method and a test system for a memory chip, belonging to the field of storage technology. The write protection test method for the memory chip comprises the following steps: initializing the memory chip; dividing the storage locations in the memory chip into two or more write protection groups, and setting two or more types of write protection groups; writing data into the memory chip, and performing power-off processing during the data writing process; and detecting whether data is written into each type of write protection group, thereby verifying whether each type of write protection meets the requirements. The write protection test method and the test system for the memory chip provided by the present invention can complete the verification of multiple write protection functions.

Description

Technical Field

[0001] The invention belongs to the field of storage technology, and in particular relates to a write protection test method and a test system for a storage chip. Background Art

[0002] A write protection function is set in the memory chip. When a storage location in the memory chip is set with the write protection function, the data stored in the storage location can be protected from accidental modification or erasure, thereby ensuring the integrity and security of the data in the storage location.

[0003] Therefore, before the memory chip leaves the factory, the write protection function of the memory chip needs to be verified, which plays an important role in the subsequent inspection and improvement of the security of the memory chip. However, memory chips have multiple types of write protection, and there is no systematic verification method for multiple types of write protection functions. Summary of the invention

[0004] The object of the present invention is to provide a write protection test method and a test system for a memory chip, which can solve the problem that there is no systematic write protection test method to verify various write protection performances of the memory chip.

[0005] To achieve the above object, the present invention provides a write protection test method and a test system for a memory chip, and the write protection test method for the memory chip at least comprises the following steps:

[0006] Performing an initialization operation on the storage chip;

[0007] Dividing the storage locations in the storage chip into two or more write protection groups, and setting two or more types of write protection groups;

[0008] Writing data into the storage chip and performing power-off processing during the data writing process; and

[0009] Check whether data is written into each type of write protection group, and then verify whether each type of write protection meets the requirements.

[0010] In one embodiment of the present invention, all storage locations in the storage chip are equally divided into a plurality of write protection groups.

[0011] In one embodiment of the present invention, all storage locations in the storage chip are set to temporary write protection, and then a write protection group where a logical block address is located is selected and set as power-on write protection, and the write protection group where the temporary write protection is located is a first type write protection group, and the write protection group where the power-on write protection is located is a second type write protection group.

[0012] In one embodiment of the present invention, the position of the second type write protection group and the positions of two first type write protection groups adjacent to the second type write protection group are acquired.

[0013] In one embodiment of the present invention, the position of the second type write protection group is obtained by the following formula:

[0014] WPG i =[LBAi / WP SiZE ];

[0015] Among them, WPG i is the position of the second type of write protection group in all write protection groups, LBAi is the selected logical block address, WP SiZE The size of a write protection group.

[0016] In one embodiment of the present invention, the starting logical address and the ending logical address of the second type write protection group are obtained by the following formula:

[0017] LBA S =WPG i ×WP SiZE ;

[0018] LBA e =LBA S +WP SiZE ;

[0019] Among them, LBA S is the starting logical address of the second type write protection group, LBA e The end logical address of the second type write protection group.

[0020] In one embodiment of the present invention, the logical address range of the first type write protection group before the second type write protection group is: (LBA S -WP SiZE , LBA S -1); and

[0021] The logical address range of the first type write protection group after the second type write protection group is: (LBA e +1, LBA e +WP SiZE ).

[0022] In an embodiment of the present invention, the write protection test method further includes setting a power-down mode of the memory chip, and setting a power-down mode in each cycle test.

[0023] In one embodiment of the present invention, if software power-off processing is performed during data writing, and after data writing is completed, there is no written data in the first type write protection group and the second type write protection group, then temporary write protection and power-on write protection meet the requirements.

[0024] In one embodiment of the present invention, if hardware power-off processing or physical power-off processing is performed during the data writing process, and after the data writing is completed, there is write data in the second type write protection group, and there is no write data in the first type write protection group, then temporary write protection and power-on write protection meet the requirements.

[0025] The present invention also provides a write protection test system for a memory chip, the write protection test system comprising:

[0026] An initialization module, performing an initialization operation on the storage chip;

[0027] A write protection group setting module, which divides the storage locations in the storage chip into two or more write protection groups and sets two or more types of write protection groups;

[0028] a data writing module, which writes data into the storage chip and performs power-off processing during the data writing process; and

[0029] The data verification module detects whether data is written into each type of write protection group, and further verifies whether each type of write protection meets the requirements.

[0030] In summary, the present invention provides a write protection test method and test system for a memory chip, which sets two or more types of write protection groups, writes data to the two or more types of write protection groups, and performs different power-off processing during the data writing process. Then, whether the write protection type corresponding to the write protection is valid is judged by whether data is written into the multiple write protection groups. This provides a systematic method for testing multiple write protection functions at the same time, and solves the problem of no systematic write protection test method to verify the multiple write protection performance of memory chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0032] Figure 1 It is a connection diagram between a host and a storage chip in one embodiment of the present application.

[0033] Figure 2This is a flow chart of a write protection test method for a memory chip in one embodiment of the present application.

[0034] Figure 3 It is a structural block diagram of a write protection test system for a memory chip in one embodiment of the present application. DETAILED DESCRIPTION

[0035] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thoroughly and comprehensively understood.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0037] In the description of the present invention, it should be understood that the orientations or positional relationships indicated by the terms "center", "upper", "lower", "front", "back", "left", "right", etc. are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. The degrees indicated by "high" and "low" are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or component referred to must have high and low, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0038] See also Figure 1As shown, a controller 201 and a non-volatile storage unit 202 are provided in the storage chip 200. The controller 201 can execute a plurality of logic gates or control commands implemented in hardware or firmware form, and perform operations such as writing, reading and erasing data in the non-volatile storage unit 202 according to the command of the host 100. The non-volatile storage unit 202 of the storage chip 200 includes a plurality of storage locations. Among them, each binary bit is a storage location. Specifically, the non-volatile storage unit 202 includes a plurality of flash memory blocks 203, and the flash memory blocks 203 may belong to the same memory die or to different memory die. Each flash memory block 203 has a plurality of physical pages, and each physical page has at least one physical sector, wherein the physical pages belonging to the same flash memory block 203 can be written independently and erased simultaneously. For example, each flash memory block 203 is composed of 128 physical pages, and each physical page has 8 physical sectors. That is, in the example where each physical sector is 512 bytes, the capacity of each physical page is 4 kilobytes (K). However, in one embodiment, each flash memory block 203 may be composed of 64 physical pages, 256 physical pages, or any other number of physical pages.

[0039] See also Figure 1As shown, in one embodiment of the present invention, the storage chip 200 using NAND flash memory as the storage medium has the characteristics of non-volatility, fast read and write speed, shock resistance, low power consumption, small size, etc. compared with the traditional magnetic disk, and is currently widely used in embedded systems, consumer electronics, aerospace and other fields. According to the different protocols of communication between the storage chip 200 and the host 100, it can include embedded memory standard specifications (Embedded Multi Media Card, eMMC), universal flash storage (Universal Flash Storage, UFS), serial hard disk (Serial ATA, SATA) and high-speed serial computer expansion bus standard (peripheral component interconnect express, PCIe) and other products. Among them, eMMC has an absolute advantage in the embedded market with its low price. eMMC is an embedded memory standard specification established by the MMC Association, mainly for products such as mobile phones or tablets. It consists of an embedded storage solution with an MMC (Multimedia Card) interface, flash memory (nand-flash) and an eMMC controller. An obvious advantage of eMMC is that an eMMC controller is integrated into the package, which provides a standard interface and manages flash memory, allowing mobile phone manufacturers to focus on other parts of product development and shorten the time to market. More and more mobile devices are using eMMC as a storage unit. The use of the write protection function has a significant impact on the performance of the eMMC storage chip, which is intended to protect the data in the storage chip 200 from accidental modification or erasure and ensure the integrity and security of the data. Therefore, it is necessary to check whether the storage chip 200 has abnormal behavior in the write protection behavior before leaving the factory, which plays a vital role in the subsequent inspection and improvement of the security of the storage chip 200.

[0040] See also Figure 1 As shown, in one embodiment of the present invention, a write protection test system for a memory chip is provided. The write protection test system for a memory chip is equivalent to an application program stored in a host 100. The program can be divided into one or more modules. The one or more modules are stored in a memory in the host 100 and executed by a processor of the host 100 to complete the write protection test method provided by the present invention.

[0041] See also Figure 2 As shown, the present invention provides a write protection test method for a memory chip, comprising steps S101 to S104.

[0042] Step S101, initializing the storage chip.

[0043] Step S102: Divide the storage locations in the storage chip into two or more write protection groups, and set two or more types of write protection groups.

[0044] Step S103: writing data into the storage chip and performing power-off processing during the data writing process.

[0045] Step S104: Detect whether data is written into each type of write protection group, and then verify whether each type of write protection meets the requirements.

[0046] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, before the memory chip 200 is initialized, the memory chip 200 is powered off and powered on to complete the restart of the memory chip 200. Then, the memory chip 200 is initialized. When the memory chip 200 is powered on, the memory chip 200 enters the boot mode, at which time the pins of the memory chip 200 can transmit data with external devices. Subsequently, the memory chip 200 waits for the host 100 to issue a CMD0 command and enters an idle state. Next, the host 100 can send a series of commands to the memory chip 200, such as CMD1, CMD2, CMD3, CMD7, ACMD6, and CMD13, etc., to obtain the device information of the memory chip 200 and configure its working mode, such as voltage, capacity, clock frequency, bus width and other device information. These commands sent by the host 100 enable the memory chip 200 to return its own data information such as voltage or capacity, as well as the status in the status register, to ensure that data can be transferred between the memory chip 200 and the host 100.

[0047] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, after completing the initialization operation of the memory chip 200, the reset function of the memory chip 200 is turned on. Specifically, for example, it is a low-level reset function (RST-N), that is, the reset end of the memory chip 200 is reset when receiving a low level, and the reset end of the memory chip 200 works normally when receiving a high level. During the test process of the memory chip 200, the memory chip 200 can be restored to the initial state or the set default state by turning on the reset function of the memory chip 200.

[0048] See also Figure 1 and Figure 2As shown, in one embodiment of the present invention, after completing the initialization operation of the memory chip 200, the storage locations in the memory chip 200 are divided into two or more write protection groups, and the type of the write protection group is set according to the write protection type to be tested. Among them, the write protection type of the memory chip 200 includes power-on write protection, permanent write protection and temporary write protection. When a storage location is set with power-on write protection, the write protection function of the data at the storage location fails after power-off and power-on. When a storage location is set with permanent write protection, the storage location is always in a write protection state unless the card is reopened. When a storage location is set with temporary write protection, the storage location is write-protected by a protection command, and when a protection cancel command is received, the write protection function of the storage location fails. Among the three write protection functions, the permanent write protection function does not fail during the power-off and power-on process when the card is not reopened, so the permanent write protection function can be tested without testing the permanent write protection function, and only the temporary write protection and power-on write protection need to be tested. In this embodiment, when testing temporary write protection and power-on write protection, since temporary write protection and power-on write protection can overlap each other, all storage locations in the storage chip 200 can be set to temporary write protection first, and then one or more write protection groups can be set to power-on write protection.

[0049] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, all storage locations in the storage chip 200 can be equally divided into a plurality of write protection groups, and the capacity of each write protection group is the same. Specifically, a flash memory block 203 can be used as a write protection group, a physical page can be used as a write protection group, or a physical sector can be used as a write protection group. The size of a write protection group can be flexibly set according to the needs.

[0050] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, after all storage locations in the memory chip 200 are set to temporary write protection, a write protection group where a logical block address is located is selected and set to power-on write protection, and the logical block address is, for example, LBAi. At this time, the write protection group where the temporary write protection is located is defined as a first type of write protection group, and the write protection type of the first type of write protection group is temporary write protection. The write protection group where the power-on write protection is located is defined as a second type of write protection group, and the protection type of the second type of write protection group is power-on write protection. Then, in the memory chip 200, the write protection group where the logical block address LBAi is located is a second type of write protection group, and the other write protection groups are all first type of write protection groups.

[0051] It should be noted that in other embodiments, the specific type of the write protection group can be set arbitrarily, and is not limited to the power-on write protection and temporary write protection mentioned in this application. For example, permanent write protection can also be verified, that is, the write protection group where another logical block is located is set to a permanent write protection group.

[0052] It should also be noted that, in the present embodiment, only the write protection group where the logical block address LBAi is located is set as the second type of write protection group. In other embodiments, the write protection group where the logical block address LBAi is located and the write protection group where the logical block address LBAj is located can also be set as the second type of write protection group, wherein the logical block address LBAi and the logical block address LBAj are located in different write protection groups. Alternatively, the write protection group where the logical block address LBAi is located, the write protection group where the logical block address LBAj is located, and the write protection group where the logical block address LBAk is located are set as the second type of write protection group. That is, the present application does not limit the number and position of the second type of write protection groups that are set, and the present application only takes the write protection group where the logical block address LBAi is located as the second type of write protection group as an example for explanation.

[0053] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, in order to verify the functionality of the first type write protection group and the second type write protection group, it is necessary to obtain the positions of at least one first type write protection group and at least one second type write protection group as the verification write protection group, so that in the subsequent write protection verification, the specific positions of writing verification data and reading verification data can be clearly identified. In this embodiment, the position of the second type write protection group where the logical block address LBAi is located, and the positions of two first type write protection groups adjacent to the write protection group where the logical block address LBAi is located can be obtained as the verification write protection group.

[0054] The second type write protection group where the logical block address LBAi is located can be obtained by the following formula:

[0055] WPG i =[LBAi / WP SiZE ];

[0056] That is LBAi divided by WP SiZE The result is an integer, where WPG i is the position of the second type write protection group where the logical block address LBAi is located in all write protection groups, that is, the i-th write protection group starting from the first write protection group. LBAi is the address of the i-th logical block, WP SiZE The size of a write protection group.

[0057] The starting logical address and ending logical address of the second type write protection group are obtained by the following formula:

[0058] LBA S =WPG i ×WP SiZE ;

[0059] LBA e =LBA S +WP SiZE ;

[0060] Among them, LBA S The starting logical address of the second type write protection group, LBA e It is the ending logical address of the second type write protection group.

[0061] The logical address range of the first type write protection group before the second type write protection group where the logical block address LBAi is located is: (LBA S -WP SiZE , LBA S -1).

[0062] The logical address range of the first type write protection group following the second type write protection group where the logical block address LBAi is located is: (LBA e +1, LBA e +WP SiZE ).

[0063] It should be noted that the number of verification write protection groups of each type can be flexibly set. In this embodiment, the second type write protection is provided with 1 verification write protection group, and the first type write protection is provided with 2 verification write protection groups. In other embodiments, the second type write protection is provided with 2, 3, 4 or 5 verification write protection groups, and the first type write protection is provided with 1, 3, 4 or 5 verification write protection groups. This application is not limited to this.

[0064] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, after obtaining the position of the write protection group for verification, the power-off mode of the memory chip 200 is set, and a power-off mode is set in each cycle test. The power-off modes of the present application include software power-off, hardware power-off and physical power-off. Software power-off refers to the host 100 sending a software command to reset the memory chip 200, and the software command is, for example, CMD0+0. Hardware power-off is that the host 100 resets the memory chip 200 by sending a low-level hardware electrical signal to the low-level reset function end of the memory chip 200. Physical power-off is to directly disconnect the power supply end of the memory chip 200, and a control switch can be set at the input end of the power supply end of the memory chip 200 to control the physical power-off and power-on of the memory chip 200.

[0065] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, after obtaining the position of the verification write protection group and setting the power-off mode of the memory chip 200, data is written to the memory chip 200, and power-off processing is performed during the data writing process. Wherein, when writing data to the memory chip 200, data can be written only to the verification write protection group. In this embodiment, data is written to a second type write protection group and two first type write protection groups. During the process of writing data to the first type write protection group and the second type write protection group, the memory chip 200 is powered off. Wherein, the power-off mode can be any one of software power-off, hardware power-off and physical power-off. In this embodiment, during the process of writing data to the verification write protection group for the first time, software power-off processing is performed on the memory chip 200. During the process of writing data to the verification write protection group for the second time, hardware power-off processing is performed on the memory chip 200. During the process of writing data to the verification write protection group for the third time, physical power-off processing is performed on the memory chip 200. The first data writing to the verification write protection group is in the first cycle, the second data writing to the verification write protection group is in the second cycle, and the third data writing to the verification write protection group is in the third cycle. Initializing the memory chip 200, dividing the write protection group and setting the type of the write protection group, writing data into the memory chip 200 and performing power-off processing during the data writing process, and verifying whether each type of write protection meets the requirements is a cyclic process.

[0066] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, during the data writing process, data may be first written into the first type write protection group and the second type write protection group. After the data writing into the first type write protection group and the second type write protection group is completed, a power-off process is performed, and after the power-off process, data may be written into the first type write protection group and the second type write protection group.

[0067] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, during the data writing process, any logical block address can be selected from the logical address range of the first type write protection group before the second type write protection group as the starting address of the written data, and any logical block address can be selected from the logical address range of the first type write protection group after the second type write protection group as the starting address of the written data. That is, the starting logical address of the written data is located at (LBA S -WP SiZE , LBA S -1), the end logical address of the written data is located at (LBAe +1, LBA e +WP SiZE )middle.

[0068] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, after writing data to the first type write protection group and the two second type write protection groups, and performing power-off processing during the data writing process, it is detected whether data is written into each type of write protection group, and then it is verified whether each type of write protection meets the requirements. Specifically, it can be verified whether the write protection meets the requirements by reading whether there is data in each type of write protection group.

[0069] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, in the first cycle, in the process of writing data to the first type write protection group and the second type write protection group, the memory chip 200 is powered off by software. After the data is written, if there is no written data in the first type write protection group and the second type write protection group, it indicates that the temporary write protection corresponding to the first type write protection group and the power-on write protection corresponding to the second type write protection group are valid, and the temporary write protection and the power-on write protection meet the requirements. If there is written data in any one of the first type write protection group and the second type write protection group, it indicates that the write protection type corresponding to the type of write protection group is invalid, and the type of write protection does not meet the requirements, and the write protection function of the memory chip 200 needs to be analyzed.

[0070] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, in the second cycle, in the process of writing data to the first type write protection group and the second type write protection group, the memory chip 200 is powered off by hardware. After the data is written, if there is write data in the second type write protection group, and there is no write data in the first type write protection group, it indicates that the temporary write protection corresponding to the first type write protection group is valid, the power-on write protection corresponding to the second type write protection group is invalid, and the power-on write protection and temporary write protection meet the requirements. If there is no write data in any of the second type write protection groups, or there is write data in any of the first type write protection groups, the write protection corresponding to this type of write protection group does not meet the requirements, and the write protection function of the memory chip 200 needs to be analyzed.

[0071] See also Figure 1 and Figure 2As shown, in one embodiment of the present invention, in the third cycle, during the process of writing data to the first type write protection group and the second type write protection group, the memory chip 200 is physically powered off. After the data is written, if there is write data in the second type write protection group, and there is no write data in the first type write protection group, it indicates that the temporary write protection corresponding to the first type write protection group is valid, the power-on write protection corresponding to the second type write protection group is invalid, and the power-on write protection and temporary write protection meet the requirements. If there is no write data in any of the second type write protection groups, or there is write data in any of the first type write protection groups, the write protection corresponding to this type of write protection group does not meet the requirements, and the write protection function of the memory chip 200 needs to be analyzed.

[0072] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, three types of power-off processing are completed in three cycles, and in each power-off mode, it is queried whether there is write data in each type of verification protection group to verify whether each write protection function of the storage chip 200 meets the requirements.

[0073] See also Figure 3 As shown, in one embodiment of the present invention, a write protection test system for a memory chip is also provided, and the write protection test system includes an initialization module 101, a write protection group setting module 102, a data writing module 103, and a data verification module 104. Among them, the initialization module 101 performs an initialization operation on the memory chip 200, the write protection group setting module 102 divides the storage locations in the memory chip 200 into two or more write protection groups, and sets two or more types of write protection groups, the data writing module 103 writes data into the memory chip 200, and performs power-off processing during the data writing process, and the data verification module 104 detects whether data is written into each type of write protection group, and then verifies whether each type of write protection meets the requirements.

[0074] See also Figure 1 As shown, the embodiment of the present application provides a memory, a processor and a program stored in the memory and executable on the processor in the host 100, and the processor executes and implements the above-mentioned write protection test method.

[0075] The memory includes at least one type of readable storage medium, and the readable storage medium includes a flash memory, a mobile hard disk, a multimedia card, a card-type memory (for example, SD or DX memory, etc.), a magnetic memory, a magnetic disk, an optical disk, etc. In some embodiments, the memory may be an internal storage unit of a data storage device, such as a mobile hard disk of the data storage device. In other embodiments, the memory may also be an external storage device of a data storage device, such as a plug-in mobile hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), etc. equipped on the data storage device. Furthermore, the memory may also include both an internal storage unit of a data storage device and an external storage device. The memory may be used not only to store application software and various types of data installed in the data storage device, but also to temporarily store data that has been output or is to be output.

[0076] In some embodiments, the processor may be composed of an integrated circuit, for example, a single packaged integrated circuit, or a plurality of packaged integrated circuits with the same or different functions, including one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and a combination of various control chips. The processor is the control core (Control Unit) of the host, and uses various interfaces and lines to connect various components of the entire host, and executes various functions of the host and processes data by running or executing programs or modules stored in the memory, and calling data stored in the memory.

[0077] The processor executes the operating system of the vehicle-mounted device and various installed application programs. The processor executes the application programs to implement the steps in the above method embodiment.

[0078] Exemplarily, the program may be divided into one or more modules, which are stored in the memory and executed by the processor to complete the present invention. The one or more modules may be a series of program command segments capable of completing specific functions, which are used to describe the execution process of the program in the vehicle-mounted device.

[0079] The above-mentioned integrated unit implemented in the form of a software function module can be stored in a computer-readable storage medium. The above-mentioned software function module is stored in a storage medium, and includes a number of commands for enabling a computer device (which can be a personal computer, a computer device, or a network device, etc.) or a processor to perform part of the functions of the lithium battery cold solder joint detection method of each embodiment of the present invention.

[0080] In summary, the present invention provides a write protection test method and test system for a memory chip, which sets two or more types of write protection groups, writes data to the two or more types of write protection groups, and performs different power-off processing during the data writing process. Then, whether the write protection type corresponding to the write protection is valid is judged by whether data is written into the multiple write protection groups. This provides a systematic method for testing multiple write protection functions at the same time, and solves the problem of no systematic write protection test method to verify the multiple write protection performance of memory chips.

[0081] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A write protection test method for a memory chip, characterized in that: At least the following steps are included: Performing an initialization operation on the storage chip; Dividing the storage locations in the storage chip into two or more write protection groups, and setting two or more types of write protection groups; Writing data into the storage chip and performing power-off processing during the data writing process; as well as Detect whether data is written into each type of write protection group, and then verify whether each type of write protection meets the requirements; Wherein, all storage locations in the storage chip are set to temporary write protection, and then a write protection group where a logical block address is located is selected to be set as power-on write protection, and the write protection group where the power-on write protection is located is a second type write protection group, and the write protection groups where other temporary write protections are located are first type write protection groups; The position of the second type write protection group is obtained by the following formula: WPG i =[LBAi / WP SiZE ]; Among them, WPG i is the position of the second type of write protection group in all write protection groups, LBAi is the selected logical block address, WP SiZE The size of a write protection group.

2. A write protection test method for a memory chip according to claim 1, characterized in that: All storage locations in the storage chip are equally divided into a plurality of write protection groups.

3. The write protection test method of a memory chip according to claim 1, characterized in that: The position of the second-type write protection group and the positions of two first-type write protection groups adjacent to the second-type write protection group are obtained.

4. The write protection test method of a memory chip according to claim 1, characterized in that: The starting logical address and the ending logical address of the second type write protection group are obtained by the following formula: LBA S =WPG i ×WP SiZE ; LBA e =LBA S +WP SiZE ; Among them, LBA S is the starting logical address of the second type write protection group, LBA e The end logical address of the second type write protection group.

5. A write protection test method for a memory chip according to claim 4, characterized in that: The logical address range of the first type write protection group before the second type write protection group is: (LBA S -WP SiZE , LBA S -1); and The logical address range of the first type write protection group after the second type write protection group is: (LBA e +1, LBA e +WP SiZE ).

6. The write protection test method of a memory chip according to claim 1, characterized in that: The write protection test method further includes setting a power-off mode of the memory chip, and setting a power-off mode in each cycle test.

7. A write protection test method for a memory chip according to claim 1, characterized in that: If software power-off processing is performed during the data writing process, and after the data writing is completed, there is no written data in the first type write protection group and the second type write protection group, then the temporary write protection and power-on write protection meet the requirements.

8. The write protection test method of a memory chip according to claim 1, characterized in that: If hardware power-off or physical power-off is performed during the data writing process, and after the data writing is completed, there is write data in the second type write protection group and there is no write data in the first type write protection group, then temporary write protection and power-on write protection meet the requirements.

9. A write protection test system for a memory chip, characterized in that: The write protection test system comprises: An initialization module, performing an initialization operation on the storage chip; A write protection group setting module, which divides the storage locations in the storage chip into two or more write protection groups and sets two or more types of write protection groups; a data writing module, which writes data into the storage chip and performs power-off processing during the data writing process; and The data verification module detects whether data is written into each type of write protection group, and further verifies whether each type of write protection meets the requirements; Wherein, all storage locations in the storage chip are set to temporary write protection, and then a write protection group where a logical block address is located is selected to be set as power-on write protection, and the write protection group where the power-on write protection is located is a second type write protection group, and the write protection groups where other temporary write protections are located are first type write protection groups; The position of the second type write protection group is obtained by the following formula: WPG i =[LBAi / WP SiZE ]; Among them, WPG i is the position of the second type of write protection group in all write protection groups, LBAi is the selected logical block address, WP SiZE The size of a write protection group.

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