A memory chip testing method and testing device

Abstract

The present invention provides a test method and a test device for a memory chip, belonging to the field of memory technology. The test method for the memory chip comprises the following steps: writing data in a storage location of the memory chip; overwriting a plurality of storage locations where data has been written to form a plurality of bad data blocks; performing a full disk read on the memory chip to obtain the address and number of the bad data blocks; performing garbage collection on the memory chip; and detecting whether the valid data on the bad data blocks has been transferred to a spare flash memory block, and whether the bad data blocks have been recycled. Through the test method and the test device for a memory chip provided by the present invention, a test method for increasing bad blocks is provided.

Description

Technical Field

[0001] The present invention belongs to the field of storage technology, and in particular relates to a testing method and a testing device for a storage chip. Background Art

[0002] In memory chips, there are factory bad blocks and growth bad blocks. Among them, factory bad blocks are bad blocks formed when the memory chip is manufactured, while growth bad blocks are formed due to wear during use.

[0003] Before the memory chip leaves the factory, it is necessary to perform functional tests on the memory chip to ensure that the functions of the memory chip meet the standards. For the factory bad blocks in the memory chip, the flash memory blocks will be checked before leaving the factory to query the specific location of the factory bad blocks and mark the factory bad blocks. However, since there are no growing bad blocks when the memory chip leaves the factory, there is no systematic testing method for the management of growing bad blocks and the data in them. Summary of the invention

[0004] The purpose of the present invention is to provide a test method and a test device for a memory chip, which can solve the problem that there is no systematic test method for the management of the bad blocks and the data therein because there are no bad blocks when the memory chip leaves the factory.

[0005] To achieve the above object, the present invention provides a memory chip testing method and a memory chip testing device, and the memory chip testing method at least comprises the following steps:

[0006] Writing data into a storage location of a memory chip;

[0007] Overwrite multiple storage locations where data has been written, resulting in multiple bad data blocks;

[0008] Performing a full disk read on the storage chip to obtain the address and number of the bad data blocks;

[0009] performing garbage collection on the storage chip;

[0010] It is detected whether the valid data on the bad data block is transferred to the spare flash memory block, and whether the bad data block is recycled.

[0011] In one embodiment of the present invention, writing data in a storage location of a storage chip comprises the following steps:

[0012] sequentially writing data to the storage locations of the storage chip until the storage locations to which data has been written reach a first threshold; and

[0013] Randomly write data to the storage location of the storage chip until the storage location of the storage chip is full of data and garbage collection is started.

[0014] In an embodiment of the present invention, the first threshold is equal to 65% to 85% of the total capacity of the memory chip.

[0015] In one embodiment of the present invention, forming the bad data block comprises the following steps:

[0016] Select a target flash block;

[0017] Determining whether the target flash memory block meets the overwrite condition; and

[0018] If the target flash block meets the overwrite condition, the data is overwritten to the target flash block; if the target flash block does not meet the overwrite condition, the next flash block after the target flash block is selected as the new target flash block until the target flash block that meets the overwrite condition is selected.

[0019] In one embodiment of the present invention, in the target flash memory block that meets the overwrite condition, the memory unit is a multi-layer unit flash memory, a triple-layer unit flash memory or a quad-layer unit flash memory.

[0020] In one embodiment of the present invention, in the target flash memory block that meets the overwrite condition, the storage location of the written data is greater than or equal to a second threshold, and the second threshold = the total capacity of the target flash memory block × (the number of data bits stored in each string unit - 1) / the number of data bits stored in each string unit.

[0021] In one embodiment of the present invention, when overwriting data into the target flash memory block, the target flash memory block is adjusted to a pseudo single-layer cell flash memory mode.

[0022] In one embodiment of the present invention, performing full disk reading on the storage chip to obtain the address and number of the bad data blocks includes the following steps:

[0023] Performing a full disk read on the storage chip, and adding information of the bad data block to a bad block table; and

[0024] The information of the bad data blocks in the bad block table is read to obtain the addresses and the number of the bad data blocks.

[0025] In an embodiment of the present invention, before performing garbage collection on the storage chip, the testing method further includes checking whether the formed bad data blocks are as expected.

[0026] In an embodiment of the present invention, the testing method further comprises verifying the reliability of the bad data block formed by overwriting the storage location where the data has been written.

[0027] In one embodiment of the present invention, verifying the reliability of the bad data block includes the following steps:

[0028] sequentially writing data to the storage locations of the storage chip until the storage locations to which data has been written reach a first threshold;

[0029] Repeating and alternating random writing and overwriting the storage location where the data has been written to form the bad data block;

[0030] When the storage location of the storage chip is full of data, it is detected whether the data stored in the storage location that has not been overwritten is correct.

[0031] The present invention also provides a testing device, comprising:

[0032] a memory storing program commands; and

[0033] A processor runs the program command to implement any one of the above-mentioned methods for testing the memory chip.

[0034] In summary, the present invention provides a memory chip testing method and testing device, which overwrites the target flash memory block that meets the overwrite conditions to form a data bad block, simulating the growth of the bad block formed during the use of the memory chip. After the bad block is formed, it is verified whether the valid data of the bad block is transferred during garbage collection, whether the bad block can be recycled, etc. The memory chip testing method and testing device provided by the present invention can generate simulated growth bad blocks and complete the system test of the bad block. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0036] Figure 1 It is a schematic diagram of the structure of a storage chip in one embodiment of the present application.

[0037] Figure 2 It is a schematic diagram of the storage unit structure in one embodiment of the present application.

[0038] Figure 3 It is a flow chart of a method for testing a memory chip in one embodiment of the present application.

[0039] Figure 4 It is a flow chart of a method for forming a bad data block in one embodiment of the present application.

[0040] Figure 5 It is a flow chart of a method for testing the reliability of bad data blocks in one embodiment of the present application.

[0041] Figure 6 It is a schematic diagram of the structure of a testing device in one embodiment of the present application. DETAILED DESCRIPTION

[0042] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thoroughly and comprehensively understood.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0044] In the description of the present invention, it should be understood that the orientations or positional relationships indicated by the terms "center", "upper", "lower", "front", "back", "left", "right", etc. are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. The degrees indicated by "high" and "low" are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or component referred to must have high and low, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0045] See also Figure 1As shown, in one embodiment of the present invention, the memory chip 20 using NAND flash memory as the storage medium has the characteristics of non-volatility, fast read and write speed, shock resistance, low power consumption, small size, etc., and is currently widely used in embedded systems, consumer electronics, aerospace and other fields. According to the different protocols of communication between the memory chip 20 and the host 10, it can be divided into embedded memory standard specifications (Embedded Multi Media Card, eMMC), universal flash storage (Universal Flash Storage, UFS), serial hard disk (Serial ATA, SATA) and high-speed serial computer expansion bus standard (peripheralcomponent interconnect express, PCIe), etc. The host 10 is electrically connected to the memory chip 20, and the host 10 can send commands such as write, read and erase to the memory chip 20. The memory chip 20 can execute multiple logic gates or control commands implemented in hardware or firmware, and perform operations such as writing, reading and erasing data according to the commands of the host 10.

[0046] See also Figure 1 As shown, in one embodiment of the present invention, the storage chip 20 includes a front-end layer 21, a middle layer 22 and a back-end layer 23. The front-end layer 21 includes a control unit 211 and a cache unit 212, and the cache unit 212 is, for example, a random access memory (RAM), the middle layer 22 is, for example, a flash translation layer (FTL), and the back-end layer 23 includes a plurality of flash blocks 231. When the storage chip 20 receives the instruction data sent by the host 10, after the data is verified, the relevant data is first stored in the cache unit 212, and the middle layer 22 allocates a flash address to each logical data block. When the data reaches a certain amount, the middle layer 22 sends a write flash request to the back-end layer 23. The back-end layer 23 writes the data in the cache unit 212 to the corresponding flash block 231, or reads the data in the corresponding flash block 231 according to the instruction data request.

[0047] See also Figure 1As shown, in one embodiment of the present invention, the middle layer 22 includes an address conversion unit 222, which can complete the conversion or mapping of the logical data block to the physical space of the flash memory. At the same time, the middle layer 22 also has a garbage collection unit 223 for erasing invalid data. The flash memory block 231 cannot be overwritten. As the user data is continuously written, garbage data (invalid data) will be generated in the flash memory block 231. The garbage data will occupy the space of the flash memory block 231. When the flash memory block 231 has insufficient available space, the garbage collection unit 223 needs to perform garbage collection, that is, to move out the valid data on several flash memory blocks 231, write them to a new flash memory block 231, and then erase these previous flash memory blocks 231 to obtain available flash memory blocks 231. In addition, the middle layer 22 also includes a wear leveling unit 224 that ensures balanced writing of each flash memory block 231, and a bad block management unit 221 that implements bad block management.

[0048] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, in the back-end layer 23, the bottom layer of the memory chip 20 is provided with a plurality of channels (channel, CH), Figure 2In the embodiment, the structure in a channel 0 is used as an example for explanation. And each channel has multiple parallel logical units (Logical Unit, LU). In this embodiment, two logical units are provided in each channel, namely logical unit 0 and logical unit 1. In other embodiments, multiple logical units may be provided in each channel. Each logical unit includes multiple planes, page registers and cache registers, wherein the page registers and cache registers store data to be written to the physical storage unit or just read from the storage unit. In this embodiment, two planes are provided in each logical unit, namely plane 0 and plane 1. In other embodiments, multiple planes may be provided in each logical unit. In each plane, a page register and a cache register are provided. In each plane, multiple flash memory blocks (blocks) 231 are provided, and multiple flash memory pages (Pages) are provided in each flash memory block 231, and each flash memory page also includes multiple memory cells. In this embodiment, for example, 990 flash memory blocks 231 are provided in each plane, and for example, 1152 flash memory pages are provided in each flash memory block 231. In this embodiment, each memory cell is, for example, a floating gate transistor, and each floating gate transistor is provided with at least one storage location. The address of the memory where the data actually exists is called a physical address, and the control unit 211 uses a logical address, which corresponds to the physical address, and stores the physical address and the logical address in the form of a mapping table. Among them, the memory cell data block in the flash memory block 231 can be configured into different storage modes according to actual needs, and the memory cell includes, for example, SLC (single-level cell flash memory, Single-Level Cell, 1bit / cell) and XLC. Among them, SLC means that each memory cell in the flash memory block 231 stores only one bit of data, and the SLC memory cell has a higher number of erase times, for example, 50,000 to 100,000 times. The XLC storage mode means that each memory cell in the flash memory block 231 stores multiple bits of data, and XLC includes MLC (Multi-Level Cell, 2bit / cell), TLC (Trinary-Level Cell, 3bit / cell) and QLC (Quad-Level Cell, 4bit / cell), and the XLC memory cell has a lower erase count, for example, 500 to 10,000 times. Compared with the XLC memory cell, the performance of the SLC memory cell is more stable. When storing data, the data is written into the XLC memory cell, and the more important data is stored in the SLC memory cell.

[0049] See also Figure 1 to Figure 2As shown, in one embodiment of the present invention, there are some bad blocks in the storage chip 20, some of which are bad blocks when the solid-state drive leaves the factory. And during the use of the solid-state drive, when the flash memory block 231 is erased and written too many times, it may cause permanent damage to the flash memory block 231 and increase the bad blocks. When a bad block appears in the solid-state drive, other flash memory blocks 231 that can be used normally are used as spare flash memory blocks for the bad blocks when necessary, and the bad block management unit 221 moves the data in the bad block to the spare flash memory block. When the solid-state drive needs to read or write a bad block, the spare flash memory block for the bad block is read or written.

[0050] See also Figure 1 As shown, in one embodiment of the present invention, before the memory chip 20 leaves the factory, a series of functional tests need to be performed on the memory chip 20. However, since the flash memory block 231 needs to be erased and written many times before a bad block grows, and the formed bad block grows permanently, there has been no systematic testing method for the bad block. The present application provides a memory chip testing method and a testing device, which can test the bad block of the memory chip 20. For details, please refer to Figure 3 As shown, the memory chip testing method includes steps S101 to S105.

[0051] Step S101, writing data into a storage location of a storage chip.

[0052] Step S102: Overwrite a plurality of storage locations where data has been written to form a plurality of bad data blocks.

[0053] Step S103: perform a full disk read on the storage chip to obtain the address and number of bad data blocks.

[0054] Step S104: performing garbage collection on the storage chip.

[0055] Step S105: Detect whether valid data on the bad data block is transferred to the spare flash memory block, and whether the bad data block is recycled.

[0056] See also Figures 1 to 3As shown, in one embodiment of the present invention, in step S101, writing data in the storage location of the storage chip 20 includes two steps. First, data is sequentially written to the storage location of the storage chip 20 until the storage location where the data has been written reaches a first threshold. Among them, the first threshold is, for example, 65% to 85% of the total capacity of the storage chip 20, specifically, for example, 70%, 80% or 85%. Secondly, when the storage location where the data has been written reaches the first threshold, data is randomly written to the storage location of the storage chip 20 until the storage location of the storage chip 20 is full of data and garbage collection is started. When the storage chip 20 is always writing sequentially, the efficiency of writing data is high, but the storage chip 20 will not start garbage collection, so it is necessary to write sequentially first to write data to most of the storage locations of the storage chip 20. When random writing is performed later, when the data written in the storage chip 20 exceeds the limit value, the storage chip 20 will start garbage collection.

[0057] See also Figures 1 to 4 As shown, in one embodiment of the present invention, in step S102, after all storage locations of the storage chip 20 are filled with data, multiple storage locations with written data are overwritten to form multiple data bad blocks. When forming data bad blocks, the data bad blocks can be formed by overwriting to the flash memory pages that meet the conditions. Specifically, forming data bad blocks includes steps S201 to S204.

[0058] S201, selecting a target flash memory block.

[0059] In one embodiment of the present invention, the selected target flash memory block may be any flash memory block 231 in the back-end layer 23. In this embodiment, the selected target flash memory block is, for example, the first flash memory block with a channel address of 0, a logical unit of 0, and a page of 2. In other embodiments, the selected target flash memory block may also be any flash memory block with a channel address of 1.

[0060] S202, determine whether the target flash memory block meets the overwrite condition, if the target flash memory block meets the overwrite condition, execute step S203, if the target flash memory block does not meet the overwrite condition, execute step S204.

[0061] In one embodiment of the present invention, when determining whether a target flash memory block meets the overwrite condition, it is first determined whether the memory cell in the target flash memory block is a single-layer unit flash memory. If the memory cell in the target flash memory block is a single-layer unit flash memory, the target flash memory block does not meet the overwrite condition. If the memory cell in the target flash memory block is not a single-layer unit flash memory, but a multi-layer unit flash memory, a three-layer unit flash memory, or a four-layer unit flash memory, it is determined whether the storage position of the written data in the target flash memory block is greater than or equal to the second threshold. Wherein, the second threshold = the total capacity of the target flash memory block × (the number of data bits stored in each memory cell - 1) / the number of data bits stored in each memory cell. If the storage position of the written data in the target flash memory block is greater than or equal to the second threshold, the target flash memory block meets the overwrite condition. If the storage position of the written data in the target flash memory block is less than the second threshold, the target flash memory block does not meet the overwrite condition.

[0062] Therefore, in this application, the target flash memory block that meets the overwrite conditions needs to meet two conditions. First, in the target flash memory block that meets the overwrite conditions, the memory unit is a multi-layer unit flash memory, a three-layer unit flash memory, or a four-layer unit flash memory. Second, in the target flash memory block that meets the overwrite conditions, the storage location of the written data is greater than or equal to the second threshold, and the second threshold = the total capacity of the target flash memory block × (the number of data bits stored in each memory cell - 1) / the number of data bits stored in each memory cell.

[0063] S203: Copy data to the target flash memory block.

[0064] In one embodiment of the present invention, when overwriting data in a target flash memory block, the target flash memory block is adjusted to a pseudo-single-level cell flash memory (Pseudo-Single Level Cell, pSLC) mode. At this time, the storage location where the data has been written can be overwritten. When the data written in the storage location is A, and the data written to the storage location during overwriting is B, then after overwriting, the data stored in the storage location is A+B. Among them, when writing data to the target flash memory block, a part of the storage locations where the data has been written in the target flash memory block is overwritten, and another part of the flash memory pages in the target flash memory block are retained as flash memory pages for normal data storage. It is only necessary to ensure that when the target flash memory block is performing data verification, the verification result of the target flash memory block is not passed. At this time, if the verification result in the target flash memory block exceeds the correction capability of the error checking and correction technology (Error Checking and Correcting, ECC), the system determines that the target flash memory block is a bad block, that is, a data bad block in this application.

[0065] S204, select the next flash memory block after the target flash memory block as a new target flash memory block, and return to step S202.

[0066] In one embodiment of the present invention, after selecting the next flash memory block 231 of the target flash memory block as the new target flash memory block, the process returns to step S202 to re-determine whether the target flash memory block meets the overwrite condition until a target flash memory block that meets the overwrite condition is selected.

[0067] See also Figure 3 As shown, in one embodiment of the present invention, after overwriting data in multiple target flash memory blocks, the logical addresses of the target flash memory blocks where the data is overwritten can be derived and saved. The number of target flash memory blocks where the data is overwritten is set according to demand.

[0068] See also Figure 1 , Figure 3 and Figure 4 As shown, in one embodiment of the present invention, after forming a plurality of bad data blocks according to the method of step S201 to step S204, the memory chip 20 is fully read to obtain the address and number of the bad data blocks. Among them, step S103 of obtaining the address and number of the bad data blocks also includes two steps. First, the memory chip 20 is fully read, and the information of the bad data blocks is added to the bad block table. In the bad block table, the information of the bad data blocks, that is, the physical address of the bad data blocks, is stored. When the memory chip 20 is read, if the flash memory block 231 is a bad data block, the information of the bad data block is added to the bad block table, indicating that the flash memory block 231 is in an unavailable state. Secondly, after the full disk is read, the information of all bad data blocks will be saved in the bad block table. At this time, the information of the bad data blocks in the bad block table can be read by sending a custom command to obtain the address and number of the bad data blocks.

[0069] See also Figure 1 and Figure 3 As shown, in one embodiment of the present invention, before garbage collection is performed on the storage chip 20, it is also possible to check whether the formed bad data block meets expectations. Specifically, it includes checking whether the position of the overwritten data is correct, and whether the data stored in the unoverwritten data position in the bad data block can be read. When checking whether the overwritten data position is correct, the physical address of the bad data block obtained in step S103 can be compared with the physical address corresponding to the logical address of the derived target flash memory block, and then checking whether the overwritten data position is correct.

[0070] See also Figure 1 and Figure 3 As shown, in one embodiment of the present invention, before garbage collection is performed on the memory chip 20, a power-on read-write test may be performed on the memory chip 20. That is, the memory chip 20 is subjected to multiple cycles of power-off, power-on, data reading, and data writing. It should be noted that when the power-on read-write test is performed on the memory chip 20, no operation is performed on the bad data block when reading and writing data on the memory chip 20.

[0071] See also Figure 1 and Figure 3 As shown, in one embodiment of the present invention, when garbage collection is performed on the storage chip 20, garbage collection is performed on the entire disk of the storage chip 20. At this time, the data stored in the data position that has not been overwritten in the bad data block will be moved to the spare flash memory block, and then all the data in the bad data block will be erased, and the data stored in the overwritten data position will be discarded.

[0072] See also Figure 3 As shown, in one embodiment of the present invention, after garbage collection is completed, the data in the spare flash memory block is compared with the data in the bad data block to detect whether the valid data on the bad data block has been transferred to the spare flash memory block. Then, it is detected whether there is still data in the bad data block to determine whether the bad data block has been recycled. When the bad data block is recycled, the bad data block is a blank flash memory block.

[0073] See also Figure 1 and Figure 5 As shown, in one embodiment of the present invention, the test method further includes verifying the reliability of forming a bad data block by rewriting the storage location of the written data. It mainly includes steps S301 to S302.

[0074] Step S301: sequentially write data to storage locations of a storage chip until the storage locations to which data has been written reach a first threshold.

[0075] The first threshold is, for example, 65% to 85% of the total capacity of the memory chip 20 , and specifically, for example, 70%, 80% or 85%.

[0076] Step S302: Repeating the random writing and overwriting the storage location of the written data alternately to form a bad data block.

[0077] It should be noted that when the storage location of the written data is overwritten to form a bad data block, the logical address of the flash memory block 231 of the overwritten data is exported and saved.

[0078] Step S303: When the storage location of the storage chip is full of data, it is detected whether the data stored in the data storage location that has not been overwritten is correct.

[0079] It should be noted that when checking whether the data stored in the data storage location that has not been overwritten is correct, the logical address of the flash memory block of the overwritten data is skipped based on the logical address of the flash memory block of the exported overwritten data, and only the data stored in the data storage location that has not been overwritten is checked whether it is correct.

[0080] In one embodiment of the present invention, if the data stored in the data storage location that has not been overwritten is correct, or the accuracy of the data stored in the overwritten data storage location exceeds a set threshold, the storage location where the data has been written is overwritten, and the resulting bad data block has reliability.

[0081] See also Figure 6 As shown, an embodiment of the present application provides a testing device, which also includes a memory 302, a processor 301 and a program stored in the memory and executable on the processor, and the processor executes a testing method for implementing the above-mentioned storage chip.

[0082] See also Figure 6 As shown, the memory 302 includes at least one type of readable storage medium, and the readable storage medium includes a flash memory, a mobile hard disk, a multimedia card, a card-type memory (for example, SD or DX memory, etc.), a magnetic memory, a disk, an optical disk, etc. The memory may be an internal storage unit of the test device in some embodiments, such as a mobile hard disk of the test device. The memory may also be an external storage device of the test device in other embodiments, such as a plug-in mobile hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), etc. equipped on the test device. Further, the memory may also include both an internal storage unit and an external storage device of the test device. The memory may be used not only to store application software and various types of data installed in the test device, but also to temporarily store data that has been output or is to be output.

[0083] See also Figure 6 As shown, in some embodiments, the processor 301 can be composed of an integrated circuit, for example, it can be composed of a single packaged integrated circuit, or it can be composed of multiple packaged integrated circuits with the same function or different functions, including one or more central processing units (CPU), microprocessors, digital processing chips, graphics processors and a combination of various control chips.

[0084] The processor executes the operating system of the vehicle-mounted device and various installed application programs. The processor executes the application programs to implement the steps in the above method embodiment.

[0085] Exemplarily, the program may be divided into one or more modules, which are stored in the memory and executed by the processor to complete the present invention. The one or more modules may be a series of program command segments capable of completing specific functions, which are used to describe the execution process of the program in the vehicle-mounted device.

[0086] The above-mentioned integrated unit implemented in the form of a software function module can be stored in a computer-readable storage medium. The above-mentioned software function module is stored in a storage medium, and includes a number of commands for enabling a computer device (which can be a personal computer, a computer device, or a network device, etc.) or a processor to perform part of the functions of the lithium battery cold solder joint detection method of each embodiment of the present invention.

[0087] In summary, the present invention provides a test method and a test device for a memory chip, which includes writing data in a storage location of a memory chip, and overwriting multiple storage locations where data has been written, to form multiple bad data blocks. After that, the memory chip is fully read to obtain the address and number of bad data blocks. Next, garbage collection is performed on the memory chip to detect whether valid data on the bad data blocks are transferred to spare flash memory blocks, and whether the bad data blocks are recycled.

[0088] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for testing a memory chip, characterized in that: At least the following steps are included: Writing data into a storage location of a memory chip; Overwrite multiple storage locations where data has been written, resulting in multiple bad data blocks; Performing a full disk read on the storage chip to obtain the address and number of the bad data blocks; performing garbage collection on the storage chip; Detecting whether valid data on the bad data block is transferred to a spare flash memory block, and whether the bad data block is recycled; Wherein, forming the bad data block comprises the following steps: Select a target flash block; Determining whether the target flash memory block meets the overwrite condition; and If the target flash block meets the overwrite condition, the data is overwritten to the target flash block; if the target flash block does not meet the overwrite condition, a flash block after the target flash block is selected as a new target flash block until the target flash block that meets the overwrite condition is selected; In the target flash memory block that meets the overwrite condition, the storage location of the written data is greater than or equal to a second threshold, and the second threshold = the total capacity of the target flash memory block × (the number of data bits stored in each string unit - 1) / the number of data bits stored in each string unit.

2. A memory chip testing method according to claim 1, characterized in that: Writing data in a storage location of a memory chip includes the following steps: sequentially writing data to the storage locations of the storage chip until the storage locations to which data has been written reach a first threshold; and Randomly write data to the storage location of the storage chip until the storage location of the storage chip is full of data and garbage collection is started.

3. The memory chip testing method according to claim 1, characterized in that: In the target flash memory block meeting the overwrite condition, the memory cell is a multi-layer cell flash memory, a triple-layer cell flash memory or a quad-layer cell flash memory.

4. The method for testing a memory chip according to claim 1, characterized in that: When overwriting data into the target flash memory block, the target flash memory block is adjusted to a pseudo single-layer cell flash memory mode.

5. The method for testing a memory chip according to claim 1, characterized in that: Performing a full disk read on the storage chip to obtain the address and number of the bad data blocks includes the following steps: Performing a full disk read on the storage chip, and adding information of the bad data block to a bad block table; and The information of the bad data blocks in the bad block table is read to obtain the addresses and the number of the bad data blocks.

6. The method for testing a memory chip according to claim 1, characterized in that: Before performing garbage collection on the storage chip, the testing method further includes checking whether the formed bad data blocks are in accordance with expectations.

7. The memory chip testing method according to claim 1, characterized in that: The testing method further includes verifying the reliability of the bad data block formed by overwriting the storage location where the data has been written.

8. The method for testing a memory chip according to claim 7, characterized in that: Verifying the reliability of the bad data block includes the following steps: sequentially writing data to the storage locations of the storage chip until the storage locations to which data has been written reach a first threshold; Repeating and alternating random writing and overwriting the storage location where the data has been written to form the bad data block; When the storage location of the storage chip is full of data, it is detected whether the data stored in the storage location that has not been overwritten is correct.

9. A testing device, characterized in that: The testing device comprises: a memory storing program commands; and A processor runs the program command to implement the test method of the memory chip according to any one of claims 1 to 8.

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