A memory chip testing method and testing device

Abstract

The present invention provides a test method and a test device for a memory chip, belonging to the field of memory technology. The test method for the memory chip comprises the following steps: sending multiple read commands to the memory chip; after waiting for a preset time, executing a read command according to the order and number of cycles of the read commands; recording the time interval from executing the read command to feeding back the data; judging whether the time interval is less than a preset time threshold, if the time interval is less than the preset time threshold, cyclically executing the process of sending multiple read commands to the memory chip until judging whether the time interval is less than the preset time threshold, until the time interval is greater than or equal to the preset time threshold, and obtaining the capacity of the memory chip read buffer according to the sequence number of the read command. The capacity of the read buffer can be obtained by the test method and the test device for the memory chip provided by the present invention.

Description

Technical Field

[0001] The present invention belongs to the field of storage technology, and in particular relates to a testing method and a testing device for a storage chip. Background Art

[0002] Solid-state memory is a new type of storage device. It can be used to make a variety of storage chips, such as solid-state hard disks, embedded multimedia memory cards, universal flash storage, security cards and other storage chips. The new storage chip is equipped with a controller, a cache and a memory, and the cost of the cache is much higher than that of the memory.

[0003] When doing competitive product analysis, it is necessary to evaluate the capacity of the cache. Although the size of the internal cache can be detected through physical means such as X-rays, this method is expensive and cannot obtain the size of specific types of caches in the cache, such as the size of the read cache. Summary of the invention

[0004] The object of the present invention is to provide a memory chip testing method and a testing device, which can solve the problem of being unable to effectively obtain the size of a specific type of buffer in the memory chip.

[0005] To achieve the above object, the present invention provides a memory chip testing method and a memory chip testing device, and the memory chip testing method at least comprises the following steps:

[0006] Send multiple read commands to the memory chip;

[0007] After waiting for a preset time, a read command is executed according to the order and number of cycles of the read commands;

[0008] Record the time interval from executing the read command to feeding back the data;

[0009] Determine whether the time interval is less than a preset time threshold, and if the time interval is less than the preset time threshold, cyclically execute the process of sending multiple read commands to the storage chip to determine whether the time interval is less than the preset time threshold, until the time interval is greater than or equal to the preset time threshold;

[0010] The capacity range of the storage chip read buffer is obtained according to the sequence number of the read command executed when the time interval is greater than or equal to the preset time threshold.

[0011] In one embodiment of the present invention, when multiple read commands are sent to the memory chip, the total amount of data in the multiple read commands is greater than the capacity of the read buffer, and the amount of data in each of the read commands is equal.

[0012] In one embodiment of the present invention, when multiple read commands are sent to a memory chip, the memory chip is set to a multiple command queue mode.

[0013] In an embodiment of the present invention, the preset waiting time is greater than or equal to the time required to copy the data in the read command from the memory to the read buffer until the read buffer is filled.

[0014] In one embodiment of the present invention, in the first cycle, the sequence number of the read command executed for the first time is smaller than the quotient of the capacity of the read buffer and the amount of data in each read command.

[0015] In an embodiment of the present invention, the preset time threshold is the minimum time required to read data from the flash memory block.

[0016] In one embodiment of the present invention, the capacity range of the read buffer is obtained by the following formula:

[0017] X = (Y-1) × M ~ Y × M;

[0018] Among them, Y is the number of the read commands required to fill the read buffer, and Y is equal to the sequence number of the read command executed when the time interval is equal to or greater than the preset time threshold, and M is the amount of data in each of the read commands.

[0019] In one embodiment of the present invention, after obtaining the capacity range of the memory chip read buffer, the memory chip testing method further includes:

[0020] The value of the data amount in each read command is reduced, and a plurality of read commands are sent to the memory chip in a repeated cycle to obtain the capacity range of the memory chip read buffer, thereby obtaining the size of the memory chip read buffer capacity.

[0021] In one embodiment of the present invention, after obtaining the capacity range of the memory chip read buffer, in the memory chip testing method, the sequence number of the read command executed for the first time is obtained by the following formula:

[0022] y = (Y-1) × M / M1;

[0023] Among them, Y is the number of read commands required to fill the read buffer after the previous cycle process; M is the amount of data in each read command in the previous cycle process; M1 is the amount of data in each read command in this cycle process.

[0024] The present invention also provides a test device for a memory chip, the test device comprising:

[0025] a memory storing program instructions; and

[0026] The processor runs the program instructions to implement any one of the methods for testing the storage chip described above.

[0027] In summary, the present invention provides a memory chip testing method and testing device, wherein a host sends a read command to a memory chip, and then executes the read command, obtains the time interval for the memory chip to feedback data after executing the read command, obtains the sequence number of the read command when the read buffer is full, and then obtains the capacity range of the read buffer. Therefore, the present application can more accurately test the size of the read buffer when the internal structure of the memory chip is unclear. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0029] Figure 1 It is a schematic diagram of the structure of a storage chip in one embodiment of the present application.

[0030] Figure 2 It is a flow chart of a method for testing a memory chip in one embodiment of the present application.

[0031] Figure 3 It is a schematic diagram of the structure of a testing device in one embodiment of the application. DETAILED DESCRIPTION

[0032] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thoroughly and comprehensively understood.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0034] In the description of the present invention, it should be understood that the orientations or positional relationships indicated by the terms "center", "upper", "lower", "front", "back", "left", "right", etc. are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. The degrees indicated by "high" and "low" are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or component referred to must have high and low, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0035] See also Figure 1 As shown, in one embodiment of the present invention, the storage chip 200 using Nand flash memory as the storage medium has the characteristics of non-volatility, fast read and write speed, shock resistance, low power consumption, small size, etc. compared with the traditional magnetic disk, and is currently widely used in embedded systems, consumer electronics, aerospace and other fields. According to the different protocols of communication between the storage chip 200 and the host 100, it can be divided into embedded memory standard specifications (Embedded Multi Media Card, eMMC), universal flash storage (Universal Flash Storage, UFS), serial hard disk (Serial ATA, SATA) and high-speed serial computer expansion bus standard (peripheral component interconnect express, PCIe), etc.

[0036] See also Figure 1 As shown, in one embodiment of the present invention, a memory chip 200 is provided with a controller 201, a buffer 202 and a memory 203. The controller 201 can execute a plurality of logic gates or control instructions implemented in hardware or firmware, and perform operations such as writing, reading and erasing data in the memory 203 according to the instructions of the host 100.

[0037] See also Figure 1As shown, in one embodiment of the present invention, the memory 203 is a non-volatile storage unit, and the memory 203 stores data written by the host 100 and other necessary data such as a mapping table. Among them, the memory 203 can be a NAND flash memory, a vertical NAND (VNAND), a NOR flash memory, a resistance random access memory (RRAM), a phase change memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM) or a spin transfer torque random access memory (STT-RAM). The memory 203 may include a memory cell array block connected to a word line, a string selection line, a ground selection line and a bit line. The memory 203 may include a super block including a plurality of storage blocks. The plurality of storage blocks may include a plurality of pages. The memory 203 may include a two-dimensional (2D) memory 203 array block or a three-dimensional (3D) memory 203 array block. Other types of non-volatile storage units 202 may also be used. In this embodiment, the structure of the NAND flash memory 203 is taken as an example for description, and the memory 203 includes a plurality of flash memory blocks 2031. It is understandable that in other embodiments, the memory 203 may also adopt other types of non-volatile storage unit structures.

[0038] See also Figure 1 As shown, in one embodiment of the present invention, the cache 202 is a high-speed storage device with a faster access speed than the memory 203. When the host 100 wants to read a piece of data, it first searches from the cache 202. If it is found, it is immediately read and sent to the controller 201 for processing. If it is not found in the cache 202, it is read from the memory 203 with a relatively slow speed and sent to the controller 201 for processing. At the same time, the data block where the data is located is transferred into the cache, so that the entire block of data can be read from the cache in the future without calling the memory. This greatly saves the time of data reading and also makes the controller 201 basically do not need to wait when reading data.

[0039] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, the buffer 202 includes a read buffer 2021 and a read buffer 2022. The read buffer 2021 stores the copy data of part of the data in the memory 203. When the data read by the host 100 is stored in the read buffer 2021, when the host 100 reads the data, the buffer 202 can send the copy data stored therein to the host 100. However, the size of the read buffer 2021 is limited. The present invention provides a test method and a test device for a memory chip, which can obtain the size of the read buffer 2021 in the memory chip 200. Specifically, the test method for the memory chip 200 includes steps S101 to S107.

[0040] Step S101: Send multiple read commands to a storage chip.

[0041] Step S102: Wait for a preset time.

[0042] Step S103: execute a read command according to the order and loop number of the read commands.

[0043] Step S104: Record the time interval from executing the read command to feeding back the data.

[0044] Step S105, determine whether the time interval is less than the preset time threshold, if the time interval is less than the preset time threshold, execute step S106, if the time interval is greater than or equal to the preset time threshold, execute step S107.

[0045] Step S106: increase the value of the sequence number of the executed read command, and return to step S101.

[0046] Step S107: Obtain the capacity range of the storage chip read buffer according to the sequence number of the executed read command.

[0047] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, in step S101, during the test, the memory chip 200 is set to a multi-command queue mode. At this time, the host 100 can send multiple read commands to the memory chip 200 at one time, and the memory chip 200 will cache the data in the read command in the read buffer 2021, waiting to receive the read command. In this embodiment, the amount of data in each read command is equal. And the total amount of data in the multiple read commands sent to the memory 203 is greater than the capacity of the read buffer 2021, ensuring that the capacity of the read buffer 2021 can be obtained by the sequence number when the read command is executed later. If the capacity of the read buffer 2021 is X, and the amount of data read in each read command is M, then the number of read commands required to fill the read buffer 2021 is X / M, and the number of commands sent to the memory chip 200 at one time is greater than or equal to X / M. Among them, if X / M is a decimal, X / M can be rounded up, and the rounding is, for example, Y. That is, if X / M=5.2, then Y=6.

[0048] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, if the capacity of the read buffer 2021 cannot be confirmed, the processing is performed according to the maximum capacity of the read buffer 2021 on the market, or according to double or triple the maximum capacity of the read buffer 2021 on the market. This makes the total amount of data in the multiple read commands sent by the host 100 to the storage chip 200 at one time much larger than the capacity of the read buffer 2021.

[0049] Please note that, see Figure 1 and Figure 2 As shown, in the subsequent execution of the test method for the memory chip 200, steps S101 to S105 need to be executed repeatedly. During each execution of step S101, the host 100 sends an equal number of read commands to the memory chip 200 at one time.

[0050] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, in step S102, the preset waiting time is greater than or equal to the time required to copy the data in the read command from the memory 203 to the read buffer 2021 until the read buffer 2021 is filled. For example, the number of read commands required to fill the read buffer 2021 is Y, and the time required to copy the data in each read command from the memory 203 to the read buffer 2021 is t, then the preset waiting time is greater than or equal to Y×t.

[0051] Please note that, see Figure 1 and Figure 2 As shown, if the capacity of the read buffer 2021 cannot be confirmed, the number of read commands sent by the host 100 to the storage chip 200 at one time in step S101 multiplied by the time it takes to copy the data in each read command from the memory 203 to the read buffer 2021 can be used as the preset waiting time.

[0052] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, after a preset waiting time, all or part of the data in the multiple read commands sent by the host 100 to the storage chip 200 fills the read buffer 2021. At this time, a read command is executed according to the order of the read commands and the number of cycles. In the first cycle, the sequence number of the read command executed for the first time is less than the quotient of the capacity of the read buffer 2021 and the amount of data in each read command, that is, X / M. Because the data in the read command executed at this time has been copied to the read buffer 2021. Among them, the amount of data in each read command refers to the amount of data read in each read command. The sequence number of the read command refers to the order in which the read command is sent by the host 100 to the storage chip 200 when the host 100 sends multiple read commands to the storage chip 200 at one time. In this embodiment, since the size of the read buffer 2021 is unknown, the present application starts from the first read command. In other embodiments, it can also be executed from the second, third or fourth read command.

[0053] See also Figure 1 and Figure 2As shown, in one embodiment of the present invention, after the execution of the command begins, a timer can be used to record the time interval from the execution of the read command to the feedback of the returned data. Among them, the time of executing the read command refers to the time when the host 100 sends the execution read command to the storage chip 200, and the time of feeding back the returned data is the time when the storage chip 200 starts to pass the data in the read command to the host 100. When the data in the execution instruction is stored in the memory 203, it is necessary to first query the physical location of the data in the execution instruction from the logical address to the physical address mapping table, and then retrieve the data from the data block corresponding to the physical address and pass it to the host 100. This process of transferring data requires a long time interval due to the need to perform address query and data retrieval. When the data in the execution instruction has been cached in the read buffer 2021, the data in the read buffer 2021 can be directly transferred to the host 100. There is no need to go through the process of searching and retrieving data in a large number of flash memory blocks 2031, so a shorter time interval is required.

[0054] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, in step S105, the preset time threshold is set as the minimum time required to read the data in the flash memory block 2031. That is, when the memory chip 200 receives a read command, and the data in the read command is stored in the memory 203, the minimum time interval for the memory chip 200 to read the data in the read command from the memory 203 and start to pass it to the host 100. The time interval for reading data directly from the read buffer 2021 is much shorter than the preset time threshold. In this embodiment, the preset time threshold is, for example, 50us. In other embodiments, the preset time interval can be set according to the specific performance of the memory chip 200, and the range of the preset time threshold is, for example, 30us~80us, specifically, for example, 40us, 45us, 55us, 60us or 70us.

[0055] See also Figure 1 and Figure 2As shown, in one embodiment of the present invention, the time interval obtained in step S104 is compared with the preset time threshold in step S105. If the time interval is less than the preset time threshold, it means that the data in the read command executed this time has been cached in the read buffer 2021. At this time, step S106 is executed, the value of the sequence number of the read command executed is increased, and step S101 is returned. That is, if the read command executed this time is the first read command among multiple read commands issued at one time, then when returning to step S101 and re-executing the loop from step S101 to step S105, in step S103, the read command executed is the second read command. Then, in the subsequent loop process of executing steps S101 to step S105, according to the number of loops, in the third loop, the read command executed is the third read command, and in the fourth loop, the read command executed is the fourth read command. Therefore, in one embodiment of the present invention, in step S103, according to the sequence of the read commands and the number of loops, in executing a read command, according to the sequence of the read commands, the sequence number of the executed read command is equal to the number of loops.

[0056] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, the time interval obtained in step S104 is compared with the preset time threshold in step S105. If the time interval is greater than or equal to the preset time threshold, it means that the data in the read command executed this time is not stored in the read buffer 2021, that is, the data in the read command executed this time is stored in the memory 203, and the data in the command executed this time needs to be retrieved from the memory 203 and then transmitted to the host 100. At this time, the time required to execute this read command is equal to or greater than the preset time threshold, then in this cycle, the sequence number of this read command is equal to the number Y of read commands required to fill the read buffer 2021.

[0057] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, after obtaining the number Y of read commands required to fill the read buffer 2021, the capacity range of the read buffer 2021 is obtained by the following formula:

[0058] X=(Y-1)×M~Y×M.

[0059] Wherein, Y is the number of read commands required to fill the read buffer, and Y is equal to the sequence number of the read commands executed when the time interval is equal to or greater than the preset time threshold, and M is the amount of data in each read command.

[0060] See also Figure 1 and Figure 2As shown, in one embodiment of the present invention, when it is necessary to obtain a more accurate capacity of the read buffer 2021, the value of the amount of data in each read command can be reduced. For example, M1. After that, steps S101 to S107 are repeatedly executed in a loop until the size of the capacity of the read buffer 2021 is obtained. As the value of the amount of data in each read command decreases, the capacity range of the read buffer 2021 decreases, and the range of the capacity of the read buffer 2021 obtained is more accurate. And in step S103, the sequence number of the instruction executed in the first loop may not start from 1, and the sequence number of the first execution is obtained by the following formula:

[0061] y = (Y-1) × M / M1;

[0062] Among them, Y is the number of read commands required to fill the read buffer after the previous cycle process, and Y is equal to the sequence number of the read command executed when the time interval is equal to or greater than the preset time threshold after the previous cycle process; M is the amount of data in each read command in the previous cycle process; M1 is the amount of data in each read command in this cycle process.

[0063] Specifically, in an embodiment of the present invention, for example, the amount of data in each read command is reduced by half, then M=2M1, y=2(Y-1). Then, only a few cycles are required to obtain a more accurate range of the capacity of the read buffer 2021.

[0064] See also Figure 1 and Figure 2 As shown, in a specific embodiment of the present invention, in step S101, the host 100 sends 100 read commands to the storage chip 200 at one time, for example, and the amount of data M in each read command is, for example, 32KB. In step S102, the time t for copying the data in each read command from the memory 203 to the read buffer 2021 is, for example, 100us, and the preset waiting time is 10ms. In step S105, the preset time threshold is set to, for example, 50us. Then, the test method for the storage chip provided by the present application includes the following loops:

[0065] In the first cycle, the host 100 first sends 100 read commands with a data volume of 32KB to the storage chip 200. After waiting for 10ms, it sends an execution command and executes the first read command in the order of the read commands. The timing starts when the execution command is sent. After that, it waits for the storage chip 200 to send back data. When the host 100 receives the returned data, it stops counting, obtains the time interval, and determines whether the time interval is less than the preset time threshold.

[0066] If the time interval in the first cycle is less than the preset time threshold, the second cycle is executed, and the host 100 first sends 100 read commands with a data volume of 32KB to the storage chip 200. After waiting for 10ms, the execution command is sent again, and the second read command is executed in the order of the read commands, and the timing starts when the execution command is sent. After that, wait for the storage chip 200 to return data, stop counting when the host 100 receives the returned data, obtain the time interval, and determine whether the time interval is less than the preset time threshold.

[0067] Repeat the steps of the first cycle and the second cycle until in the Yth cycle, the time interval is greater than or equal to the preset time threshold, where Y is, for example, 50. Then the capacity range of the read buffer 2021 is (50-1)×32KB to 50×32KB, that is, 1568KB to 1600KB.

[0068] See also Figure 3 As shown, the present application also provides a testing device for a storage chip, which is arranged in a host 100, and includes a memory 302, a processor 301, and a program stored in the memory 203 and executable on the processor, and the processor executes a testing method for implementing the above-mentioned storage chip 200.

[0069] See also Figure 3 As shown, the memory 302 includes at least one type of readable storage medium, and the readable storage medium includes a flash memory, a mobile hard disk, a multimedia card, a card-type memory (for example, SD or DX memory, etc.), a magnetic memory, a disk, an optical disk, etc. In some embodiments, the memory may be an internal storage unit of an electronic device, such as a mobile hard disk of the electronic device. In other embodiments, the memory may also be an external storage device of an electronic device, such as a plug-in mobile hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), etc. equipped on the electronic device. Further, the memory may also include both an internal storage unit of the electronic device and an external storage device. The memory may be used not only to store application software and various types of data installed in the electronic device, but also to temporarily store data that has been output or is to be output.

[0070] See also Figure 3As shown, in some embodiments, the processor 301 may be composed of an integrated circuit, for example, a single packaged integrated circuit, or a plurality of packaged integrated circuits with the same or different functions, including one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and combinations of various control chips. The processor is the control core (Control Unit) of the host, and executes various functions of the host and processes data by running or executing programs or modules stored in the memory, and calling data stored in the memory.

[0071] The processor executes the operating system of the host and various installed application programs. The processor executes the application programs to implement the steps in the above method embodiment.

[0072] Exemplarily, the program may be divided into one or more modules, which are stored in the memory and executed by the processor to complete the present invention. The one or more modules may be a series of program instruction segments capable of completing specific functions, which are used to describe the execution process of the program in the host.

[0073] The above-mentioned integrated unit implemented in the form of a software function module can be stored in a computer-readable storage medium. The above-mentioned software function module is stored in a storage medium, and includes a number of instructions for enabling a computer device (which can be a personal computer, a computer device, or a network device, etc.) or a processor to execute the test method of the storage chip in each embodiment of the present invention.

[0074] In summary, a method and device for testing a memory chip include sending multiple read commands to the memory chip and waiting for a preset time. Afterwards, a read command is executed according to the order and number of cycles of the read commands. The time interval from executing the read command to feeding back the data is recorded, and it is determined whether the time interval is less than the preset time threshold. If the time interval is less than the preset time threshold, the value of the sequence number of the executed read command is increased, and the process of sending multiple read commands to the memory chip is repeated until it is determined whether the time interval is less than the preset time threshold, until the time interval is greater than or equal to the preset time threshold, and the capacity of the memory chip read buffer is obtained according to the sequence number of the executed read command.

[0075] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for testing a memory chip, characterized in that: At least the following steps are included: Send multiple read commands to the memory chip; After waiting for a preset time, a read command is executed according to the order and number of cycles of the read commands; Record the time interval from executing the read command to feeding back the data; Determine whether the time interval is less than a preset time threshold, if the time interval is less than the preset time threshold, increase the value of the sequence number of the executed read instruction, and cyclically execute the process of sending multiple read commands to the storage chip to determine whether the time interval is less than the preset time threshold, until the time interval is greater than or equal to the preset time threshold; Acquire the capacity range of the storage chip read buffer according to the sequence number of the read command executed when the time interval is greater than or equal to the preset time threshold; The value of the data amount in each read command is reduced, and a plurality of read commands are sent to the memory chip in a repeated cycle to obtain the capacity range of the memory chip read buffer, thereby obtaining the size of the memory chip read buffer capacity.

2. A memory chip testing method according to claim 1, characterized in that: When multiple read commands are sent to the memory chip, the total amount of data in the multiple read commands is greater than the capacity of the read buffer, and the amount of data in each of the read commands is equal.

3. The memory chip testing method according to claim 1, characterized in that: When multiple read commands are sent to a memory chip, the memory chip is set to a multiple command queue mode.

4. The method for testing a memory chip according to claim 1, characterized in that: The preset waiting time is greater than or equal to the time required to copy the data in the read command from the memory to the read buffer until the read buffer is filled.

5. The method for testing a memory chip according to claim 1, characterized in that: In the first cycle, the sequence number of the read command executed for the first time is smaller than the quotient of the capacity of the read buffer and the amount of data in each read command.

6. The method for testing a memory chip according to claim 1, characterized in that: The preset time threshold is the minimum time required to read the data in the flash memory block.

7. The memory chip testing method according to claim 1, characterized in that: The capacity range of the read buffer is obtained by the following formula: X = (Y-1) × M ~ Y × M; Among them, Y is the number of the read commands required to fill the read buffer, and Y is equal to the sequence number of the read command executed when the time interval is equal to or greater than the preset time threshold, and M is the amount of data in each of the read commands.

8. The method for testing a memory chip according to claim 1, characterized in that: After obtaining the capacity range of the memory chip read buffer, in the memory chip testing method, the sequence number of the read command executed for the first time is obtained by the following formula: y = (Y-1) × M / M1; Among them, Y is the number of read commands required to fill the read buffer after the previous cycle process; M is the amount of data in each read command in the previous cycle process; M1 is the amount of data in each read command in this cycle process.

9. A memory chip testing device, characterized in that: The testing device comprises: a memory storing program instructions; and A processor runs the program instructions to implement the method for testing the storage chip according to any one of claims 1 to 8.

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