Semiconductor device and processing method thereof

Abstract

The invention provides a semiconductor device and a processing method thereof. The processing method comprises the following steps that a to-be-processed sample is prepared, the to-be-processed sample comprises a substrate and a semiconductor device located on the substrate, and the semiconductor device comprises a power area and a logic circuit area; performing deep trench etching on at least one target position between the power region and the logic circuit region to form at least one isolation trench reaching the substrate; performing deep trench backfilling on each isolation trench to form at least one isolation cavity of which the top is sealed by a hard mask layer; and performing planarization processing on the hard mask layer to obtain the semiconductor device with a flat surface and at least one isolation cavity with a sealed top. According to the invention, the defect of step difference formed at the isolation groove in a wet deposition process for preparing the semiconductor device can be avoided, and meanwhile, the requirement on the HARP process filling rate can be reduced, so that the process speed is increased, and the process cost is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor processing, and in particular to a processing method of a semiconductor device and a semiconductor device. Background Art

[0002] With the iteration of chips and the expansion of application fields, BCD (Bipolar-CMOS-DMOS) chips are widely used in new energy vehicles, smart furniture, 5G communications and other fields. Faced with the market demand for the increase of power device voltage platform and further improvement of integration, the isolation between the power area and the logic circuit is the top priority of device integration. Deep Trench Isolation (DTI) is widely used in medium and high voltage power devices due to its excellent isolation performance and low device area.

[0003] At present, the industry usually adds deep trench process before and after shallow trench isolation (STI) process to achieve isolation between devices. Figures 1A to 1G , during the groove processing, Figure 1A As shown in the figure, a shallow trench isolation 111 is formed directly on the substrate (SUB) 110, and then a hard mask (HM) layer 120 is deposited on the shallow trench isolation 111. Figure 1B As shown in FIG. 1 , a photoresist (PR) layer 130 is formed by coating a photoresist on the hard mask layer 120, and then an etching region 131 is defined by photolithography. Figure 1C As shown in FIG. 1 , hard mask etching is performed in the determined etching area 131. Then, as shown in FIG. Figure 1D As shown, the substrate 110 is deep-grooved by using the hard mask layer 120 as a shield to form a deep trench 1310 in the substrate 120. Then, as shown in FIG. Figure 1E As shown, the deep trench 1310 is backfilled with a filling dielectric 140, wherein the oxide layer used to fill the deep trench 1310 can be deposited until it is higher than the hard mask layer 120. Thereafter, as shown in FIG. Figure 1F As shown, chemical mechanical planarization is performed to remove the filling dielectric 140 above the hard mask layer 120. Finally, as shown in FIG. Figure 1G As shown, a wet etching process may be used to accurately etch the semiconductor device to form a deep trench isolation 141 .

[0004] However, in the process of implementing the above process, on the one hand, due to the large depth-to-width ratio of the deep trench 1310, it will increase the difficulty of subsequent trench backfilling, and a special machine is required to implement a high aspect ratio process (High Aspect Ratio Process, HARP), which will increase the equipment cost. On the other hand, since the closing position of the filling medium 140 will determine the process window, if the closing position is close to the top, such as Figure 1G As shown, in the wet etching process, a small gap 1410 may be eaten out of the deep trench isolation 141, affecting its isolation performance. In addition, the filling medium of the shallow trench isolation 111 is different from that of the deep trench isolation 141. After the wet etching process, the different densities of the thin film (such as the oxide layer) will cause differences in etching rates, which will eventually lead to a step difference at the boundary between the deep trench isolation 141 and the shallow trench isolation 111, thereby introducing unnecessary impurity residues. At present, multiple backfilling and chemical mechanical polishing (CMP) are required to ensure the consistency of the closing position of the isolation medium and the properties of the top film, which increases time consumption, affects production capacity and increases process costs.

[0005] In order to solve the above-mentioned problems existing in the prior art, the art urgently needs a semiconductor device processing technology that can avoid the defect of step difference formed at the isolation groove in the wet deposition process of preparing semiconductor devices, and at the same time reduce the requirements for the HARP process filling rate, thereby improving the process speed and reducing the process cost. Summary of the invention

[0006] A brief summary of one or more aspects is given below to provide a basic understanding of these aspects. This summary is not an exhaustive overview of all conceived aspects, and is neither intended to identify the key or decisive elements of all aspects nor to define the scope of any or all aspects. Its only purpose is to give some concepts of one or more aspects in a simplified form as a prelude to a more detailed description that will be given later.

[0007] In order to overcome the above-mentioned defects in the prior art, the present invention provides a method for processing a semiconductor device and a semiconductor device, which can avoid the defect of forming a step difference at the isolation groove in the wet deposition process for preparing the semiconductor device, and at the same time reduce the requirements for the filling rate of the HARP process, thereby improving the process speed and reducing the process cost.

[0008] Specifically, the processing method of the above-mentioned semiconductor device provided according to the first aspect of the present invention includes the following steps: preparing a sample to be processed, wherein the sample to be processed includes a substrate, and a semiconductor device located on the substrate, and the semiconductor device includes a power area and a logic circuit area; performing deep trench etching on at least one target position between the power area and the logic circuit area to form at least one isolation trench reaching the substrate; performing deep trench backfilling on each of the isolation trenches to form at least one isolation cavity whose top is sealed by a hard mask layer; and flattening the hard mask layer to obtain a semiconductor device with a flat surface and at least one isolation cavity sealed on the top.

[0009] Furthermore, in some embodiments of the present invention, the step of preparing the sample to be processed includes: preparing a substrate; and performing at least one deposition process and at least one wet etching process on the substrate to generate at least one semiconductor device with the power area and the logic circuit area on the substrate.

[0010] Further, in some embodiments of the present invention, the step of performing deep trench etching on at least one target position between the power area and the logic circuit area to form at least one isolation groove reaching the substrate includes: depositing a hard mask layer on the sample to be processed to generate a hard mask layer thereon; generating a photoresist layer on the hard mask layer; masking the pattern of the isolation groove, and exposing and developing the photoresist layer to obtain the photoresist layer with the pattern removed; and performing the deep trench etching on the photoresist layer with the pattern removed and the hard mask layer of the pattern area of ​​the isolation groove to form the isolation groove.

[0011] Further, in some embodiments of the present invention, the step of depositing a hard mask layer on the sample to be processed to form a hard mask layer thereon comprises: depositing SiO2 on the sample to be processed to form a hard mask layer with a thickness of SiO2 hard mask layer.

[0012] Furthermore, in some embodiments of the present invention, the step of forming a photoresist layer on the hard mask layer includes: performing photoresist spin coating on the hard mask layer to form a photoresist layer with a thickness of 1.5 um to 3 um thereon.

[0013] Furthermore, in some embodiments of the present invention, the step of performing the deep trench etching on the photoresist layer for removing the pattern and the hard mask layer in the pattern area of ​​the isolation groove to form the isolation groove includes: performing hard mask etching on the photoresist layer for removing the pattern and the hard mask layer in the pattern area of ​​the isolation groove via a mixed gas of C4F8 and O2; and performing the deep trench etching on the sample to be processed that has passed the hard mask etching via a mixed gas of SF6 and O2 to form the isolation groove.

[0014] Further, in some embodiments of the present invention, the step of backfilling each of the isolation trenches to form at least one isolation cavity sealed at the top by a hard mask layer comprises: backfilling each of the isolation trenches to form a deep trench to form at least one isolation cavity sealed at the top by a hard mask layer; SiO2 is deposited to form at least one isolation cavity topped by a SiO2 hard mask layer.

[0015] Further, in some embodiments of the present invention, the step of planarizing the hard mask layer includes: planarizing the hard mask layer to a thickness of The chemical mechanical grinding is performed, and a thickness of not less than The top seal.

[0016] Furthermore, in some embodiments of the present invention, the semiconductor device is selected from at least one of a bipolar transistor, a CMOS transistor, and a DMOS transistor.

[0017] In addition, the above-mentioned semiconductor device provided according to the second aspect of the present invention is located on a substrate to include a power area and a logic circuit area, and there is at least one isolation cavity reaching the substrate and having a top seal between the power area and the logic circuit area, and the top seal of the isolation cavity forms an integrally formed flat surface with the hard mask layer above the power area and the logic circuit area. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above features and advantages of the present invention can be better understood after reading the detailed description of the embodiments of the present disclosure in conjunction with the following drawings. In the drawings, the components are not necessarily drawn to scale, and components with similar related properties or features may have the same or similar reference numerals.

[0019] Figures 1A to 1G A schematic diagram of the preparation process of the trench process in the prior art is shown;

[0020] Figure 2 A flow chart of a method for processing a semiconductor device according to some embodiments of the present invention is shown;

[0021] Figure 3 A schematic structural diagram of a sample to be processed of a semiconductor device provided in some embodiments of the present invention is shown;

[0022] Figure 4 A schematic structural diagram of depositing a hard mask layer on a sample to be processed of a semiconductor device according to some embodiments of the present invention is shown;

[0023] Figure 5 A schematic structural diagram of depositing a photoresist layer on a hard mask layer of a semiconductor device provided in some embodiments of the present invention is shown;

[0024] Figure 6 A schematic diagram of the structure of a semiconductor device after the pattern is removed from a photoresist layer according to some embodiments of the present invention is shown;

[0025] Figure 7 A schematic diagram of a structure for performing hard mask etching in a semiconductor device according to some embodiments of the present invention is shown;

[0026] Figure 8 A schematic diagram of a structure for performing deep trench etching in a semiconductor device according to some embodiments of the present invention is shown;

[0027] Fig. 9 A schematic diagram showing a structure of backfilling a deep trench in a semiconductor device according to some embodiments of the present invention is shown; and

[0028] Fig.10 A schematic structural diagram of chemical mechanical planarization in a semiconductor device provided in some embodiments of the present invention is shown.

[0029] Reference numerals

[0030] 101 logic circuit area;

[0031] 102 non-logical area;

[0032] 110 substrate;

[0033] 111 shallow trench isolation;

[0034] 120, 330 hard mask layer;

[0035] 130, 340 photoresist layer;

[0036] 131 Etched area;

[0037] 1310 deep groove;

[0038] 140 filling medium;

[0039] 141 Deep Trench Isolation;

[0040] 1410 small seam;

[0041] Steps S210 to S240;

[0042] 300 samples to be processed;

[0043] 310 substrate;

[0044] 320 Semiconductor devices;

[0045] 341 removing the patterned photoresist layer;

[0046] 3410 hard mask etch area;

[0047] 350 isolation trench; and

[0048] 360 Isolation Cavity. DETAILED DESCRIPTION

[0049] The following specific embodiments illustrate the implementation of the present invention, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. Although the description of the present invention will be introduced in conjunction with the preferred embodiment, this does not mean that the features of this invention are limited to this implementation. On the contrary, the purpose of introducing the invention in conjunction with the implementation is to cover other options or modifications that may be extended based on the claims of the present invention. In order to provide a deep understanding of the present invention, the following description will include many specific details. The present invention can also be implemented without using these details. In addition, in order to avoid confusion or blurring the focus of the present invention, some specific details will be omitted in the description.

[0050] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0051] In addition, the terms "upper", "lower", "left", "right", "top", "bottom", "horizontal" and "vertical" used in the following description should be understood as the directions shown in the paragraph and the related drawings. Such relative terms are only used for the convenience of description and do not mean that the device described therein must be manufactured or operated in a specific direction, and therefore should not be understood as limiting the present invention.

[0052] It is understood that although the terms "first", "second", "third", etc. may be used herein to describe various components, regions, layers and / or parts, these components, regions, layers and / or parts should not be limited by these terms, and these terms are only used to distinguish different components, regions, layers and / or parts. Therefore, the first component, region, layer and / or part discussed below may be referred to as a second component, region, layer and / or part without departing from some embodiments of the present invention.

[0053] As described above, in the process of implementing the above process, on the one hand, since the depth-width ratio of the deep trench 1310 is relatively large, this will increase the difficulty of subsequent trench backfilling, and a special machine is required to implement HARP, thereby increasing the equipment cost. On the other hand, since the closing position of the filling medium 140 will determine the process window, if the closing position is close to the top, such as Figure 1G As shown, in the wet etching process, a small gap 1410 may be eaten out of the deep trench isolation 141, affecting its isolation performance. In addition, the filling medium of the shallow trench isolation 111 is different from that of the deep trench isolation 141. After the wet etching process, the different densities of the thin film (such as the oxide layer) will cause differences in etching rates, which will eventually lead to a step difference at the boundary between the deep trench isolation 141 and the shallow trench isolation 111, thereby introducing unnecessary impurity residues. At present, multiple backfilling and CMP are required to ensure the consistency of the closing position of the isolation medium and the properties of the top film, which increases time consumption, affects production capacity and increases process costs.

[0054] In order to solve the above-mentioned problems existing in the prior art, the present invention provides a processing method of a semiconductor device and a semiconductor device, which can avoid the defect of step difference formed at the isolation groove in the wet deposition process of preparing the semiconductor device, and at the same time reduce the requirements for the filling rate of the HARP process, thereby improving the process speed and reducing the process cost.

[0055] In some non-limiting embodiments, the processing method of the semiconductor device provided in the first aspect of the present invention can be used to prepare the semiconductor device provided in the second aspect of the present invention.

[0056] The following will describe the various steps in the processing method of the above-mentioned semiconductor device in conjunction with some embodiments of semiconductor devices. Those skilled in the art will understand that these embodiments of semiconductor devices are only some non-limiting implementation methods provided by the present invention, which are intended to clearly demonstrate the main concept of the present invention and provide some specific solutions that are convenient for the public to implement, rather than to limit all steps of the processing method of the semiconductor device, and do not limit the implementation subject of each step. Similarly, the processing method of the semiconductor device is also only a non-limiting implementation method provided by the present invention, and does not limit all working modes or all functions of the semiconductor device.

[0057] Please see Figure 2 , Figure 2 A flow chart of a method for processing a semiconductor device according to some embodiments of the present invention is shown.

[0058] like Figure 2 As shown, in some embodiments of the present invention, a method for processing a semiconductor device may include the following steps: First, step S210 may be performed: preparing a sample to be processed.

[0059] Specifically, please combine Figure 3 Common understanding, Figure 3 A schematic structural diagram of a sample of a semiconductor device to be processed provided according to some embodiments of the present invention is shown.

[0060] like Figure 3 As shown, in some embodiments, a substrate 310 may be prepared first, and then the substrate 310 may be subjected to at least one deposition process and at least one wet etching process to generate at least one semiconductor device 320 with a logic circuit area 101 and a non-logic area 102 on the substrate 310, and obtain a sample to be processed 300. Here, a variety of circuit structures may be integrated in the semiconductor device 320 of the sample to be processed 300, wherein the logic circuit area 101 is used to centrally set the logic units of each circuit structure, and the non-logic area 102 is used to set the remaining structures such as power units in each circuit structure except the logic unit.

[0061] Optionally, the semiconductor device 320 may be selected from at least one of, including but not limited to, a bipolar transistor, a CMOS transistor, and a DMOS transistor.

[0062] Continue back Figure 2 After obtaining the sample 300 to be processed, step S220 may be performed: deep trench etching is performed on at least one target position between the power area and the logic circuit area to form at least one isolation trench reaching the substrate.

[0063] Specifically, please combine Figure 4 Common understanding, Figure 4 A schematic structural diagram of depositing a hard mask layer on a sample to be processed of a semiconductor device provided in some embodiments of the present invention is shown.

[0064] like Figure 4 As shown, in some embodiments, a hard mask layer may be deposited on the sample 300 to form a hard mask layer 330 thereon. Specifically, during the deposition of the hard mask layer 330, SiO2 may be deposited on the sample 300 to form a hard mask layer 330 with a thickness of 100 mm. A SiO2 hard mask layer 330 is formed.

[0065] Furthermore, since the material of the semiconductor device 320 is usually silicon, the material of the hard mask layer 330 can be nitride such as titanium nitride or silicon nitride. Preferably, in order to effectively reduce the stress between the nitride mask and the silicon, a thin oxide layer, i.e., a pad oxide layer, can be generated between the nitride and the silicon. The hard mask layer 330 can include a pad oxide layer and SiO2 from bottom to top, wherein SiO2 can be arranged in the above-mentioned manner according to the depth of the deep trench (DT). Select within the range.

[0066] Afterwards, if Figure 5 As shown, a photoresist layer 340 can be formed on the hard mask layer 330. Specifically, optionally, photoresist can be spin-coated on the surface of the hard mask layer 330 to form a photoresist layer 340 with a thickness of 1.5um to 3um. The photoresist formed by spin coating with a certain thickness can be used as a barrier layer in the hard mask etching process.

[0067] Afterwards, if Figure 6 As shown, the pattern of the isolation groove is blocked, and then the photoresist layer 340 is exposed and developed to display a pattern with deep groove etching on the photoresist layer 340, and obtain a photoresist layer 341 with the pattern removed, thereby determining a hard mask etching area 3410.

[0068] Afterwards, if Figure 7 As shown, the photoresist layer 341 with the pattern removed and the hard mask layer 330 in the pattern area of ​​the isolation groove can be subjected to deep trench etching to obtain the isolation groove 350. Specifically, the present invention can perform hard mask etching on the photoresist layer 341 with the pattern removed and the hard mask layer 330 in the pattern area of ​​the isolation groove by using a mixed gas of C4F8 and O2. Here, the gas mixture ratio of C4F8 and O2 can be 1:1. Afterwards, the present invention can use the hard mask layer 330 as an etching barrier layer, and further perform deep trench etching on the sample to be processed 300 that has been hard mask etched by using an etching gas (for example: a mixed gas of SF6 and O2 with a mixing ratio of 1:0.8 to 1:2) to form Figure 8 Isolation trench 350 is shown.

[0069] Continue back Figure 2 After the isolation trenches 350 are obtained, step S230 may be performed: deep trench backfilling is performed on each isolation trench to form at least one isolation cavity whose top is sealed by a hard mask layer.

[0070] Specifically, please combine Fig. 9 Common understanding, Fig. 9 A schematic structural diagram of deep trench backfilling in a semiconductor device provided in some embodiments of the present invention is shown.

[0071] like Fig. 9 As shown, in some embodiments, the sample 300 to be processed with the isolation trench 350 formed therein can be backfilled with a deep trench by chemical vapor deposition (CVD). Further, based on the CVD principle, a HARP process can be performed to deposit SiO2 in the isolation trench 350, wherein the deposition thickness of SiO2 can be between 100 and 200 nm. In the backfill deposition process, since the gas flow rate above the isolation trench 350 is larger than the gas flow rate at the bottom of the isolation trench 350, the film deposition rate above the isolation trench 350 is faster. That is, when the isolation trench 350 is sealed, the bottom of the isolation trench 350 may still not be filled, thereby forming a cavity structure. Fig. 9 As shown, at least one isolation cavity 360 with a top sealed by a SiO 2 hard mask layer may be finally formed in the sample 300 to be processed.

[0072] Continue back Figure 2 After completing the above-mentioned deep trench backfilling step, step S240 may be performed: planarizing the hard mask layer to obtain a semiconductor device with an isolated cavity having a flat surface and at least one top seal.

[0073] Specifically, please combine Fig.10 Common understanding, Fig.10 A schematic structural diagram of chemical mechanical planarization in a semiconductor device provided in some embodiments of the present invention is shown.

[0074] like Fig.10 As shown, in some embodiments, the upper surface of the hard mask layer 330 may be provided with a preset thickness (eg: ) to grind the upper surface of the hard mask layer 330 flat and retain a predetermined thickness H (for example: The top seal of the above). The SiO2 that has not been ground off can be used as an interlayer dielectric. Since there is no risk of hydrofluoric acid penetration in the present invention, the position requirements for the top seal of the groove are reduced, which can greatly reduce the requirements for the aspect ratio capability of the backfill process. There is no need to use a special machine for the HARP process, which can reduce equipment costs. It is worth noting that the CMP process time needs to be controlled to prevent the isolation cavity 360 in the isolation groove 350 from being ground into during the CMP process, resulting in pores on the wafer surface.

[0075] Although the above methods are illustrated and described as a series of actions for simplicity of explanation, it should be understood and appreciated that these methods are not limited by the order of the actions, because according to one or more embodiments, some actions may occur in a different order and / or concurrently with other actions from those illustrated and described herein or not illustrated and described herein but understandable to those skilled in the art.

[0076] Through the semiconductor device processing method including steps S210 to S240, a semiconductor device provided in another aspect of the present invention can be finally obtained.

[0077] like Fig.10 As shown, in some embodiments of the present invention, the semiconductor device 320 is located on the substrate 310, including the logic circuit area 101 and the non-logic area 102. There is at least one isolation cavity 360 with a top seal that reaches the substrate 320 between the logic circuit area 101 and the non-logic area 120. The top seal of the isolation cavity 360 and the hard mask layer 330 above the logic circuit area 101 and the non-logic area 102 form an integrally formed flat surface. In this embodiment, by sealing the filling medium in the isolation trench 350 below the surface of the interlayer dielectric, the risk of a small gap in the DTI being eaten during the wet process, thereby affecting its isolation performance, can be effectively avoided.

[0078] Those skilled in the art will appreciate that the above-mentioned embodiment of preparing the isolation cavity between the logic circuit area 101 and the non-logic area 102 is only a non-limiting implementation method provided by the present invention, which is intended to demonstrate the main concept of the present invention and provide a specific solution that is convenient for the public to implement, rather than to limit the scope of protection of the present invention.

[0079] Optionally, in other embodiments, those skilled in the art may also, based on the above concept, concentrate non-power devices such as logic units and storage units of each circuit structure in a non-power area, concentrate power units in each circuit structure in a power area, and prepare the above-mentioned isolation cavity between the non-power area and the power area to achieve the same electrical isolation effect.

[0080] Optionally, in other embodiments, those skilled in the art may also, based on the above concept, concentrate a portion of non-power devices that are not resistant to high voltage, such as logic units and storage units of each circuit structure, in a non-power area, and concentrate the power units in each circuit structure and another portion of non-power devices that are resistant to high voltage in a non-logic area, and prepare the above-mentioned isolation cavity between the non-power area and the non-logic area to achieve the same electrical isolation effect.

[0081] Therefore, based on the description of the above-mentioned various alternative implementations, the present invention can meet the electrical isolation requirements of the BCD chip as long as the isolation cavity is prepared between the power area and the logic circuit area of ​​the semiconductor device.

[0082] Furthermore, in each of the above embodiments provided by the present invention, after the wet deposition process (step S210) for preparing the semiconductor device is implemented, a deep trench etching process (step S230), a deep trench backfilling process (step S230) and a planarization process (step S240) are implemented on the semiconductor device 320. By postponing the deep trench etching process to the deposition of the interlayer dielectric (ILD), the present invention can completely solve the problem of step difference caused by different etching rates between dielectrics in the wet etching process, thereby solving the defect problem that may affect the product yield by optimizing the process flow. Moreover, since there is no large amount of wet process in the second half of the steps, the present invention leaves a sufficient process window after the deep trench backfilling forms the isolation cavity 360 structure, so it does not need to be completely filled, thereby reducing the demand for the HARP process, and reducing the equipment cost and the manufacturing cost of the semiconductor device.

[0083] In addition, in the prior art, Figures 1A to 1G In the process of preparing the semiconductor device shown in , before the semiconductor device is prepared, deep trench etching is directly performed on the substrate. The deep trench etching will produce some lattice defects on the side wall of the substrate, and usually a sacrificial oxide layer needs to be deposited and then removed to repair the defects. In the present invention, by preparing the deep trench (i.e., the isolation trench 350) after the interlayer dielectric (such as SiO2), the silicon on the surface of the trench can be removed by chemical etching, thereby ensuring that the lattice defects on the surface of the deep trench are reduced as much as possible.

[0084] In summary, the present invention provides a method for processing a semiconductor device and a semiconductor device, which can avoid the defect of step difference formed at the isolation groove in the wet deposition process of preparing the semiconductor device, and at the same time provide a sufficient process window, reduce the requirements for the HARP process filling rate, thereby improving the process speed and reducing the process cost.

[0085] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but should be granted the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for processing a semiconductor device, characterized in that: The following steps are involved: Preparing a sample to be processed, wherein the sample to be processed includes a substrate and a semiconductor device located on the substrate, and the semiconductor device includes a power area and a logic circuit area; Performing deep trench etching on at least one target location between the power area and the logic circuit area to form at least one isolation trench reaching the substrate; Performing deep trench backfilling on each of the isolation trenches to form at least one isolation cavity whose top is sealed by a hard mask layer; and The hard mask layer is planarized to obtain a semiconductor device with a flat surface and an isolated cavity with at least one top seal.

2. The processing method according to claim 1, characterized in that: The steps of preparing the sample to be processed include: preparing a substrate; and The substrate is subjected to at least one deposition process and at least one wet etching process to generate at least one semiconductor device having the power region and the logic circuit region on the substrate.

3. The processing method according to claim 1, characterized in that: The step of performing deep trench etching on at least one target position between the power area and the logic circuit area to form at least one isolation trench reaching the substrate comprises: Depositing a hard mask layer on the sample to be processed to form a hard mask layer thereon; forming a photoresist layer on the hard mask layer; shielding the pattern of the isolation groove, and exposing and developing the photoresist layer to obtain the photoresist layer with the pattern removed; and The deep trench etching is performed on the photoresist layer with the pattern removed and the hard mask layer in the pattern area of ​​the isolation trench to form the isolation trench.

4. The processing method according to claim 3, characterized in that: The step of depositing a hard mask layer on the sample to be processed to form a hard mask layer thereon comprises: SiO2 is deposited on the sample to be processed to form a layer with a thickness of SiO2 hard mask layer.

5. The processing method according to claim 3, characterized in that: The step of forming a photoresist layer on the hard mask layer comprises: The hard mask layer is subjected to photoresist spin coating to form a photoresist layer with a thickness of 1.5um to 3um thereon.

6. The processing method according to claim 3, characterized in that: The step of performing the deep trench etching on the photoresist layer for removing the pattern and the hard mask layer in the pattern area of ​​the isolation trench to form the isolation trench comprises: Performing hard mask etching on the photoresist layer to remove the pattern and the hard mask layer in the pattern area of ​​the isolation trench through a mixed gas of C4F8 and O2; and The deep trench etching is performed on the sample to be processed after the hard mask etching by using a mixed gas of SF6 and O2 to form the isolation trench.

7. The processing method according to claim 1, characterized in that: The step of backfilling each of the isolation trenches to form at least one isolation cavity whose top is sealed by a hard mask layer comprises: The sample to be processed for forming the isolation trench is processed SiO2 is deposited to form at least one isolation cavity topped by a SiO2 hard mask layer.

8. The processing method according to claim 1, characterized in that: The step of planarizing the hard mask layer comprises: The hard mask layer is formed to a thickness of The chemical mechanical grinding is performed, and a thickness of not less than The top seal.

9. The processing method according to claim 1, characterized in that: The semiconductor device is selected from at least one of a bipolar transistor, a CMOS transistor, and a DMOS transistor.

10. A semiconductor device, located on a substrate, comprising a power region and a logic circuit region, characterized in that: There is at least one isolation cavity between the power area and the logic circuit area, which reaches the substrate and has a top seal. The top seal of the isolation cavity and the hard mask layer above the power area and the logic circuit area form an integrally formed flat surface.

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