Formation method of semiconductor structure

Abstract

The embodiment of the invention discloses a method for forming a semiconductor structure. The method comprises the steps of providing a semiconductor layer and a dielectric layer located on the semiconductor layer; the semiconductor layer comprises an array region and a peripheral region which are arranged in parallel along a first direction; a conductive structure is formed in the dielectric layer right above the peripheral region; the first direction is perpendicular to the thickness direction of the semiconductor layer; through holes penetrating through the dielectric layer and extending to the semiconductor layer are formed in the two opposite sides of the conductive structure in the first direction; forming a protective layer on the side wall and the bottom wall of the through hole; removing the protection layer on the bottom wall of the through hole to expose the semiconductor layer; cleaning the through hole by using a cleaning agent; the cleaning agent comprises ammonia water, ultrapure water and hydrofluoric acid.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a method for forming a semiconductor structure. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a common storage device with the characteristics of high integration, fast read and write speed, and low price. It is widely used in various consumer electronic products such as computers, mobile phones, set-top boxes, etc.

[0003] However, there are still many problems to be solved in dynamic random access memory.

[0004] Public Content

[0005] In view of this, an embodiment of the present disclosure provides a method for forming a semiconductor structure, the method for forming a semiconductor structure comprising:

[0006] A semiconductor layer and a dielectric layer located on the semiconductor layer are provided; the semiconductor layer comprises an array region and a peripheral region arranged in parallel along a first direction; a conductive structure is formed in the dielectric layer located directly above the peripheral region; the first direction is perpendicular to the thickness direction of the semiconductor layer;

[0007] Forming through holes penetrating the dielectric layer and extending to the semiconductor layer on two opposite sides of the conductive structure along the first direction;

[0008] forming a protective layer on the sidewalls and bottom wall of the through hole;

[0009] removing the protective layer on the bottom wall of the through hole to expose the semiconductor layer;

[0010] The through hole is cleaned by using a cleaning agent; the cleaning agent includes ammonia water, ultrapure water, and hydrofluoric acid.

[0011] In the above scheme, the cleaning process of the through hole using a cleaning agent includes:

[0012] The semiconductor layer exposed in the through hole is cleaned once by using a first cleaning agent; the first cleaning agent includes ammonia water, ultrapure water, and hydrofluoric acid.

[0013] In the above scheme, the volume ratio of ammonia water to ultrapure water in the first cleaning agent ranges from 100:1 to 400:1.

[0014] In the above scheme, the time range of the cleaning treatment is 10s-30s.

[0015] In the above solution, the material of the protective layer includes silicon nitride, and the material of the dielectric layer includes one or more of silicon oxide and silicon oxynitride.

[0016] In the above scheme, the cleaning process of the through hole using a cleaning agent includes:

[0017] Using a second cleaning agent to perform a first cleaning process on the semiconductor layer exposed in the through hole; the second cleaning agent includes hydrofluoric acid;

[0018] The semiconductor layer exposed in the through hole is cleaned for the second time using a third cleaning agent; the third cleaning agent includes hydrofluoric acid, ammonia water, and ultrapure water.

[0019] In the above scheme, the method further includes:

[0020] After the through hole is cleaned by a cleaning agent, a contact structure is formed in the through hole.

[0021] In the above solution, the forming of the contact structure comprises:

[0022] forming a metal layer at the bottom of the through hole;

[0023] The metal layer and the semiconductor layer are subjected to heat treatment so that the metal layer and the semiconductor layer react to generate a metal-semiconductor compound layer.

[0024] In the above scheme, the method further includes:

[0025] After forming the metal semiconductor compound layer, the through hole is cleaned for a third time using a fourth cleaning agent; the fourth cleaning agent includes hydrofluoric acid, and the time range of the third cleaning treatment is 20s-50s.

[0026] In the above solution, the forming of the contact structure further comprises:

[0027] forming a metal nitride layer covering the sidewall of the protective layer and the metal semiconductor compound layer;

[0028] After the metal nitride layer is formed, a conductive material layer is filled in the through hole.

[0029] The present embodiment discloses a method for forming a semiconductor structure, comprising: providing a semiconductor layer and a dielectric layer located on the semiconductor layer; the semiconductor layer comprises an array area and a peripheral area arranged in parallel along a first direction; a conductive structure is formed in the dielectric layer directly above the peripheral area; the first direction is perpendicular to the thickness direction of the semiconductor layer; through holes are formed on opposite sides of the conductive structure along the first direction, penetrating the dielectric layer and extending to the semiconductor layer; a protective layer is formed on the side walls and bottom walls of the through hole; the protective layer on the bottom wall of the through hole is removed to expose the semiconductor layer; and the through hole is cleaned using a cleaning agent; the cleaning agent comprises ammonia water, ultrapure water, and hydrofluoric acid. In the embodiment of the present disclosure, before forming the metal semiconductor compound, the exposed semiconductor layer is cleaned, and the cleaning agent includes ammonia water, ultrapure water, and hydrofluoric acid. The mixture of ammonia water and ultrapure water can effectively remove the polysilicon in the second layer of the semiconductor layer, and the hydrofluoric acid can effectively remove the silicon oxide in the third layer and the second layer of the semiconductor layer, so that the oxide layer on the surface of the semiconductor layer can be cleaned, and the surface of the semiconductor layer can be effectively cleaned, so that the contact structure formed in the subsequent process can be in good contact with the semiconductor layer, and the contact resistance between the semiconductor layer and the contact structure can be reduced, so that the performance of the semiconductor structure can be improved. In addition, in the embodiment of the present disclosure, after the through hole is formed, a protective layer is formed on the side wall of the through hole, so that in the subsequent cleaning process and etching process, the protective layer can protect the dielectric layer, so that the problem of short circuit between the contact structure and the conductive structure caused by the increase in size of the through hole in the subsequent cleaning and etching process can be improved, which is conducive to improving the performance and yield of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figures 1 to 6 A schematic structural diagram of a formation process of a semiconductor structure according to an embodiment of the present disclosure;

[0031] Figure 7 is an enlarged structural schematic diagram of a semiconductor layer according to an embodiment of the present disclosure;

[0032] Figure 8 is a schematic cross-sectional structural diagram of a semiconductor structure according to an embodiment of the present disclosure;

[0033] Fig. 9 A schematic diagram of a process for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0034] Figures 10 to 16 A structural schematic diagram of a semiconductor structure forming process provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0035] In order to make the technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation methods described herein. On the contrary, these implementation methods are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0036] The present disclosure is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present disclosure.

[0037] It will be understood that the meaning of “on,” “over,” and “over” in this disclosure should be interpreted in the broadest manner, so that “on” not only means that it is “on” something with no intervening features or layers (i.e., directly on something), but also includes the meaning that it is “on” something with intervening features or layers.

[0038] Additionally, for ease of description, spatially relative terms such as "on," "over," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0039] In the disclosed embodiments, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can include a variety of semiconductor materials, such as silicon, silicon germanium, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of non-conductive materials, such as glass, plastic, or sapphire wafers.

[0040] In the disclosed embodiments, the term "layer" refers to a material portion including an area with a thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range that is smaller than the range of a lower or upper structure. In addition, a layer may be a region of a homogeneous or inhomogeneous continuous structure having a thickness that is less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. For example, an interconnect layer may include one or more conductors and contact sublayers (where interconnects and / or via contacts are formed), and one or more dielectric sublayers.

[0041] In the embodiments of the present disclosure, the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0042] In DRAM, a 1T1C structure consisting of a transistor and a capacitor is usually used as a storage unit. The voltage signal on the word line can control the opening or closing of the transistor, and then read the data in the capacitor through the bit line, or write the data into the capacitor through the bit line for storage. DRAM includes an array area and a peripheral area. The array area is used to store data. The peripheral circuits in the peripheral area can be connected to the bit lines and word lines, and the storage units in the array area are controlled by the bit lines and word lines to store or read data information. Exemplarily, the peripheral circuits may include a write circuit, a read circuit, a control logic, an input and output circuit, a row address decoder, a column address decoder, etc.

[0043] Figures 1 to 6 A schematic diagram of a semiconductor structure forming process provided by an embodiment of the present disclosure, wherein: Figure 1 is a top view schematic diagram of the semiconductor structure, Figures 2 to 6 is a cross-sectional schematic diagram of the semiconductor structure. Figures 2 to 6 The cross-sectional view of the array area is Figure 1 The cross-sectional view at the AA' position, Figures 2 to 6 The cross-sectional view of the central and peripheral regions is Figure 1 The cross-sectional view of the BB' position. Figures 1 to 6 A method for forming a semiconductor structure provided in an embodiment of the present disclosure is introduced.

[0044] like Figure 1 as well as Figure 2As shown, a semiconductor layer 101 and a dielectric layer 102 are provided, and the semiconductor layer 101 includes an array area and a peripheral area arranged in parallel along the X direction, and a conductive structure 103 is formed in the dielectric layer 102 on the peripheral area. The array area includes a plurality of active areas 110, and the plurality of active areas 110 are arranged in an array, and each active area 110 can be used to form one or two transistors. In this embodiment, each active area 110 is used to form two transistors arranged in a thickness direction perpendicular to the semiconductor layer 101, and the two transistors share a first electrode area and can be connected to the same bit line, and the second electrode area of ​​one of the two transistors is connected to a capacitor, and the second electrode area of ​​the other transistor is connected to another capacitor.

[0045] In some specific examples, the dielectric layer 102 includes a first sub-dielectric layer 126 and a second sub-dielectric layer 127 . The material of the first sub-dielectric layer 126 includes silicon oxide, and the material of the second sub-dielectric layer 127 includes silicon nitride.

[0046] In some specific examples, the material of the semiconductor layer 101 includes polysilicon.

[0047] like Figure 1 As shown, the semiconductor structure further includes a plurality of word lines 111 and a plurality of bit lines 112, the word lines 111 pass through the active area 110, each word line 111 extends along the X direction and is connected to the channel regions of a plurality of transistors arranged in parallel along the X direction, and the plurality of word lines 111 are arranged along the Y direction. The bit lines 112 are located on the semiconductor layer 101, the bit lines 112 extend along the Y direction, and are connected to the first electrode regions of a plurality of transistors arranged in parallel along the Y direction.

[0048] In some specific examples, the first electrode region may be a drain of a transistor, and the second electrode region may be a source of the transistor.

[0049] like Figure 2 As shown, the word line 111 is formed in the array region, and the word line 111 may be a composite word line layer, including a first sub-word line layer 115 and a second sub-word line layer 116 located on the first sub-word line layer 115. The material of the first sub-word line layer 115 includes but is not limited to titanium nitride, and the material of the second sub-word line layer 116 includes but is not limited to polysilicon. A capacitor contact structure 117 is also formed on the word line 111, and the capacitor contact structure 117 can be used to connect the capacitor to the second electrode region of the active region 110.

[0050] like Figure 2 As shown, the capacitor contact structure 117 is covered with a first insulating layer 118 formed in the previous process, which will affect the contact between the capacitor contact structure 117 and the capacitor, so the first insulating layer 118 needs to be removed in the subsequent process. In some specific examples, the material of the first insulating layer 118 includes silicon nitride.

[0051] like Figure 2 As shown, a through hole 104 is formed in the dielectric layer 102 directly above the peripheral region, penetrating the dielectric layer 102 and extending into the semiconductor layer 101, and the through hole 104 is located on two opposite sides of the conductive structure 103 along the X direction. In some specific examples, the through hole 104 can be formed by a dry etching process.

[0052] In the process of forming the through hole 104 by using the dry etching process, byproducts including polymers and particles are formed. Therefore, it is necessary to perform a first cleaning process on the semiconductor structure after forming the through hole 104 to avoid affecting the performance of the semiconductor structure.

[0053] Next, if Figure 3 As shown, the first insulating layer 118 on the array region is removed by a dry etching process.

[0054] In addition, the first insulating layer 118 is generally removed by a dry etching process, which will form byproducts including polymers and particles. Therefore, after removing the first insulating layer 118, the semiconductor structure needs to be cleaned for a second time, and the cleaning agent for the second cleaning process includes hydrofluoric acid. And because the semiconductor layer is exposed after the through hole is formed, the surface of the semiconductor layer is oxidized to form silicon oxide, so a vapor strip process (Vapor Strip) is used to remove the silicon oxide on the surface of the semiconductor layer. Specifically, HF, NH3 and other gases that consume silicon oxide can be used to remove the oxide layer on the surface of the semiconductor layer.

[0055] Next, if Figure 4 As shown, a metal semiconductor compound layer 107 is formed at the bottom of the through hole 104. Since silicon oxide is easily formed when the metal semiconductor compound layer 107 is formed, a third cleaning process is required after the metal semiconductor compound layer 107 is formed to clean the surface of the metal semiconductor compound layer 107.

[0056] Next, if Figure 5 As shown, a metal nitride layer 108 is formed on the bottom and sidewall of the through hole 104 where the metal semiconductor compound layer 107 is formed.

[0057] Next, if Figure 6 As shown, a conductive material layer 109 is formed on the sidewall and bottom of the through hole 104 where the metal nitride layer 108 is formed.

[0058] In the process of forming the semiconductor structure provided in the above embodiment, during the process of removing the first insulating layer 118, since etching gas such as oxygen is used, and before the second cleaning process is performed, the semiconductor structure may be in contact with air, so that the surface of the exposed semiconductor layer 101 is oxidized, and since the oxygen plasma formed when the first insulating layer 118 is removed by dry etching has a certain energy and can enter the interior of the semiconductor layer 101, the semiconductor layer 101 appears as follows: Figure 7 In the layered structure shown, the first layer at the bottom is polysilicon, the third layer at the top is silicon oxide, and the second layer between the first layer and the third layer is a mixed layer of silicon oxide and polysilicon. In the second cleaning process of the above embodiment, the hydrofluoric acid used can only clean and remove the silicon oxide in the third layer, while the silicon oxide in the second layer is difficult to remove, so that the contact resistance between the contact structure formed subsequently and the semiconductor layer 101 is large, which affects the performance of the device.

[0059] In addition, when the first insulating layer 118 is removed, the first sub-dielectric layer 126 on the side wall of the through hole is also partially consumed, so that the size of the through hole 104 in the direction perpendicular to the thickness of the semiconductor layer 101 increases, and in the process of removing silicon oxide on the surface of the semiconductor layer during the first cleaning process, the second cleaning process, the third cleaning process and the steam removal process, the dielectric layer 102 on the side wall of the through hole 104 is exposed, so that a certain amount of the dielectric layer 102 is consumed, so that the size of the through hole 104 in the direction perpendicular to the thickness of the semiconductor layer 101 is further increased, thereby forming a Figure 8 In the semiconductor structure shown, the size of the portion of the contact structure 106 located in the first sub-dielectric layer 126 is relatively large, which reduces the distance between the conductive structure 103 and the contact structure 106, making it easy to cause a short circuit, resulting in device failure and reduced production yield. As the size of the semiconductor structure continues to shrink, this phenomenon becomes more serious.

[0060] Based on this, in order to solve the above problems, the present disclosure provides a method for forming a semiconductor structure. Fig. 9 The following is a flow chart of a method for forming a semiconductor structure provided by an embodiment of the present disclosure. Fig. 9 As shown, the method for forming a semiconductor structure provided by the embodiment of the present disclosure includes the following steps:

[0061] S1100: providing a semiconductor layer and a dielectric layer located on the semiconductor layer; the semiconductor layer comprises an array region and a peripheral region arranged in parallel along a first direction; a conductive structure is formed in the dielectric layer located directly above the peripheral region; the first direction is perpendicular to a thickness direction of the semiconductor layer;

[0062] S1200: forming through holes penetrating the dielectric layer and extending to the semiconductor layer on two opposite sides of the conductive structure along the first direction;

[0063] S1300: forming a protective layer on the side wall and the bottom wall of the through hole;

[0064] S1400: removing the protective layer on the bottom wall of the through hole to expose the semiconductor layer;

[0065] S1500: cleaning the through hole with a cleaning agent; the cleaning agent includes ammonia water, ultrapure water, and hydrofluoric acid.

[0066] It should be understood that Fig. 9 The steps shown in the operation are not exclusive, and other steps may be performed before, after or between any steps in the operation shown; Fig. 9 The steps shown in the figure can be adjusted in sequence according to actual needs.

[0067] Figures 10 to 16 A schematic diagram of another semiconductor structure during the formation process provided by the embodiment of the present disclosure. Figures 10 to 16 The method for forming the semiconductor structure provided in the embodiment of the present disclosure is specifically introduced.

[0068] See also Fig.10 , perform step S1100 to provide a semiconductor layer 101 and a dielectric layer 102, wherein the semiconductor layer 101 includes an array region and a peripheral region arranged along a first direction.

[0069] Here, the first direction can be as follows Fig.10 The X direction shown in .

[0070] like Fig.10 As shown, the word line 111 is formed in the array region, and a first isolation structure 113 or a second isolation structure 114 is formed between two adjacent word lines 111 to isolate the adjacent word lines 111. The word line 111 includes a first sub-word line layer 115 and a second sub-word line layer 116 located on the first sub-word line layer 115. The material of the first sub-word line layer 115 includes but is not limited to titanium nitride, and the material of the second sub-word line layer 116 includes but is not limited to polysilicon. A capacitor contact structure 117 is also formed on the word line 111, and the capacitor contact structure 117 can be used to connect the capacitor to the second electrode region of the active region 110.

[0071] In some specific examples, the semiconductor layer 101 may include but is not limited to a substrate. The substrate may be made of silicon, germanium, silicon germanium semiconductor, silicon carbide, etc., or may be silicon on insulator (SOI) or germanium on insulator (GOI), or may be other materials, such as III or V group compounds such as gallium arsenide.

[0072] In some embodiments, the material of the dielectric layer 102 includes one or more of silicon oxide and silicon oxynitride.

[0073] In some specific examples, the dielectric layer 102 may be a single layer material or a multi-layer material. Fig.10 As shown, the dielectric layer 102 includes a first sub-dielectric layer 126 and a second sub-dielectric layer 127 located on the first sub-dielectric layer 126. The material of the first sub-dielectric layer 126 includes silicon oxide, and the material of the second sub-dielectric layer 127 includes silicon nitride.

[0074] In some specific examples, the peripheral device can be formed by implanting different concentrations and types of doping ions into the peripheral region to form the source and drain of the transistor, or the well region, deep well region, etc. of other devices. The peripheral region also includes a third isolation structure 128 to isolate adjacent devices.

[0075] like Fig.10 As shown, a conductive structure 103 is formed on the peripheral region, and the conductive structure 103 can constitute a part of a peripheral gate structure (Periphery Gate, PG). The gate structure can be used to form transistors in the peripheral circuit, and various devices formed by transistors (such as inverters). The gate structure also includes a gate dielectric layer, which is provided between the conductive structure 103 and the semiconductor layer 101, and is used to isolate the conductive structure 103 from the semiconductor layer 101. The conductive structure 103 and the gate dielectric layer constitute a gate structure.

[0076] In some specific examples, the conductive structure 103 may include a polysilicon layer 119, a first metal nitride layer 120, and a first metal layer 121 stacked sequentially from bottom to top. The polysilicon layer 119 may include doped polysilicon, the material of the first metal nitride layer 120 includes but is not limited to titanium nitride, tungsten nitride, and tantalum nitride, and the material of the first metal layer 121 includes but is not limited to tungsten, copper, aluminum, cobalt, and the like.

[0077] In some specific examples, the semiconductor structure further includes a third isolation structure 128 located in the peripheral region, and the material of the third isolation structure 128 includes silicon nitride and silicon oxide. The third isolation structure 128 is used to isolate adjacent devices.

[0078] In some specific examples, the semiconductor structure further includes a fourth isolation structure 122 covering the sidewall of the conductive structure 103. By way of example, the fourth isolation structure 122 includes a first nitride layer 123, an oxide layer 124, and a second nitride layer 125 sequentially stacked on the sidewall of the conductive structure 103. By way of example, the material of the first nitride layer 123 includes silicon nitride, the material of the oxide layer 124 includes silicon oxide, and the material of the second nitride layer 125 includes silicon nitride.

[0079] See also Fig.11 , perform step S1200 to form a through hole 104 that penetrates the dielectric layer 102 and extends to the semiconductor layer 101.

[0080] In some specific examples, a method of forming the through hole 104 includes, but is not limited to, a dry etching process.

[0081] In some specific examples, the method further includes cleaning the through hole 104 after forming the through hole 104, and the cleaning solution includes hydrofluoric acid.

[0082] It is understandable that in the process of forming the through hole 104 by dry etching, byproducts such as polymers and particles will be formed on the sidewalls of the through hole 104. Cleaning can effectively remove the byproducts and particles remaining in the through hole 104 and reduce the generation of defects.

[0083] See also Fig.12 , executing step S1300 , forming a protection layer 105 on the sidewalls and bottom wall of the through hole 104 .

[0084] In some specific examples, the method of forming the protective layer 105 includes but is not limited to physical vapor deposition (PVD) process, chemical vapor deposition (CVD) process, atomic layer deposition (ALD) process and the like.

[0085] Taking atomic layer deposition as an example, the protective layer 105 obtained by the atomic layer deposition process is uniform and dense, has a good step coverage, and the deposition thickness is controllable.

[0086] In some specific examples, a protection layer 105 is also formed on the surface of the dielectric layer 102 .

[0087] In some specific examples, the material of the protection layer 105 includes but is not limited to silicon nitride.

[0088] See also Fig.13 , perform step S1400 to remove the protection layer 105 on the bottom wall of the through hole 104 to expose the semiconductor layer 101.

[0089] Here, after the protective layer 105 on the bottom wall of the through hole 104 is removed, the semiconductor layer 101 is exposed, so that the contact structure formed subsequently is connected to the semiconductor layer 101 .

[0090] In some specific examples, the method of removing the protective layer 105 covering the bottom wall of the through hole 104 includes but is not limited to a dry etching process. When the dry etching process is used to remove the first insulating layer 118, the protective layer 105 at the bottom of the through hole 104 can be etched to remove the protective layer 105 at the bottom of the through hole 104. In this way, the process steps can be reduced and the process cycle can be shortened.

[0091] In the method for forming a semiconductor structure provided by an embodiment of the present disclosure, after forming the through hole 104, a protective layer 105 is formed on the side wall of the through hole 104. Since the material of the protective layer 105 is different from the material of the first sub-dielectric layer 126, and the material of the protective layer 105 is silicon nitride, the protective layer 105 can protect the dielectric layer 102 during the subsequent cleaning and etching processes, thereby improving the problem of short circuit between the contact structure and the conductive structure 103 caused by the increase in size of the through hole 104 during the cleaning and etching processes, which is beneficial to improving the performance and yield of the device.

[0092] Next, step S1500 is performed to clean the through hole 104 using a cleaning agent. The cleaning agent includes ammonia water, ultrapure water, and hydrofluoric acid.

[0093] It is understood that, in the embodiment of the present disclosure, before forming the metal semiconductor compound, the exposed semiconductor layer 101 is cleaned, and the cleaning agent includes ammonia water, ultrapure water, and hydrofluoric acid. Figure 7 In the three layers shown, the mixture of ammonia water and ultrapure water can effectively remove the polysilicon of the second layer, and the hydrofluoric acid can effectively remove the silicon oxide, so that the oxide layer on the surface of the semiconductor layer 101 can be cleaned up, thereby having a good cleaning effect on the surface of the semiconductor layer 101, so that the contact structure formed in the subsequent process can have a good contact with the semiconductor layer 101, and reduce the contact resistance between the semiconductor layer 101 and the contact structure, so that the performance of the semiconductor structure can be improved.

[0094] The cleaning process of the first layer and the second layer on the surface of the semiconductor layer can be completed in one cleaning or in two cleanings. The process of one cleaning will be first introduced below.

[0095] In some embodiments, the cleaning process of the through hole 104 using a cleaning agent includes:

[0096] The semiconductor layer 101 exposed in the through hole 104 is cleaned once by using a first cleaning agent; the first cleaning agent includes ammonia water, ultrapure water, and hydrofluoric acid.

[0097] In some embodiments, the volume ratio of ammonia water to ultrapure water in the first cleaning agent ranges from 100:1 to 400:1.

[0098] In some embodiments, the time range of the cleaning process is 10s-30s.

[0099] Here, the time for one cleaning can be set according to actual needs. Since the protective layer 105 is formed on the side wall of the through hole, the dielectric layer 102 can be protected, so the influence of cleaning on the dielectric layer 102 can be eliminated, so that the cleaning process does not need to shorten the cleaning time due to the influence on the dielectric layer 102, which ultimately causes the problem of incomplete cleaning.

[0100] It can be understood that in the above embodiment, the surface of the semiconductor layer 101 is cleaned once, so that the cleaning efficiency can be improved.

[0101] The process of cleaning the first layer and the second layer on the surface of the semiconductor layer is introduced below in two cleaning steps.

[0102] In some embodiments, the cleaning process of the through hole 104 using a cleaning agent includes:

[0103] Performing a first cleaning treatment on the semiconductor layer 101 exposed in the through hole 104 using a second cleaning agent; the second cleaning agent includes hydrofluoric acid;

[0104] The semiconductor layer 101 exposed in the through hole 104 is cleaned for the second time using a third cleaning agent; the third cleaning agent includes hydrofluoric acid, ammonia water, and ultrapure water.

[0105] It can be understood that in the above embodiment, the cleaning treatment of the first layer and the second layer on the surface of the semiconductor layer is completed twice. The second cleaning agent of the first cleaning treatment includes hydrofluoric acid, which can be used to first remove the silicon oxide of the third layer, and then perform the second cleaning treatment. The third cleaning agent of the second cleaning treatment includes hydrofluoric acid, ammonia water, and ultrapure water, which can achieve the removal of the mixed layer of silicon oxide and polysilicon on the second layer.

[0106] In some embodiments, Figures 14 to 16 As shown, the method also includes:

[0107] After the through hole 104 is cleaned with a cleaning agent, a contact structure 106 is formed in the through hole 104 .

[0108] In some embodiments, Fig.14 As shown, a metal semiconductor compound layer 107 is formed at the bottom of the through hole 104 , and the metal semiconductor compound layer 107 is connected to the semiconductor layer 101 .

[0109] In some embodiments, forming the contact structure 106 includes:

[0110] forming a metal layer at the bottom of the through hole 104;

[0111] The metal layer and the semiconductor layer 101 are heat-treated so that the metal layer and the semiconductor layer 101 react to generate a metal-semiconductor compound layer 107 .

[0112] In some specific examples, the material of the metal layer includes but is not limited to cobalt (Co). In the case where the semiconductor layer is a silicon-based substrate, after heat treatment of the metal layer and the semiconductor layer 101, the metal layer at the bottom of the through hole 104 chemically reacts with the semiconductor layer 101 to generate cobalt silicide. The metal semiconductor compound layer 107 can reduce the contact resistance of the device.

[0113] In some specific examples, the material of the metal semiconductor compound layer 107 includes cobalt silicide, titanium silicide, molybdenum silicide, tungsten silicide, etc.

[0114] In some embodiments, the method further comprises:

[0115] After the metal semiconductor compound layer 107 is formed, the through hole 104 is cleaned for the third time using a fourth cleaning agent; the fourth cleaning agent includes hydrofluoric acid, and the third cleaning time ranges from 20s to 50s.

[0116] It is understandable that after the metal semiconductor compound layer 107 is formed, there will be a certain amount of silicon oxide on the surface of the metal semiconductor compound layer 107, which needs to be removed accordingly to reduce the contact resistance between the metal semiconductor compound layer 107 and the subsequently formed metal nitride layer 108. In the embodiment of the present disclosure, when the protective layer 105 is used to protect the side wall of the dielectric layer 102, the consumption of the dielectric layer 102 by the fourth cleaning agent can be avoided. Therefore, the time of the third cleaning treatment is not limited, and the time of the third cleaning treatment can be increased as needed, so that the silicon oxide on the surface of the metal semiconductor compound layer 107 can be removed cleanly.

[0117] In some embodiments, Fig.15 as well as Fig.16 As shown, the forming of the contact structure 106 further includes:

[0118] forming a metal nitride layer 108 covering the sidewall of the protection layer 105 and the metal semiconductor compound layer 107;

[0119] After the metal nitride layer 108 is formed, the through hole 104 is filled with a conductive material layer 109 .

[0120] In some specific examples, the material of the metal nitride layer 108 includes but is not limited to titanium nitride, tungsten nitride, tantalum nitride, etc. The material of the conductive material layer 109 includes but is not limited to tungsten, aluminum, copper, titanium, cobalt, molybdenum, etc.

[0121] In some specific examples, the metal nitride layer 108 and the conductive material layer 109 also cover the surface of the dielectric layer 102 . In subsequent processes, the metal nitride layer 108 and the conductive material layer 109 on the surface of the dielectric layer 102 can be removed, while the metal nitride layer 108 and the conductive material layer 109 in the through hole 104 are retained.

[0122] In some specific examples, the metal nitride layer 108 and the conductive material layer 109 may be formed by a deposition process.

[0123] In the several embodiments provided in the present disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-targeted manner. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the components shown or discussed are coupled or directly coupled to each other.

[0124] The features disclosed in several method or device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0125] The specific embodiments of the present disclosure are disclosed, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a semiconductor layer and a dielectric layer located on the semiconductor layer; The semiconductor layer includes an array region and a peripheral region arranged in parallel along a first direction; A conductive structure is formed in the dielectric layer directly above the peripheral region; the first direction is perpendicular to the thickness direction of the semiconductor layer; Forming through holes penetrating the dielectric layer and extending to the semiconductor layer on two opposite sides of the conductive structure along the first direction; forming a protective layer on the sidewalls and bottom wall of the through hole; removing the protective layer on the bottom wall of the through hole to expose the semiconductor layer; The through hole is cleaned by using a cleaning agent; the cleaning agent includes ammonia water, ultrapure water, and hydrofluoric acid.

2. The forming method according to claim 1, characterized in that: The step of cleaning the through hole with a cleaning agent comprises: The semiconductor layer exposed in the through hole is cleaned once by using a first cleaning agent; the first cleaning agent includes ammonia water, ultrapure water, and hydrofluoric acid.

3. The forming method according to claim 2, characterized in that: The volume ratio of ammonia water to ultrapure water in the first cleaning agent is in the range of 100:1-400:

1.

4. The forming method according to claim 2, characterized in that: The time range of the cleaning process is 10s-30s.

5. The forming method according to claim 1, characterized in that: The material of the protection layer includes silicon nitride, and the material of the dielectric layer includes one or more of silicon oxide and silicon oxynitride.

6. The forming method according to claim 1, characterized in that: The step of cleaning the through hole with a cleaning agent comprises: Using a second cleaning agent to perform a first cleaning process on the semiconductor layer exposed in the through hole; the second cleaning agent includes hydrofluoric acid; The semiconductor layer exposed in the through hole is cleaned for the second time using a third cleaning agent; the third cleaning agent includes hydrofluoric acid, ammonia water, and ultrapure water.

7. The forming method according to claim 1, characterized in that: The method further comprises: After the through hole is cleaned by a cleaning agent, a contact structure is formed in the through hole.

8. The forming method according to claim 7, characterized in that: The forming of the contact structure comprises: forming a metal layer at the bottom of the through hole; The metal layer and the semiconductor layer are subjected to heat treatment so that the metal layer and the semiconductor layer react to generate a metal-semiconductor compound layer.

9. The forming method according to claim 8, characterized in that: The method further comprises: After forming the metal semiconductor compound layer, the through hole is cleaned for a third time using a fourth cleaning agent; the fourth cleaning agent includes hydrofluoric acid, and the time range of the third cleaning treatment is 20s-50s.

10. The forming method according to claim 8, characterized in that: The forming of the contact structure further comprises: forming a metal nitride layer covering the sidewall of the protective layer and the metal semiconductor compound layer; After the metal nitride layer is formed, a conductive material layer is filled in the through hole.

Images