Interposer and manufacturing method thereof

Abstract

The invention discloses an interposer and a manufacturing method thereof, and the interposer comprises the components of a substrate which is provided with an inductor forming region; the plurality of grooves are formed in the inductor forming area of the substrate; a buffer layer which pads the inner surfaces of the plurality of trenches and forms air gaps in the plurality of trenches; and an inductance coil pattern embedded in the buffer layer within the inductance formation region.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an improved interposer and a manufacturing method thereof. Background Art

[0002] As electronic devices become increasingly miniaturized, there is a need to integrate high-performance capacitors and inductors into semiconductor devices. Many inductors formed on semiconductor substrates typically have a spiral shape.

[0003] On-chip inductor implementation faces many challenges in integrated circuit applications, such as meeting the requirements of high quality factor (Qfactor), small area consumption, limited parasitic coupling, and easy layout and manufacturing.

[0004] In order to improve the quality factor, an additional metal layer of the chip or die interconnect structure is usually used in the flip chip packaging manufacturing process. However, this additional metal layer increases the chip area and manufacturing cost, and has a negative impact on manufacturing yield. Summary of the invention

[0005] The main purpose of the present invention is to provide an improved interposer and a method for manufacturing the same to solve the deficiencies or shortcomings of the prior art.

[0006] On the one hand, the present invention provides an intermediate layer, comprising: a substrate having an inductor forming region thereon; a plurality of grooves arranged in the inductor forming region of the substrate; a buffer layer lining the inner surfaces of the plurality of grooves and forming air gaps in the plurality of grooves; and an inductor coil pattern embedded in the buffer layer in the inductor forming region.

[0007] According to an embodiment of the present invention, the plurality of trenches in the inductor forming region and the buffer layer in the plurality of trenches are surrounded by a fluorosilicate glass layer in the substrate.

[0008] According to an embodiment of the present invention, the buffer layer includes an organic silicate glass layer.

[0009] According to an embodiment of the present invention, the inductor coil pattern includes a titanium nitride layer and a copper layer stacked on the titanium nitride layer.

[0010] According to an embodiment of the present invention, the intermediate layer further includes: a dielectric covering layer covering the inductor coil pattern and the buffer layer in the inductor forming area.

[0011] According to an embodiment of the present invention, the dielectric cover layer includes a silicon nitride layer or a nitrogen-doped silicon carbide layer.

[0012] According to an embodiment of the present invention, the interposer further includes: an etch stop layer disposed on the dielectric cover layer; and an insulating layer disposed on the etch stop layer.

[0013] According to an embodiment of the present invention, the etching stop layer includes a silicon nitride layer.

[0014] According to an embodiment of the present invention, the interposer further includes: a cavity located in the insulating layer within the inductor forming region.

[0015] According to an embodiment of the present invention, the inductor coil pattern includes a multi-layer metal structure.

[0016] Another aspect of the present invention provides a method for forming an intermediate layer, comprising: providing a substrate having an inductor forming region thereon; forming a plurality of grooves in the inductor forming region of the substrate; forming a buffer layer lining the inner surfaces of the plurality of grooves and forming air gaps in the plurality of grooves; and forming an inductor coil pattern embedded in the buffer layer in the inductor forming region.

[0017] According to an embodiment of the present invention, the plurality of trenches in the inductor forming region and the buffer layer in the plurality of trenches are surrounded by a fluorosilicate glass layer in the substrate.

[0018] According to an embodiment of the present invention, the buffer layer includes an organic silicate glass layer.

[0019] According to an embodiment of the present invention, the inductor coil pattern includes a titanium nitride layer and a copper layer stacked on the titanium nitride layer.

[0020] According to an embodiment of the present invention, the method further includes: forming a dielectric cover layer covering the inductor coil pattern and the buffer layer in the inductor forming region.

[0021] According to an embodiment of the present invention, the dielectric cover layer includes a silicon nitride layer or a nitrogen-doped silicon carbide layer.

[0022] According to an embodiment of the present invention, the method further includes: forming an etch stop layer on the dielectric cap layer; and forming an insulating layer on the etch stop layer.

[0023] According to an embodiment of the present invention, the etching stop layer includes a silicon nitride layer.

[0024] According to an embodiment of the present invention, the method further includes: forming a cavity in the insulating layer within the inductor forming region.

[0025] According to an embodiment of the present invention, the inductor coil pattern includes a multi-layer metal structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figures 1 to 8 A schematic diagram of a method for forming an intermediate layer according to an embodiment of the present invention;

[0027] Fig. 9 and Fig.10 It is a schematic diagram of the three-dimensional radio frequency multi-chip structure of the present invention.

[0028] Main component symbols

[0029] 1a, 1b 3D RF multi-chip structure

[0030] 10 Intermediary Layer

[0031] 100 Substrate

[0032] 101, 103 groove

[0033] 102 Fluorine doped region

[0034] 106 Through Silicon Via

[0035] 110 Oxide layer

[0036] 112 Fluorosilicate glass layer

[0037] 120 Buffer layer

[0038] 121 Capacitor groove pattern

[0039] 122 Inductor groove pattern

[0040] 123 pad groove pattern

[0041] 124 pad groove pattern

[0042] 200 Metal-Insulator-Metal (MIM) Capacitor Stack Layers

[0043] 201 bottom electrode layer

[0044] 202 capacitor dielectric layer

[0045] 203 Top electrode layer

[0046] 210 Copper layer

[0047] 220 Dielectric Covering

[0048] 301a, 301b, 303, 304 contact structures

[0049] 310 Etch stop layer

[0050] 320 Insulation layer

[0051] 320c Cavity

[0052] 50 The first radio frequency chip

[0053] 501 Micro Bump

[0054] 60 Second RF chip

[0055] 601 Micro Bump

[0056] AG Air Gap

[0057] CA MIM capacitor structure

[0058] CL contact hole

[0059] CR capacitor formation area

[0060] IP Inductor Coil Pattern

[0061] IR inductor formation area

[0062] PA pad structure

[0063] PP pad structure

[0064] PR Through Silicon Via Input and Output Area

[0065] h1, h2 depth

[0066] w1, w2 width DETAILED DESCRIPTION

[0067] In the following, the details will be described with reference to the accompanying drawings, which also constitute part of the detailed description of the specification and are illustrated in a specific way that the embodiment can be implemented. The following embodiments have been described in sufficient detail to enable a person skilled in the art to implement them.

[0068] Of course, other embodiments may be adopted, or any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the following detailed description should not be considered as limiting, but rather, the embodiments included therein will be defined by the appended claims.

[0069] See also Figures 1 to 8 , which is a schematic diagram of a method for forming an intermediate layer according to an embodiment of the present invention. Figure 1 As shown, a substrate 100 is first provided, for example, a semiconductor substrate such as a silicon substrate. According to an embodiment of the present invention, the substrate 100 includes a capacitor forming region CR, an inductor forming region IR, and a through silicon via input / output (TSV IO) region PR. According to an embodiment of the present invention, an ion implantation process is first performed to implant fluorine ions into the substrate 100 in the inductor forming region IR to form a fluorine doped region 102.

[0070] like Figure 2 As shown, a photolithography process and an etching process are performed to form a plurality of trenches 101 and a plurality of trenches 103 in the substrate 100 in the capacitor forming region CR and the inductor forming region IR, respectively. According to an embodiment of the present invention, the plurality of trenches 101 have the same width w1, and the plurality of trenches 103 have the same width w2. According to an embodiment of the present invention, the width w1 of the trench 101 is greater than the width w2 of the trench 103. According to an embodiment of the present invention, the plurality of trenches 101 have the same depth h1, and the plurality of trenches 103 have the same depth h2. According to an embodiment of the present invention, the depth h1 of the trench 101 is greater than the depth h2 of the trench 103. According to an embodiment of the present invention, all of the trenches 103 are located in the fluorine-doped region 102.

[0071] like Figure 3 As shown, an oxidation process is performed to form an oxide layer 110 on the surface of the substrate 100, and at the same time, the fluorine-doped region 102 is transformed into a fluorosilicate glass (FSG) layer 112 with a low dielectric constant. At this time, the plurality of grooves 103 are located in the fluorosilicate glass layer 112. According to an embodiment of the present invention, the oxide layer 110 may be a silicon oxide layer, which is conformally formed on the surface of the substrate 100 and the inner surfaces of the plurality of grooves 101. According to an embodiment of the present invention, the oxide layer 110 is connected to the fluorosilicate glass layer 112.

[0072] like Figure 4 As shown, a deposition process is then performed to form a buffer layer 120 on the oxide layer 110. According to an embodiment of the present invention, the buffer layer 120 may include an organo-silicate glass (OSG) layer. According to an embodiment of the present invention, the buffer layer 120 lines the inner surfaces of the plurality of grooves 101 and 103, and the thickness of the buffer layer 120 is sufficient to form an air gap AG in the groove 103. Since the width w1 of the groove 101 is greater than the width w2 of the groove 103, the buffer layer 120 does not form an air gap in the groove 101. According to an embodiment of the present invention, the groove 103 in the inductor formation region IR and the buffer layer 120 in the groove 103 are surrounded by the fluorosilicate glass layer 112 in the substrate 100.

[0073] like Figure 5 As shown, a photolithography process and an etching process are then performed to form a capacitor groove pattern 121 in the capacitor formation region CR, an inductor groove pattern 122 and a pad groove pattern 123 in the inductor formation region IR, and a pad groove pattern 124 in the through silicon via input / output region PR. At this time, the air gap AG in the trench 103 in the inductor formation region IR is still sealed by the buffer layer 120.

[0074] like Figure 6 As shown, then, a metal-insulator-metal (MIM) capacitor stack layer 200 is fully deposited on the substrate 100. According to an embodiment of the present invention, the MIM capacitor stack layer 200 may include a bottom electrode layer 201, a capacitor dielectric layer 202 and a top electrode layer 203. According to an embodiment of the present invention, for example, the bottom electrode layer 201 may include titanium nitride (TiN), but is not limited thereto. According to an embodiment of the present invention, for example, the top electrode layer 201 may include titanium nitride (TiN) or tantalum nitride (TaN), but is not limited thereto. According to an embodiment of the present invention, for example, the capacitor dielectric layer 202 may include hafnium oxide (HfO2), silicon nitride or silicon oxide, but is not limited thereto.

[0075] Then, a photolithography process and an etching process are performed to remove the MIM capacitor stack layer 200 in the inductor formation region IR and the through silicon via input / output region PR. According to an embodiment of the present invention, the bottom electrode layer 201 can be retained in the inductor groove pattern 122, the pad groove pattern 123, and the pad groove pattern 124. The bottom electrode layer 201 in the inductor groove pattern 122 and the pad groove pattern 123 is disconnected from the bottom electrode layer 201 in the capacitor formation region CR.

[0076] like Figure 7 As shown, a metallization process is then performed, such as a copper electroplating process and a chemical mechanical polishing (CMP) process, to fill the copper layer 210 into the groove 101, the inductor groove pattern 122, the pad groove pattern 123 and the pad groove pattern 124, so as to form a MIM capacitor structure CA in the capacitor forming region CR, form an inductor coil pattern IP and a pad structure PA in the inductor forming region IR, and form a pad structure PP in the through silicon via input and output region PR. According to an embodiment of the present invention, the inductor coil pattern IP includes a titanium nitride layer and a copper layer stacked on the titanium nitride layer. According to other embodiments of the present invention, the inductor coil pattern IP may include a multi-layer metal structure.

[0077] Then, a dielectric capping layer 220 is deposited all over to cover the buffer layer 120, the MIM capacitor structure CA, the inductor coil pattern IP, the pad structure PA and the pad structure PP. According to an embodiment of the present invention, the dielectric capping layer 220 may include a silicon nitride layer or a nitrogen-doped silicon carbide layer, but is not limited thereto.

[0078] like Figure 8As shown, a photolithography process and an etching process are then performed to form a contact hole CL in the capacitor formation region CR that is connected to the bottom electrode layer 201 in the MIM capacitor stack layer 200, exposing a portion of the bottom electrode layer 201. Subsequently, an etch stop layer 310 is conformally deposited on the dielectric cap layer 220 and in the contact hole CL. According to an embodiment of the present invention, for example, the etch stop layer 310 may include a silicon nitride layer. Next, an insulating layer 320, for example, a silicon oxide layer, is formed on the etch stop layer 320.

[0079] Then, a photolithography process, an etching process and a metallization process are performed to form contact structures 301a and 301b, a contact structure 303 and a contact structure 304 in the insulating layer 320, the etching stop layer 320 and the dielectric cover layer 220. According to an embodiment of the present invention, the contact structure 301a is formed in the contact hole CL and directly contacts the bottom electrode layer 201 of the MIM capacitor stack layer 200. According to an embodiment of the present invention, the contact structure 301b directly contacts the top electrode layer 203 of the MIM capacitor stack layer 200. According to an embodiment of the present invention, the contact structure 303 and the contact structure 304 directly contact the pad structure PA and the pad structure PP, respectively.

[0080] Next, a through silicon via 106 is formed in the substrate 100 to electrically connect the pad structure PP. Finally, the insulating layer 320 directly above the inductor coil pattern IP in the inductor forming region IR can be removed to form a cavity 320c to reduce the inductor substrate loss, thus completing the manufacture of the interposer 10 integrating the capacitor and the inductor.

[0081] Structurally, such as Figure 8 As shown, the interposer 10 of the present invention includes: a substrate 100 having an inductor forming region IR thereon; a plurality of grooves 103 disposed in the inductor forming region IR of the substrate 100; a buffer layer 120 lining the inner surfaces of the plurality of grooves 103 and forming air gaps AG in the plurality of grooves 103; and an inductor coil pattern IP embedded in the buffer layer 120 in the inductor forming region IR.

[0082] According to an embodiment of the present invention, the plurality of trenches 103 in the inductor forming region IR and the buffer layer 120 in the plurality of trenches 103 are surrounded by the fluorosilicate glass layer 112 in the substrate 100. According to an embodiment of the present invention, the buffer layer 120 includes an organic silicate glass layer.

[0083] According to an embodiment of the present invention, the inductor coil pattern IP may include a titanium nitride layer and a copper layer stacked on the titanium nitride layer.

[0084] According to an embodiment of the present invention, the interposer 10 further includes a dielectric cover layer 220 covering the inductor coil pattern IP and the buffer layer 120 in the inductor forming region IR. According to an embodiment of the present invention, the dielectric cover layer 220 may include a silicon nitride layer or a nitrogen-doped silicon carbide layer.

[0085] According to an embodiment of the present invention, the interposer 10 further includes: an etch stop layer 310 disposed on the dielectric cap layer 220; and an insulating layer 320 disposed on the etch stop layer 310. According to an embodiment of the present invention, the etch stop layer 310 may include a silicon nitride layer.

[0086] According to the embodiment of the present invention, the interposer 10 further includes: a cavity 320 c located in the insulating layer 310 within the inductor forming region IR.

[0087] According to an embodiment of the present invention, the inductor coil pattern IP may include a multi-layer metal structure.

[0088] See also Fig. 9 and Fig.10 , which illustrates the three-dimensional radio frequency multi-chip structure of the present invention.

[0089] like Fig. 9 As shown, the three-dimensional RF multi-chip structure 1a includes a first RF chip 50, which is disposed on the interposer 10 and is electrically connected to the contact structures 301a and 301b and the contact structure 303 through the micro-bumps 501. The three-dimensional RF multi-chip structure 1a also includes a second RF chip 60, which is disposed on the interposer 10 and is electrically connected to the contact structures 303 and 304 through the micro-bumps 601. Neither the first RF chip 50 nor the second RF chip 60 overlaps the cavity 320c.

[0090] like Fig.10 As shown, the three-dimensional RF multi-chip structure 1b includes a first RF chip 50, which is disposed on the interposer 10 and electrically connected to the contact structure 301b through the micro-bump 501. The three-dimensional RF multi-chip structure 1b also includes a second RF chip 60, which is disposed on the interposer 10 and electrically connected to the contact structure 303a, the contact structure 303, and the contact structure 304 through the micro-bump 601. The second RF chip 60 spans the cavity 320c and overlaps with the cavity 320c.

[0091] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. An intermediary layer, comprising: a substrate having an inductor forming region thereon; A plurality of grooves are provided in the inductor forming region of the substrate; a buffer layer lining inner surfaces of the plurality of grooves and forming air gaps within the plurality of grooves; as well as An inductor coil pattern is embedded in the buffer layer in the inductor forming region.

2. The interposer according to claim 1, characterized in that: The plurality of trenches in the inductor forming region and the buffer layer in the plurality of trenches are surrounded by a fluorosilicate glass layer in the substrate.

3. The interposer according to claim 2, characterized in that: The buffer layer includes an organosilicate glass layer.

4. The interposer according to claim 1, characterized in that: The inductor coil pattern includes a titanium nitride layer and a copper layer stacked on the titanium nitride layer.

5. The interposer according to claim 1, characterized in that: Also includes: A dielectric cover layer covers the inductor coil pattern and the buffer layer in the inductor forming area.

6. The interposer according to claim 5, characterized in that: The dielectric cap layer includes a silicon nitride layer or a nitrogen-doped silicon carbide layer.

7. The interposer according to claim 5, characterized in that: Also includes: an etch stop layer disposed on the dielectric cap layer; as well as The insulating layer is disposed on the etching stop layer.

8. The interposer according to claim 7, characterized in that: The etch stop layer includes a silicon nitride layer.

9. The interposer according to claim 7, characterized in that: Also includes: A cavity is located in the insulating layer within the inductor forming region.

10. The interposer according to claim 1, characterized in that: The inductor coil pattern includes a multi-layer metal structure.

11. A method for forming an interposer, comprising: providing a substrate having an inductor forming region thereon; forming a plurality of trenches in the inductor formation region of the substrate; forming a buffer layer lining inner surfaces of the plurality of grooves and forming air gaps within the plurality of grooves; as well as An inductor coil pattern embedded in the buffer layer in the inductor forming region is formed.

12. The method according to claim 11, characterized in that The plurality of trenches in the inductor formation region and the buffer layer in the plurality of trenches are surrounded by a fluorosilicate glass layer in the substrate.

13. The method according to claim 12, characterized in that The buffer layer includes an organosilicate glass layer.

14. The method according to claim 11, characterized in that The inductor coil pattern includes a titanium nitride layer and a copper layer stacked on the titanium nitride layer.

15. The method according to claim 11, characterized in that Also includes: A dielectric cover layer covering the inductor coil pattern and the buffer layer is formed in the inductor forming region.

16. The method according to claim 15, characterized in that The dielectric cap layer includes a silicon nitride layer or a nitrogen-doped silicon carbide layer.

17. The method according to claim 15, characterized in that Also includes: forming an etch stop layer on the dielectric cap layer; as well as An insulating layer is formed on the etch stop layer.

18. The method according to claim 17, characterized in that The etch stop layer includes a silicon nitride layer.

19. The method according to claim 17, characterized in that Also includes: A cavity is formed in the insulating layer within the inductor forming region.

20. The method according to claim 11, characterized in that The inductor coil pattern includes a multi-layer metal structure.

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