Power supply circuit for supplying power to load

Abstract

The invention discloses a power supply circuit which is characterized by comprising a power supply loop and a voltage slew rate boosting circuit. The power supply loop is connected with a load through a power supply node and provides a power supply current to the load so as to supply energy required by operation of the load. When the power supply loop supplies power to the load, an output voltage is generated on the power supply node. The voltage slew rate boosting circuit is used for detecting the voltage change of the output voltage on the power supply node. When the voltage slew rate boosting circuit detects that the voltage level of the output voltage drops downwards, the power supply loop is controlled to output more power supply current, so that the voltage level of the output voltage can be quickly recovered to the original preset voltage level or is close to the original preset voltage level, and the slew rate of the voltage is improved.

Description

[0001] This application is a divisional application of the invention patent application with application number 202410912554.2. The filing date of the original application is July 9, 2024. Technical Field

[0002] The present invention belongs to the technical field of power supply circuits, and in particular to a power supply circuit capable of improving the stability of power supply to a load. Background Art

[0003] In a driver integrated circuit or a single-chip integrated circuit, a power supply circuit is usually built in to reduce or divide the input power supply (VDD) into one or more power supplies (N>=1) for use by the load. These divided or reduced power supplies may be fine when used for static loads; however, when the load suddenly requires a larger power supply energy, a large current will be drawn instantly, causing the voltage level of the power supply to drop.

[0004] In order to detect whether the voltage level of the power supply drops, a feedback circuit for detecting the voltage level of the power supply can be set in the power supply circuit in the past. When the power supply circuit detects that the voltage level of the power supply drops through the feedback circuit, the voltage level of the power supply will be adjusted to restore the voltage level of the power supply to the original preset voltage level. However, in the circuit design of the previous power supply circuit, after the voltage level of the power supply drops, it often takes a long time to restore to the preset voltage level, which will cause instability in the load operation.

[0005] In view of this, how to design a power circuit that can quickly restore the voltage level of the power supply to a preset voltage level after the load instantly draws a large current will be a breakthrough issue in the power supply field. Summary of the invention

[0006] The present invention proposes an innovative power supply circuit to solve the deficiencies in the prior art, the purpose of which is to increase the voltage slew rate so that the voltage level of the power supply that drops due to the load instantly drawing a large current can be quickly pulled back to a preset voltage level, thereby reducing the time the load operates with insufficient power supply voltage and improving the stability of the load power supply.

[0007] In order to achieve the above object, the present invention adopts the following technical solutions:

[0008] To achieve the above-mentioned purpose, the present invention provides a power supply circuit, characterized in that it includes: a power supply circuit, connected to a load through a power supply node, providing a power supply current to the load, and generating a first output voltage on the power supply node, the power supply circuit includes: a first amplifier, connected to the power supply node and a first control point, receiving a first reference voltage and a first output voltage, and generating a first control voltage on the first control point; and a first output stage, connected to the first control point and the power supply node, controlling the magnitude of the power supply current output by the first output stage with the first control voltage; and a voltage slew rate enhancement circuit, including: a second amplifier, connected to the power supply node and a second control point, receiving the first reference voltage and the first output voltage, and generating a second control voltage on the second control point; a second output stage, connected to the second control point and the power supply node, controlling the conduction or shutdown of the second output stage with the second control voltage, wherein the first output The length and width of the transistor of the first output stage are much larger than the length and width of the transistor of the second output stage; a hysteresis circuit connected to the second control point to receive the second control voltage and output a driving voltage, wherein the hysteresis circuit has a hysteresis function, applies a hysteresis reaction to the second control voltage to delay the transition of the driving voltage; and a driver connected to the hysteresis circuit and the first control point, receives the driving voltage, and when the driver is driven to turn on by the driving voltage, the voltage level of the first control voltage on the first control point is adjusted; wherein the first amplifier and the second amplifier preset the first output voltage to be equal to N times the first reference voltage, N being a multiple of 1 or greater; when the first output voltage is less than N times the first reference voltage, the voltage slew rate enhancement circuit starts the control loop, the second control voltage controls the second output stage to turn on and drives the driver to turn on through the hysteresis circuit, so as to adjust the first control voltage on the first control point through the turned-on driver.

[0009] Preferably, the hysteresis circuit is implemented with an inverter and includes a PMOS transistor and an NMOS transistor, wherein the PMOS transistor is a long-channel PMOS transistor. When the inverter receives a second control voltage whose voltage level drops downward, the PMOS transistor delays the response to the second control voltage whose voltage level drops downward, thereby delaying the conduction time of the PMOS transistor and delaying the transition of the driving voltage.

[0010] Preferably, the hysteresis circuit is implemented with an inverter and includes a PMOS transistor and an NMOS transistor, wherein the NMOS transistor is a long-channel NMOS transistor. When the inverter receives a second control voltage whose voltage level is rising, the NMOS transistor delays the response to the second control voltage whose voltage level is rising, thereby delaying the conduction time of the NMOS transistor and delaying the transition of the driving voltage.

[0011] Preferably, the hysteresis circuit is implemented with a Schmitt trigger, which has a first threshold voltage and a second threshold voltage, wherein the first threshold voltage is greater than the second threshold voltage. When the Schmitt trigger receives a second control voltage whose voltage level is rising, the voltage level of the second control voltage must rise above the first threshold voltage before the driving voltage changes state; or, when the Schmitt trigger receives a second control voltage whose voltage level is falling, the voltage level of the second control voltage must drop below the second threshold voltage before the driving voltage changes state.

[0012] Preferably, the hysteresis circuit is implemented with a voltage comparator, which receives a reference voltage and a second control voltage. The reference voltage serves as a threshold for a driving voltage transition. When the voltage comparator receives a second control voltage with an increasing voltage level, the voltage level of the second control voltage must rise above the reference voltage before the driving voltage transitions. Alternatively, when the voltage comparator receives a second control voltage with a decreasing voltage level, the voltage level of the second control voltage must drop below the reference voltage before the driving voltage transitions.

[0013] In addition, the present invention provides a power supply circuit, characterized in that it includes: a power supply circuit, connected to a load through a power supply node, providing a power supply current to the load, and generating a first output voltage on the power supply node, the power supply circuit includes: a first amplifier, connected to the power supply node and a first control point, receiving a first reference voltage and a first output voltage, and generating a first control voltage on the first control point; and a first output stage, connected to the first control point and the power supply node, controlling the magnitude of the output power supply current of the first output stage with the first control voltage; and a voltage slew rate enhancement circuit, connected to the power supply node of the power supply circuit through a detection node to detect the voltage change of the first output voltage, and generating a second output voltage on the detection node, including: a second amplifier, connected to the detection node and a second control point, receiving a second reference voltage and a second output voltage, and generating a second control voltage on the second control point; a second output stage, connected to the second control point and the detection node, controlling the second output stage with the second control voltage The first output stage is turned on or off, wherein the length and width of the transistor of the first output stage is much larger than the length and width of the transistor of the second output stage; a hysteresis circuit is connected to the second control point to receive the second control voltage and output a driving voltage, wherein the hysteresis circuit has a hysteresis function, which applies a hysteresis reaction to the second control voltage to delay the transition of the driving voltage; and a driver is connected to the hysteresis circuit and the first control point, receives the driving voltage, and when the driver is driven to turn on by the driving voltage, the voltage level of the first control voltage on the first control point is adjusted; wherein the second amplifier presets the first output voltage on the power supply node to be greater than the second output voltage on the detection node; when the second amplifier determines that the first output voltage is less than the second output voltage through the voltage change of the second output voltage on the detection node, the voltage slew rate enhancement circuit starts the control loop, the second control voltage controls the second output stage to turn on and drives the driver to turn on through the hysteresis circuit, so as to adjust the first control voltage on the first control point through the turned-on driver.

[0014] Due to the adoption of the above scheme, the beneficial effect of the present invention is that the power supply circuit is provided with a voltage slew rate enhancement circuit. When the load transiently draws too much power supply current, the voltage slew rate enhancement circuit can reduce the amplitude of the output voltage drop on the power supply node, and can accelerate the output voltage on the power supply node to be pulled up and restored to the originally preset voltage level or close to the originally preset voltage level, so as to improve the power supply stability of the power supply circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 FIG. 4 is a block diagram of a power supply circuit according to an embodiment of the present invention.

[0016] Figure 2 FIG. 4 is a circuit diagram of an embodiment of a first amplifier and a first output stage in a power supply circuit of the present invention.

[0017] Figure 3FIG. 4 is a circuit diagram of an embodiment of a second amplifier and a second output stage in a power supply circuit of the present invention.

[0018] Figure 4 It is a circuit diagram of an embodiment of a hysteresis circuit and a driver in a power circuit of the present invention.

[0019] Figure 5 The circuit diagram of another embodiment of the hysteresis circuit and the driver in the power circuit of the present invention.

[0020] Figure 6 for Figure 5 Working curve diagram of the hysteresis circuit.

[0021] Figure 7 The circuit diagram of another embodiment of the hysteresis circuit and the driver in the power circuit of the present invention.

[0022] Figure 8 for Figure 7 Working curve diagram of the hysteresis circuit.

[0023] Fig. 9 For the present invention Figure 1 The curve diagram of the power supply circuit operation.

[0024] Fig.10 for Fig. 9 Enlarged graph of period A.

[0025] Fig.11 FIG. 4 is a block diagram of another embodiment of the power supply circuit of the present invention.

[0026] Fig.12 The circuit diagram of another embodiment of the first amplifier and the first output stage in the power supply circuit of the present invention.

[0027] Fig.13 FIG. 4 is a circuit diagram of another embodiment of the second amplifier and the second output stage in the power supply circuit of the present invention.

[0028] Fig.14 The circuit diagram of another embodiment of the hysteresis circuit and the driver in the power circuit of the present invention.

[0029] Fig.15 FIG. 4 is a block diagram of another embodiment of the power supply circuit of the present invention.

[0030] Fig.16 The circuit diagram of another embodiment of the first amplifier and the first output stage in the power supply circuit of the present invention.

[0031] Fig.17 FIG. 4 is a circuit diagram of another embodiment of the second amplifier and the second output stage in the power supply circuit of the present invention.

[0032] Description of Reference Numerals

[0033] 100, 101, 102: Power supply circuit

[0034] 10, 10A, 10B: Power supply circuit

[0035] 11, 11A, 11B: First amplifier

[0036] 12: First control point

[0037] 13, 13A, 13B: First output stage

[0038] 14: Power supply node

[0039] 20, 20A, 20B: Voltage slew rate enhancement circuit

[0040] 21, 21A, 21B: Second amplifier

[0041] 22: Second control point

[0042] 23, 23A, 23B: Second output stage

[0043] 24: Detection Node

[0044] 25, 25A: Hysteresis circuit

[0045] 251, 251A: PMOS transistor

[0046] 252, 252A: NMOS transistor

[0047] 253: Schmitt trigger

[0048] 254: Voltage Comparator

[0049] 27, 27A: Driver

[0050] 30: Load

[0051] 901, 911, 912, 921, 922, 931: Curve

[0052] 941: Lead DETAILED DESCRIPTION

[0053] In order to make the objects, features and advantages of the present invention more obvious and easy to understand, the present application is further described in detail below in conjunction with drawings and specific implementation methods.

[0054] First, see Figure 1 , Figure 2 , Figure 3 and Figure 4, which are respectively a block diagram of an embodiment of a power supply circuit of the present invention, a circuit diagram of an embodiment of a first amplifier and a first output stage in the power supply circuit of the present invention, a circuit diagram of an embodiment of a second amplifier and a second output stage in the power supply circuit of the present invention, and a circuit diagram of an embodiment of a hysteresis circuit and a driver in the power supply circuit of the present invention. Figure 1 As shown, the power circuit 100 includes a power supply circuit 10 and a voltage slew rate enhancement circuit 20. The power supply circuit 10 is connected to a load 30 through a power supply node 14 and provides a power supply current I S The power supply circuit 10 supplies the load 30 with the energy required for the operation of the load 30. The load 30 may also be a resistive load or a capacitive load. Furthermore, when the power supply circuit 10 supplies power to the load 30, a first output voltage (V O1 ).

[0055] See also Figure 1 and Figure 2 The power supply circuit 10 includes a first amplifier 11 and a first output stage 13. The first amplifier 11 is a single-stage or multi-stage transconductance amplifier (OTA) or a gain stage operational amplifier. An input terminal (such as a non-inverting input terminal) of the first amplifier 11 receives a first reference voltage (V REF1 ), and the other input terminal (such as the inverting input terminal) is connected to the power supply node 14 and receives the first output voltage (V O1 ), and the output terminal is connected to a first control point 12 and a first control voltage (V CT1 In the present invention, the first amplifier 11 presets a first output voltage (V O1 ) is equal to N times the first reference voltage (V REF1 ), such as V O1 =N×V REF1 , N can also be 1 or a multiple of 1 or more. The first output stage 13 is the main output power supply component in the power supply circuit 100. Therefore, a transistor with a larger length and width is selected for implementation, such as a PMOS transistor with a larger length and width. The first output stage 13 is implemented by a transistor with a larger length and width, which has a smaller impedance, so as to provide a large power supply current I S To the load 30. A first terminal (such as a drain terminal) of the first output stage 13 is connected to the power supply node 14, and a second terminal (such as a source terminal) is connected to a working voltage (V SS ) and a control end (such as a gate end) connected to the first control point 12.

[0056] When the load 30 is static, the load 30 stably draws a certain amount of supply current IS Operation, the first output voltage (V O1 ) is maintained at a preset voltage level, such as V O1 =N×V REF When the load 30 suddenly enters a transient state, if the load 30 suddenly requires a larger power source energy to cope with the operation, a larger power supply current I will be drawn from the power supply circuit 10 instantly. S , the first output voltage (V O1 ) will drop below the preset voltage level, such as V O1 <N×V REF . In the past, the first output voltage (V O1 ) drops down, it often takes a long time to recover to the preset voltage level. O1 ) is too slow to recover, the load 30 will be operated for a relatively long time under the supply voltage, which will not only affect the normal operation of the load 30 but also increase the probability of failure of the load 30. O1 ) is accelerated to recover to the originally preset voltage level or a voltage level close to the originally preset voltage level. The present invention adds a voltage slew rate enhancement circuit 20 to the power circuit 100.

[0057] See also Figure 1 The voltage slew rate boosting circuit 20 is connected to the power supply node 14 to detect the first output voltage (V O1 ) voltage change. When the voltage slew rate enhancement circuit 20 detects the first output voltage (V O1 ) drops, the power supply circuit 10 is controlled to output more power supply current I S , so that the first output voltage (V O1 ) can be accelerated to recover to the originally preset voltage level or close to the originally preset voltage level to improve the voltage slew rate.

[0058] See also Figure 1 and Figure 3 The voltage slew rate enhancement circuit 20 includes a second amplifier 21 and a second output stage 23. The second amplifier 21 is a low-power electronic component, which can also be a single-stage or multi-stage transconductance operational amplifier (OTA) or a gain stage operational amplifier. An input terminal (such as a non-inverting input terminal) of the second amplifier 21 receives a first reference voltage (V REF1 ), and the other input terminal (such as the inverting input terminal) is connected to the power supply node 14 and receives the first output voltage (V O1), and the output terminal is connected to a second control point 22 and a second control voltage (V CT2 Similarly, the second amplifier 21 presets a first output voltage (V O1 ) is equal to N times the first reference voltage (V REF1 ), such as V O1 =N×V REF1 , N can also be 1 or a multiple of 1 or more. In the present invention, the second output stage 23 is not used to output power but to detect the first output voltage (V O1 ) voltage change, therefore, a transistor with smaller length and width dimensions is selected for implementation, for example, a PMOS transistor with smaller length and width dimensions. A first end (such as a drain end) of the second output stage 23 is connected to the power supply node 14, a second end (such as a source end) is connected to the operating voltage (Vss), and a control end (such as a gate end) is connected to the second control point 22. Therefore, the length and width dimensions of the transistor of the second output stage 23 are much smaller than the length and width dimensions of the transistor of the first output stage 13, and the second output stage 23 has a smaller parasitic capacitance, while the first output stage 13 has a larger parasitic capacitance. The size of the parasitic capacitance of the transistor will affect the response speed of the transistor, therefore, the response speed of the second output stage 23 will be faster than the response speed of the first output stage 13. Going back to the above, when the load 30 suddenly enters a transient state, it will instantly draw a larger supply current I from the power supply circuit 10. S , the first output voltage (V O1 ) will drop instantly below the preset voltage level, such as V O1 <N×V REF The first output voltage (V O1 ) drops down instantly, the second control voltage (V CT2 ) will also drop down instantaneously and quickly control the channel conduction of the second output stage 23 with smaller parasitic capacitance.

[0059] Further, see also Figure 1 , Figure 3 and Figure 4 The slew rate enhancement circuit 20 further includes a hysteresis circuit 25 and a driver 27. The input end of the hysteresis circuit 25 is connected to the second control point 22, and the output end is connected to the driver 27. The input end of the driver 27 is connected to the hysteresis circuit 25, and the output end is connected to the first control point 12. The hysteresis circuit 25 is a circuit with a hysteresis function. When the load 30 enters a transient state, the hysteresis circuit 25 receives the second control voltage (V CT2 ), and for the second control voltage (V CT2) is applied with hysteresis to output a driving voltage (Vd), and the driving voltage (Vd) is used to drive the driver 27 to turn on, so as to quickly pull down the first control voltage (V CT1 In one embodiment of the present invention, the hysteresis circuit 25 is an inverter, which includes a PMOS transistor 251 and an NMOS transistor 252. The source of the PMOS transistor 251 is connected to the working voltage (V SS ), the source of the NMOS transistor 252 is grounded, the gate of the PMOS transistor 251 and the gate of the NMOS transistor 252 are connected to the second control point 22 and serve as the input of the hysteresis circuit 25, and the drain of the PMOS transistor 251 and the drain of the NMOS transistor 252 are connected to serve as the output of the hysteresis circuit 25. In one embodiment of the present invention, the driver 27 is implemented by an NMOS transistor, whose drain (such as the output) is connected to the first control point 12, the gate (such as the input) is connected to the output of the hysteresis circuit 25, and the source is grounded. When the input of the hysteresis circuit 25 receives the second control voltage (V CT2 ), the PMOS transistor 251 will be turned on, and the hysteresis circuit 25 outputs a high-level driving voltage (Vd), which turns on the driver 27 to make the first control voltage (V TC1 ) is pulled to ground. The first control voltage (V CT1 ) pulls the channel that can control the first output stage 13 further open, so that the first output stage 13 outputs more power supply current (I S ) to the power supply node 14, and then the first output voltage (V O1 ) can be accelerated to recover to the originally preset voltage level or close to the originally preset voltage level.

[0060] In addition, in order to prevent the voltage slew rate boosting circuit 20 from increasing the supply voltage (such as the first output voltage (V O1 )) is too sensitive to small changes, the voltage slew rate boosting circuit 20 will use a hysteresis circuit 25 to delay the reaction time. In this embodiment, the hysteresis circuit 25 implemented as an inverter will use a long channel type (Long Channel) PMOS transistor 251 to add a hysteresis function. Since the long channel type transistor has the characteristics of large impedance and slow channel conduction speed, when the input end of the hysteresis circuit 25 receives the second control voltage (V CT2 ), the long-channel PMOS transistor 251 delays the voltage level of the second control voltage (V CT2 ) response, and continues to receive the second control voltage (VCT2 ), the channel can be turned on, so that the inverter outputs a high-level driving voltage (Vd) to the driver 27 to turn on the driver 27.

[0061] In the above embodiment of the present invention, the voltage slew rate boosting circuit 20 implements the hysteresis circuit 25 with an inverter of a long channel type PMOS transistor 251; or, in another embodiment of the present invention, the voltage slew rate boosting circuit 20 can also use a Schmitt trigger to implement the hysteresis circuit 25. Figure 1 , Figure 3 , Figure 5 and Figure 6 The hysteresis circuit 25 includes a Schmitt trigger 253. The Schmitt trigger 253 is an inverting Schmitt trigger, and its input terminal is connected to the second control point 22 to receive the second control voltage (V CT2 ), and the output terminal is connected to the driver 27 to provide a driving voltage (Vd) to the driver 27. The Schmitt trigger 253 has two threshold voltages U1 and U2, U1>U2. In terms of the characteristics of the inverting Schmitt trigger, the second control voltage (V CT2 ) during the rising process, the voltage level of the driving voltage Vd will be greater than the threshold voltage U1, and the voltage level of the driving voltage Vd will be turned into a low level state (-U V ); On the contrary, the second control voltage (V CT2 ) decreases, the voltage level of the driving voltage Vd will be lower than the threshold voltage U2, and the voltage level of the driving voltage Vd will be changed to a high level state (+U V ). Therefore, when the second control voltage (V CT2 ) is decreasing, if the second control voltage (V CT2 ) is not lower than the threshold voltage U2, the Schmitt trigger 253 delays the transition of the driving voltage (Vd), and waits for the second control voltage (V CT2 ) is lower than the threshold voltage U2, the potential of the driving voltage (Vd) output by the Schmitt trigger 253 will change from a low level to a high level.

[0062] In the above embodiment of the present invention, the voltage slew rate boosting circuit 20 selects an inverter of a long channel type PMOS transistor 251 or selects a Schmitt trigger to implement the hysteresis circuit 25; or, in another embodiment of the present invention, the voltage slew rate boosting circuit 20 can also use a voltage comparator to implement the hysteresis circuit 25. Figure 1 , Figure 3 , Figure 7 and Figure 8 The hysteresis circuit 25 includes a voltage comparator 254. The voltage comparator 254 includes an inverting input terminal connected to the second control point 22 for receiving a second control voltage (VCT2 ), the non-inverting input terminal is connected to a reference voltage (V REF ), and the output terminal is connected to the driver 27 to provide a driving voltage (Vd) to the driver 27. ref ) is equal to 1 / 2 of the operating voltage (V CC ) and serves as the threshold value for the driving voltage (Vd) to switch state. CT2 ) is decreasing, if the second control voltage (V CT2 ) is not lower than the reference voltage (V ref ), the voltage comparator 254 delays the transition of the driving voltage (Vd) until the second control voltage (V CT2 ) is lower than the reference voltage (V ref ), the potential of the driving voltage (Vd) output by the voltage comparator 254 will change from a low level to a high level.

[0063] Therefore, a hysteresis circuit 25 is added to the voltage slew rate boosting circuit 20 to adjust the sensitivity of the voltage slew rate boosting circuit 20 to the supply voltage change of the power supply circuit 10 through the hysteresis function provided by the hysteresis circuit 25, so as to avoid affecting the stability of the power supply of the power supply circuit 10.

[0064] See also Fig. 9 and Fig.10 , respectively, of the present invention Figure 1 The power circuit operation curve and Fig. 9 A zoomed-in graph of the middle period A. See also Figure 1 , Fig. 9 and Fig.10 Curve 901 is a curve when the load 30 draws current, and curve 911 is a first output voltage (V O1 ) curve, curve 912 is the first output voltage (V O1 ) curve, curve 921 is the first control voltage (V CT1 ) curve, curve 922 is the second control voltage (V CT1 ) and curve 931 are the second control voltage (V CT2 ) graph.

[0065] When the power circuit 100 is operating, during period A, the load 30 enters a transient state, and the curve 901 suddenly rises, indicating that the load 30 draws a larger supply current I from the power supply circuit 10. SBefore the voltage slew rate boosting circuit 20 is added to the power supply circuit 100, in the period A, the first output voltage (V O1 ) drops rapidly, such as from 1.52V to 1.42V. After the power circuit 100 is added with the voltage slew rate enhancement circuit 20, in period A, the first output voltage (V O1 ) also drops rapidly, but the voltage drop is not large, for example, it only drops from 1.52V to 1.49V. In addition, in period A, the second control voltage (V CT2 ) is directly pulled down when the load 30 enters the transient state. Furthermore, as shown by the lead 941, the first control voltage (V CT1 ) is pulled down by the second control voltage (V CT2 ) will be controlled, and it will soon accelerate downward. Therefore, compared with curve 921 and curve 922, the first control voltage (V CT1 ) drops much faster. The first control voltage (V CT1 ) can expand the channel of the first output stage 13 in advance so that the first output stage 13 can output more power supply current (I S ) to the power supply node 14.

[0066] Here, the power circuit 100 of the present invention is provided with the voltage slew rate enhancement circuit 20. When the load 30 transiently draws too much power supply current, the voltage slew rate enhancement circuit 20 can not only reduce the output voltage (V O1 ) drops, and can accelerate the output voltage (V O1 ) is restored to an originally preset voltage level or a voltage level close to an originally preset voltage level so as to improve the power supply stability of the power supply circuit 100.

[0067] See also Fig.11 , Fig.12 , Fig.13 and Fig.14, which are respectively a block diagram of another embodiment of the power supply circuit of the present invention, a circuit diagram of another embodiment of the first amplifier and the first output stage in the power supply circuit of the present invention, a circuit diagram of another embodiment of the second amplifier and the second output stage in the power supply circuit of the present invention, and a circuit diagram of another embodiment of the hysteresis circuit and the driver in the power supply circuit of the present invention. The circuit structure of the power circuit 101 of the present embodiment is similar to the circuit structure of the power circuit 101 of the above embodiment, and the difference is that: the first output stage 13 of the above embodiment is implemented by a PMOS transistor with a larger length and width, while the first output stage 13A of the present embodiment is implemented by an NMOS transistor with a larger length and width; the second output stage 23 of the above embodiment is implemented by a PMOS transistor with a smaller length and width, while the second output stage 23A of the present embodiment is implemented by an NMOS transistor with a smaller length and width; when the hysteresis circuit 25 of the above embodiment is implemented as an inverter, a PMOS transistor 251 with a long channel type is used to add a hysteresis function, while when the hysteresis circuit 25 of the present embodiment is implemented as an inverter, a NMOS transistor 252A with a long channel type is used to add a hysteresis function; the driver 27 of the above embodiment is implemented by an NMOS transistor, while the driver 27A of the present embodiment is implemented by a PMOS transistor.

[0068] See also Fig.11 The power circuit 101 includes a power supply circuit 10A and a voltage slew rate enhancement circuit 20A. The power supply circuit 10A is connected to the load 30 through the power supply node 14 and provides a power supply current I S When the power supply circuit 10A supplies power to the load 30, a first output voltage (V O1 ). When the load 30 enters a transient state, a larger supply current I S , the first output voltage (V O1 ) will drop down instantly. At this time, the voltage slew rate enhancement circuit 20A will control the power supply circuit 10A to provide more power supply current I S , so that the first output voltage (V O1 ) can be accelerated to recover to the originally preset voltage level or close to the originally preset voltage level so as to improve the voltage slew rate.

[0069] See also Fig.11 and Fig.12 The power supply circuit 10A includes a first amplifier 11A and a first output stage 13A. An input terminal (such as a non-inverting input terminal) of the first amplifier 11A is connected to the power supply node 14 and receives a first output voltage (V O1 ), and the other input terminal (such as the inverting input terminal) receives a first reference voltage (VREF1 ), and the output terminal is connected to a first control point 12 and a first control voltage (V CT1 In the present invention, the first amplifier 11A presets a first output voltage (V O1 ) is equal to N times the first reference voltage (V REF1 ), such as V O1 =N×V REF1 , N can also be 1 or a multiple of 1 or more. The first output stage 13A is implemented by using an NMOS transistor with a larger length and width. The first output stage 13A is implemented by using a transistor with a larger length and width, which has a smaller impedance, so as to provide a large supply current I S To the load 30. A first terminal (eg, drain terminal) of the first output stage 13A is connected to a working voltage (V DD ), a second end (such as a source end) connected to the power supply node 14 and a control end (such as a gate end) connected to the first control point 12.

[0070] See also Fig.11 and Fig.13 The voltage slew rate enhancement circuit 20A includes a second amplifier 21A and a second output stage 23A. The second amplifier 21A is a low-power electronic component, which can also be a single-stage or multi-stage transconductance operational amplifier (OTA) or a gain stage operational amplifier. An input terminal (such as a non-inverting input terminal) of the second amplifier 21A is connected to the power supply node 14 and receives the first output voltage (V O1 ), and the other input terminal (such as the inverting input terminal) receives a first reference voltage (V REF1 ), and the output terminal is connected to a second control point 22 and a second control voltage (V CT2 Similarly, the second amplifier 21A presets a first output voltage (V O1 ) is equal to N times the first reference voltage (V REF1 ), such as V O1 =N×V REF1 The second output stage 23A is implemented by using an NMOS transistor with a relatively small length and width. A first terminal (such as a drain terminal) of the second output stage 23A is connected to the working voltage (V DD), a second end (such as a source end) connected to the power supply node 14 and a control end (such as a gate end) connected to the second control point 22. The length and width of the transistor of the second output stage 23A are much smaller than the length and width of the transistor of the first output stage 13A. Therefore, the second output stage 23A has a smaller parasitic capacitance, while the first output stage 13A has a larger parasitic capacitance. The response speed of the second output stage 23A will be faster than the response speed of the first output stage 13A. Back to the above, when the load 30 suddenly enters the transient state, it will instantly draw a larger supply current I S , the first output voltage (V O1 ) will drop instantly below the preset voltage level, such as V O1 <N×V REF The first output voltage (V O1 ) drops down instantly, the second control voltage (V CT2 ) will rise instantaneously and quickly control the channel expansion of the second output stage 23A with smaller parasitic capacitance.

[0071] Further, see also Fig.11 , Fig.13 and Fig.14 The slew rate enhancement circuit 20A further includes a hysteresis circuit 25A and a driver 27A. The input end of the hysteresis circuit 25A is connected to the second control point 22, and the output end is connected to the driver 27A. The input end of the driver 27A is connected to the hysteresis circuit 25A, and the output end is connected to the first control point 12. When the load 30 enters the transient state, the hysteresis circuit 25A receives the second control voltage (V CT2 ), and for the second control voltage (V CT2 ) is applied with hysteresis to output a driving voltage (Vd), and the driving voltage (Vd) is used to drive the driver 27A to turn on, so as to quickly increase the first control voltage (V CT1 In one embodiment of the present invention, the hysteresis circuit 25A is an inverter, which includes a PMOS transistor 251A and an NMOS transistor 252A. The source of the PMOS transistor 251A is connected to the working voltage (V SS), the source of the NMOS transistor 252A is grounded, the gate of the PMOS transistor 251A and the gate of the NMOS transistor 252A are connected to the second control point 22 and serve as the input of the hysteresis circuit 25A, and the drain of the PMOS transistor 251A and the drain of the NMOS transistor 252A are connected to serve as the output of the hysteresis circuit 25A. In one embodiment of the present invention, the driver 27A is implemented by an NMOS transistor, whose drain (such as the output) is connected to the first control point 12, the gate (such as the input) is connected to the output of the hysteresis circuit 25A, and the source is connected to the working voltage (V SS When the input terminal of the hysteresis circuit 25A receives the second control voltage (V CT2 ), the NMOS transistor 252A will be turned on, and the hysteresis circuit 25A outputs a low-level driving voltage (Vd). If the driving signal is connected to the ground, the driver 27A is turned on by the low-level driving voltage (Vd), so that the first control voltage (V TC1 ) is pulled to the power supply potential (V SS ). The first control voltage (V CT1 ) pulls the channel that can control the first output stage 13A further open, so that the first output stage 13A outputs more power supply current (I S ) to the power supply node 14, and then the first output voltage (V O1 ) can be accelerated to recover to the originally preset voltage level or close to the originally preset voltage level.

[0072] In addition, in order to prevent the voltage slew rate boosting circuit 20A from increasing the supply voltage (such as the first output voltage (V O1 )) is too sensitive to small changes in the voltage. The voltage slew rate boosting circuit 20A will use a hysteresis circuit 25A to delay the reaction time. In this embodiment, the hysteresis circuit 25A implemented as an inverter will use a long channel type NMOS transistor 252A to add a hysteresis function. Since the long channel type transistor has the characteristics of large impedance and slow channel conduction speed, when the input end of the hysteresis circuit 25A receives the second control voltage (V CT2 ), the long-channel NMOS transistor 252A delays the second control voltage (V CT2 ) response, and continues to receive the second control voltage (V CT2 ), the channel can be turned on.

[0073] The voltage slew rate boosting circuit 20A uses the inverter of the long channel NMOS transistor 252A to implement the hysteresis circuit 25A, which is only one embodiment. Alternatively, you can also refer to Figure 5or Figure 7 In the embodiment, the hysteresis circuit 25A is implemented by a Schmitt trigger or a voltage comparator.

[0074] Therefore, a hysteresis circuit 25A is added to the voltage slew rate boosting circuit 20A to adjust the sensitivity of the voltage slew rate boosting circuit 20A to the voltage change of the power supply voltage of the power supply circuit 10A through the hysteresis function provided by the hysteresis circuit 25A, so as to avoid affecting the stability of the power supply of the power supply circuit 10A.

[0075] See See Fig.15 , Fig.16 and Fig.17 , are respectively a block diagram of another embodiment of the power supply circuit of the present invention, a circuit diagram of another embodiment of the first amplifier and the first output stage in the power supply circuit of the present invention, and a circuit diagram of another embodiment of the second amplifier and the second output stage in the power supply circuit of the present invention. Fig.15 As shown, the power circuit 102 includes a power supply circuit 10B and a voltage slew rate enhancement circuit 20B. The power supply circuit 10B is connected to a load 30 through a power supply node 14 to provide a power supply current I S to the load 30, so that a first output voltage (V O1 The voltage slew rate boosting circuit 20B includes a detection node 24, which generates a second output voltage (V O2 ), and connects the power supply node 14 of the power supply loop 10B through the detection node 24 to detect the first output voltage (V O1 ) to determine whether to control the power supply circuit 10B to provide more power supply current I S To load 30.

[0076] See also Fig.15 and Fig.16 The power supply circuit 10B includes a first amplifier 11B and a first output stage 13B. The first amplifier 11B is a transconductance operational amplifier (OTA) or a gain stage operational amplifier of a single-stage or multi-stage structure. An input terminal (such as a non-inverting input terminal) of the first amplifier 11B receives a first reference voltage (V REF1 ), and the other input terminal (such as the inverting input terminal) is connected to the power supply node 14 and receives the first output voltage (V O1 ), and the output terminal is connected to a first control point 12 and a first control voltage (V CT1 In the present invention, the first amplifier 11B presets a first output voltage (V O1 ) is equal to N times the first reference voltage (V REF1 ), such as V O1 =N×V REF1, N can also be 1 or a multiple of 1 or more. The first output stage 13B is implemented by using a PMOS transistor with a larger length and width. The drain terminal of the first output stage 13B is connected to the power supply node 14, and the source terminal is connected to the working voltage (V SS ) is connected to the first control point 12 via the gate terminal.

[0077] See also Fig.15 and Fig.17 The voltage slew rate enhancement circuit 20B includes a second amplifier 21B and a second output stage 23B. The second amplifier 21B is a low-power electronic component, which can also be a single-stage or multi-stage transconductance operational amplifier (OTA) or a gain stage operational amplifier. An input terminal (such as a non-inverting input terminal) of the second amplifier 21B receives a second reference voltage (V REF2 ), the other input terminal (such as the inverting input terminal) is connected to the detection node 24 and a second output voltage (V O2 ), and the output terminal is connected to a second control point 22 and a second control voltage (V CT2 ). The second output stage 23B is implemented by a PMOS transistor with a smaller length and width. The drain terminal of the second output stage 23B is connected to the detection node 24, the source terminal is connected to the working voltage (Vss) and the gate terminal is connected to the second control point 22. In the present invention, the length and width of the transistor of the second output stage 23B is much smaller than the length and width of the transistor of the first output stage 13B.

[0078] In this embodiment, the second amplifier 21B of the voltage slew rate boosting circuit 20B presets a first output voltage (V O1 ) is greater than the second output voltage (V O2 When the second amplifier 21B detects the second output voltage (V O2 ) voltage change (such as the second output voltage (V O2 ) becomes larger) and determines the first output voltage (V O1 ) is greater than the second output voltage (V O2 ), the control loop of the voltage slew rate enhancement circuit 20B will be closed, for example, the channel of the second output stage 23B will be closed, and the driver 27 cannot be turned on through the hysteresis circuit 25. When the second amplifier 21B detects the second output voltage (V O2 ) voltage change (such as the second output voltage (V O2 ) becomes smaller) and determines the first output voltage (V O1 ) is less than the second output voltage (V O2), the control loop of the voltage slew rate enhancement circuit 20B will be started, for example: the channel of the second output stage 23B is turned on, and the second control voltage (V CT2 ) drives the driver 27 to be turned on through the hysteresis circuit 25. The turned-on driver 27 adjusts the first control voltage (V CT1 ) voltage level (such as pulling down the first control voltage (V CT1 )) so that the adjusted first control voltage (V CT1 ) can control the channel expansion of the first output stage 13B to output more power supply current (I S ) to the power supply node 14, thereby making the first output voltage (V O1 ) can be accelerated to recover to the originally preset voltage level or close to the originally preset voltage level.

[0079] Here, the voltage slew rate enhancement circuit 20B of the present invention can adjust the circuit sensitivity through the hysteresis circuit 25 and can also adjust the circuit sensitivity through the two output voltages (V O1 )、(V O2 ) to adjust the circuit sensitivity.

[0080] In addition, the hysteresis circuit 25 of the power supply circuit 102 of this embodiment can also refer to Figure 4 , Figure 5 , Figure 7 or Fig.14 This is implemented by an inverter, a Schmitt trigger or a voltage comparator, and will not be described again here.

[0081] The above is only a preferred specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can make equivalent substitutions or changes within the technical scope disclosed in the present application according to the technical solution and application concept of the present application, which should be covered by the protection scope of the present application.

Claims

1. A power supply circuit, characterized in that: include: A power supply circuit is connected to a load through a power supply node, provides a power supply current to the load, and generates a first output voltage on the power supply node. The power supply circuit includes: A first amplifier is connected to the power supply node and a first control point, receives a first reference voltage and the first output voltage, and generates a first control voltage at the first control point; and A first output stage is connected to the first control point and the power supply node, and controls the magnitude of the power supply current output by the first output stage by the first control voltage; and The voltage slew rate enhancement circuit is connected to the power supply node of the power supply loop through a detection node to detect the voltage change of the first output voltage and generate a second output voltage on the detection node, comprising: A second amplifier is connected to the detection node and a second control point, receives a second reference voltage and the second output voltage, and generates a second control voltage at the second control point; A second output stage is connected to the second control point and the detection node, and the second control voltage is used to control the on or off of the second output stage, wherein the length and width of the transistor of the first output stage is much larger than the length and width of the transistor of the second output stage; a hysteresis circuit connected to the second control point to receive the second control voltage and output a driving voltage, wherein the hysteresis circuit has a hysteresis function to apply a hysteresis reaction to the second control voltage to delay the transition of the driving voltage; and A driver connected to the hysteresis circuit and the first control point, receiving the driving voltage, and adjusting the voltage level of the first control voltage on the first control point when the driver is driven to conduct by the driving voltage; The second amplifier presets the first output voltage on the power supply node to be greater than the second output voltage on the detection node; when the second amplifier determines that the first output voltage is less than the second output voltage through the voltage change of the second output voltage on the detection node, the voltage slew rate enhancement circuit starts the control loop, the second control voltage controls the second output stage to be turned on and drives the driver to be turned on through the hysteresis circuit, so as to adjust the first control voltage on the first control point through the turned-on driver.

2. The power supply circuit according to claim 1, characterized in that The first amplifier presets the first output voltage to be equal to N times the first reference voltage, where N is 1 or greater.

3. The power supply circuit according to claim 1, characterized in that The hysteresis circuit is implemented with an inverter and includes a PMOS transistor and an NMOS transistor. The PMOS transistor is a long-channel PMOS transistor. When the inverter receives the second control voltage whose voltage level drops, the PMOS transistor delays the response to the second control voltage whose voltage level drops, thereby delaying the conduction time of the PMOS transistor and delaying the transition of the driving voltage.

4. The power supply circuit according to claim 1, characterized in that: The hysteresis circuit is implemented with an inverter and includes a PMOS transistor and an NMOS transistor. The NMOS transistor is a long-channel NMOS transistor. When the inverter receives the second control voltage with a rising voltage level, the NMOS transistor delays the response to the second control voltage with a rising voltage level, thereby delaying the conduction time of the NMOS transistor and delaying the transition of the driving voltage.

5. The power supply circuit according to claim 1, characterized in that: The hysteresis circuit is implemented with a Schmitt trigger, which has a first threshold voltage and a second threshold voltage. The first threshold voltage is greater than the second threshold voltage. When the Schmitt trigger receives the second control voltage with a rising voltage level, the voltage level of the second control voltage must rise above the first threshold voltage before the driving voltage changes state; or, when the Schmitt trigger receives the second control voltage with a falling voltage level, the voltage level of the second control voltage must drop below the second threshold voltage before the driving voltage changes state.

6. The power supply circuit according to claim 1, characterized in that: The hysteresis circuit is implemented with a voltage comparator, which receives a reference voltage and the second control voltage. The reference voltage serves as a threshold for the driving voltage to change state. When the voltage comparator receives the second control voltage with an increasing voltage level, the voltage level of the second control voltage must increase above the reference voltage before the driving voltage changes state; or, when the voltage comparator receives the second control voltage with a decreasing voltage level, the voltage level of the second control voltage must decrease below the reference voltage before the driving voltage changes state.

Images