Bootstrap switch circuit

Abstract

The invention relates to a bootstrap switch circuit. Example embodiments include a bootstrap switch circuit comprising: a positive output node (109 +); a negative output node; a first input node configured to receive a first input voltage; and a second input node configured to receive a second input voltage. First, second, third, and fourth switches are coupled between the input and output nodes. A first negative bootstrap level shifter and a first positive bootstrap level shifter coupled between the first input node and a first clock signal circuit provide control signals to the first and second switches. A second negative bootstrap level shifter and a second positive bootstrap level shifter coupled between the second input node and a second ground reference power line provide control signals to the third and fourth switches. Each of the first, second, third, and fourth switches includes first and second MOSFETs of opposite types arranged in a series connection.

Description

Technical Field

[0001] The present disclosure relates to a bootstrap switch circuit for use in an analog front end of a data acquisition system, such as a battery management system. Background Art

[0002] Battery management systems are used to monitor voltage and / or current to protect the battery from overcharging, electrical overstress, or inducing overvoltage, thereby optimizing battery performance, and therefore require measuring the voltage across individual cells in the battery.

[0003] Battery management systems are often required to operate within a wide range of common-mode voltages, which depend on the location of the battery cells within the battery stack. For example, a battery for an electric motor may include a stack of battery cells with common-mode voltages ranging from a few volts up to 100V or more.

[0004] The battery management system analog front end (AFE) can use a differential analog multiplexer (AMUX) that operates in a wide range of common mode voltages to measure battery cell voltages up to 5V. Metal shunts may be connected to the AFE input instead of the battery cell, so the voltage across the shunt also needs to be measured. The use of shunts will produce a bipolar differential input signal (e.g., -2V to +5V). The AMUX at the input of the AFE can also be used as a chopper, which produces a high voltage differential output (e.g., -5V to +5V). Under these conditions, leakage through the switch of the AMUX cannot be allowed because the leakage will cause input to output differential signal transmission errors and possible additional errors caused by undesirable IR drops on the resistors of the external anti-aliasing filter.

[0005] Traditionally, the method to avoid leakage uses a complementary T-type switch in a high voltage AMUX, where the gate of the switch is controlled by a voltage ranging from 0V to 5V when the lower of the two input potentials is involved. This method requires determining which of the two input potentials is lower. Circuits can be used to determine the detection of the lower of the two inputs, but such circuits will require many high voltage components, which require more space than low voltage components.

[0006] What is therefore needed is a method to overcome leakage without having to determine a lower input signal among multiple input signals and preferably using minimal high voltage rated components. Summary of the invention

[0007] According to a first aspect, there is provided a bootstrap switching circuit, comprising:

[0008] Positive output node;

[0009] Negative output node;

[0010] a first input node configured to receive a first input voltage;

[0011] a second input node configured to receive a second input voltage;

[0012] a first switch coupled between the first input node and the positive output node;

[0013] a second switch coupled between the first input node and the negative output node;

[0014] a third switch coupled between the second input node and the negative output node;

[0015] a fourth switch coupled between the second input node and the positive output node;

[0016] a first negative bootstrap level shifter and a first positive bootstrap level shifter each coupled between the first input node and a first clock signal circuit and configured to provide control signals to the first and second switches;

[0017] a second negative bootstrap level shifter and a second positive bootstrap level shifter, each coupled between the second input node and a second clock signal circuit and configured to provide control signals to the third and fourth switches,

[0018] Each of the first, second, third and fourth switches includes first and second MOSFETs of opposite types arranged in a series connection.

[0019] The bootstrap switch circuit can be used in an analog front end of a data acquisition system such as a battery management system, where an output node is sampled to measure the voltage across first and second input nodes connected across cells of a battery.

[0020] Each of the bootstrapped level shifters may include:

[0021] a first level shifter MOSFET;

[0022] a second level shifter MOSFET;

[0023] a first level shifter capacitor connected between a drain of the first level shifter MOSFET and a first output of a corresponding clock signal circuit, the drain of the first level shifter MOSFET being connected to a gate of the second level shifter MOSFET; and

[0024] A second level shifter capacitor is connected between a drain of the second level shifter MOSFET and a second output of a corresponding clock signal circuit, the drain of the second level shifter MOSFET being connected to a gate of the first level shifter MOSFET.

[0025] The first and second clock signal circuits may each include:

[0026] Clock signal source;

[0027] A first inverter connected between the clock signal source and the first output; and

[0028] A second inverter is connected between the first inverter and the second output.

[0029] In some examples, the first and second level-shifter MOSFETs of the first and second negative bootstrap level shifters are P-channel MOSFETs, and the first and second level-shifter MOSFETs of the first and second positive bootstrap level shifters are N-channel MOSFETs.

[0030] Some examples of switching circuits:

[0031] The sources of the first MOSFETs of the first and second switches are connected to the first input node;

[0032] The source of the second MOSFET of the first and second switches is connected to the drain of the first MOSFET of the first and second switches;

[0033] The drain of the second MOSFET of the first switch is connected to the positive output node; and

[0034] The drain of the second MOSFET of the second switch is connected to the negative output node,

[0035] The first MOSFETs of the first and second switches are n-channel MOSFETs, and the second MOSFETs of the first and second switches are p-channel MOSFETs.

[0036] Some examples of switching circuits:

[0037] The drains of the first MOSFETs of the third and fourth switches are connected to the second input node;

[0038] The drain of the second MOSFET of the third and fourth switches is connected to the source of the first MOSFET of the third and fourth switches;

[0039] A source of the second MOSFET of the third switch is connected to the positive output node; and

[0040] The source of the second MOSFET of the fourth switch is connected to the negative output node,

[0041] The first MOSFETs of the third and fourth switches are p-channel MOSFETs, and the second MOSFETs of the third and fourth switches are n-channel MOSFETs.

[0042] Some examples of switching circuits:

[0043] a gate of the first MOSFET of the first switch is connected to a drain of the first level shifter MOSFET of the first positive bootstrap level shifter, and a gate of the second MOSFET of the first switch is connected to a drain of the second level shifter MOSFET of the first negative bootstrap level shifter;

[0044] a gate of the first MOSFET of the second switch is connected to a drain of the second level shifter MOSFET of the first positive bootstrap level shifter, and a gate of the second MOSFET of the second switch is connected to a drain of the first level shifter MOSFET of the first negative bootstrap level shifter;

[0045] a gate of the first MOSFET of the third switch is connected to a drain of the first level-shifter MOSFET of the second positive bootstrap level shifter, and a gate of the second MOSFET of the third switch is connected to a drain of the second level-shifter MOSFET of the second negative bootstrap level shifter; and

[0046] The gate of the first MOSFET of the fourth switch is connected to the drain of the second level shifter MOSFET of the second positive bootstrap level shifter, and the gate of the second MOSFET of the fourth switch is connected to the drain of the first level shifter MOSFET of the second negative bootstrap level shifter.

[0047] The switching circuit can be configured to operate in the following modes:

[0048] a first mode in which the first and third switches are closed to connect the first input node to the positive output node and the second input node to the negative output node, and the second and fourth switches are open; and

[0049] a second mode in which the second and fourth switches are closed to connect the first input node to the negative output node and the second input node to the positive output node, while the first and third switches are open.

[0050] The switching circuit may also include a first tank capacitor circuit, which includes first, second, third and fourth tank diodes and first and second tank capacitors, the first tank capacitor being connected between the first input node and the cathode terminals of the third and fourth tank diodes, and the second tank capacitor being connected between the first input node and the anode terminals of the first and second tank diodes.

[0051] Anode terminals of the first and second tank diodes of the first tank capacitor circuit may be connected to the first and second level shifter capacitors of the first positive bootstrap level shifter. Cathode terminals of the third and fourth tank diodes of the first tank capacitor circuit may be connected to the first and second level shifter capacitors of the first negative bootstrap level shifter.

[0052] The first and second tank diodes of the first tank capacitor circuit may be p-channel MOSFETs connected as pn junction diodes, and the third and fourth tank diodes of the first tank capacitor circuit may be n-channel MOSFETs connected as pn junction diodes.

[0053] The switching circuit may also include a second tank capacitor circuit, which includes first, second, third and fourth tank diodes and first and second tank capacitors, the first tank capacitor is connected between the second input node and the anode connector of the first and second tank diodes, and the second tank capacitor is connected between the second input node and the cathode connector of the first and second tank diodes.

[0054] Anode connections of the first and second tank diodes of the second tank capacitor circuit may be connected to first and second level shifter capacitors of the second positive bootstrap level shifter. Cathode connections of the third and fourth tank diodes of the second tank capacitor circuit may be connected to the first level shifter capacitor of the second negative bootstrap level shifter.

[0055] The first and second tank diodes of the second tank capacitor circuit may be p-channel MOSFETs connected as pn junction diodes, and the third and fourth tank diodes of the second tank capacitor circuit may be n-channel MOSFETs connected as pn junction diodes.

[0056] Each switch of the switching circuit may further include:

[0057] A first switching inverter connected to the gate of the first MOSFET; and

[0058] A second switch inverter is connected to the gate of the second MOSFET.

[0059] According to a second aspect, a battery management system is provided, comprising an analog front end and a digital sampling module, the analog front end comprising a plurality of switch circuits according to the first aspect, the first and second input nodes of each switch circuit being connected to the respective first and second output connections of each battery cell in a respective plurality of battery cells of a battery, the digital sampling module being connected to sample the voltage across the positive and negative output nodes of each switch circuit in the analog front end. Other features associated with the first aspect may also apply to the battery management system of the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] Embodiments will now be described by way of example with reference to the accompanying drawings, in which:

[0061] Figure 1 is a block diagram showing a bootstrap switch circuit for an analog front end of a battery management system;

[0062] Figure 2A is a schematic diagram illustrating example first and second switches for a bootstrap switching circuit;

[0063] Figure 2B is a schematic diagram illustrating example third and fourth switches for a bootstrap switching circuit;

[0064] Figure 3 is a schematic diagram of a dual bootstrap level shifter;

[0065] Figure 4 is a schematic diagram of a dual bootstrap level shifter;

[0066] Figure 5 is a block diagram of a bootstrap switch circuit;

[0067] Figure 6 is a block diagram of a bootstrap switch circuit with an intermediate tank capacitor;

[0068] Figure 7 is a schematic diagram of the intermediate tank capacitor;

[0069] Figure 8 is a block diagram of a bootstrap switch circuit with an intermediate tank capacitor;

[0070] Fig. 9 is a schematic diagram of an intermediate tank capacitor circuit for a bootstrap switching circuit;

[0071] Fig.10 is a schematic diagram of an intermediate tank capacitor circuit of a bootstrap switching circuit;

[0072] Fig.11 is a schematic diagram of an example switch for a bootstrap switch circuit having an intermediate tank capacitor circuit;

[0073] Fig.12 is a schematic diagram of an example battery management system including a plurality of bootstrap switch circuits;

[0074] Fig.13 is a schematic diagram of an example bootstrap switch circuit connected to an integrator of a delta-sigma modulator for a battery management system;

[0075] Fig.14 yes Fig.13 A schematic diagram of a switch arrangement in a bootstrap switch circuit;

[0076] Fig.15a and 15b yes Fig.14 A schematic diagram of the first and second switches of the arrangement in an off mode; and

[0077] Fig.16a and 16b yes Fig.14 Schematic diagram of the third and fourth switches of the arrangement in the off mode. DETAILED DESCRIPTION

[0078] Figure 1 An example switching circuit 100 for an analog front end of a battery management system (BMS) for battery cell voltage measurement is shown. The circuit 100 is configured to measure a differential voltage between two input voltages, where the lower voltage of the two voltages may be unknown. In a battery management system, the differential voltage will correspond to the voltage across one battery cell or shunt within a battery stack. The circuit 100 includes: a first input node 106a, which is configured to receive a first input voltage Vin1; a second input node 106b, which is configured to receive a second input voltage Vin2; a positive output node 109+; a negative output node 109-; a first switch 101, which is coupled between the first input node 106a and the positive output node 109+; a second switch 102, which is coupled between the first input node 106a and the negative output node 109-; a third switch 103, which is coupled between the second input node 106b and the negative output node 109-; and a fourth switch 104, which is coupled between the second input node 106b and the positive output node 109+. The first negative bootstrap level shifter 107a and the first positive bootstrap level shifter 107b are each coupled between the first input node 106a and the first clock signal circuit 110a and are configured to provide negative and positive switching signals to the first switch 101 and the second switch 102. The second negative bootstrap level shifter 108a and the second positive bootstrap level shifter 108b are each coupled between the second input node 106b and the second clock signal circuit 110b and are configured to provide negative and positive switching signals to the third switch 103 and the fourth switch 104.

[0079] Figure 2A An example circuit 200a is shown including a first switch 101 and a second switch 102. Each switch 101, 102 includes a first MOSFET 201a, 202a having a source coupled to an input node 106a, and a second MOSFET 201b, 202b connected in series with the first MOSFET 201a, 202a. A body diode is indicated as part of each MOSFET, which is inherent to each device. The drain of the first MOSFET 201a, 202a of each switch 101, 102 is connected to the source of the second MOSFET 201b, 202b. The drain of the second MOSFET 201b in the first switch 101 is connected to the positive output node 109+, and the drain of the second MOSFET 202b in the second switch 102 is connected to the negative output node 109-. The first and second MOSFETs 201a, 201b, 202a, 202b in each switch 101, 102 are of opposite types, wherein the first MOSFET 201a, 202a is an N-channel MOSFET and the second MOSFET 201b, 202b is a P-channel MOSFET.

[0080] As described in further detail below, gate signals g1, gn1, pg1, pgn1 are provided to the gates of first and second MOSFETs 201a, 201b, 202a, 202b of first and second switches 101 and 102 by first negative and first positive bootstrap level shifters 107a, 107b.

[0081] Figure 2B An example circuit 200b including a third switch 103 and a fourth switch 104 is shown. As with the first switch 101 and the second switch 202, each switch 103, 104 includes a first MOSFET 203a, 204a and a second MOSFET 203b, 204b of opposite types arranged in a series connection. However, in the third switch 103 and the fourth switch 104, the first MOSFET 203a, 204a in each switch 103, 104 is a P-channel MOSFET, and the second MOSFET 203b, 204b is an N-channel MOSFET. This topological difference allows the dynamic range of the input signal (i.e., the battery cell voltage) to be increased while remaining within the safe operating area (SOA) of the MOSFETs in the switches 103, 104.

[0082] The drain of the first MOSFET 203a, 204a in each of the third switch 103 and the fourth switch 104 is connected to the input node 106a. The source of the first MOSFET 203a, 204a in each of the third switch 103 and the fourth switch 104 is connected to the drain of the second MOSFET 203b, 204b in each of the third switch 103 and the fourth switch 104. The source of the second MOSFET 203b in the third switch 103 is connected to the positive output node 109+, and the source of the second MOSFET 204b in the fourth switch 104 is connected to the negative output node 109-.

[0083] As described in further detail below, gate signals g2, gn2, pg2, pgn2 are provided to the gates of first and second MOSFETs 203a, 203b, 204a, 204b of third and fourth switches 103, 104 by second negative bootstrap level shifter 108a and second positive bootstrap level shifter 108b.

[0084] Figure 3 Show Figure 1 1 and 10. An example configuration of a first negative bootstrap level shifter 107a and a positive bootstrap level shifter 107b of a switch circuit 100 is shown. The first negative bootstrap level shifter 107a includes a first P-channel MOSFET 301 and a second P-channel MOSFET 302, a first level shifter capacitor 307 and a second level shifter capacitor 308, and a resistor 311 connecting the first negative bootstrap level shifter 107a to the first input node 106a to protect the MOSFETs 301 and 302. The first positive level shifter 107b similarly includes a first N-channel MOSFET 303 and a second N-channel MOSFET 304, a first level shifter capacitor 309 and a second level shifter capacitor 310, and a resistor 312 connecting the first positive level shifter 107b to the first input node 106a to protect the MOSFETs 303 and 304. The resistors 311 and 312 are provided as part of the analog circuit to represent the connection resistance and may not need to be separate components in an embodiment.

[0085] In a general aspect, each level shifter includes a first level shifter MOSFET 301, 303, a second level shifter MOSFET 302, 304, a first level shifter capacitor 307, 309 coupled between the clock signal circuit 110a, the drain of the first level shifter MOSFET 301, 303 and the gate of the second level shifter MOSFET 302, 304, and a second level shifter capacitor 308, 310 coupled between the clock signal circuit 110a, the drain of the second level shifter MOSFET 302, 304 and the gate of the first level shifter MOSFET 301, 303. The sources of the first and second level shifter MOSFETs are connected to the respective input nodes 106a, 106b.

[0086] The only high voltage rated components required in the switch circuit 100 are capacitors 307-310, which must have a rating high enough to handle the battery voltage. One side of the capacitors 307-310 is subjected to a voltage close to the input Vin1, which may be close to 100V, while the other side is connected to the clock signal circuit 110a, the output of which may be switched between 0V and 5V. The inputs to the level shifters 107a, 107b are determined by the clock signal circuit 110a. Each level shifter receives a first input in1_1 and a second input in1_2 from the clock signal circuit 110a, which originate from a clock signal source 313. In the first mode, the clock signal may be equal to a logic low state (i.e., 0V), so in1_1 is in a logic high state, and in1_2 is in a logic low state due to the placement of the inverters 305, 306. In the second mode, the clock signal may be equal to a logic high state (eg, 5V), and in1_1 exhibits a logic low, while in1_2 is a logic high.

[0087] The bootstrap level shifters 107a, 107b are connected to the first input node 106a to receive the first input voltage Vin1 and the switching signals in1_1, in1_2. The first negative bootstrap level shifter 107a is configured to generate negative shift voltages pg1, pgn1 relative to Vin1, so that as Vin1 changes, the voltages V(pgn1) and V(pg1) remain lower than X volts of Vin1, that is:

[0088] V(pgn1)=V(Vin1)-X

[0089] V(pg1)=V(Vin1)-X

[0090] The signals pgn1 and pg1 are used to drive the gates of the P-channel MOSFETS 201 b and 202 b of the first switch 101 and the second switch 102 , respectively, in different operation modes.

[0091] The first positive bootstrap level shifter 107b is configured to provide a positive shift voltage g1, gn1 relative to Vin1, namely:

[0092] V(g1)=V(Vin1)+X

[0093] V(gn1)=V(Vin1)+X

[0094] The signals g1 and gn1 are used to drive the gates of the N-channel MOSFETs 201 a , 202 a of the first switch 101 and the second switch 102 , respectively, in different operation modes.

[0095] The switch has Figure 2A In the case of the configuration shown in , the negative shift voltages pgn1, pg1 drive the gates of the P-channel MOSFETs 201b, 202b in the first and second switches, respectively, and the positive shift voltages g1, gn1 drive the gates of the first MOSFETs 201a, 202a of the first and second switches, respectively.

[0096] Figure 4 FIG. 4 shows an example configuration of the second positive and negative bootstrap level shifters 108a, 108b in the switch circuit 100. The bootstrap level shifters 108a, 108b have the same Figure 3 , where the shifted voltage is now relative to the second input voltage Vin2 and is used to drive the MOSFETs in the third switch 103 and the fourth switch 104. The second negative bootstrap level shifter 108a provides negative shifted voltages pgn2, pg2 relative to the input voltage Vin2 to drive the gates of the P-channel MOSFETs 203a, 204a of the third switch 103 and the fourth switch 104, respectively, in different operation modes, where:

[0097] V(pgn2)=V(Vin2)-X

[0098] V(pg2)=V(Vin2)-X

[0099] The second positive bootstrap level shifter 108b provides positive shift voltages g2, gn2 relative to the input voltage Vin2 to drive the gates of the N-channel MOSFETs 203b, 204b of the third switch 103 and the fourth switch 104, respectively, in different operation modes, wherein:

[0100] V(g2)=V(Vin2)+X

[0101] V(gn2)=V(Vin2)+X

[0102] In general terms, negative level shifters 107a, 108a are used to drive P-channel MOSFETs of switches 101-104, and positive level shifters 107b, 108b are used to drive N-channel MOSFETs of switches 101-104.

[0103] First Mode

[0104] Figure 5 The circuit 100 shown in is configured to operate in a first mode, wherein the first switch 101 and the third switch 103 are closed to connect the first input node 106a to the positive output node 109+ and the second input node 106b to the negative output node 109-, while the second and fourth switches (102, 104) are open.

[0105] Considering that switches 101-104 belong to Figure 2A , in a first mode, inputs in1_1 and in2_1 are set to logic high, and inputs in1_2 and in2_2 are set to logic low.

[0106] The voltage level at pgn1 of the first negative bootstrap level shifter presents a voltage lower than the voltage level at pg1, so that PMOS 301 is driven into an on state and PMOS 302 is driven into an off state. The voltage level at pgn1 drives the gate of PMOS 201b of the first switch 101. The voltage level at g1 of the first positive bootstrap level shifter presents a voltage higher than the voltage level at gn1, so that NMOS 304 is driven into an on state and NMOS 303 is driven into an off state. The voltage level at g1 drives the gate of NMOS 201a of the first switch 101. This first operation mode connects the first input voltage Vin1 to the positive output node 109+ via the first switch 101.

[0107] The voltage level at pgn2 of the second negative bootstrap level shifter presents a voltage lower than the voltage level at pg2, so that PMOS 401 is driven into an on state and PMOS 402 is driven into an off state. The voltage level at pgn2 drives the gate of PMOS 203a of the third switch 103. The voltage level at g2 of the second positive bootstrap level shifter presents a voltage higher than the voltage level at gn2, so that NMOS 404 is driven into an on state and NMOS 403 is driven into an off state. The voltage level at g2 drives the gate of NMOS 203b of the third switch 103. This first operation mode connects the second input voltage Vin2 to the negative output node 109- via the third switch 103.

[0108] Second Mode

[0109] The circuit is also configured to operate in a second mode, wherein the second switch 102 and the fourth switch 104 are closed to connect the first input node 106a to the negative output node 109- and the second input node 106b to the positive output node 109+, while the first switch 101 and the third switch 103 are open.

[0110] In the second operating mode, switches 101-104 are Figure 2A In the case of the type depicted, inputs in1_1 and in2_1 are set to logic low, and in1_2 and in2_2 are set to logic high.

[0111] The voltage level at pg1 of the first negative bootstrap level shifter now presents a voltage lower than the voltage level at pgn1, so that PMOS 302 is driven into the on state and PMOS 301 is driven into the off state. The voltage level at pg1 drives the gate of PMOS 202b of the second switch 102. The voltage level at gn1 of the first positive bootstrap level shifter now presents a level higher than the voltage level at g1, and NMOS 303 is now driven into the on state, while NMOS 304 is driven into the off state. The voltage level at gn1 now drives the gate of NMOS transistor 202a of the second switch 102. This second operation mode connects the first input voltage Vin1 to the negative output node 109- via the second switch 102.

[0112] The voltage level at pg2 of the second negative bootstrap level shifter now presents a voltage lower than the voltage level at pgn2, so that PMOS 402 is driven into the on state and PMOS 401 is driven into the off state. The voltage level at pg2 drives the gate of PMOS 204a of the fourth switch 104. The voltage level at gn2 of the second positive bootstrap level shifter now presents a level higher than the voltage level at g2, and NMOS 403 is driven into the on state, while NMOS 404 is driven into the off state. The voltage level at gn2 now drives the gate of NMOS transistor 204b of the fourth switch 104. This second operating mode connects the second input voltage Vin2 to the positive output node 109+ via the fourth switch 104.

[0113] This configuration of switches has the advantage that the previous requirement to know the lower of the two inputs Vin1 and Vin2 is eliminated, which in turn reduces the size of the circuit and the number of high voltage components required.

[0114] When operating in the first mode, the first switch 101 and the third switch 103 connect Vin1 and Vin2 to the positive output node 109+ and the negative output node 109-, respectively, while also connecting Vin1 to the output side of the fourth switch and connecting Vin2 to the output side of the second switch, which may cause leakage in conventional topologies. The switches of opposite types in the circuit described herein avoid reversely turning on the other MOSFET in each switch, thereby preventing leakage when processing bipolar input signals.

[0115] Output nodes 109+ and 109- may be provided by other circuitry 501 (e.g., as described below with respect to Fig.12 The measurement module 1202 described above is processed to measure the differential voltage across the inputs Vin1 and Vin2.

[0116] Figure 6 An example bootstrap switch circuit similar to that disclosed in US8963630B2 is shown in combination with additional components acting as intermediate tank capacitor circuits 610, 611. The addition of the tank capacitor circuits reduces the size requirements of the capacitors within the level shifter 607, thereby reducing the overall size of the bootstrap switch circuit 600. Figure 7 Show Figure 6 6, wherein a tank capacitor circuit 610 is connected to an input node 606a, the input node 606a being configured to receive a first input voltage Vin1. The tank capacitor circuit 610 includes a tank capacitor 705, and two MOSFETs of the opposite type to those in the level shifter 607, which are P-channel in the case of a positive bootstrap level shifter. The MOSFETs 703, 704 are connected to act as diodes. The tank capacitor 705 is connected to the source and gate of the tank capacitor circuit MOSFETs 703, 704. The drain of the tank capacitor circuit MOSFET is connected to the level shifter capacitor.

[0117] As circuit requirements change, the size of MOSFET 601 may increase, requiring larger high voltage capacitors in level shifter 607. It may be advantageous to add inverter 706 to drive MOSFET 601. Power for inverter 706 may be derived from the voltage developed across capacitor 705.

[0118] The tank capacitor 705 has lower voltage requirements than the voltage requirements of the level shifter 607 and can therefore be made smaller, thereby achieving higher circuit density.

[0119] The circuit should not be limited to just the example shown, but may instead include a PMOS switch with a negative bootstrap level shifter and a tank capacitor circuit including an N-channel MOSFET. Figure 6 The additional tank capacitor circuit 611 in follows the same connection to the level shifter 608 and the second input node 606b.

[0120] Figure 8 The concept of adding a tank capacitor circuit to the bootstrap switch circuit 100 is shown. The switch circuit 800 also includes the details in Fig. 9 and 10 1 and 10. The first tank capacitor circuit 801a and the second tank capacitor circuit 801b are further shown in FIG. Each tank capacitor circuit 801a, 801b includes a first, second, third and fourth tank MOSFET 901-904, 1001-1004 and a first and second tank capacitor 905a, 905b, 1005a, 1005b. The first and second MOSFET 901, 902, 1001, 1002 are p-channel MOSFETs, while the third and fourth MOSFET 903, 904, 1003, 1004 are n-channel MOSFETs. The MOSFETs 901-904, 1001-1004 are arranged and connected to act as diodes, i.e., with the gate and source (or body) connected together. In the first tank capacitor circuit 801a, the first tank capacitor 905a is connected between the first input node 106a and the gate and source connections of the third tank MOSFET 903 and the fourth tank MOSFET 904, and the second tank capacitor 905b is connected between the first input node 106a and the gate and source connections of the first tank MOSFET 901 and the second tank MOSFET 902. In the second tank capacitor circuit 801b, the first tank capacitor 1005a is connected between the second input node 106b and the gate and source connections of the third tank MOSFET 1003 and the fourth tank MOSFET 1004, and the second tank capacitor 1005b is connected between the second input node 106b and the gate and source connections of the first tank MOSFET 1001 and the second tank MOSFET 1002. The drain connections of the first tank MOSFET 901 and the second tank MOSFET 902 of the first tank capacitor circuit 801a are connected to the first positive bootstrap level shifter 107b (see Figure 3 ) and the drain connections of the third tank MOSFET 903 and the fourth tank MOSFET 904 of the first tank capacitor circuit 801a are connected to the first negative bootstrap level shifter 107a (see Figure 3) of the first level shifter capacitor 307 and the second level shifter capacitor 308. Similarly, the drains of the first tank MOSFET 1001 and the second tank MOSFET 1002 of the second tank capacitor circuit 801b are connected to the second positive bootstrap level shifter 108b (see Figure 4 ) and the drains of the third tank MOSFET 1003 and the fourth tank MOSFET 1004 of the second tank capacitor circuit 801b are connected to the second negative bootstrap level shifter 108a (see Figure 4 )'s first and second level shifter capacitors 407, 408.

[0121] Fig. 9 and 10 The MOSFETs 901-904, 1001-1004 shown in the are shown as enhancement mode n-channel and p-channel MOSFETs connected as PN junction diodes. In a general aspect, the MOSFETs can be defined as diodes, where the first and second diodes 901, 902, 1001, 1002 in each circuit 801a, 801b have cathode connections connected to respective capacitors 905b, 1005b, and the third and fourth diodes 903, 904, 1003, 1004 have anode connections connected to respective capacitors 905a, 1005a. Reference Fig. 9 , current flows from g1 and gn1 into the circuit, through the first diode 901 and the second diode 902 to the second capacitor 905b, causing the voltage on the capacitor 905b to rise relative to Vin1. For the third diode 903 and the fourth diode 904, current flows from the node 106b to the first capacitor 905a, and from the capacitor 905a toward pg1 and pgn1 through the diodes 903, 904. The voltage on the capacitor 905a will therefore drop relative to Vin1.

[0122] Incorporating tank capacitors into the bootstrap switch circuitry allows the size of low density high voltage capacitors within the positive and negative bootstrap level shifters to be reduced, but at the expense of adding smaller area low to medium voltage capacitors. The increase in area required for circuit components allows for a more efficient time when charging the tank capacitors to a voltage sufficient to reduce the RDS(on) of the switches 101-104 to below an acceptable threshold.

[0123] Alternative arrangements of switches 101-104 are Fig.11, where inverters 1101, 1102 are disposed between the switching signal input and the gates of the first MOSFET 201a and the second MOSFET 201b. Such an arrangement may be used in combination with the tank capacitor circuit example described above. The voltage accumulated across the tank capacitors 905a, 905b, 1005a, 1005b is used to power the inverters 1101, 1102. When fully charged, the tank capacitors are large enough to deliver or withdraw the necessary charge to switch the inverters and associated MOSFETs 201, 202, 203 within the required time.

[0124] The combination of features disclosed, particularly the switch configuration that eliminates leakage through the switch and the tank capacitor, reduces both the circuit and component size of the switch circuit since fewer high voltage components are required.

[0125] Fig.12 An example battery management system 1200 is shown that includes an analog front end 1201 and a measurement module 1202. The analog front end 1201 includes a plurality of switch circuits as described herein, wherein first and second input nodes of each switch circuit are connected to respective first and second output connections of each of a respective plurality of battery cells of a battery 1203. The measurement module 1202 is connected to sample the voltage across the positive and negative output nodes of each switch circuit in the analog front end.

[0126] Fig.13 An example circuit 1300 is shown that includes a combination of a bootstrap switch circuit 1301 and a delta-sigma modulator 1302. The bootstrap switch circuit 1301 is on the high voltage (HV) side of the circuit 1300 and is capacitively coupled to the delta-sigma modulator 1302 on the low voltage (LV) side of the circuit 1300. The delta-sigma modulator 1302 has a first input terminal 1303 and a second input terminal 1304 connected to the positive output node 109+ and the negative output node 109- of the switch circuit 1301. The switch circuit 1301 is similar to Figure 1 The switch circuit shown in and described above, wherein the first to fourth switches are shown as switch 1305, described in more detail below. The control of switch 1305 is as described above, which is performed using level shifter circuit 1306.

[0127] like Fig.14As shown in FIG, the asymmetric four switches 101-104 limit the maximum voltage according to the maximum value permitted by the technology, which is +10V / -5V in this example. Depending on the switching phase p1 or p2 considered, each switch can withstand +10V / -5V or +5V / -10V. The switches 101-104 are organized in a simple way that ensures that the gate-to-source voltage of any device does not experience a voltage higher than 5V, while the drain-to-source voltage is limited to 10V. Each switch will experience voltages up to ±5V or ±10V only in the off state (i.e., when it is not conducting). In the case where the switch is turned on, the voltage across the switch will be equal to (or close to) 0V by definition after a certain stabilization time. This is the basic principle of all switched capacitor circuits.

[0128] Fig.15a and 15b A representation of the first switch 101 in an off mode is shown, where the voltage across the MOSFETs 201a, 201b is +10V (at Fig.15a in) or -5V (in Fig.15b 1 ). Since switches 201a, 201b are turned off, the associated driver circuit will set the gate voltage equal to the input voltage Vin, which is represented by the connection between input 106a and the gate of each MOSFET 201a, 201b. The input voltage Vin may vary, for example, between about 2V and 90V in a typical application. The second switch 102 operates similarly because the first MOSFET 202a and the second MOSFET 202b operate in the same manner.

[0129] Fig.16a and 16b A representation of the third switch 103 in an off mode is shown, wherein the voltage across the MOSFETs 203a, 203b is +5V (at Fig.16a in) or -10V (in Fig.16b ). Since switches 203a, 203b are off, the associated driver circuit will set the gate voltage equal to the input voltage Vin, which is represented by the connection between input 106b and the gate of each MOSFET 203a, 203b. The input voltage Vin may vary, for example, between about 2V and 90V in a typical application. The fourth switch 104 operates similarly because the first MOSFET 204a and the second MOSFET 204b operate in the same manner.

[0130] From reading this disclosure, other variations and modifications will be apparent to the skilled person.Such variations and modifications may involve equivalent and other features which are already known in the art of battery management systems and which may be used as alternatives or supplements to the features already described herein.

[0131] Although the attached claims refer to specific combinations of features, it should be understood that the scope of the disclosure of the present invention also includes any novel feature or any novel combination of features or any generalized form thereof disclosed explicitly or implicitly herein, regardless of whether it relates to the same invention currently claimed in any claim or whether it alleviates any or all technical problems that are the same as the technical problems alleviated by the present invention.

[0132] Features described in the context of separate embodiments may be provided in combination in a single embodiment. Conversely, various features described in the context of a single embodiment for the sake of brevity may also be provided separately or in any suitable subcombination. Applicants hereby caution that new claims may be formulated based on such features and / or combinations of such features during the prosecution of this application or any further application derived therefrom.

[0133] For the sake of completeness, it is also stipulated that the term "comprising" does not exclude other elements or steps, the term "a" or "an" does not exclude that a plurality of or a single processor or other unit may realize the functions of several components recited in the claims, and the reference signs in the claims should not be construed as limiting the scope of the claims.

Claims

1. A bootstrap switch circuit (100), characterized in that: include: Positive output node (109+); Negative output node (109-); a first input node (106a) configured to receive a first input voltage (Vin1); a second input node (106b) configured to receive a second input voltage (Vin2); a first switch (101) coupled between the first input node (106a) and the positive output node (109+); a second switch (102) coupled between the first input node (106a) and the negative output node (109-); a third switch (103) coupled between the second input node (106b) and the negative output node (109-); a fourth switch (104) coupled between the second input node (106b) and the positive output node (109+); a first negative bootstrap level shifter (107a) and a first positive bootstrap level shifter (107b), each coupled between the first input node (106a) and a first clock signal circuit (110a) and configured to provide control signals to the first and second switches (101, 102); as well as a second negative bootstrap level shifter (108a) and a second positive bootstrap level shifter (108b), each coupled between the second input node (106b) and a second clock signal circuit (110b) and configured to provide control signals to the third and fourth switches (103, 104), Each of the first, second, third and fourth switches (101, 102, 103, 104) comprises first and second MOSFETs (201a, 201b, 202a, 202b, 203a, 203b, 204a, 204b) of opposite types arranged in series connection.

2. The switch circuit (100) according to claim 1, characterized in that: Each of the bootstrap level shifters (107a, 107b, 108a, 108b) comprises: first level shifter MOSFET (301, 303, 401, 403); a second level shifter MOSFET (302, 304, 402, 404); a first level shifter capacitor (307, 309, 407, 409) connected between a drain of the first level shifter MOSFET (301, 303, 401, 403) and a first output of a corresponding clock signal circuit (110a, 110b), the drain of the first level shifter MOSFET (301, 303, 401, 403) being connected to a gate of the second level shifter MOSFET (302, 304, 402, 404); and A second level shifter capacitor (308, 310, 408, 410) connected between the drain of the second level shifter MOSFET (302, 304, 402, 404) and a second output of the corresponding clock signal circuit (110a, 110b), the drain of the second level shifter MOSFET (302, 304, 402, 404) being connected to the gate of the first level shifter MOSFET (301, 303, 401, 403).

3. The switch circuit (100) according to claim 2, characterized in that: The first and second clock signal circuits (110a, 110b) each include: Clock signal source (313, 314); a first inverter (305, 405) connected between the clock signal source (313, 413) and the first output; and A second inverter (306, 406) is connected between the first inverter (305, 405) and the second output.

4. The switch circuit (100) according to claim 2 or claim 3, characterized in that: The first and second level shifter MOSFETs (301, 302, 401, 402) of the first and second negative bootstrap level shifters (107a, 108a) are P-channel MOSFETs, and the first and second level shifter MOSFETs (303, 304, 403, 404) of the first and second positive bootstrap level shifters (107b, 108b) are N-channel MOSFETs.

5. The switch circuit (100) according to any one of claims 2 to 4, characterized in that: The sources of the first MOSFETs (201a, 202a) of the first and second switches (101, 102) are connected to the first input node (106a); The source of the second MOSFET (201b, 202b) of the first and second switches (101, 102) is connected to the drain of the first MOSFET (201a, 202a) of the first and second switches; The drain of the second MOSFET (201b) of the first switch (101) is connected to the positive output node (109+); and The drain of the second MOSFET (202b) of the second switch (102) is connected to the negative output node (109-), The first MOSFET (201a, 202a) of the first and second switches (101, 102) are n-channel MOSFETs, and the second MOSFET (201b, 202b) of the first and second switches (101, 102) are p-channel MOSFETs.

6. The switch circuit (100) according to any one of claims 2 to 5, characterized in that: The drains of the first MOSFETs (203a, 204a) of the third and fourth switches (103, 104) are connected to the second input node (106b); The drain of the second MOSFET (203b, 204b) of the third and fourth switches (103, 104) is connected to the source of the first MOSFET (203a, 204a) of the third and fourth switches (103, 104); The source of the second MOSFET (203b) of the third switch (103) is connected to the positive output node (109+); and The source of the second MOSFET (204b) of the fourth switch (104) is connected to the negative output node (109-), The first MOSFET (203a, 204a) of the third and fourth switches (103, 104) are p-channel MOSFETs, and the second MOSFET (203b, 204b) of the third and fourth switches (103, 104) are n-channel MOSFETs.

7. The switch circuit (100) according to any one of claims 2 to 6, characterized in that: The gate of the first MOSFET (201a) of the first switch (101) is connected to the drain of the first level shifter MOSFET (303) of the first positive bootstrap level shifter (107b), and the gate of the second MOSFET (201b) of the first switch (101) is connected to the drain of the second level shifter MOSFET (302) of the first negative bootstrap level shifter (107a); The gate of the first MOSFET (202a) of the second switch (102) is connected to the drain of the second level shifter MOSFET (304) of the first positive bootstrap level shifter (107b), and the gate of the second MOSFET (202b) of the second switch (102) is connected to the drain of the first level shifter MOSFET (301) of the first negative bootstrap level shifter (107a); The gate of the first MOSFET (203a) of the third switch (103) is connected to the drain of the first level shifter MOSFET (303) of the second positive bootstrap level shifter (108b), and the gate of the second MOSFET (203b) of the third switch (103) is connected to the drain of the second level shifter MOSFET (402) of the second negative bootstrap level shifter (108a); and The gate of the first MOSFET (204a) of the fourth switch (104) is connected to the drain of the second level shifter MOSFET (404) of the second positive bootstrap level shifter (108b), and the gate of the second MOSFET (204b) of the fourth switch (104) is connected to the drain of the first level shifter MOSFET (401) of the second negative bootstrap level shifter (108a).

8. The switching circuit (100) according to any one of the preceding claims, characterized in that The switching circuit (100) is configured to operate in the following modes: a first mode in which the first and third switches (101, 103) are closed to connect the first input node (106a) to the positive output node (109+) and the second input node (106b) to the negative output node (109-), while the second and fourth switches (102, 104) are open; as well as a second mode in which the second and fourth switches (102, 104) are closed to connect the first input node (106a) to the negative output node (109-) and the second input node (106b) to the positive output node (109+), while the first and third switches (101, 103) are open.

9. The switching circuit (800) according to any one of the preceding claims, characterized in that The invention also includes a first tank capacitor circuit (801a), wherein the first tank capacitor circuit (801a) includes first, second, third and fourth tank diodes (901, 902, 903, 904) and first and second tank capacitors (905a, 905b), wherein the first tank capacitor (905a) is connected between the first input node (106a) and the cathode terminals of the third and fourth tank diodes (903, 904), and the second tank capacitor (905b) is connected between the first input node (106a) and the anode terminals of the first and second tank diodes (901, 902).

10. A battery management system (1200), characterized in that: It comprises an analog front end (1201) and a measurement module (1202), wherein the analog front end (1201) comprises a plurality of switching circuits (100, 800) according to any of the preceding claims, the first and second input nodes (106a, 106b) of each switching circuit being connected to the corresponding first and second output connections of each battery cell in a corresponding plurality of battery cells of a battery (1203), and the measurement module (1202) being connected to sample the voltages across the positive and negative output nodes of each switching circuit (100, 800) in the analog front end (1201).

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