Polarization code DJSCC fast decoding design method based on FPGA

Abstract

The invention discloses a polar code DJSCC fast decoding design method based on an FPGA (Field Programmable Gate Array) from the generality of a polar code DJSCC and a traditional polar code in SC decoding. Code words of the polar code are divided into four sub-codes based on the distribution characteristics of frozen bits and information bits of the polar code, the decoding mode can be converted into parallel decoding of each sub-code from bit-by-bit decoding, and meanwhile, parallel iteration is performed on arithmetic units in a decoding tree of the same layer based on the parallel characteristics of an FPGA (Field Programmable Gate Array). Simulation results show that compared with SC decoding under the same hardware framework, the method can effectively reduce the number of iterations of decoding on the premise of almost not losing the anti-error code performance and not excessively increasing the resource consumption, thereby improving the throughput rate of decoding.

Description

Technical Field

[0001] The invention belongs to source coding technology, and in particular relates to a polar code DJSCC fast decoding design method based on FPGA. Background Art

[0002] With the rapid development of the Internet of Things, wireless sensor networks have been widely used in various fields. With the increasing number of devices and data, wireless sensor devices tend to develop in the direction of low power consumption and miniaturization. In order to solve the problems of high complexity and high power consumption of the traditional discrete source-channel coding framework, the Slepian-Wolf theory and the Wyner-Ziv theory show that the correlation between sources can be used for joint decoding, thereby transferring the complexity from the transmitter to the receiver. This is also the theoretical basis of Distributed Source Coding (DSC). Distributed Joint Source-Channel Coding (DJSCC) is a special case of DSC that takes channel conditions into consideration. The source is effectively compressed and has a certain anti-interference ability.

[0003] In 2009, Professor Arikan of Turkey proposed polar codes based on channel polarization. Polar codes are a channel coding method that has been strictly proven to reach the Shannon limit in theory. Subsequently, Arikan extended polar codes to source coding based on source polarization. The emergence of polar codes provides a new research direction for DJSCC.

[0004] The serial cancellation (SC) decoding of polar codes is a serial decoding scheme, so the SC decoder has a high latency problem. In order to solve the problem of high latency in polar code decoding, many scholars have conducted meaningful research on this issue. One direction is to start from the distribution characteristics of the information bits and frozen bits of polar codes. Different from the polar codes used for channel codes, the DJSCC based on polar codes aims to obtain high compression performance while having good error resistance. The difference in the transmitted codewords determines the difference in their decoding methods. Regarding how to reduce the time complexity of DJSCC decoding based on polar codes and the corresponding FPGA design scheme, no relevant research results have been published so far. Summary of the invention

[0005] The purpose of the present invention is to study a high-throughput polar code decoding scheme. The present invention utilizes the similarity of decoding iteration structure between polar codes under the DJSCC framework and traditional polar codes, and extends the Fast Simplified Successive Cancellation (Fast-SSC) decoding scheme of traditional polar codes to the DJSCC framework, supplementing the original 4-seed code decoding method of Fast-SSC decoding. Compared with the original SC decoding, the method of the present invention can effectively reduce the number of decoding iterations, thereby achieving the purpose of improving the decoding throughput.

[0006] For the convenience of explanation, the following concepts are introduced:

[0007] Distributed Joint Source-Channel Coding (DJSCC): DJSCC takes the channel conditions into consideration while performing distributed source coding (DSC).

[0008] Fast Simplified Successive Cancellation (Fast-SSC) decoding: Fast-SSC decoding is based on SC decoding. It divides the codewords of the polar code and decodes the subcodes of the polar code in parallel, thereby reducing the number of iteration layers of SC decoding.

[0009] Rate-0 code: a rate-0 code with a code length of N. All bits of this polar code subcode are frozen bits.

[0010] SPC (Single Parity Check) code: single-even parity check code, a polar code with a code length of N. Only the first bit u0 is a frozen bit, and the remaining bits u1 to u N-1 It is the information bit. The characteristic of this codeword is that the result of taking the sum of all bits modulo 2 is 0. If the verification result at the receiving end is 1, it means that there is an error in the transmission.

[0011] The basic idea of ​​the present invention is to use a specific combination of polar code frozen bits and information bits to form a new decoding method, divide the polar code into 4 subcodes, and the parallel decoding of the subcode nodes can reduce the number of decoding iterations, thereby achieving the purpose of improving decoding efficiency. Polar code-based DJSCC decoding can be divided into two processes. First, the side information and the companion formula obtained at the receiving end are used to perform SC decoding to recover the information lost by compression at the encoding end, and finally a polar code encoding is performed to reversely recover the source. The specific process steps include the following:

[0012] (1) Division of polar code subcodes: After the code length and code rate of the polar code are selected, the distribution of its frozen bits and information bits is determined accordingly. According to their distribution characteristics, the polar code codewords are divided into four subcodes, namely Rate-0 code, Rate-1 code, SPC-0 code and SPC-1 code. The code length, position and subcode type of each subcode are stored in the ROM memory for use in the decoding process.

[0013] (2) Polar code encoding: Polar code encoding is performed on a binary code sequence of length N, and the frozen bit set is taken as the compressed code word. The compressed code word and the related information source are transmitted to the receiving end through the channel for joint decoding. This is also the basic framework of DJSCC.

[0014] (3) Polar code iterative decoding: The process can be divided into two iterations in different directions, namely, the iteration of log-likelihood ratio from top to bottom and the iteration of intermediate bit value from bottom to top. The decoding process can be summarized as the iteration of log-likelihood ratio and the iteration of intermediate bit value. When performing the top-down log-likelihood ratio iterative operation, after iterating to the subcode node, different parallel decoding schemes are selected according to the subcode type.

[0015] (4) Rate-0 code decoding: Rate-0 code is the code rate zero, which is composed of frozen bits. In the DJSCC framework, the frozen bits are compressed code words. Different sources generate different Rate-0 code sequences, which are different from the original Rate-0 code, which is a fixed value. Therefore, the receiver needs to iterate the bit value from bottom to top according to the received syndrome, and finally obtain the estimated value of the Rate-0 code word;

[0016] (5) SPC code decoding: SPC code is a single-even parity check code. Only the first bit of the codeword is a frozen bit, and the rest are information bits. The SPC code under the DJSCC framework is expanded into SPC-0 code and SPC-1 code according to the actual value of the frozen bit, and the parity is divided into odd parity and even parity.

[0017] (6) Secondary polar code encoding: The decoding result of the Fast-SSC iteration needs to be encoded with a polar code to recover the information lost by compression. The combination of this result and the syndrome is the encoding result of the polar code at the transmitting end. After another polar code encoding, the signal source can be recovered, and the final decoding result is obtained.

[0018] Compared with the prior art, the present invention has the following beneficial effects:

[0019] (1) The iterative decoding process of the present invention is general to the iterative decoding process of SC decoding, and the algorithm proposed by the present invention can be used without modifying the overall decoding framework, while also ensuring that the application of the present invention does not lead to more resource consumption;

[0020] (2) The present invention proposes that the resources required for subcode parallel decoding can reuse the log-likelihood ratio iteration processing unit PE and the intermediate bit value iteration processing unit CE of the original decoding framework, thereby achieving the purpose of saving resources;

[0021] (3) The fast decoding scheme proposed in the present invention under the DJSCC framework greatly improves the decoding rate of polar codes under the DJSCC framework through parallel decoding of subcodes. At the same time, the decoding scheme proposed in the present invention ensures the robustness of the system, and almost does not lose the error-resistant performance while improving the decoding rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is the overall framework of the present invention.

[0023] Figure 2 It is the algorithm flow chart of the present invention.

[0024] Figure 3 This is a diagram of the BER performance comparison test results of the present invention.

[0025] Figure 4 This is a diagram showing the simulation time results of the improved Fast-SSC decoding in the present invention.

[0026] Figure 5 This is a graph showing the FPGA resource consumption results in the present invention. DETAILED DESCRIPTION

[0027] The present invention is further described in detail below in conjunction with the embodiments. It is necessary to point out that the following embodiments are only used to further illustrate the present invention and cannot be understood as limiting the scope of protection of the present invention. Technical personnel familiar with the relevant field may make some non-essential improvements and adjustments to the present invention according to the above invention content for specific implementation, which should still fall within the scope of protection of the present invention.

[0028] 1. Overall decoding framework and processing process

[0029] The decoding framework proposed by the present invention is as follows Figure 1 As shown, the decoding module stores the received side information and syndrome through RAM, and starts decoding after receiving the complete code segment. The processing unit PE iterates the log-likelihood ratio, and after iterating to a specific number of layers, selects the corresponding subcode decoding method according to the subnode type, and then iterates the intermediate bit value in the processing unit CE. The specific decoding process can be summarized as the following steps:

[0030] (1) Division of subcodes. After the code length and code rate of the polar code are selected, the distribution of the frozen bits and information bits is determined accordingly. According to the distribution characteristics, the codewords of the polar code are divided into four subcodes, namely Rate-0 code, Rate-1 code, SPC-0 code and SPC-1 code. The code length, position and subcode type of each subcode are stored in the ROM memory for use in the decoding process.

[0031] (2) Iterative decoding, the process can be divided into two iterations in different directions, namely, the iteration of the log-likelihood ratio from top to bottom and the iteration of the intermediate bit value from bottom to top. The decoding process can be summarized as first iterating the log-likelihood ratio and then iterating the intermediate bit value according to the situation. Decoding can be performed after the side information and the companion matrix of a complete code segment are input into the cache. When performing the top-down log-likelihood ratio iteration operation, after iterating to the subcode node, different parallel decoding schemes are selected according to the type of subcode;

[0032] (3) Polar code encoding: The iterative decoding result in step (2) needs to be encoded with polar code once to recover the compressed and lost information. Then, the sequence is combined with the syndrome, i.e., the encoding result of the polar code at the transmitting end. Finally, it is encoded with polar code once more to recover the source information.

[0033] 2. Rate-0 code decoding

[0034] The present invention proposes a polar code DJSCC fast decoding design method based on FPGA. The decoding of Rate-0 code is different from the Rate-0 code of the traditional polar code. The frozen bits of the polar code under the DJSCC framework are no longer fixed known sequences, but compressed code words, that is, the Rate-0 code sequences generated by different sources are also different, so additional iterative decoding is required. Based on the parallel characteristics of FPGA, the iteration of Rate-0 code can be independent of the log-likelihood ratio of the decoding process and the iteration of the intermediate bit value, and the resources of the intermediate bit value iteration operation unit can be reused. Therefore, the decoding of Rate-0 code under the DJSCC framework proposed by the present invention can also be decoded in parallel, and can achieve the purpose of improving the decoding throughput without increasing resource consumption.

[0035] 3.SPC code decoding

[0036] The present invention proposes a polar code DJSCC fast decoding design method based on FPGA. The SPC code has only one frozen bit located at the leftmost end of the codeword. In the DJSCC framework, the frozen bit is a compressed codeword. According to its actual value, its verification mode can be divided into odd verification and even verification. The SPC code with a frozen bit value of 0 is defined as the SPC-0 code, which satisfies the even verification. The SPC code with a frozen bit value of 1 is defined as the SPC-1 code, which satisfies the odd verification. The decoding principle of the two is: when the verification condition is not met, the bit value of the index position with the smallest absolute value of the log-likelihood ratio is inverted. The frozen bit position of the SPC-0 code is 0, which satisfies the even verification. The decoding method of SPC-0 code is the same as the original SPC code. The frozen bit of SPC-1 code is 1, which satisfies odd parity check. set up is the hard decision result of the LLR of the decoding subnode. The decision formula of SPC-1 code is

[0037]

[0038] When the SPC-0 or SPC-1 code verification condition is not met, it is necessary to address the index with the smallest absolute value of the log-likelihood ratio. The f function in the decoding iteration operation unit includes the comparison operation of the absolute value of the log-likelihood ratio. Therefore, by reusing the f function, the resource consumption of this type of subcode decoding method can be reduced. The f function is expressed as follows:

[0039] f(L1,L2)=sgn(L1)sgn(L2)min(|L1|,|L2|)

[0040] 4. Polarization code encoding

[0041] The decoding scheme proposed in the present invention includes two polar code encodings that do not overlap in time, and resource consumption can be reduced by reusing the same encoder. The encoding process of the polar code can be equivalent to the result of multiplying a binary sequence by a binary two-dimensional matrix and then taking the modulo 2. The polar code encoding matrices of different code lengths are unique. In the circuit design of FPGA, the present invention can fix the encoding matrix in the form of N N-dimensional wire-type vectors. These N vectors correspond to the N columns of the binary encoding matrix. When the sequence input by the encoder is operated with each column of the encoding matrix, the encoded bit sequence can be obtained. In the above-mentioned matrix multiplication operation process, the AND operation is used instead of the multiplication, and the XOR reduction operator is used instead of the summation and modulo 2 operation, and the encoding result is obtained within one clock cycle.

[0042] 5. Performance Testing

[0043] The present invention is a polar code DJSCC fast decoding design method based on FPGA. To verify the effectiveness of the present invention, the comparison process with the SC decoding algorithm under the same hardware framework is as follows:

[0044] (1) Error code performance test. In matlab, the code length is set to N = 256, the source cross probability is 0.01, and the compression rate is about 0.3. After the compression rate is determined, the codewords of the polarization code are delineated, and the side information generated by the source and the encoded codeword sequence are analyzed. The source compressed codewords are modulated by BPSK and passed through the AWGN channel. The receiving end adopts SC decoding and improved Fast-SSC decoding respectively. Figure 2 As shown in the figure, the error curves of the two algorithms are almost overlapped, which proves that the improved Fast-SSC decoding algorithm and the SC decoding algorithm have similar error resistance performance.

[0045] (2) Vivado functional verification simulation: To verify the correctness of the design function and the specific delay, the simulation uses the simulation tool provided by Vivado. Figure 3 The following table shows the minimum number of clocks consumed by the improved Fast-SSC decoding. The comparison of the decoding time consumed by the improved Fast-SSC decoding and SC decoding is shown in Table 1. It can be seen that under the framework of DJSCC, the improved Fast-SSC algorithm proposed in this paper has a higher throughput than the traditional SC decoding;

[0046] (3) VC707 comprehensive results. The quantization method of the log-likelihood ratio is fixed-point quantization, which is set to a 5-bit signed integer. According to the comprehensive results, on the VC707 hardware development platform, under the framework of similar decoding numbers, the resource consumption LUT and FF of the Fast-SSC decoder designed by the present invention is compared with the SC decoder, and the resource consumption growth is within a reasonable range;

[0047] On the VC707 hardware development platform, the Fast-SSC decoder designed by the present invention consumes LUT and FF resources, the number of clock cycles required for decoding, and the maximum clock frequency F m As shown in Table 1 below. To verify the effectiveness of the algorithm and design, Table 1 gives the relevant data of the SC decoding module under the same hardware framework. As can be seen from Table 1, under the framework of DJSCC, the improved Fast-SSC algorithm proposed in the present invention can obtain a higher throughput rate with a reasonable increase in resource consumption compared to traditional SC decoding.

[0048] Table 1 Comparison of implementation results of the scheme of the present invention and the SC decoding scheme

[0049] Decoding algorithm LUT FF Fmax / MHz Number of clocks SC 7693 3529 134 1016 Fast-SSC 10531 5116 113 185

[0050] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A polar code DJSCC fast decoding design method based on FPGA, characterized by The main process steps include: (1) Division of polar code subcodes: After the code length and code rate of the polar code are selected, the distribution of its frozen bits and information bits is determined accordingly. According to their distribution characteristics, the polar code codewords are divided into four subcodes, namely Rate-0 code, Rate-1 code, SPC-0 code and SPC-1 code. The code length, position and subcode type of each subcode are stored in the ROM memory for use in the decoding process. (2) Polar code encoding: Polar code encoding is performed on a binary code sequence of length N, and the frozen bit set is taken as the compressed code word. The compressed code word and the related source are transmitted to the receiving end through the channel for joint decoding. This is also the basic framework of Distributed Joint Source-Channel Coding (DJSCC). (3) Polar code iterative decoding: The process can be divided into two iterations in different directions, namely, the iteration of log-likelihood ratio from top to bottom and the iteration of intermediate bit value from bottom to top. The decoding process can be summarized as the iteration of log-likelihood ratio and the iteration of intermediate bit value. When performing the top-down log-likelihood ratio iterative operation, after iterating to the subcode node, different parallel decoding schemes are selected according to the subcode type. (4) Rate-0 code decoding: Rate-0 code is a code with a rate of zero, which is composed of frozen bits. In the framework of Distributed Joint Source-Channel Coding (DJSCC), the frozen bits are compressed code words. Different sources generate different Rate-0 code sequences, which are different from the original Rate-0 code with a fixed value. Therefore, the receiver needs to iterate the bit value from bottom to top according to the received syndrome, and finally obtain the estimated value of the Rate-0 code word. (5) SPC code decoding: SPC code is a single-even parity check code. Only the first bit of the codeword is a frozen bit, and the rest are information bits. The SPC code under the DJSCC framework is expanded into SPC-0 code and SPC-1 code according to the actual value of the frozen bit, and the parity is divided into odd parity and even parity. (6) Secondary polar code encoding: The decoding result of the Fast Simplified Successive Cancellation (Fast-SSC) iteration needs to be encoded with polar code once to recover the information lost by compression. The combination of this result and the syndrome is the encoding result of the polar code at the transmitting end. After another polar code encoding, the source can be recovered, and the final decoding result is obtained.

2. A polar code DJSCC fast decoding design method based on FPGA as described in claim 1, characterized in that The Rate-0 code composition and its decoding scheme in step (4) are composed of frozen bits. The codeword sequence of the Rate-0 code under the DJSCC framework is an uncertain value. The frozen bits are the codewords after encoding and compression. The Rate-0 code needs to be additionally iterated and decoded. Based on the parallel characteristics of FPGA, the iteration of the Rate-0 subcode can be independent of the log-likelihood ratio of the decoding process and the iteration of the intermediate bit value. At the same time, by reusing the resources of the intermediate bit value iteration operation unit, the subcode can improve the decoding efficiency without increasing resource consumption.

3. A polar code DJSCC fast decoding design method based on FPGA as described in claim 1, characterized in that The expansion of the SPC code in step (5) and its decoding scheme, the SPC code has only the leftmost bit as a frozen bit. In the DJSCC framework, the frozen bit is a compressed codeword. According to its actual value, its check mode can be divided into odd check and even check. The SPC code with a frozen bit value of 0 is defined as an SPC-0 code that needs to meet the even check, and the SPC code with a frozen bit value of 1 is defined as an SPC-1 code that needs to meet the odd check. The decoding principle of the two is: when the SPC-0 or SPC-1 code check condition is not met, it is necessary to address the index with the smallest absolute value of the log-likelihood ratio and invert the bit value. The f function in the decoding iteration operation unit includes a comparison operation of the absolute value of the log-likelihood ratio. Therefore, by reusing the f function, the resource consumption of this type of subcode decoding method can be reduced.

4. A polar code DJSCC fast decoding design method based on FPGA as described in claim 1, characterized in that In the secondary polar code encoding and the corresponding encoder design scheme in step (6), the two polar code encodings are non-overlapping in time, and the resource consumption is reduced by reusing the same encoder. In the circuit design of the FPGA of the present invention, the encoding matrix is ​​fixed in the form of N N-dimensional wire-type vectors, where N is the code length, and the N vectors correspond to N columns of the binary encoding matrix. When the sequence input by the encoder is operated with each column of the encoding matrix, the encoded bit sequence can be obtained. At the same time, in the above-mentioned matrix multiplication operation process, the AND operation is used instead of the multiplication, and the XOR reduction operator is used instead of the summation and the modulo 2 operation, so that the encoding result is obtained within one clock cycle.

5. A design method for fast decoding of polar codes DJSCC based on FPGA for executing claims 1 to 4.

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