Field stop type IGBT (Insulated Gate Bipolar Translator) device and manufacturing method thereof

Abstract

The invention discloses a field stop type IGBT (Insulated Gate Bipolar Translator) device and a manufacturing method thereof. The device comprises a semiconductor substrate; the first surface of the semiconductor substrate comprises a first drift region; the second surface of the semiconductor substrate comprises a collector region; the semiconductor substrate further comprises a buffer region which is located on one side, far away from the second surface, of the collector region; the semiconductor substrate between the first drift region and the buffer region is multiplexed as a second drift region; the resistivity of the first drift region is greater than that of the second drift region, and the resistivity of the second drift region is greater than that of the buffer region; the epitaxial layer is located on the first surface of the semiconductor substrate; the third surface of the epitaxial layer comprises an emitter region; the fourth surface of the epitaxial layer comprises a base region; and the gate structure is located on the third surface of the epitaxial layer or extends from the third surface into the emitter region. According to the technical scheme provided by the embodiment of the invention, the drop amplitude of the electric field from the drift region to the buffer region is effectively reduced, so that the switching oscillation of the field stop type IGBT device is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a field stop IGBT device and a manufacturing method thereof. Background Art

[0002] The field-stop insulated gate bipolar transistor (FS-IGBT) device has a buffer layer between the drift region and the collector region to obtain better switching characteristics.

[0003] When the switching speed of the existing FS-IGBT device is fast, the electric field drop from the drift region to the buffer region is too large, which causes the switching oscillation of the FS-IGBT device to be more serious. Summary of the invention

[0004] The present invention provides a field stop IGBT device and a manufacturing method thereof, so as to effectively reduce the electric field drop from a drift region to a buffer region, thereby reducing the switching oscillation of the field stop IGBT device.

[0005] A field stop IGBT device according to the present invention comprises:

[0006] A semiconductor substrate, which is set to a first conductivity type; the semiconductor substrate comprises a first surface and a second surface which are arranged opposite to each other;

[0007] The first surface of the semiconductor substrate includes a first drift region, which is set to a first conductivity type; the second surface of the semiconductor substrate includes a collector region, which is set to a second conductivity type; the semiconductor substrate also includes a buffer region, which is set to the first conductivity type, and the buffer region is located on a side of the collector region away from the second surface; the semiconductor substrate between the first drift region and the buffer region is reused as a second drift region; the resistivity of the first drift region is greater than the resistivity of the second drift region, and the resistivity of the second drift region is greater than the resistivity of the buffer region;

[0008] an epitaxial layer, the epitaxial layer being located on the first surface of the semiconductor substrate and being set to be of the first conductivity type; the epitaxial layer comprising a third surface and a fourth surface that are arranged opposite to each other; the fourth surface of the epitaxial layer being in contact with the first surface of the semiconductor substrate;

[0009] The third surface of the epitaxial layer includes an emitter region; the fourth surface of the epitaxial layer includes a base region, the base region is set to be of the second conductivity type, and the emitter region and the base region are adjacently arranged;

[0010] A gate structure, located on a third surface of the epitaxial layer or extending from the third surface into the emitter region;

[0011] An emitter, located at a side of the epitaxial layer away from the semiconductor substrate;

[0012] The collector is located on the second surface of the semiconductor substrate.

[0013] Optionally, the gate structure extends from the third surface into the first drift region.

[0014] Optionally, when the first conductivity type is N-type, the first drift region is an N-- doped region;

[0015] The second drift region is an N- semiconductor substrate;

[0016] The buffer zone is an N-type buffer zone.

[0017] Optionally, the gate structure extends from the third surface into the emitter region, the field stop type IGBT device comprises a plurality of field stop type IGBT units, and emitters of the plurality of field stop type IGBT units are connected;

[0018] The emitters of part or all of the field stop IGBT units extend from the third surface of the epitaxial layer through the emitter region into the base region.

[0019] Optionally, the gate structure includes a gate oxide layer and a polysilicon layer; and / or,

[0020] An interlayer insulating layer is also included, which is located between the emitter and the gate structure.

[0021] According to another aspect of the present invention, there is provided a method for manufacturing a field stop IGBT device, comprising:

[0022] Providing a semiconductor substrate, wherein the semiconductor substrate is set to a first conductivity type and includes a first surface and a second surface arranged opposite to each other;

[0023] forming a first drift region on a first surface of the semiconductor substrate, wherein the first drift region is set to be of a first conductivity type;

[0024] An epitaxial layer is formed on the first surface of the semiconductor substrate, wherein the epitaxial layer is set to be of a first conductivity type; the epitaxial layer includes a third surface and a fourth surface that are arranged opposite to each other; and the fourth surface of the epitaxial layer is in contact with the first surface of the semiconductor substrate;

[0025] forming a gate structure on a third surface of the epitaxial layer;

[0026] A base region and an emitter region are formed in the epitaxial layer, the emitter region is located on the third surface, the base region is located on the fourth surface, the base region is set to be of the second conductivity type, and the emitter region and the base region are adjacently arranged; the gate structure is located on the third surface of the epitaxial layer or extends from the third surface to the emitter region;

[0027] forming an emitter on a side of the epitaxial layer away from the semiconductor substrate;

[0028] A collector region and a buffer region are formed on the second surface of the semiconductor substrate; the collector region is set to be of the second conductivity type and is located on the second surface; the buffer region is set to be of the first conductivity type and is located on a side of the collector region away from the second surface; the semiconductor substrate between the first drift region and the buffer region is reused as a second drift region; the resistivity of the first drift region is greater than the resistivity of the second drift region, and the resistivity of the second drift region is greater than the resistivity of the buffer region;

[0029] A collector electrode is formed on the second surface of the semiconductor substrate.

[0030] Optionally, forming a gate structure on the third surface of the epitaxial layer includes:

[0031] A gate structure is formed on the third surface of the epitaxial layer, extending from the third surface into the first drift region.

[0032] Optionally, when the first conductivity type is N-type, the first drift region is an N-- doped region;

[0033] The second drift region is an N- semiconductor substrate;

[0034] The buffer zone is an N-type buffer zone.

[0035] Optionally, forming a first drift region on the first surface of the semiconductor substrate includes:

[0036] A second conductive type ion implantation and an annealing process are performed on the first surface of the semiconductor substrate to form a first drift region on the first surface of the semiconductor substrate.

[0037] Optionally, forming a base region and an emitter region in the epitaxial layer includes:

[0038] A base region and an emitter region are formed in the epitaxial layer by an ion implantation process.

[0039] In the field stop IGBT device and manufacturing method provided by the embodiment of the present invention, the semiconductor substrate between the first drift region and the buffer region is reused as the second drift region, the resistivity of the first drift region is greater than the resistivity of the second drift region, and the resistivity of the second drift region is greater than the resistivity of the buffer region, so that the electric field strength of the first drift region is greater than the electric field strength of the second drift region, and the electric field strength of the second drift region is greater than the electric field strength of the buffer region. In the FS-IGBT device, the decrease in the electric field strength from the first drift region, the second drift region to the buffer region is gradually reduced, thereby effectively reducing the electric field drop of the FS-IGBT device from the drift region to the buffer region, thereby reducing the switching oscillation of the field stop IGBT device. In addition, the emitter region and the base region are located in the epitaxial layer, which improves the quality of the emitter region and the base region, reduces internal defects, thereby improving the switching speed of the device and reducing the switching loss.

[0040] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0042] Figure 1 It is a structural schematic diagram of a field stop IGBT device provided by an embodiment of the present invention;

[0043] Figure 2 yes Figure 1 Schematic diagram of the change of electric field intensity in the first drift region, the second drift region and the buffer zone;

[0044] Figure 3 is a flow chart of a method for manufacturing a field stop IGBT device provided by an embodiment of the present invention;

[0045] Figure 4-Figure 11 yes Figure 3 Schematic diagram of the structure corresponding to each relevant step in . DETAILED DESCRIPTION

[0046] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solution in the embodiment of the present invention will be described clearly and completely in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0047] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or devices is not necessarily limited to those steps or devices that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0048] In order to effectively reduce the electric field drop from the drift region to the buffer region of the FS-IGBT device, thereby reducing the switching oscillation of the field stop IGBT device, the embodiment of the present invention provides the following technical solutions:

[0049] like Figure 1 As shown, Figure 11 is a schematic structural diagram of a field-stop IGBT device provided by an embodiment of the present invention, wherein the field-stop IGBT device comprises: a semiconductor substrate 100, which is set to a first conductivity type; the semiconductor substrate 100 comprises a first surface 101 and a second surface 102 which are arranged opposite to each other; the first surface 101 of the semiconductor substrate 100 comprises a first drift region 103, which is set to the first conductivity type; the second surface 102 of the semiconductor substrate 100 comprises a collector region 104, which is set to the second conductivity type; the semiconductor substrate 100 further comprises a buffer region 105, which is set to the first conductivity type, and the buffer region 105 is located on a side of the collector region 104 away from the second surface 102; the semiconductor substrate 100 between the first drift region 103 and the buffer region 105 is reused as a second drift region 106, which is set to the first conductivity type; the resistivity of the first drift region 103 is greater than that of the second drift region 106 The resistivity of the second drift region 106 is greater than the resistivity of the buffer region 105; the epitaxial layer 200, the epitaxial layer 200 is located on the first surface 101 of the semiconductor substrate 100 and is set to the first conductivity type; the epitaxial layer 200 includes a third surface 201 and a fourth surface 202 that are relatively set; the fourth surface 202 of the epitaxial layer 200 is in contact with the first surface 101 of the semiconductor substrate 100; the third surface 201 of the epitaxial layer 200 includes an emitter region 203; the fourth surface 202 of the epitaxial layer 200 includes a base region 204, the base region 204 is set to the second conductivity type, and the emitter region 203 and the base region 204 are adjacently arranged; the gate structure 300, located on the third surface 201 of the epitaxial layer 200 or extending from the third surface 201 to the emitter region 203; the emitter 400, located on the side of the epitaxial layer 200 away from the semiconductor substrate 100; the collector 500, located on the second surface 102 of the semiconductor substrate 100.

[0050] In order to comprehensively consider the on-resistance and withstand voltage of the field-stop IGBT device, the resistivity of the drift region in the existing FS-IGBT device is uniform, and the difference in resistivity of the drift region in contact with the buffer zone is too large, resulting in an excessively large drop in the electric field from the drift region to the buffer zone of the field-stop IGBT device, thereby causing more severe switching oscillations of the field-stop IGBT device.

[0051] In an embodiment of the present invention, the first conductivity type is N type, and the second conductivity type is P type. Alternatively, the first conductivity type is P type, and the second conductivity type is N type.

[0052] like Figure 2 As shown, Figure 2 yes Figure 1Schematic diagram of the change of electric field strength in the first drift region, the second drift region and the buffer region, the electric field strength of the first drift region 103 is greater than the electric field strength of the second drift region 106, and the electric field strength of the second drift region 106 is greater than the electric field strength of the buffer region 105. It should be noted that, Figure 2 The electric field strength of the first drift region 103 is the electric field strength at the contact surface between the first drift region 103 and the second drift region 106 .

[0053] According to the technical solution provided by the embodiment of the present invention, the semiconductor substrate 100 between the first drift region 103 and the buffer region 105 is reused as the second drift region 106, the resistivity of the first drift region 103 is greater than the resistivity of the second drift region 106, and the resistivity of the second drift region 106 is greater than the resistivity of the buffer region 105, so that the electric field strength of the first drift region 103 is greater than the electric field strength of the second drift region 106, and the electric field strength of the second drift region 106 is greater than the electric field strength of the buffer region 105. In the FS-IGBT device, the decrease in electric field strength from the first drift region 103, the second drift region 106 to the buffer region 105 is gradually reduced, thereby effectively reducing the electric field drop of the FS-IGBT device from the drift region to the buffer region, and further reducing the switching oscillation of the field-stop IGBT device. Furthermore, the emitter region 203 and the base region 204 are located in the epitaxial layer 200 , which improves the quality of the emitter region 203 and the base region 204 and reduces internal defects, thereby increasing the switching speed of the device and reducing the switching loss.

[0054] Optionally, based on the above technical solution, Figure 1 As shown, the gate structure 300 extends from the third surface 201 into the first drift region 103 .

[0055] Specifically, the gate structure 300 extends from the third surface 201 into the first drift region 103, realizing a vertical channel structure, eliminating the JFET effect, increasing the channel density and near-surface carrier density, thereby reducing the on-state voltage drop and enhancing the anti-latch capability.

[0056] Optionally, based on the above technical solution, when the first conductivity type is N-type, the first drift region 103 is an N- doped region; the second drift region 106 is an N- semiconductor substrate; and the buffer region 105 is an N-type buffer region.

[0057] Specifically, the resistivity of the N-- doped region is greater than the resistivity of the N-- semiconductor substrate, and the resistivity of the N-- semiconductor substrate is greater than the resistivity of the N--type buffer region, so that the electric field strength of the first drift region 103 is greater than the electric field strength of the second drift region 106, and the electric field strength of the second drift region 106 is greater than the electric field strength of the buffer region 105. In the FS-IGBT device, the decrease in electric field strength from the first drift region 103, the second drift region 106 to the buffer region 105 is gradually reduced, thereby effectively reducing the electric field drop of the FS-IGBT device from the drift region to the buffer region, and further reducing the switching oscillation of the field-stop IGBT device.

[0058] Optionally, based on the above technical solution, Figure 1 As shown, the gate structure 300 extends from the third surface 201 to the emitter region 203, and the FS-IGBT device includes a plurality of field-stop IGBT units, and the emitters 400 of the plurality of field-stop IGBT units are connected; the emitters 400 of some or all of the field-stop IGBT units extend from the third surface 201 of the epitaxial layer 200 through the emitter region 203 to the base region 204.

[0059] Specifically, when the gate structure 300 is a trench structure, that is, the gate structure 300 extends from the third surface 201 to the emitter region 203, the emitter 400 extends from the third surface 201 of the epitaxial layer 200 through the emitter region 203 to the base region 204, which can effectively alleviate the electric field distribution under the trench gate structure 300.

[0060] It should be noted that, in other optional embodiments, for the planar gate structure 300 , the FS-IGBT device may also include a plurality of field stop IGBT units.

[0061] Optionally, based on the above technical solution, Figure 1 As shown, the gate structure 300 includes a gate oxide layer 301 and a polysilicon layer 302 ; and / or, further includes an interlayer insulating layer 600 located between the emitter 400 and the gate structure 300 .

[0062] Specifically, the gate oxide layer 301 is used to insulate the polysilicon layer 302 and the epitaxial layer 200. The interlayer insulating layer 600 is located between the emitter 400 and the gate structure 300 and is used to insulate the emitter 400 and the gate structure 300.

[0063] The embodiment of the present invention also provides a method for manufacturing a field stop IGBT device. Figure 3 As shown, Figure 3 1 is a flow chart of a method for manufacturing a field stop type IGBT device provided by an embodiment of the present invention. The method for manufacturing a field stop type IGBT device comprises the following steps:

[0064] S110 , providing a semiconductor substrate, wherein the semiconductor substrate is set to be of a first conductivity type and includes a first surface and a second surface that are oppositely arranged.

[0065] like Figure 4 As shown, a semiconductor substrate 100 is provided. The semiconductor substrate 100 is set to a first conductivity type and includes a first surface 101 and a second surface 102 that are oppositely arranged.

[0066] In an embodiment of the present invention, the first conductivity type is N type, and the second conductivity type is P type. Alternatively, the first conductivity type is P type, and the second conductivity type is N type.

[0067] S120 , forming a first drift region on the first surface of the semiconductor substrate, wherein the first drift region is set to be of a first conductivity type.

[0068] The process of forming the first drift region 103 on the first surface 101 of the semiconductor substrate 100 is as follows:

[0069] like Figure 5 As shown, at least one second conductivity type ion implantation and annealing process is performed on the first surface 101 of the semiconductor substrate 100. When the first conductivity type is N type, P type ion implantation and annealing process is performed on the first surface 101 of the semiconductor substrate 100.

[0070] like Figure 6 As shown, a first drift region 103 is formed on a first surface 101 of a semiconductor substrate 100. The first drift region 103 is set to be of a first conductivity type.

[0071] S130, forming an epitaxial layer on the first surface of the semiconductor substrate, wherein the epitaxial layer is set to a first conductivity type; the epitaxial layer includes a third surface and a fourth surface that are oppositely arranged; and the fourth surface of the epitaxial layer is in contact with the first surface of the semiconductor substrate.

[0072] like Figure 7 As shown, an epitaxial layer 200 is formed on the first surface 101 of the semiconductor substrate 100 by an epitaxial process, and the epitaxial layer 200 is set to a first conductivity type; the epitaxial layer 200 includes a third surface 201 and a fourth surface 202 that are relatively set; the fourth surface 202 of the epitaxial layer 200 is in contact with the first surface 101 of the semiconductor substrate 100.

[0073] S140, forming a gate structure on the third surface of the epitaxial layer.

[0074] The process of forming the gate structure 300 on the third surface 201 of the epitaxial layer 200 is as follows:

[0075] like Figure 8As shown, taking the gate structure 300 as a trench gate structure as an example, a trench T1 is formed on the third surface 201 of the epitaxial layer 200. Exemplarily, the depth of the trench T1 is greater than the thickness of the epitaxial layer 200.

[0076] like Fig. 9 As shown, a gate oxide layer 301 and a polysilicon layer 302 are sequentially formed in the trench T1 , and the gate oxide layer 301 is used to insulate the polysilicon layer 302 and the epitaxial layer 200 .

[0077] S150, forming a base region and an emitter region in the epitaxial layer, the emitter region is located on the third surface, the base region is located on the fourth surface, the base region is set to the second conductivity type, and the emitter region and the base region are adjacent to each other; the gate structure is located on the third surface of the epitaxial layer or extends from the third surface to the emitter region.

[0078] like Fig.10 As shown, a base region 204 and an emitter region 203 are formed in the epitaxial layer 200 by an ion implantation process, the emitter region 203 is located on the third surface 201, the base region 204 is located on the fourth surface 202, the base region 204 is set to the second conductivity type, and the emitter region 203 and the base region 204 are adjacently arranged; the gate structure 300 is located on the third surface 201 of the epitaxial layer 200 or extends from the third surface 201 to the emitter region 203. Exemplarily, Fig.10 In the embodiment, the gate structure 300 extends from the third surface 201 to the emitter region 203 .

[0079] S160, forming an emitter on a side of the epitaxial layer away from the semiconductor substrate.

[0080] like Fig.11 As shown, an emitter 400 is formed on a side of the epitaxial layer 200 away from the semiconductor substrate 100. Optionally, based on the above technical solution, before forming the emitter 400, an interlayer insulating layer 600 is formed. The interlayer insulating layer 600 is located between the emitter 400 and the gate structure 300 to insulate the emitter 400 from the gate structure 300.

[0081] Optionally, the gate structure 300 extends from the third surface 201 to the emitter region 203, and the FS-IGBT device includes multiple field-stop IGBT units, and the emitters 400 of the multiple field-stop IGBT units are connected; the emitters 400 of some or all of the field-stop IGBT units extend from the third surface 201 of the epitaxial layer 200 through the emitter region 203 to the base region 204.

[0082] Specifically, when the gate structure 300 is a trench structure, that is, the gate structure 300 extends from the third surface 201 to the emitter region 203, the emitter 400 extends from the third surface 201 of the epitaxial layer 200 through the emitter region 203 to the base region 204, which can effectively alleviate the electric field distribution under the trench gate structure 300.

[0083] It should be noted that, in other optional embodiments, for the planar gate structure 300 , the FS-IGBT device may also include a plurality of field stop IGBT units.

[0084] S170. A collector region and a buffer region are formed on the second surface of the semiconductor substrate; the collector region is set to the second conductivity type and is located on the second surface; the buffer region is set to the first conductivity type and is located on the side of the collector region away from the second surface; the semiconductor substrate between the first drift region and the buffer region is reused as the second drift region; the resistivity of the first drift region is greater than the resistivity of the second drift region, and the resistivity of the second drift region is greater than the resistivity of the buffer region.

[0085] like Fig.11 As shown, a collector region 104 and a buffer region 105 are formed on the second surface 102 of the semiconductor substrate 100 by an ion implantation process; the collector region 104 is set to the second conductivity type and is located on the second surface 102; the buffer region 105 is set to the first conductivity type and is located on the side of the collector region 104 away from the second surface 102; the semiconductor substrate 100 between the first drift region 103 and the buffer region 105 is reused as the second drift region 106; the resistivity of the first drift region 103 is greater than the resistivity of the second drift region 106, and the resistivity of the second drift region 106 is greater than the resistivity of the buffer region 105.

[0086] S180, forming a collector electrode on the second surface of the semiconductor substrate.

[0087] like Figure 1 As shown, a collector electrode 500 is formed on the second surface 102 of the semiconductor substrate 100 .

[0088] According to the technical solution provided by the embodiment of the present invention, the semiconductor substrate 100 between the first drift region 103 and the buffer region 105 is reused as the second drift region 106, the resistivity of the first drift region 103 is greater than the resistivity of the second drift region 106, and the resistivity of the second drift region 106 is greater than the resistivity of the buffer region 105, so that the electric field strength of the first drift region 103 is greater than the electric field strength of the second drift region 106, and the electric field strength of the second drift region 106 is greater than the electric field strength of the buffer region 105. In the FS-IGBT device, the decrease in electric field strength from the first drift region 103, the second drift region 106 to the buffer region 105 is gradually reduced, thereby effectively reducing the electric field drop of the FS-IGBT device from the drift region to the buffer region, and further reducing the switching oscillation of the field-stop IGBT device. Furthermore, the emitter region 203 and the base region 204 are located in the epitaxial layer 200 , which improves the quality of the emitter region 203 and the base region 204 and reduces internal defects, thereby increasing the switching speed of the device and reducing the switching loss.

[0089] Optionally, based on the above technical solution, S140 forming a gate structure on the third surface of the epitaxial layer includes:

[0090] A gate structure extending from the third surface to the first drift region is formed on the third surface of the epitaxial layer.

[0091] like Fig.10 As shown, a gate structure 300 is formed on the third surface 201 of the epitaxial layer 200 and extends from the third surface 201 into the first drift region 103 .

[0092] Specifically, the gate structure 300 extends from the third surface 201 into the first drift region 103, realizing a vertical channel structure, eliminating the JFET effect, increasing the channel density and near-surface carrier density, thereby reducing the on-state voltage drop and enhancing the anti-latch capability.

[0093] Optionally, based on the above technical solution, when the first conductivity type is N-type, the first drift region is an N- doped region; the second drift region is an N- semiconductor substrate; and the buffer region is an N-type buffer region.

[0094] Specifically, the resistivity of the N-- doped region is greater than the resistivity of the N-- semiconductor substrate, and the resistivity of the N-- semiconductor substrate is greater than the resistivity of the N--type buffer region, so that the electric field strength of the first drift region 103 is greater than the electric field strength of the second drift region 106, and the electric field strength of the second drift region 106 is greater than the electric field strength of the buffer region 105. In the FS-IGBT device, the decrease in electric field strength from the first drift region 103, the second drift region 106 to the buffer region 105 is gradually reduced, thereby effectively reducing the electric field drop of the FS-IGBT device from the drift region to the buffer region, and further reducing the switching oscillation of the field-stop IGBT device.

[0095] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0096] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A field stop IGBT device, characterized in that: include: A semiconductor substrate, which is set to a first conductivity type; the semiconductor substrate comprises a first surface and a second surface which are arranged opposite to each other; The first surface of the semiconductor substrate includes a first drift region, which is set to a first conductivity type; the second surface of the semiconductor substrate includes a collector region, which is set to a second conductivity type; the semiconductor substrate also includes a buffer region, which is set to the first conductivity type, and the buffer region is located on a side of the collector region away from the second surface; the semiconductor substrate between the first drift region and the buffer region is reused as a second drift region; the resistivity of the first drift region is greater than the resistivity of the second drift region, and the resistivity of the second drift region is greater than the resistivity of the buffer region; an epitaxial layer, the epitaxial layer being located on the first surface of the semiconductor substrate and being set to be of the first conductivity type; the epitaxial layer comprising a third surface and a fourth surface that are arranged opposite to each other; the fourth surface of the epitaxial layer being in contact with the first surface of the semiconductor substrate; The third surface of the epitaxial layer includes an emitter region; the fourth surface of the epitaxial layer includes a base region, the base region is set to be of the second conductivity type, and the emitter region and the base region are adjacently arranged; A gate structure, located on a third surface of the epitaxial layer or extending from the third surface into the emitter region; An emitter, located at a side of the epitaxial layer away from the semiconductor substrate; The collector is located on the second surface of the semiconductor substrate.

2. The field stop IGBT device according to claim 1, characterized in that: The gate structure extends from the third surface into the first drift region.

3. The field stop IGBT device according to claim 1, characterized in that: When the first conductivity type is N-type, the first drift region is an N-- doped region; The second drift region is an N- semiconductor substrate; The buffer zone is an N-type buffer zone.

4. The field stop IGBT device according to claim 1, characterized in that: The gate structure extends from the third surface into the emitter region, the field stop type IGBT device comprises a plurality of field stop type IGBT units, and the emitters of the plurality of field stop type IGBT units are connected; The emitters of part or all of the field stop IGBT units extend from the third surface of the epitaxial layer through the emitter region into the base region.

5. The field stop IGBT device according to claim 1, characterized in that: The gate structure includes a gate oxide layer and a polysilicon layer; and / or, An interlayer insulating layer is also included, which is located between the emitter and the gate structure.

6. A method for manufacturing a field stop IGBT device, characterized in that: include: Providing a semiconductor substrate, wherein the semiconductor substrate is set to a first conductivity type and includes a first surface and a second surface arranged opposite to each other; forming a first drift region on a first surface of the semiconductor substrate, wherein the first drift region is set to be of a first conductivity type; An epitaxial layer is formed on the first surface of the semiconductor substrate, wherein the epitaxial layer is set to be of a first conductivity type; the epitaxial layer includes a third surface and a fourth surface that are arranged opposite to each other; and the fourth surface of the epitaxial layer is in contact with the first surface of the semiconductor substrate; forming a gate structure on a third surface of the epitaxial layer; A base region and an emitter region are formed in the epitaxial layer, the emitter region is located on the third surface, the base region is located on the fourth surface, the base region is set to be of the second conductivity type, and the emitter region and the base region are adjacently arranged; the gate structure is located on the third surface of the epitaxial layer or extends from the third surface to the emitter region; forming an emitter on a side of the epitaxial layer away from the semiconductor substrate; A collector region and a buffer region are formed on the second surface of the semiconductor substrate; the collector region is set to be of the second conductivity type and is located on the second surface; the buffer region is set to be of the first conductivity type and is located on a side of the collector region away from the second surface; the semiconductor substrate between the first drift region and the buffer region is reused as a second drift region; the resistivity of the first drift region is greater than the resistivity of the second drift region, and the resistivity of the second drift region is greater than the resistivity of the buffer region; A collector electrode is formed on the second surface of the semiconductor substrate.

7. The method for manufacturing a field stop IGBT device according to claim 6, characterized in that: Forming a gate structure on the third surface of the epitaxial layer includes: A gate structure is formed on the third surface of the epitaxial layer, extending from the third surface into the first drift region.

8. The method for manufacturing a field stop IGBT device according to claim 6, characterized in that: When the first conductivity type is N-type, the first drift region is an N-- doped region; The second drift region is an N- semiconductor substrate; The buffer zone is an N-type buffer zone.

9. The method for manufacturing a field stop IGBT device according to claim 6, characterized in that: Forming a first drift region on the first surface of the semiconductor substrate includes: A second conductive type ion implantation and an annealing process are performed on the first surface of the semiconductor substrate to form a first drift region on the first surface of the semiconductor substrate.

10. The method for manufacturing a field stop IGBT device according to claim 6, characterized in that: Forming a base region and an emitter region in the epitaxial layer includes: A base region and an emitter region are formed in the epitaxial layer by an ion implantation process.

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