Shield gate groove type MOSFET device and manufacturing method thereof
By setting up gate polysilicon with concave notch structure and source polysilicon with lead holes in shielded gate trench MOSFET devices, the production capacity limitation and cost increase caused by the increase in polysilicon deposition thickness is solved, the GS capacitance value of the device is reduced, and the optimization of the Dynamic parameters.
Patent Information
- Application Number
- CN202411576432.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-06
- Publication Date
- 2025-02-18
AI Technical Summary
In the production process of existing shielded gate trench MOSFET devices, the increase in polysilicon deposition thickness leads to capacity limitations and cost increases. At the same time, the GS capacitance value of the device is relatively high, affecting dynamic parameters.
By setting the gate polysilicon into a concave notch structure, the GS capacitance value is reduced, and the lead-out hole is formed on the source polysilicon, which is directly drawn from the active area, saving chip area and simplifying the production process.
It realizes reducing the GS capacitance value of the device, saving polysilicon deposition capacity, reducing manufacturing costs, and optimizing device dynamic parameters.
Smart Images
Figure CN119486177A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of semiconductors, and in particular relates to a shielded gate trench MOSFET device and a manufacturing method thereof. Background Art
[0002] Shielded Gate Trench Power MOSFET, referred to as SGT-MOS, is an abbreviation of Split Gate Trench-MOSFET. The SGT-MOS series products adopt the shielded gate trench (Split Gate Trench) technology with charge balancing function, which comprehensively improves the switching characteristics and conduction characteristics of the device, while reducing the characteristic on-resistance (Rsp) and gate charge (Qg) of the device.
[0003] Compared with conventional Trench and Planner MOS, the electric field of SGT-MOS is more concentrated. The higher the withstand voltage, the stronger the electric field. In order to withstand the electric field, the thickness of the field oxide layer (FOX) increases with the increase of voltage. As the thickness of the field oxide layer increases, the width of the trench also increases, resulting in an increase in the filling thickness of the gate polysilicon (gate poly).
[0004] The increase in the filling thickness of the gate poly will seriously limit the production capacity of polysilicon deposition (poly dep) in the manufacturing process and greatly increase the cost.
[0005] In order to improve the above problems, this case proposes a shielded gate trench MOSFET device and a manufacturing method thereof, which can not only save poly dep production capacity and reduce costs, but also further reduce the GS capacitance value (Cgs) of the device and optimize the dynamic parameters of the device. Summary of the invention
[0006] In view of this, the object of the present invention is to provide a shielded gate trench MOSFET device and a method for manufacturing the same, in which the gate polysilicon is set into a concave notch structure, thereby reducing the GS capacitance value of the device, and by setting a source lead-out hole, the source polysilicon can be directly led out from the active area without the need to set up a separate area lead-out, thereby saving chip area.
[0007] To achieve the above object, the present invention provides a method for manufacturing a shielded gate trench MOSFET device, comprising the following steps:
[0008] Providing an epitaxial layer, and disposing a barrier layer on the epitaxial layer;
[0009] Etching the epitaxial layer and the barrier layer to form a groove;
[0010] forming a field oxide layer inside the trench;
[0011] Depositing polysilicon inside the trench, and etching the field oxide layer and the polysilicon to form source polysilicon;
[0012] forming an isolation oxide layer on the source polysilicon;
[0013] forming a gate oxide layer on the sidewall of the trench above the isolation oxide layer;
[0014] Depositing polysilicon on the isolation oxide layer and in the gate oxide layer, and etching to form gate polysilicon, wherein the gate polysilicon is a concave notch structure;
[0015] Performing ion implantation in the epitaxial layer to form a body region and a well region;
[0016] Deposition is performed on the epitaxial layer to form an insulating dielectric layer;
[0017] The insulating dielectric layer is etched to form a source lead-out hole, wherein the source lead-out hole penetrates the insulating dielectric layer and extends into the source polysilicon.
[0018] Preferably, it also includes:
[0019] The insulating dielectric layer is etched to form a contact hole and a gate lead-out hole, wherein the contact hole penetrates the insulating dielectric layer and extends into the body region, and the gate lead-out hole penetrates the insulating dielectric layer and extends into the gate polysilicon.
[0020] Preferably, it also includes:
[0021] Deposition is performed on the insulating dielectric layer to form a metal layer.
[0022] Preferably, the shielded gate MOSFET device comprises an active region and a terminal region, and a floating gate polysilicon is disposed outside the terminal region.
[0023] Another aspect of the present invention provides a shielded gate trench MOSFET device, comprising
[0024] Epitaxial layer;
[0025] A trench, the trench being disposed in the epitaxial layer;
[0026] An insulating dielectric layer, wherein the insulating dielectric layer is disposed above the epitaxial layer;
[0027] A contact hole, wherein the contact hole penetrates the insulating dielectric layer and extends into the body region;
[0028] A metal layer, the metal layer being disposed on the insulating dielectric layer and in the groove;
[0029] The trench also includes a field oxide layer, an isolation oxide layer and a gate oxide layer arranged in sequence from bottom to top, the field oxide layer is provided with source polysilicon, the gate oxide layer is provided with gate polysilicon, and the gate polysilicon is a concave notch structure;
[0030] The shielded gate trench MOSFET device also includes a source lead-out hole, which penetrates downward from the insulating dielectric layer and extends to the source polysilicon through the concave notch structure.
[0031] Preferably, it also includes a gate lead-out hole, which penetrates the insulating dielectric layer and extends into the gate polysilicon.
[0032] Preferably, the shielded gate MOSFET device comprises an active region and a terminal region, and a floating gate polysilicon is disposed outside the terminal region.
[0033] The beneficial effects of the present invention are:
[0034] (1) The present invention sets the gate polysilicon into a concave notch structure, which reduces the GS capacitance value of the device. In addition, in the manufacturing process, it is not necessary to fill the trench when depositing the gate polysilicon, which can save a step compared with the conventional SGT device manufacturing process;
[0035] (2) The present invention allows the source polysilicon to be directly led out from the active area by setting a source lead-out hole, without the need for a separate area to be set up, thereby saving chip area. In addition, compared with the conventional SGT device manufacturing process, there is no need to form an "isolation oxide layer" and "gate polysilicon" in the active area, which greatly reduces the process time and saves manufacturing costs.
[0036] (3) The manufacturing method of the present invention can simultaneously form device structures in the active region and the terminal region. In conventional manufacturing methods, the terminal region device structure needs to be blocked by a mask when manufacturing the active region device structure, and then manufactured separately after the active region device structure is manufactured. The present invention simplifies the manufacturing process. BRIEF DESCRIPTION OF THE DRAWINGS
[0037] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0038] Figures 1 to 14 Schematic diagram of an embodiment of the present invention. DETAILED DESCRIPTION
[0039] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0040] Embodiment 1
[0041] Figures 1 to 12 A method for manufacturing a shielded gate trench MOSFET device provided in this embodiment is shown, comprising the following steps:
[0042] S1: Figure 1 As shown, a substrate 1 is prepared, an epitaxial layer 2 is formed on the substrate 1, and a barrier layer 3 is provided on the epitaxial layer 2. It should be noted that Figures 1 to 13 In the figure, the device structure on the left is the device structure of the active region, and the device structures on the right are all device structures of the terminal region.
[0043] S2: Figure 2 As shown, etching is performed on the epitaxial layer 1 and the barrier layer 2 to form a trench 4. The depth and width of the trench 4 can be adjusted by those skilled in the art according to actual needs.
[0044] S3: Figure 3 As shown, a field oxide layer 5 is formed in the trench 4. In this embodiment, the field oxide layer 5 is formed by thermal oxidation and deposition.
[0045] S4: Figure 4 As shown, polysilicon 6 is filled by deposition.
[0046] S5: Figure 5 As shown, the polysilicon 6 is etched back, and the field oxide layer 5 is also etched to form a source polysilicon 61.
[0047] S6: Figure 6 As shown, an isolation oxide layer 7 is formed on the source polysilicon 61. In this embodiment, the isolation oxide layer 7 is formed by HDP and etching, or by thermal oxidation. In conventional manufacturing methods, the trench will be filled when the isolation oxide layer 7 is formed, but the terminal area does not need to form gate polysilicon, so the isolation oxide layer in the active area needs to be removed by IPO lithography and etching to remove a portion of the isolation oxide layer 7.
[0048] S7: Figure 7As shown, a gate oxide layer 8 is formed on the sidewall of the trench 4 above the isolation oxide layer 7, and then polysilicon 6 is deposited. The polysilicon 6 does not need to fill the trench 4, and the polysilicon 6 forms a recessed structure. In the conventional method for manufacturing a shielded gate trench MOSFET device, since the trench 4 is relatively wide, it is necessary to deposit the polysilicon 6 twice in order to fill the trench 4 with polysilicon 6; however, in this embodiment, polysilicon deposition can be performed only once, and there is no need to fill the trench 4. Figure 7 The polysilicon 6 in the trench 4 is not fully filled, thereby forming a recessed structure.
[0049] S8: Figure 8 As shown, the polysilicon 6 is back-etched to form a gate polysilicon 62. The gate polysilicon 62 is a concave notch structure, that is, it is divided into two parts, left and right, in the groove 4, with a gap in the middle. The concave notch structure can reduce the GS capacitance value; because of the recessed structure, the source polysilicon 61 at the bottom can be led out from the middle gap of the recessed structure. Therefore, compared with the conventional manufacturing method, the manufacturing steps of this embodiment do not need to distinguish between the active area and the terminal area, saving many process steps that need to be separately manufactured in the terminal area, such as adding a mask on the terminal area when etching the isolation oxide layer 7, and adding a mask on the active area when subsequently leading out the source polysilicon 61, etc., to distinguish between the active area and the terminal area. In this embodiment, the same steps are performed.
[0050] S9: Fig. 9 As shown, ion implantation is performed on the epitaxial layer 1 to form a body region 9 and a source region 10 respectively, and then deposition is performed on the epitaxial layer 1 to form an insulating dielectric layer 11;
[0051] S10.1: If Fig.10 As shown, etching is performed in the insulating dielectric layer 11 to form a source lead-out hole 12. The source lead-out hole 12 penetrates the insulating dielectric layer 11, then passes through the concave notch structure of the gate polysilicon 62 and extends into the source polysilicon 61. The source polysilicon 61 can be directly led out through the source lead-out hole 12 to be electrically connected to the outside. The source polysilicon lead-out of a conventional shielded gate trench MOSFET device also requires a separate lead-out area. Therefore, compared with the conventional shielded gate trench MOSFET device, this embodiment greatly saves the layout area of the shielded gate trench MOSFET.
[0052] In some other embodiments, the following steps are also included:
[0053] S10.2: If Fig.11 and Fig.12As shown, etching is performed on the insulating dielectric layer 11 to form a contact hole 13 and a gate lead hole 14, wherein the contact hole 13 penetrates the insulating dielectric layer 11 and extends into the body region 9, and the gate lead hole 14 penetrates the insulating dielectric layer 11 and extends into the gate polysilicon 62. Step S10.2 can be performed simultaneously with step S10.1, or step S10.1 can be completed first and then step S10.2. Those skilled in the art can make adjustments according to actual conditions, and no limitation is made here.
[0054] In some other embodiments, the following steps are also included:
[0055] S11: Fig.12 As shown, deposition is performed on the insulating dielectric layer 11 to form a metal layer 15. At this time, the basic structure of the shielded gate trench MOSFET device has been completed. The subsequent production steps can be known to those skilled in the art through conventional technical means and will not be repeated here.
[0056] In a preferred embodiment, if Fig.13 As shown, the shielded gate trench MOSFET device includes an active region and a terminal region, and a floating gate polysilicon is arranged on the outermost side of the terminal region. The specific manufacturing method is: in step S10.2, when etching to form the gate lead-out hole 14, no etching is performed on the outermost side of the terminal region ( Fig.13 Therefore, the outermost polysilicon 6 of the terminal region is not connected to the outside world, forming a floating gate polysilicon 63, which can prevent the voltage at the drain end of the shielded gate trench MOSFET device from being fully loaded on the gate oxide layer 8, causing damage to the gate oxide layer 8 and leakage.
[0057] It should be noted that the gate and the source need to be connected to different metal areas, so the gate lead-out hole 14 and the source lead-out hole 12 need to be respectively set under two different and separate metal areas that are not interconnected during the actual manufacturing process. In order to facilitate observation and comparison, Figures 1 to 12 The diagram shows a perspective cross-sectional view from the front, so the gate lead-out hole 14 is in the same figure as the source lead-out hole 12 and the contact hole 13. However, in reality, after the gate lead-out hole 14 and the source lead-out hole 12 are deposited to form the metal layer 15, the gate and the source are not interconnected, wherein the source lead-out hole 12 and the contact hole 13 are located under the same and interconnected metal region, and both are located under different and non-interconnected metal regions with the gate lead-out hole 14, as shown in FIG. Fig.13 FIG. 1 is a cross-sectional view of the location of the gate lead-out hole 14. Fig.14 2 is a cross-sectional view showing the locations of the source lead-out hole 12 and the contact hole 13 .
[0058] Embodiment 2
[0059] like Fig.12As shown, this embodiment provides a shielded gate trench MOSFET device, including:
[0060] Epitaxial layer 2;
[0061] A trench 4, wherein the trench 4 is arranged in the epitaxial layer 2;
[0062] An insulating dielectric layer 11, wherein the insulating dielectric layer 11 is disposed above the epitaxial layer 2;
[0063] A contact hole 13, the contact hole 13 penetrates the insulating dielectric layer 11 and extends into the body region 9;
[0064] A metal layer 15, wherein the metal layer 15 is disposed on the insulating dielectric layer 11 and in the groove 4;
[0065] The trench 4 also includes a field oxide layer 5, an isolation oxide layer 7 and a gate oxide layer 8 arranged in sequence from bottom to top. The field oxide layer 5 is provided with a source polysilicon 61, and the gate oxide layer 8 is provided with a gate polysilicon 62. The gate polysilicon 62 is a concave notch structure.
[0066] The shielded gate trench MOSFET device further includes a source lead-out hole 12, which penetrates downward from the insulating dielectric layer 11 and extends to the source polysilicon 61 through the concave notch structure;
[0067] In a preferred embodiment, the shielded gate trench MOSFET device further includes a gate lead-out hole 14 , which penetrates the insulating dielectric layer 11 and extends into the gate polysilicon 62 .
[0068] In a preferred embodiment, the shielded gate MOSFET device includes an active region and a terminal region, and a floating gate polysilicon 63 is disposed outside the terminal region, that is, the gate polysilicon 62 outside the terminal region is not connected to the outside.
[0069] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.
[0070] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A method for manufacturing a shielded gate trench MOSFET device, characterized in that: The steps include: Providing an epitaxial layer, and disposing a barrier layer on the epitaxial layer; Etching the epitaxial layer and the barrier layer to form a groove; forming a field oxide layer inside the trench; Depositing polysilicon inside the trench, and etching the field oxide layer and the polysilicon to form source polysilicon; forming an isolation oxide layer on the source polysilicon; forming a gate oxide layer on the sidewall of the trench above the isolation oxide layer; Depositing polysilicon on the isolation oxide layer and in the gate oxide layer, and etching to form gate polysilicon, wherein the gate polysilicon is a concave notch structure; Performing ion implantation in the epitaxial layer to form a body region and a well region; Deposition is performed on the epitaxial layer to form an insulating dielectric layer; The insulating dielectric layer is etched to form a source lead-out hole, wherein the source lead-out hole penetrates the insulating dielectric layer and extends into the source polysilicon.
2. The method according to claim 1, characterized in that: Also includes: The insulating dielectric layer is etched to form a contact hole and a gate lead-out hole, wherein the contact hole penetrates the insulating dielectric layer and extends into the body region, and the gate lead-out hole penetrates the insulating dielectric layer and extends into the gate polysilicon.
3. The method according to claim 1, characterized in that: Also includes: Deposition is performed on the insulating dielectric layer to form a metal layer.
4. The method according to claim 1, characterized in that: The shielded gate MOSFET device comprises an active region and a terminal region, and a floating gate polysilicon is arranged outside the terminal region.
5. A shielded gate trench MOSFET device, characterized in that: include Epitaxial layer; A trench, the trench being disposed in the epitaxial layer; An insulating dielectric layer, wherein the insulating dielectric layer is disposed above the epitaxial layer; A contact hole, wherein the contact hole penetrates the insulating dielectric layer and extends into the body region; A metal layer, the metal layer being disposed on the insulating dielectric layer and in the groove; The trench also includes a field oxide layer, an isolation oxide layer and a gate oxide layer arranged in sequence from bottom to top, the field oxide layer is provided with source polysilicon, the gate oxide layer is provided with gate polysilicon, and the gate polysilicon is a concave notch structure; The shielded gate trench MOSFET device also includes a source lead-out hole, which penetrates downward from the insulating dielectric layer and extends to the source polysilicon through the concave notch structure.
6. The shielded gate trench MOSFET device according to claim 5, characterized in that: The invention also comprises a gate lead-out hole, wherein the gate lead-out hole penetrates the insulating dielectric layer and extends into the gate polysilicon.
7. The shielded gate trench MOSFET device according to claim 5, characterized in that: The shielded gate MOSFET device comprises an active region and a terminal region, and a floating gate polysilicon is arranged outside the terminal region.