Semiconductor structure and method for manufacturing the same

Abstract

The present disclosure relates to a semiconductor structure and a preparation method thereof, the preparation method comprising: forming a stacked layer on a substrate, the stacked layer comprising a layer to be protected, a protective layer and a first sacrificial protective layer formed in sequence, and there being a pinhole defect in the protective layer that penetrates the protective layer along the thickness direction of the protective layer; after completing a preset semiconductor process for the stacked layer, a chemical vapor etching process is used to remove the first sacrificial protective layer, and solid byproducts generated in the process of removing the first sacrificial protective layer by chemical vapor etching fill the pinholes to prevent the etching gas from etching and damaging the layer to be protected through the pinholes; wherein the etching selectivity ratio of the first sacrificial protective layer to the protective layer in the chemical vapor etching process is greater than or equal to 100:1; after the first sacrificial protective layer is completely removed, the protective layer is heated to treat the solid byproducts filled in the pinholes so that the solid byproducts filled in the pinholes are sublimated or decomposed into gaseous substances and then sucked away. The preparation method disclosed in the present disclosure can reduce structural defects and improve product reliability.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for preparing the same. Background Art

[0002] Non-planar semiconductor structures are widely used in mobile devices such as mobile phones and tablet computers due to their advantages of small size, large capacity, high integration and fast transmission speed. However, structural defects are prone to occur during the preparation of non-planar semiconductor structures, resulting in poor product reliability.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0004] The embodiments of the present disclosure provide a semiconductor structure and a method for preparing the same, which can reduce structural defects and improve product reliability and electrical performance.

[0005] According to one aspect of the present disclosure, there is provided a method for preparing a semiconductor structure, comprising:

[0006] Forming a stacked layer on a substrate, the stacked layer comprising a to-be-protected layer, a protective layer, and a first sacrificial protective layer formed in sequence, wherein a pinhole defect penetrating the protective layer along a thickness direction of the protective layer exists in the protective layer;

[0007] After completing the preset semiconductor process for the stacked layer, a chemical vapor etching process is used to remove the first sacrificial protective layer, and solid byproducts generated in the process of removing the first sacrificial protective layer by the chemical vapor etching fill the pinholes to prevent the etching gas from passing through the pinholes to etch and damage the layer to be protected; wherein the etching selectivity ratio of the first sacrificial protective layer to the protective layer in the chemical vapor etching process is greater than or equal to 100:1;

[0008] After the first sacrificial protective layer is completely removed, the protective layer is heated to allow the solid byproducts filled in the pinholes to sublime or decompose into gaseous substances that are then removed by suction.

[0009] In an exemplary embodiment of the present disclosure, the layer to be protected is a gate oxide layer, the material of the gate oxide layer includes silicon oxide, the material of the first sacrificial protection layer is silicon oxide, the material of the protection layer is polysilicon, the etching gas includes hydrogen fluoride and ammonia, the solid byproduct is ammonium fluorosilicate, and the chemical reaction formula for removing the first sacrificial protection layer by using a chemical vapor etching process is as follows:

[0010] ;

[0011] ;

[0012] After the first sacrificial protective layer is completely removed, the protective layer is heated to decompose the solid byproducts filled in the pinholes into gaseous substances and then be removed by suction. The chemical reaction formula of the decomposition reaction is as follows:

[0013] .

[0014] In an exemplary embodiment of the present disclosure, the heating temperature of the heat treatment of the protective layer is greater than or equal to 80°C.

[0015] In an exemplary embodiment of the present disclosure, the stacked layer further includes a second sacrificial protection layer formed on the surface of the first sacrificial protection layer, and before removing the first sacrificial protection layer by using a chemical vapor etching process, the preparation method further includes:

[0016] The second sacrificial protection layer is removed by a wet etching process.

[0017] In an exemplary embodiment of the present disclosure, the layer to be protected is a gate oxide layer of a transistor with a surround gate vertical channel structure, a gate material layer parallel to the substrate is formed on the substrate, a plurality of array-arranged channel holes are formed on the gate material layer, the channel holes extend in a direction perpendicular to the substrate and penetrate the gate material layer, and the stacked layer is formed at least on the sidewalls of the channel holes.

[0018] In an exemplary embodiment of the present disclosure, a first source-drain layer and a first insulating layer, both parallel to the substrate, are further formed on the substrate, the first insulating layer is located between the first source-drain layer and the gate material layer, the channel hole penetrates the gate material layer and extends into the first insulating layer; the first source-drain layer includes a plurality of first source-drain portions, the number of the first source-drain portions corresponds to the number of the channel holes, and two adjacent first source-drain portions are isolated by insulating materials;

[0019] The steps of forming the stacked layer include:

[0020] forming the to-be-protected layer, the protective layer and the first sacrificial protective layer on at least the sidewall and the bottom of the channel hole;

[0021] The step of completing a preset semiconductor process on the stacked layer comprises:

[0022] A dry etching process is used to remove a portion of the stacked layer and a portion of the first insulating layer located at the bottom of the channel hole and above the first source and drain portion to expose at least a portion of the upper surface of the first source and drain portion, and at the same time form a groove that penetrates the gate material layer and the first insulating layer.

[0023] In an exemplary embodiment of the present disclosure, a second insulating layer parallel to the substrate is also formed on the substrate, the gate material layer is located between the second insulating layer and the first insulating layer, the channel hole penetrates the second insulating layer and the gate material layer and extends into the first insulating layer, and the groove penetrates the second insulating layer, the gate material layer and the first insulating layer.

[0024] In an exemplary embodiment of the present disclosure, the preparation method further comprises:

[0025] After the solid byproducts filled in the pinholes are sublimated or decomposed into gaseous substances and then removed by suction, the protective layer is protected by a nitrogen atmosphere to prevent the polysilicon material from naturally oxidizing to form silicon oxide after the protective layer contacts the air.

[0026] In an exemplary embodiment of the present disclosure, the layer to be protected includes a first layer to be protected and a second layer to be protected which are sequentially deposited on at least the sidewalls and the bottom of the channel hole, the material of the second layer to be protected is silicon oxide, the dielectric constant of the first layer to be protected is greater than the dielectric constant of silicon oxide, and the material of the first layer to be protected is a dielectric material with a high dielectric constant.

[0027] In an exemplary embodiment of the present disclosure, the preparation method further comprises:

[0028] After the solid byproducts filled in the pinholes are sublimated or decomposed into gaseous substances and then removed by suction, a channel material layer is formed on the sidewalls and bottom of the groove, the interior of the groove is surrounded by the channel material layer to form a sub-groove, and the end of the channel material layer close to the substrate is in contact with and connected to the upper surface of the first source and drain portion;

[0029] Filling the sub-trench with an insulating material to form an insulating filling layer, wherein the height of the insulating filling layer is lower than or equal to the height of the uppermost side of the channel material layer;

[0030] A second source-drain layer is formed on a side of the channel material layer away from the substrate, the second source-drain layer includes a plurality of second source-drain portions, the number of the second source-drain portions corresponds one-to-one to the number of the first source-drain portions, the lower surfaces of the second source-drain portions are in contact with and connected to the channel material layer and the insulating filling layer, and two adjacent second source-drain portions are isolated by insulating material.

[0031] According to one aspect of the present disclosure, a semiconductor structure is provided. The semiconductor structure is prepared by using any one of the methods for preparing a semiconductor structure described above.

[0032] The semiconductor structure and preparation method disclosed in the present invention form at least a protective layer and a first sacrificial protective layer on the layer to be protected to protect the layer to be protected in the subsequent semiconductor process. There are pinhole defects in the protective layer that penetrate the protective layer along its thickness direction. After that, a chemical vapor etching process can be used to remove the first sacrificial protective layer. In this process, the solid byproducts generated can fill the pinhole defects in the protective layer, so that in the process of removing the first sacrificial protective layer, the solid byproducts can prevent the etching gas from penetrating into the layer to be protected, and the probability of the etching gas damaging the layer to be protected through the pinhole etching can be reduced, which helps to reduce the structural defects of the layer to be protected and improve the electrical performance and reliability of the device. In the chemical vapor etching process, since the etching selectivity ratio of the first sacrificial protective layer to the protective layer is greater than or equal to 100:1, the protective layer is almost not damaged in the process of etching the first sacrificial protective layer, and the protective effect of the protective layer on the layer to be protected can be guaranteed. At the same time, after completely removing the first sacrificial protective layer, the solid byproducts in the pinholes can be sublimated or decomposed by heating to form gas that is sucked out, ensuring that no unnecessary residue is left inside the protective layer, avoiding performance problems that may be caused by residual particles, and further ensuring the electrical performance and reliability of the device.

[0033] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0035] Figure 1 Flow chart of a method for preparing a semiconductor structure in an embodiment of the present disclosure.

[0036] Figure 2 It is a schematic diagram of a layer to be protected, a protective layer and a first sacrificial protective layer in an embodiment of the present disclosure.

[0037] Figure 3 It is a schematic diagram of the reaction between the etching gas and the first sacrificial protection layer in the embodiment of the present disclosure.

[0038] Figure 4 for Figure 3 Schematic diagram after the first sacrificial protection layer is completely removed.

[0039] Figure 5 Schematic diagram of solid byproducts in the embodiments of the present disclosure.

[0040] Figure 6 Schematic diagram of a channel hole in an embodiment of the present disclosure.

[0041] Figure 7 It is a schematic diagram of the structure after completing step S210 in the embodiment of the present disclosure.

[0042] Figure 8 Schematic diagram of the second sacrificial protection layer in an embodiment of the present disclosure.

[0043] Fig. 9 Schematic diagram of the groove in the embodiment of the present disclosure.

[0044] Fig.10 It is a schematic diagram of the structure after the second sacrificial protection layer is removed in the embodiment of the present disclosure.

[0045] Fig.11 Schematic diagram of the channel layer and the second source and drain portion in the embodiment of the present disclosure.

[0046] Description of reference numerals:

[0047] 1. Substrate; 2. Gate material layer; 201. Channel hole; 202. Groove; 3. Layer to be protected; 31. First layer to be protected; 32. Second layer to be protected; 4. Protective layer; 401. Pinhole; 5. First sacrificial protective layer; 6. Second sacrificial protective layer; 7. First source and drain; 8. Insulating layer; 9. Channel material layer; 10. Insulating filling layer; 11. Second source and drain; 12. Second insulating layer; 100. Channel layer. DETAILED DESCRIPTION

[0048] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0049] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0050] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first" and "second" are used merely as labels and are not intended to limit the quantity of their objects.

[0051] In the process of manufacturing transistors (such as a wrap-around gate vertical channel structure), during the etching of the bottom opening of the channel, it is usually necessary to protect the gate oxide layer in the opening through a sacrificial layer to prevent the gate oxide layer on the side wall of the opening from being damaged during the etching of the bottom opening. However, during the etching of the bottom opening, pinholes are likely to appear in the sacrificial layer and the protective layer under the bombardment of high bias voltage, and the protective layer and the sacrificial layer may also have pinhole defects due to process problems during the formation process. In the subsequent wet etching process to remove the sacrificial layer, the etching solution is likely to penetrate through the pinholes to the surface of the gate oxide layer, thereby damaging the gate oxide layer, resulting in structural defects in the final device, and the device reliability is low.

[0052] Based on this, the present disclosure provides a method for preparing a semiconductor structure. Figure 1 As shown, the preparation method includes steps S110 to S130, wherein:

[0053] Step S110, forming a stacked layer on the substrate, the stacked layer comprising a to-be-protected layer, a protective layer and a first sacrificial protective layer formed in sequence, and a pinhole defect penetrating the protective layer along a thickness direction of the protective layer exists in the protective layer;

[0054] Step S120, after completing the preset semiconductor process for the stacked layer, a chemical vapor etching process is used to remove the first sacrificial protective layer, and solid byproducts generated in the process of removing the first sacrificial protective layer by chemical vapor etching fill the pinholes to prevent the etching gas from passing through the pinholes to etch and damage the layer to be protected; wherein the etching selectivity ratio of the first sacrificial protective layer to the protective layer in the chemical vapor etching process is greater than or equal to 100:1;

[0055] Step S130 , after the first sacrificial protective layer is completely removed, the protective layer is heated to allow the solid byproducts filled in the pinholes to sublime or decompose into gaseous substances that are then removed by suction.

[0056] The material of the to-be-protected layer may be silicon oxide, the material of the first sacrificial protective layer may be silicon oxide, the material of the protective layer may be polycrystalline silicon, the polycrystalline silicon protective layer is prone to pinhole defects during formation, the etching gas of the chemical vapor etching includes hydrogen fluoride and ammonia, and the solid byproduct may be ammonium fluorosilicate. The heating temperature for the heat treatment of the protective layer is greater than or equal to 80°C.

[0057] The preparation method of the semiconductor structure disclosed in the present invention adopts a chemical vapor etching process to remove the first sacrificial protective layer. In the process, hydrogen fluoride and ammonia selected as etching gases can react with the first sacrificial protective layer (the material can be silicon oxide) in a targeted manner to generate a solid by-product ammonium fluorosilicate. The solid by-product ammonium fluorosilicate can fill the tiny pinholes in the polysilicon protective layer, thereby blocking the etching gas from further penetrating into the layer to be protected, reducing the risk of damage to the layer to be protected due to the etching gas passing through the pinholes, helping to maintain the integrity of the structure of the layer to be protected, and enhancing the overall stability and reliability of the device.

[0058] In the above process, since the etching selectivity ratio of the first sacrificial protective layer to the protective layer is greater than or equal to 100:1, the protective layer is hardly damaged during the etching of the first sacrificial protective layer, thereby ensuring the protective effect of the protective layer on the protective layer.

[0059] In addition, after the first sacrificial protective layer is completely removed, the protective layer can be heated at 80°C or above. The heating process can cause the solid byproduct of ammonium fluorosilicate in the pinholes to decompose and convert into gas form, which is then removed by the suction system. This step not only removes the residue inside the protective layer, but also effectively avoids the performance degradation problem that may be caused by residual particles, providing another solid guarantee for the electrical performance and reliability of the device.

[0060] The steps and specific details of the method for preparing the semiconductor structure disclosed in the present invention are described in detail below:

[0061] like Figure 1 As shown, in step S110, a stacked layer is formed on the substrate, the stacked layer including a to-be-protected layer, a protective layer and a first sacrificial protective layer formed in sequence, and there are pinhole defects in the protective layer that penetrate the protective layer along the thickness direction of the protective layer.

[0062] The substrate may be a flat plate structure, which may be rectangular, circular, elliptical, polygonal or irregular in shape, and its material may be a semiconductor material, for example, its material may be silicon, germanium or germanium silicon, etc. There is no special limitation on the shape and material of the substrate.

[0063] like Figure 2 As shown, the material of the layer to be protected 3 may be an insulating material, for example, the material of the layer to be protected 3 may include silicon oxide. In some embodiments of the present disclosure, the layer to be protected 3 may be a composite film structure, for example, the layer to be protected 3 may include a first layer to be protected 31 and a second layer to be protected 32, wherein the second layer to be protected 32 may be located on the surface of the first layer to be protected 31, and the dielectric constant of the first layer to be protected 31 is greater than the dielectric constant of the second layer to be protected 32. For example, the material of the second layer to be protected 32 may be silicon oxide, and the material of the first layer to be protected 31 may be a material with a high dielectric constant, for example, it may be aluminum oxide, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide, tantalum oxide, niobium oxide, strontium oxide or a mixture thereof, and of course, it may also be other materials, which are not listed here one by one. The layer to be protected 3 may be used as a gate oxide layer of a transistor with a surrounding gate vertical channel structure. When the layer to be protected 3 includes a material with a higher dielectric constant, due to the increase in the capacitance of the gate oxide layer of the high dielectric constant material, a stronger electric field can be generated in the channel region under the same gate voltage. This stronger electric field can more effectively control the distribution and movement of carriers in the channel, thereby improving the gate's ability to control the channel current. At the same time, because the high dielectric constant material enhances the electric field effect, the channel can be made conductive at a lower gate voltage, which helps to reduce the threshold voltage and thus reduce the device's operating voltage and power consumption.

[0064] Please continue to see Figure 2 As shown, the protective layer 4 can cover the entire surface of the layer to be protected 3, and the protective layer 4 can be used to protect the layer to be protected 3 to reduce the probability that other processes (for example, preset semiconductor processes such as dry etching) damage the layer to be protected 3. The material of the protective layer 4 can be polysilicon, and after the preset semiconductor process (for example, dry etching) that may damage the layer to be protected 3 is completed, the protective layer 4 can also be retained, and the retained protective layer 4 can be used as a part of the channel layer of the transistor with a surround gate vertical channel structure. The material of the first sacrificial protective layer 5 can be silicon oxide, and the first sacrificial protective layer 5 can cover the surface of the protective layer 4. The first sacrificial protective layer 5 can be used to protect the protective layer 4 to reduce the probability that other processes (for example, preset semiconductor processes such as dry etching) damage the protective layer 4.

[0065] For example, the to-be-protected layer 3, the protective layer 4, and the first sacrificial protective layer 5 may be sequentially formed by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. During the preset semiconductor process, the structure of the first sacrificial protective layer 5 may be destroyed, and the protective effect may be reduced, so that defects such as pinholes 401 penetrating the protective layer 4 along the thickness direction of the protective layer 4 may appear in the protective layer 4. In addition, the protective layer 4 itself may also generate pinhole defects 401 during the formation process.

[0066] In the present disclosure, after a process that may damage the protection layer 4 (eg, a predetermined semiconductor process such as dry etching) is completed, the first sacrificial protection layer 5 may be removed.

[0067] like Figure 1 As shown, in step S120, after the preset semiconductor process is completed for the stacked layer, the first sacrificial protective layer 5 is removed by a chemical vapor etching process, and the solid byproducts generated in the process of removing the first sacrificial protective layer 5 by chemical vapor etching fill the pinhole 401 to prevent the etching gas from passing through the pinhole 401 to etch and damage the layer to be protected 3; wherein, the etching selectivity ratio of the first sacrificial protective layer 5 to the protective layer 4 in the chemical vapor etching process is greater than or equal to 100:1.

[0068] like Figure 3 As shown, in the process of removing the first sacrificial protective layer 5, an etching gas may be introduced into the reaction chamber through the gas inlet, and the etching gas may include a first gas and a second gas. The first gas and the second gas may be introduced into the reaction chamber through different gas inlets, respectively. After the first gas and the second gas are mixed in the reaction chamber, they may be adsorbed on the surface of the first sacrificial protective layer 5, wherein the first gas may react with the first sacrificial protective layer 5 to generate an intermediate product, and the intermediate product may react with the first gas and the second gas to generate a solid byproduct, such as Figure 4 and Figure 5 As shown, the solid byproduct can fill the pinhole 401 in the protective layer 4 to fill the structural defects of the protective layer 4 and enhance the protective effect of the protective layer 4. It should be noted that the reaction chamber can be a vacuum chamber, and a very low pressure environment can be maintained by a vacuum pumping system, which helps to reduce the interference of unnecessary impurity gases and ensure the high purity and accuracy of the reaction. At the same time, the vacuum environment can also effectively prevent the infiltration of oxygen and water vapor, protecting other film layers that are not involved in the reaction from being oxidized.

[0069] During the reaction process, the flow rate of the first gas and the second gas, the position of the injection point of the first gas and the second gas, and the gas flow pattern of the first gas and the second gas can be pre-set by the machine to control the reaction rate and ensure that the reaction is carried out efficiently to avoid over-reaction or under-reaction. For example, the etching rate of the first sacrificial protection layer 5 can be controlled within 20 angstroms / minute to 30 angstroms / minute by setting the flow rate of the first gas and the second gas, the position of the injection point of the first gas and the second gas, and the gas flow pattern of the first gas and the second gas, and within this etching rate range, the surface uniformity of the etched film layer (for example, the first sacrificial protection layer 5) can be maintained within a range of less than 5%.

[0070] The composition of the first gas and the second gas matches the materials of the first sacrificial protective layer 5 and the protective layer 4. For example, the first gas can react with the first sacrificial protective layer 5 to remove the first sacrificial protective layer 5 (that is, the first gas can be used as an etching gas in the chemical vapor etching process of the first sacrificial protective layer 5), and in this process, neither the first gas nor the second gas will react with the protective layer 4, that is, the etching selectivity of the first gas and the second gas to the first sacrificial protective layer 5 is much higher than their etching selectivity to the protective layer 4, so that the protective layer 4 underneath will not be damaged in the process of removing the first sacrificial protective layer 5.

[0071] For example, in the chemical vapor etching process, the etching selectivity ratio of the first sacrificial protective layer 5 to the protective layer 4 is greater than or equal to 100:1, that is, the etching selectivity ratios of the first gas and the second gas to the first sacrificial protective layer 5 to the protective layer 4 are both greater than or equal to 100:1. For example, the etching selectivity ratios of the first gas and the second gas to the first sacrificial protective layer 5 to the protective layer 4 can be 100:1, 110:1, 120:1, 130:1, 140:1 or 150:1. Of course, the etching selectivity ratios of the first gas and the second gas to the first sacrificial protective layer 5 to the protective layer 4 can also be other ratios, which are not listed here one by one.

[0072] In an exemplary embodiment of the present disclosure, the first gas is used as the main etching gas, and its chemical properties need to be highly matched with the material of the first sacrificial protective layer 5 to achieve a fast etching rate. At the same time, the first gas does not react with the protective layer 4 or other non-target layers as much as possible to maintain a high etching selectivity. The second gas is used as an auxiliary gas, mainly for converting the intermediate product generated by the reaction of the first gas with the first sacrificial protective layer 5 into a solid by-product. For example, when the material of the first sacrificial protective layer 5 is silicon oxide (SiO2) and the material of the protective layer 4 is polycrystalline silicon (poly), the first gas can be hydrogen fluoride (HF) and the second gas can be ammonia (NH3), that is, the etching gas includes hydrogen fluoride and ammonia. Silicon oxide (SiO2) in the first sacrificial protective layer 5 reacts with hydrogen fluoride (HF) to generate an intermediate product, silicon tetrafluoride (SiF4), and silicon tetrafluoride (SiF4) can react with hydrogen fluoride (HF) and ammonia (NH3) to generate a solid by-product, ammonium fluorosilicate ((NH4)2SiF6). Ammonium fluorosilicate is in the form of powder particles, which can fill the pinholes 401 in the protective layer 4, so that in the process of removing the first sacrificial protective layer 5, the first gas and the second gas used will not pass through the pinholes 401 in the protective layer 4 and react with the layer to be protected 3, which can reduce the probability of the first gas and the second gas damaging the layer to be protected 3, help reduce the structural defects of the layer to be protected 3, and improve the electrical performance and reliability of the finally formed device.

[0073] In the present disclosure, the chemical reaction formula for removing the first sacrificial protection layer 5 by chemical vapor etching process is as follows:

[0074] ;

[0075] .

[0076] like Figure 1 As shown, in step S130, after the first sacrificial protection layer 5 is completely removed, the protection layer 4 is heated to allow the solid byproducts filled in the pinholes 401 to sublime or decompose into gaseous substances that are then removed by suction.

[0077] After the first sacrificial protective layer 5 is completely removed, the protective layer 4 can be heated by a machine in the reaction chamber to allow the solid byproducts (e.g., (NH4)2SiF6) in the pinholes 401 in the protective layer 4 to sublime or decompose into gaseous substances. The gaseous substances formed after the sublimation or decomposition of the solid byproducts can then be removed by suction or other means to ensure that no unnecessary residues are left inside the protective layer 4, thereby avoiding performance problems that may be caused by residual particles and further ensuring the electrical performance and reliability of the device.

[0078] In the present disclosure, when the solid by-product is (NH4)2SiF6, the chemical reaction formula for the decomposition of the solid by-product filled in the pinhole 401 is as follows:

[0079] .

[0080] In an exemplary embodiment of the present disclosure, the heating temperature for heating the protective layer 4 may be greater than or equal to 80°C. For example, the heating temperature may be 80°C, 85°C, 90°C, 95°C or 100°C. Of course, the heating temperature may also be other temperatures as long as the solid by-products can be volatilized without damaging other structures.

[0081] In an exemplary embodiment of the present disclosure, when the material of the protective layer 4 is polycrystalline silicon (poly), since polycrystalline silicon is easily oxidized, the method for preparing the semiconductor structure of the present disclosure may further include:

[0082] Step S140 , after the solid byproducts filled in the pinhole 401 are sublimated or decomposed into gaseous substances and then removed by suction, the protective layer 4 is protected by a nitrogen atmosphere to prevent the polysilicon material from naturally oxidizing to form silicon oxide after the protective layer 4 contacts the air.

[0083] After the solid by-products are completely volatilized, the wafer including the layer to be protected 3 and the protective layer 4 can be transferred to the wafer box outside the reaction chamber by the vacuum manipulator in the reaction chamber. During this process, the wafer including the layer to be protected 3 and the protective layer 4 needs to pass through the vacuum environment zone, the vacuum atmosphere conversion zone and the atmospheric environment zone in sequence. During the transfer process, the time the wafer stays in the vacuum environment zone and the vacuum atmosphere conversion zone can be appropriately increased. For example, the time the wafer stays in the atmosphere and the vacuum conversion zone can be 0.5min~1min. For example, the time the wafer stays in the vacuum atmosphere conversion zone can be 0.5min, 0.6min, 0.7min, 0.8min, 0.9min or 1min. At the same time, in order to reduce the risk of the protective layer 4 being oxidized due to the exposure of the wafer to the atmosphere, the time the wafer is exposed to the atmosphere can be reduced. For example, the time the wafer is exposed to the atmosphere can be less than 1min~2min. For example, the time the wafer is exposed to the atmosphere can be less than 1min, 1.2min, 1.4min, 1.6min, 1.8min or 2min. In addition, the wafer box can use a nitrogen wafer box. After the wafer is transferred to the wafer box, nitrogen is always purged so that the structure composed of the protective layer 3 and the protective layer 4 is in a nitrogen environment, which can reduce the probability of the protective layer 4 being exposed to the air and then oxidized, which helps to reduce structural defects and improve product reliability.

[0084] In an exemplary embodiment of the present disclosure, Figure 6 As shown, a gate material layer 2 parallel to the substrate 1 is also formed on the substrate 1. The material of the gate material layer 2 can be a material with strong conductive properties, for example, tungsten. The gate material layer 2 can be formed on the substrate 1 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. Of course, the gate material layer 2 can also be formed by other methods. The formation method of the gate material layer 2 is not particularly limited here. In some embodiments of the present disclosure, the gate material layer 2 can be used as the gate of a surround gate vertical channel structure transistor.

[0085] A plurality of channel holes 201 arranged in an array are formed on the gate material layer 2. The channel holes 201 may penetrate the gate material layer 2 in a direction perpendicular to the substrate 1. The number of the channel holes 201 may be multiple, and the multiple channel holes 201 may be spaced apart along the length direction of the gate material layer 2. For example, the channel holes 201 may be formed by etching or the like. The stacked layer may be formed at least on the sidewalls of the channel holes 201, that is, the layer to be protected 3, the protective layer 4, and the first sacrificial protective layer 5 are all at least located on the sidewalls of the channel holes 201. When the layer to be protected 3 includes the first layer to be protected 31 and the second layer to be protected 32, the first layer to be protected 31 and the second layer to be protected 32 may be deposited at least on the sidewalls and the bottom of the channel holes 201 in sequence.

[0086] In an exemplary embodiment of the present disclosure, please continue to refer to Figure 6 As shown, a first source-drain layer (not shown in the figure) and a first insulating layer 8 are also formed on the substrate 1. The first source-drain layer and the first insulating layer 8 are parallel to the substrate 1, and the first insulating layer 8 is located between the first source-drain layer and the gate material layer 2. The first source-drain layer can be a single-layer film structure or a composite film structure composed of multiple film layers, which is not particularly limited here. For example, the material of the first source-drain layer can be a metal material with good conductivity, such as tungsten. The first source-drain layer can also include a conductive barrier material, such as titanium nitride. The conductive barrier material can be located between the metal material and the first insulating layer 8. At the same time, the conductive barrier material can also be located between the metal material and the substrate 1. The conductive barrier material can prevent the metal ions in the metal material from diffusing into the first insulating layer 8 or the substrate 1, which helps to improve the reliability of the device. The first source-drain layer can include a plurality of first source-drain portions 7 distributed at intervals, and the number of the first source-drain portions 7 corresponds to the number of the channel holes 201. Two adjacent first source-drain portions 7 are isolated by insulating materials. The first source-drain portion 7 can be used as the source or drain of a transistor with a surround gate vertical channel structure. The material of the first insulating layer 8 may be silicon oxide or tetraethoxysilane (TEOS). The gate material layer 2 may be located on the surface of the first insulating layer 8. In some embodiments of the present disclosure, the channel hole 201 may not only penetrate the gate material layer 2, but also extend into the first insulating layer 8 at the bottom of the gate material layer 2.

[0087] In an exemplary embodiment of the present disclosure, please continue to refer to Figure 6 As shown, a second insulating layer 12 parallel to the substrate 1 is also formed on the substrate 1, and the gate material layer 2 is located between the second insulating layer 12 and the first insulating layer 8. The channel hole 201 can penetrate the second insulating layer 12 and the gate material layer 2 and extend into the first insulating layer 8. For example, the groove 202 can penetrate the second insulating layer 12, the gate material layer 2 and the first insulating layer 8.

[0088] In an exemplary embodiment of the present disclosure, forming a stacked layer may include the steps of:

[0089] In step S210 , a to-be-protected layer 3 , a protective layer 4 , and a first sacrificial protective layer 5 are formed on at least the sidewall and the bottom of the channel hole 201 .

[0090] like Figure 7As shown, the layer to be protected 3 can be formed at least on the sidewall and bottom of the channel hole 201 by chemical vapor deposition, physical vapor deposition or atomic layer deposition (that is, the layer to be protected 3 conformally covers the sidewall and bottom of the channel hole 201). Of course, the layer to be protected 3 can also be formed by other methods, and the formation method of the layer to be protected 3 is not specifically limited here. It should be noted that when a second insulating layer 12 is formed on the top of the gate material layer 2, for the convenience of the process, the layer to be protected 3 can simultaneously cover the surface of the second insulating layer 12 on the top of the gate material layer 2. When the layer to be protected 3 includes multiple film layers (for example, it includes a first layer to be protected 31 and a second layer to be protected 32), different film layers can be deposited in sequence. After the layer to be protected 3 is formed, a protective layer 4 can be formed on the surface of the layer to be protected 3 by chemical vapor deposition, physical vapor deposition or atomic layer deposition, and the protective layer 4 can conformally cover the entire surface of the layer to be protected 3. After the protective layer 4 is formed, a first sacrificial protective layer 5 may be formed on the surface of the protective layer 4 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. The first sacrificial protective layer 5 may cover the surface of the protective layer 4 in a conformal manner.

[0091] In an exemplary embodiment of the present disclosure, Figure 8 As shown, in order to enhance the protective effect of the protective layer 4, the stacked layer may also include a second sacrificial protective layer 6 formed on the first sacrificial protective layer 5. The material of the second sacrificial protective layer 6 may be titanium nitride. The second sacrificial protective layer 6 may be formed by chemical vapor deposition, physical vapor deposition or atomic layer deposition to conformally cover the surface of the first sacrificial protective layer 5.

[0092] In an exemplary embodiment of the present disclosure, performing a predetermined semiconductor process on a stacked layer may include:

[0093] In step S220, a dry etching process is used to remove part of the stacked layer and the first insulating layer 8 located at the bottom of the channel hole 201 and above the first source and drain portion 7 to expose at least part of the upper surface of the first source and drain portion 7, and at the same time form a groove 202 that penetrates the gate material layer 2 and the first insulating layer 8.

[0094] like Fig. 9As shown, the to-be-protected layer 3 at the bottom of the channel hole 201, the protective layer 4 at the bottom of the channel hole 201, the first sacrificial protective layer 5 at the bottom of the channel hole 201, and the first insulating layer 8 at the bottom of the channel hole 201 can be etched by capacitively coupled plasma (CCP) technology to remove at least a portion of the to-be-protected layer 3 at the bottom of the channel hole 201, at least a portion of the protective layer 4 at the bottom of the channel hole 201, at least a portion of the first sacrificial protective layer 5 at the bottom of the channel hole 201, and the first insulating layer 8 at the bottom of the channel hole 201. At least part of the first insulating layer 8 is formed, thereby forming a groove 202 that exposes at least part of the surface of the first source and drain portion 7. In the process of removing the first sacrificial protective layer 5, the protective layer 4, the layer to be protected 3 and the first insulating layer 8 at the bottom of the channel hole 201 by the capacitively coupled plasma dry etching technology, due to the high plasma energy consumption, the first sacrificial protective layer 5 and the protective layer 4 on the side wall of the channel hole 201 are easily damaged, so that during the etching process, defects such as pinholes 401 appear in the first sacrificial protective layer 5 and the protective layer 4. It should be noted that since the protective layer 4 is located below the first sacrificial protective layer 5, it is protected by the first sacrificial protective layer 5, and the pinholes 401 generated inside are relatively few, which will not affect its subsequent electrical properties when it is used as part of the channel layer of the surround gate vertical channel structure transistor.

[0095] It should be noted that when a second sacrificial protection layer 6 is also formed on the surface of the first sacrificial protection layer 5, when the material at the bottom of the channel hole 201 is removed by the capacitively coupled plasma dry etching technology to expose the first source and drain portion 7, the second sacrificial protection layer 6 at the bottom of the channel hole 201 is also removed. In this process, for each film layer located on the side wall of the channel hole 201, the second sacrificial protection layer 6 is bombarded with the most plasma. The second sacrificial protection layer 6 can protect the first sacrificial protection layer 5, thereby reducing the probability of pinholes appearing in the first sacrificial protection layer 5. At the same time, the first sacrificial protection layer 5 can protect the protective layer 4 therebelow, thereby reducing the probability of pinholes 401 appearing in the protective layer 4. The protective layer 4 can protect the layer to be protected 3 therebelow to prevent the layer to be protected 3 from being damaged. That is, under the triple protection of the second sacrificial protection layer 6, the first sacrificial protection layer 5 and the protection layer 4, the plasma damage to the protected layer 3 during the etching process is prevented, which helps to improve the reliability of the device. At the same time, under the double protection of the first sacrificial protection layer 5 and the second sacrificial protection layer 6, there may be a very small number of pinholes 401 in the protection layer 4 (due to the small number of pinholes 401, it has almost no effect on the electrical performance of the finally formed surround-gate vertical channel structure transistor).

[0096] In an exemplary embodiment of the present disclosure, when a second sacrificial protection layer 6 is further formed on the first sacrificial protection layer 5, before removing the first sacrificial protection layer 5 by using a chemical vapor etching process, the preparation method of the present disclosure further includes:

[0097] Step S230: removing the second sacrificial protection layer 6 by a wet etching process.

[0098] The etching solution of the wet etching needs to match the material of the second sacrificial protection layer 6 so that other surrounding structures will not be damaged or slightly damaged (the damage does not affect the structural performance) during the etching process of the second sacrificial protection layer 6. For example, when the material of the second sacrificial protection layer 6 is titanium nitride, the etching solution of the wet etching can be diluted hydrofluoric acid; and after removing the second sacrificial protection layer 6, an alkaline solution can be used to clean the remaining structure to remove the residue. Step S120 can be performed after removing the second sacrificial protection layer 6. In one embodiment of the present disclosure, the structure after removing the second sacrificial protection layer 6 is as follows Fig.10 shown.

[0099] In an exemplary embodiment of the present disclosure, the method for preparing a semiconductor structure of the present disclosure may further include steps S310 to S330, wherein:

[0100] In step S310, after the solid byproducts filled in the pinhole 401 are sublimated or decomposed into gaseous substances and then sucked away, a channel material layer 9 is formed on the sidewalls and bottom of the groove 202, and the interior of the groove 202 is enclosed by the channel material layer 9 to form a sub-groove, and the end of the channel material layer 9 close to the substrate 1 is in contact with the upper surface of the first source and drain portion 7.

[0101] The material of the channel material layer 9 may be polysilicon, such as Fig.11 As shown, a channel material layer 9 can be formed on the surface of the protective layer 4 on the side wall of the groove 202 by chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD). In some embodiments of the present disclosure, the protective layer 4 and the channel material layer 9 can together constitute a channel layer 100 of a surround-gate vertical channel structure transistor.

[0102] Step S320 , filling the sub-trench with insulating material to form an insulating filling layer 10 , wherein the height of the insulating filling layer 10 is lower than or equal to the height of the uppermost side of the channel material layer 9 .

[0103] For example, the insulating material may be silicon oxide, and the insulating material may be filled in the sub-groove by chemical vapor deposition, physical vapor deposition or atomic layer deposition to form an insulating filling layer 10. The insulating filling layer 10 may fill the remaining space in the sub-groove, and its surface away from the substrate 1 may be flush with the surface of the channel layer 100 away from the substrate 1.

[0104] Step S330, forming a second source-drain layer on the side of the channel material layer 9 away from the substrate 1, the second source-drain layer includes a plurality of second source-drain portions 11, the number of the second source-drain portions 11 corresponds one-to-one to the number of the first source-drain portions 7, the lower surfaces of the second source-drain portions 11 are in contact with and connected to the channel material layer 9 and the insulating filling layer 10, and two adjacent second source-drain portions 11 are isolated by insulating material.

[0105] For example, the material of the second source-drain portion 11 may be a material with strong conductivity, and the second source-drain portion 11 may be formed on the surface of the channel layer 100 away from the substrate 1 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. The second source-drain portion 11 may constitute a wrap-around gate vertical channel structure transistor together with the gate material layer 2, the first source-drain portion 7, the layer to be protected 3 and the channel layer 100, wherein the first source-drain portion 7 may serve as the source (or drain) of the wrap-around gate vertical channel structure transistor, the gate material layer 2 may serve as the gate of the wrap-around gate vertical channel structure transistor, the layer to be protected 3 may serve as the gate oxide layer of the wrap-around gate vertical channel structure transistor, the second source-drain portion 11 may serve as the drain (or source) of the wrap-around gate vertical channel structure transistor, and the channel layer 100 (including the protection layer 4 and the channel material layer 9) may serve as the channel region of the wrap-around gate vertical channel structure transistor.

[0106] It should be noted that, although the steps of the method for preparing a semiconductor structure in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc.

[0107] The present disclosure also provides a semiconductor structure, which can be prepared by a method for preparing a semiconductor structure in any of the above embodiments. The specific details and beneficial effects of the semiconductor structure of the present disclosure have been described in detail in the embodiments of the corresponding method for preparing the semiconductor structure, so they will not be repeated here.

[0108] The semiconductor structure disclosed in the present invention reduces structural defects (for example, reduces the probability of damage to the layer 3 to be protected, and avoids structural defects of the layer 3 to be protected) by optimizing the preparation process, thereby improving structural reliability; at the same time, by adding a material with a higher dielectric constant to the layer 3 to be protected, the switching current and breakdown voltage of the semiconductor structure finally formed are greatly improved. According to testing, the switching current of the semiconductor structure disclosed in the present invention is increased by 19% compared with the traditional structure formed by the traditional process (that is, using wet etching to remove three sacrificial protection layers). At the same time, the pass rate of the breakdown voltage test of the gate oxide layer is increased from 30% to 80%~93%.

[0109] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Forming a stacked layer on a substrate, the stacked layer comprising a to-be-protected layer, a protective layer, and a first sacrificial protective layer formed in sequence, wherein a pinhole defect penetrating the protective layer along a thickness direction of the protective layer exists in the protective layer; After completing the preset semiconductor process for the stacked layer, a chemical vapor etching process is used to remove the first sacrificial protective layer, and solid byproducts generated in the process of removing the first sacrificial protective layer by the chemical vapor etching fill the pinholes to prevent the etching gas from passing through the pinholes to etch and damage the layer to be protected; wherein the etching selectivity ratio of the first sacrificial protective layer to the protective layer in the chemical vapor etching process is greater than or equal to 100:1; After the first sacrificial protective layer is completely removed, the protective layer is heated to allow the solid byproducts filled in the pinholes to sublime or decompose into gaseous substances that are then removed by suction.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The layer to be protected is a gate oxide layer, the material of the gate oxide layer includes silicon oxide, the material of the first sacrificial protection layer is silicon oxide, the material of the protection layer is polysilicon, the etching gas includes hydrogen fluoride and ammonia, the solid byproduct is ammonium fluorosilicate, and the chemical reaction formula for removing the first sacrificial protection layer by chemical vapor etching process is as follows: ； ； After the first sacrificial protective layer is completely removed, the protective layer is heated to decompose the solid byproducts filled in the pinholes into gaseous substances and then be removed by suction. The chemical reaction formula of the decomposition reaction is as follows: 。 3. The method for preparing a semiconductor structure according to claim 2, characterized in that: The heating temperature of the heat treatment on the protective layer is greater than or equal to 80° C.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that: The stacked layer further includes a second sacrificial protection layer formed on the surface of the first sacrificial protection layer. Before removing the first sacrificial protection layer by using a chemical vapor etching process, the preparation method further includes: The second sacrificial protection layer is removed by a wet etching process.

5. The method for preparing a semiconductor structure according to claim 2, characterized in that: The layer to be protected is a gate oxide layer of a transistor with a surround gate vertical channel structure. A gate material layer parallel to the substrate is formed on the substrate, and a plurality of array-arranged channel holes are formed on the gate material layer. The channel holes extend in a direction perpendicular to the substrate and penetrate the gate material layer, and the stacked layer is formed at least on the sidewalls of the channel holes.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that: A first source-drain layer and a first insulating layer are also formed on the substrate, both of which are parallel to the substrate. The first insulating layer is located between the first source-drain layer and the gate material layer. The channel hole penetrates the gate material layer and extends into the first insulating layer. The first source-drain layer includes a plurality of first source-drain portions, the number of the first source-drain portions corresponds to the number of the channel holes, and two adjacent first source-drain portions are isolated by insulating materials. The steps of forming the stacked layer include: forming the to-be-protected layer, the protective layer and the first sacrificial protective layer on at least the sidewall and the bottom of the channel hole; The step of completing a preset semiconductor process on the stacked layer comprises: A dry etching process is used to remove a portion of the stacked layer and a portion of the first insulating layer located at the bottom of the channel hole and above the first source and drain portion to expose at least a portion of the upper surface of the first source and drain portion, and at the same time form a groove that penetrates the gate material layer and the first insulating layer.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that: A second insulating layer parallel to the substrate is also formed on the substrate, the gate material layer is located between the second insulating layer and the first insulating layer, the channel hole penetrates the second insulating layer and the gate material layer and extends into the first insulating layer, and the groove penetrates the second insulating layer, the gate material layer and the first insulating layer.

8. The method for preparing a semiconductor structure according to claim 2, characterized in that: The preparation method further comprises: After the solid byproducts filled in the pinholes are sublimated or decomposed into gaseous substances and then removed by suction, the protective layer is protected by a nitrogen atmosphere to prevent the polysilicon material from naturally oxidizing to form silicon oxide after the protective layer contacts the air.

9. The method for preparing a semiconductor structure according to claim 5, characterized in that: The layer to be protected includes a first layer to be protected and a second layer to be protected which are sequentially deposited on at least the sidewall and bottom of the channel hole, the material of the second layer to be protected is silicon oxide, the dielectric constant of the first layer to be protected is greater than the dielectric constant of silicon oxide, and the material of the first layer to be protected is a dielectric material with a high dielectric constant.

10. The method for preparing a semiconductor structure according to claim 6 or 7, characterized in that: The preparation method further comprises: After the solid byproducts filled in the pinholes are sublimated or decomposed into gaseous substances and then removed by suction, a channel material layer is formed on the sidewalls and bottom of the groove, the interior of the groove is surrounded by the channel material layer to form a sub-groove, and the end of the channel material layer close to the substrate is in contact with and connected to the upper surface of the first source and drain portion; Filling the sub-trench with an insulating material to form an insulating filling layer, wherein the height of the insulating filling layer is lower than or equal to the height of the uppermost side of the channel material layer; A second source-drain layer is formed on a side of the channel material layer away from the substrate, the second source-drain layer includes a plurality of second source-drain portions, the number of the second source-drain portions corresponds one-to-one to the number of the first source-drain portions, the lower surfaces of the second source-drain portions are in contact with and connected to the channel material layer and the insulating filling layer, and two adjacent second source-drain portions are isolated by insulating material.

11. A semiconductor structure, characterized in that: The semiconductor structure is manufactured by the method for manufacturing a semiconductor structure according to any one of claims 1 to 10.

Images