Semiconductor device and preparation method, power module, power conversion circuit, vehicle

Abstract

The present application provides a semiconductor device and a method for preparing the same, a power module, a power conversion circuit and a vehicle, and relates to the field of semiconductor technology. The semiconductor device includes a semiconductor body, a gate structure, a filling layer, a source and a drain. The first surface of the semiconductor body is provided with a source groove extending into the semiconductor body, and the semiconductor body also includes an insulating layer located on the inner wall of the source groove, and the insulating layer also includes at least a portion extending from the inner wall of the source groove to the outside of the source groove. The gate structure extends from the first surface into the semiconductor body. The filling layer includes a first part and a second part connected to each other, the first part is arranged in the source groove, the second part is located on a side of the first surface away from the second surface, extends toward at least one side in a first direction parallel to the first surface, and covers the insulating layer, and the material of the first part and the material of the second part are the same. The technical solution provided in the present application is intended to improve the reliability of semiconductor devices.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the same, a power module, a power conversion circuit and a vehicle. Background Art

[0002] In the preparation process of trench metal oxide semiconductor field effect transistor (Trench MOSFET), since the interlayer insulating layer and the insulating layer in the source trench are made of the same material, the insulating layer in the source trench will be over-etched during the etching of the interlayer insulating layer, so that the insulating layer in the source trench cannot cover the inner wall of the source trench, thereby causing a gap between the polysilicon (poly) in the source trench and the source trench. This gap will cause stress concentration problems in the semiconductor body, thereby adversely affecting the reliability of the semiconductor device. Summary of the invention

[0003] The present application provides a semiconductor device and a method for manufacturing the same, a power module, a power conversion circuit and a vehicle, for improving the reliability of the semiconductor device.

[0004] To achieve the above objectives, the embodiments of the present application provide the following technical solutions:

[0005] On the one hand, a semiconductor device is provided, which includes a semiconductor body, a gate structure, a filling layer, a source and a drain. The semiconductor body is set to a first conductivity type, including a first surface and a second surface arranged opposite to each other, the first surface is provided with a source trench, the source trench extends from the first surface into the semiconductor body, the semiconductor body also includes an insulating layer located on the inner wall of the source trench, and the insulating layer also includes at least a portion extending from the inner wall of the source trench to the outside of the source trench. The gate structure extends from the first surface into the semiconductor body. The filling layer includes a first part and a second part connected, the first part is arranged in the source trench, the second part is located on a side of the first surface away from the second surface, extends toward at least one side in a first direction parallel to the first surface, and covers the insulating layer, and the material of the first part is the same as the material of the second part. The source is arranged on the first surface, and the drain is arranged on the second surface.

[0006] In the above semiconductor device, the first surface of the semiconductor body is provided with a source groove extending from the first surface to the inside of the semiconductor body, and an insulating layer is provided on the inner wall of the source groove, and the insulating layer also includes at least a portion extending from the inner wall of the source groove to the outside of the source groove. It can be understood that the insulating layer at least covers the inner wall of the source groove. The filling layer includes a first part and a second part connected, and the material of the first part is the same as the material of the second part. The first part is arranged in the source groove, along the first direction, the second part extends to at least one side and covers the insulating layer, the insulating layer is located between the source groove and the filling layer, and the insulating layer at least covers the inner wall of the source groove, so that there is no gap between the filling layer and the source groove, which solves the problem of stress concentration caused by the gap in the semiconductor device, thereby improving the reliability of the semiconductor device.

[0007] In some embodiments, along the first direction, the boundary of the insulating layer is flush with or exceeds the edge of the source trench. Along the first direction, at least one side boundary of the second portion is flush with or exceeds the edge of the source trench.

[0008] In some embodiments, along the first direction, the second portion includes a first side boundary and a second side boundary, the first side boundary is flush with or exceeds the edge of the source trench, and the second side boundary is located on the inner side of the edge of the source trench, and the semiconductor device also includes an interlayer insulating layer, which is arranged between the first surface and the source, and the interlayer insulating layer is in contact with the second side boundary.

[0009] In some embodiments, along the first direction, two side boundaries of the second portion are flush with or exceed the edge of the source trench.

[0010] In some embodiments, along the first direction, when at least one side boundary of the second portion is flush with the edge of the source trench, the boundary of the second portion flush with the edge of the source trench coincides with the boundary of the insulating layer. Along the first direction, when at least one side boundary of the second portion exceeds the edge of the source trench, the boundary of the second portion exceeding the edge of the source trench coincides with the boundary of the insulating layer.

[0011] In some embodiments, along the first direction, at least one side boundary of the second portion exceeds the first portion, and a dimension of the second portion exceeding the first portion ranges from 10 nm to 2000 nm.

[0012] On the other hand, a method for preparing a semiconductor device is provided, the method comprising: forming a semiconductor body, the semiconductor body being set to a first conductive type, the semiconductor body comprising a first surface and a second surface arranged opposite to each other, the first surface also being provided with a source trench and a gate trench, the source trench extending from the first surface into the semiconductor body, and the gate trench extending from the first surface into the semiconductor body. Forming a gate structure, a filling layer and an insulating layer, the gate structure being located in the gate trench, the insulating layer being located in the inner wall of the source trench, and the insulating layer also comprising at least a portion extending from the inner wall of the source trench to outside the source trench. The filling layer comprises a first part and a second part connected to each other, the first part being located in the source trench, the second part being located on a side of the first surface away from the second surface, the second part extending toward at least one side in a first direction parallel to the first surface and covering the insulating layer, the material of the first part being the same as the material of the second part. Forming a source on the first surface, and forming a drain on the second surface.

[0013] In the above preparation method, a source groove is formed on the first surface of the semiconductor body, and an insulating layer and a filling layer are formed in the source groove. The insulating layer is located on the inner wall of the source groove and includes at least a portion extending from the inner wall of the source groove to the outside of the source groove, that is, the insulating layer at least covers the inner wall of the source groove, and the filling layer includes a first portion located in the source groove and a second portion located on a side of the first surface away from the second surface. The material of the first portion is the same as that of the second portion. The second portion extends toward at least one side in a first direction parallel to the first surface and covers the insulating layer, that is, the projection of the second portion on the second surface at least covers the projection of the source groove on the second surface, thereby protecting the insulating layer between the first portion and the source groove from being over-etched, so that there is no gap between the filling layer and the source groove, solving the problem of stress concentration caused by the gap in the semiconductor device, and thus improving the reliability of the semiconductor device.

[0014] In some embodiments, forming a filling layer and an insulating layer includes forming an insulating film and a filling portion, wherein the insulating film covers the inner wall and the first surface of the source trench, and the filling portion covers the insulating film. A mask layer covering the filling portion is formed, and along the first direction, at least one side boundary of the mask layer is flush with or exceeds the edge of the source trench. The mask layer is used as a mask to etch the filling portion, and the etched filling portion serves as the filling layer.

[0015] In some embodiments, after forming the filling layer, the preparation method further includes forming an interlayer insulating film, wherein the interlayer insulating film covers the filling layer and the insulating film. The filling layer is used as an etching stop layer, the interlayer insulating film and the insulating layer are etched, and a portion of the insulating film covered by the filling layer is retained, and the etched insulating film is used as the insulating layer, and the etched interlayer insulating film is used as the interlayer insulating layer.

[0016] In yet another aspect, a power module is provided. The power module includes a substrate and a semiconductor device according to any one of the above embodiments. The substrate is used for carrying the semiconductor device.

[0017] In another aspect, a power conversion circuit is provided, which is used for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and a semiconductor device as described in any of the above embodiments, wherein the semiconductor device is electrically connected to the circuit board.

[0018] On the other hand, a vehicle is provided, which includes a load and a power conversion circuit as described in the above embodiment, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0019] The above-mentioned power module, power conversion circuit and vehicle have the same structure and beneficial technical effects as the semiconductor devices provided in some of the above-mentioned embodiments, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the present application, the following is a brief introduction to the drawings required for use in some embodiments of the present application. Obviously, the drawings described below are only drawings of some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not intended to limit the actual size of the product involved in the embodiments of the present application, the actual process of the method, the actual timing of the signal, etc.

[0021] Figure 1 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application;

[0022] Figure 2 A schematic diagram of the structure of another semiconductor device provided in an embodiment of the present application;

[0023] Figure 3 A flow chart of the preparation method provided in the embodiments of the present application;

[0024] Figure 4 for Figure 3 Flow chart of some specific steps of step S2;

[0025] Figure 5~Figure 17 A diagram of each step of the preparation method provided in the embodiment of the present application;

[0026] Fig.18 A schematic diagram of the structure of a power module provided in an embodiment of the present application;

[0027] Fig.19A schematic diagram of the structure of a power conversion circuit provided in an embodiment of the present application;

[0028] Fig. 20 A schematic diagram of the structure of a vehicle provided in an embodiment of the present application. DETAILED DESCRIPTION

[0029] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0030] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0031] In the description of the present application, “plurality” means two or more.

[0032] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0033] On the one hand, an embodiment of the present application provides a semiconductor device, Figure 1 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, the semiconductor device 1 is a trench metal oxide semiconductor field effect transistor (Trench MOSFET), and the semiconductor device 1 includes a semiconductor body, a gate structure 11 , a filling layer 12 , a source 13 and a drain 14 .

[0034] The semiconductor body is set to a first conductivity type, the semiconductor body includes a first surface 101 and a second surface 102 arranged opposite to each other, the first surface 101 is provided with a source trench 121, the source trench 121 extends from the first surface 101 into the semiconductor body, the semiconductor body also includes a first insulating layer 122 arranged in the source trench 121, and the first insulating layer 122 also includes at least a portion extending from the inner wall of the source trench 121 to the outside of the source trench 121. It can be understood that the first insulating layer 122 covers the inner wall of the source trench 121 and extends out of the source trench 121, and exceeds the source trench 121 in the direction Z, or, as Figure 1 As shown, along a first direction X parallel to the first surface 101, at least one side boundary of the first insulating layer 122 is flush with or exceeds the edge of the source trench 121, that is, the first insulating layer 122 covers the inner wall of the source trench 121, exceeds the source trench 121 in the direction Z, and covers the portion of the first surface 101 close to the source trench 121 along the first direction X.

[0035] For example, Figure 1 As shown, the semiconductor body includes a silicon carbide substrate 103 and an epitaxial layer 104 stacked on the silicon carbide substrate 103, the "first surface 101" is the surface of the epitaxial layer 104 away from the silicon carbide substrate 103, and the "second surface 102" is the surface of the silicon carbide substrate 103 away from the epitaxial layer 104.

[0036] The semiconductor body further includes a well region 105, a first region 106, and a second region 107, and the well region 105, the first region 106, and the second region 107 can all be arranged in the epitaxial layer 104. The first region 106 is located on the first surface 101 and is set to the first conductivity type, the well region 105 is located on a side of the first region 106 away from the first surface 101, and is set to the second conductivity type, and the second region 107 is located on the first surface 101 and is located outside the first region 106 and the well region 105, and the second region 107 is set to the first conductivity type.

[0037] For example, P-type ions are injected into the well region 105 and the second region 107, and the conductivity types of both are P-type. The well region 105 can also be called a "P-type well region (P-well)", and the second region 107 can also be called a "P+ contact region". The conductivity types of the silicon carbide substrate 103, the epitaxial layer 104, and the first region 106 are all N-type, and N-type ions are injected into the first region 106. The first region 106 can also be called an "N+ contact region".

[0038] Continue to see Figure 1The first surface 101 is further provided with a gate trench 111, the gate trench 111 extends from the first surface 101 into the semiconductor body and penetrates the first region 106 and the well region 105, and the semiconductor body further includes a second insulating layer 112 disposed in the gate trench 111. The gate structure 11 is disposed in the gate trench 111 and extends from the first surface 101 into the semiconductor body, and the second insulating layer 112 is located between the gate structure 11 and the gate trench 111.

[0039] The source trench 121 extends from the first surface 101 to the second region 107, and the first insulating layer 122 is disposed between the filling layer 12 and the source trench 121. The filling layer 12 includes a first portion 123 and a second portion 124 connected to each other, and the first portion 123 is disposed in the source trench 121. Figure 1 For example, taking the second surface 102 as a reference plane, along the first direction Z, the first portion 123 includes a portion located in the source trench 121 and a portion flush with the first insulating layer 122. The material of the first portion 123 of the filling layer 12 is the same as the material of the second portion 124 of the filling layer 12. Exemplarily, the filling layer 12 can be any one of silicon nitride (SiN), oxide (Oxide), carbon (Carbon), and silicon oxynitride (SiON).

[0040] The second portion 124 is located on a side of the first surface 101 away from the second surface 102, extends toward at least one side in the first direction X, and covers the first insulating layer 122. It can be understood that at least one side boundary of the second portion 124 is flush with or exceeds the edge of the source groove 121, and at least one side boundary of the first insulating layer 122 is flush with or exceeds the edge of the source groove 121, so that the width of the second portion 124 along the first direction X is greater than or equal to the width of the first portion 123 along the first direction X, that is, the filling layer 12 has a "boss" morphology with the second portion 124 protruding.

[0041] It can be understood that the inner boundary B of the second portion 124 is flush with or exceeds the edge E of the source trench 121, in which case the inner side of the second portion 124 protrudes, or the outer boundary A of the second portion 124 is flush with or exceeds the edge E of the source trench 121, in which case the outer side of the second portion 124 protrudes, or both the outer boundary A and the inner boundary B of the second portion 124 are flush with or exceed the edge E of the source trench 121, in which case both sides of the second portion 124 protrude.

[0042] In some embodiments, Figure 1 As shown, along the first direction X, both side boundaries of the second portion 124 are flush with or beyond the edge of the source trench 121. Figure 1 The example in which both the outer boundary A and the inner boundary B of the second portion 124 exceed the edge of the source trench 121 is used for explanation. Since both side boundaries of the second portion 124 of the filling layer 12 are flush with the edge of the source trench 121, or exceed the edge of the source trench 121, and the first insulating layer 112 is located between the source trench 121 and the filling layer 12, that is, the first insulating layer 122 covers the inner wall of the entire source trench 121, there is no gap between the filling layer 12 and the source trench 121, which solves the problem of stress concentration caused by the gap in the semiconductor device 1, thereby improving the reliability of the semiconductor device 1.

[0043] The source electrode 13 is disposed on the first surface 101 and is electrically connected to the first region 106 and the second region 107. The drain electrode 14 is disposed on the second surface 102. Exemplarily, an ohmic contact layer 131 is further disposed between the source electrode 13 and the semiconductor body. The ohmic contact layer 131 may be any one of nickel (Ni), nickel titanium (Ni-Ti), nickel platinum (Ni-Pt), cobalt (Co), and nickel titanium (TiAl). The source electrode 13 is electrically connected to the first region 106 and the second region 107 through the ohmic contact layer 131.

[0044] By transmitting a turn-on voltage to the gate structure 11 , when the semiconductor device 1 is forward-conducting and the operating current is small, the operating current flows from the source 13 through the ohmic contact layer 131 , the first region 106 , the well region 105 , the epitaxial layer 104 and the silicon carbide substrate 103 to the drain 14 .

[0045] Since the P-type ion concentration in the second region 107 is higher than that in the well region 105 , more PN junctions are formed between the second region 107 and the epitaxial layer 104 . When the working current is large, the working current flows from the source 13 through the ohmic contact layer 131 , the second region 12 , the epitaxial layer 104 , and the silicon carbide substrate 103 to the drain 14 , thereby preventing the large working current from flowing through the well region 105 , thereby protecting the channel in the well region 105 .

[0046] In the above semiconductor device, the first surface 101 of the semiconductor body is provided with a source trench 121 extending from the first surface 101 to the inside of the semiconductor body, and a first insulating layer 122 arranged on the inner wall of the source trench 121, and the first insulating layer 122 also includes at least a portion extending from the inner wall of the source trench 121 to the outside of the source trench 121. It can be understood that the first insulating layer 122 at least covers the inner wall of the source trench 121. The filling layer 12 includes a first portion 123 and a second portion 124 connected to each other, the first portion 123 is arranged in the source trench 121, along the first direction X, the second portion 124 extends to at least one side and covers the first insulating layer 122, the first insulating layer 112 is located between the source trench 121 and the filling layer 12, and the first insulating layer 112 at least covers the inner wall of the source trench 121, so that there is no gap between the filling layer 12 and the source trench 121, which solves the problem of stress concentration caused by the gap in the semiconductor device 1, thereby improving the reliability of the semiconductor device 1.

[0047] Exemplarily, the semiconductor device 1 also includes a protective layer 19, which is arranged on a side of the source 13 away from the semiconductor body. The protective layer 19 includes a stacked passivation (PA) layer and a polyimide (PI) layer. The PA layer is used to protect the semiconductor device 1 from environmental influences, and the PI layer is used for electrical isolation to ensure the normal operation of the semiconductor device 1.

[0048] Figure 2 A schematic diagram of the structure of another semiconductor device provided in an embodiment of the present application is shown in FIG. Figure 2 As shown, the semiconductor device 1 is another structure of a trench metal oxide semiconductor field effect transistor (Trench MOSFET).

[0049] In some embodiments, along the first direction X, the second portion 124 includes a first side boundary and a second side boundary, the first side boundary is flush with or exceeds the edge E of the source trench 121, and the second side boundary is located inside the edge E of the source trench 121. The semiconductor device 1 also includes an interlayer insulating layer 15, which is disposed between the first surface 101 and the source 13, and the interlayer insulating layer 15 is in contact with the second side boundary. This structure can ensure the electrical connection between the source 13 and the first region 106 and the second region 107, and avoid the existence of a gap between the filling layer 12 and the source trench 122.

[0050] The first side boundary can be the outer boundary A or the inner boundary B, such as Figure 2As shown, in the case where the first side boundary is the outer side boundary A, the first side boundary is flush with or exceeds the edge E of the source trench 121, and the outer side of the second portion 124 protrudes to cover the first insulating layer 122 in the source trench 121, so that there is no gap between the filling layer 12 on the side (outer side) away from the gate structure 11 and the source trench 121. In this case, the second side boundary is the inner side boundary B, and the second side boundary is in contact with the interlayer insulating layer 15. There is no gap between the filling layer 12 on the side (inner side) close to the gate structure 11 and the source trench 121, which ensures that the first insulating layer 122 fills the space between the source trench 121 and the filling layer 12, avoiding stress concentration caused by the gap in the semiconductor device 1, and improving the reliability of the semiconductor device 1.

[0051] Similarly, when the first side boundary is the inner boundary B, the second side boundary is the outer boundary A, the second side boundary is flush with or exceeds the edge E of the source trench 121, the inner side of the second portion 124 protrudes, and the outer side of the second portion 124 (the second side boundary) contacts the interlayer insulating layer 15, which can also ensure that the first insulating layer 122 fills the space between the source trench 121 and the filling layer 12, thereby avoiding stress concentration caused by gaps in the semiconductor device 1 and improving the reliability of the semiconductor device 1.

[0052] In some embodiments, Figure 1 and Figure 2 As shown, along the first direction X, when at least one side boundary of the second portion 124 is flush with the edge E of the source trench 121, the boundary of the second portion 124 flush with the edge E of the source trench 121 coincides with the boundary F of the first insulating layer 122; along the first direction X, when at least one side boundary of the second portion 124 exceeds the edge E of the source trench 121, the boundary of the second portion 124 exceeding the edge E of the source trench 121 coincides with the boundary F of the first insulating layer 122.

[0053] It can be understood that, when the inner boundary B is flush with the edge E of the source trench 121, the inner boundary B coincides with the boundary F of the first insulating layer 122, or, when the inner boundary B exceeds the edge E of the source trench 121, the inner boundary B coincides with the boundary F of the first insulating layer 122, in which case the second portion 124 is an inner protrusion. Alternatively, when the outer boundary A is flush with the edge E of the source trench 121, the outer boundary A coincides with the boundary F of the first insulating layer 122, or, when the outer boundary A exceeds the edge E of the source trench 121, the outer boundary A coincides with the boundary F of the first insulating layer 122, in which case the second portion 124 is an outer protrusion. Alternatively, both side boundaries of the second portion 124 are flush with the edge E of the source trench 121 or exceed the edge E of the source trench 121, in which case both sides of the second portion 124 are protruding.

[0054] Regardless of whether the second portion 124 protrudes on the outside, the inside, or both sides, the boundary of one protruding side coincides with the boundary F of the first insulating layer 122, that is, the first insulating layer 122 includes a portion located in the source trench 121 and a portion located between the source trench 121 and the filling layer 12, further avoiding the occurrence of stress concentration problems caused by the gap and improving the reliability of the semiconductor device 1.

[0055] In some embodiments, Figure 1 and Figure 2 As shown, along the first direction X, at least one side boundary of the second portion 124 exceeds the first portion 123. Figure 1 The outer boundary A and the inner boundary B of the second portion 124 both exceed the first portion 123. Figure 2 The outer boundary A of the second portion 124 exceeds the first portion 123, and the inner boundary B is flush with the first portion 123. The size range of the second portion 124 exceeding the first portion 123 is 10nm~2000nm. For example, the size of the second portion 124 exceeding the first portion 123 can be 10nm, 507.5nm, 1005nm, 1502.5nm, 2000nm. Within this size range, while eliminating the gap between the filling layer 12 and the source trench 122, which causes the reliability of the semiconductor device 1 to be reduced, the conductive performance of the semiconductor device 1 can be better guaranteed.

[0056] For example, Figure 1 and Figure 2 As shown, along the direction Z, the thickness of the second portion 124 ranges from 10 nm to 3000 nm. For example, the thickness of the second portion 124 may be 10 nm, 757.5 nm, 1505 nm, 2252.5 nm, or 3000 nm.

[0057] For example, along the direction Z, the thickness of the second portion 124 may decrease sequentially to form a bull horn morphology.

[0058] On the other hand, a method for preparing a semiconductor device is also provided. Figure 3 A flow chart of the preparation method provided in the embodiments of the present application; Figure 4 for Figure 3 Flow chart of some specific steps of step S2; Figure 5~Figure 17 A diagram of each step of the preparation method provided in the embodiments of the present application.

[0059] like Figure 4 As shown, the preparation method includes the following steps S1 to S4:

[0060] Step S1: Figure 5~Figure 8As shown, a semiconductor body is formed, and the semiconductor body is set to a first conductive type. The semiconductor body includes a first surface 101 and a second surface 102 that are relatively set. The first surface 101 is also provided with a source trench 121 and a gate trench 111. The source trench 121 extends from the first surface 102 into the semiconductor body, and the gate trench 111 extends from the first surface 101 into the semiconductor body.

[0061] Step S1 is specifically as follows: Figure 5 As shown, an epitaxial layer 104 is formed on a silicon carbide substrate 103, the silicon carbide substrate 103 and the epitaxial layer 104 are set to be of the first conductivity type, the side of the epitaxial layer 104 away from the silicon carbide substrate 103 is a first surface 101, and the side of the silicon carbide substrate 103 away from the epitaxial layer 104 is a second surface 102. Then as Figure 6 As shown, ions of the first conductivity type and the second conductivity type are implanted into the first surface 101 to form a well region 105 and a first region 106. The first region 106 is located on the first surface 101 and is set to the first conductivity type. The well region 105 is located on a side of the first region 106 away from the first surface 101 and is set to the second conductivity type.

[0062] Then as Figure 7 As shown, a gate trench 111 and source trenches 121 located on both sides of the gate trench 111 are formed on the first surface 101, and then Figure 8 As shown, ions of the second conductivity type are implanted on the surface of the source trench 121 to form the second region 107 , wherein the concentration of the second conductivity type ions in the second region 107 is greater than the concentration of the second conductivity type ions in the well region 105 .

[0063] For example, P-type ions are injected into the well region 105 and the second region 107, and the conductivity types of both are P-type. The well region 105 can also be called a "P-type well region (P-well)", and the second region 107 can also be called a "P+ contact region". The conductivity types of the silicon carbide substrate 103, the epitaxial layer 104, and the first region 106 are all N-type, and N-type ions are injected into the first region 106. The first region 106 can also be called an "N+ contact region".

[0064] Step S2: Figure 9~Figure 15As shown, a gate structure 11, a second insulating layer 112, a filling layer 12 and a first insulating layer 122 are formed, the gate structure 11 is located in the gate trench 111, the second insulating layer 112 is located between the gate structure 11 and the gate trench 111, the first insulating layer 122 is located on the inner wall of the source trench 121, and the first insulating layer 122 also includes at least a portion extending from the inner wall of the source trench 121 to the outside of the source trench 121. The filling layer 12 includes a first portion 123 and a second portion 124 connected to each other, the material of the first portion 123 and the material of the second portion 124 are the same, the first portion 123 is located in the source trench 121, the second portion 124 is located on a side of the first surface 101 away from the second surface 102, and the second portion 124 extends toward at least one side in a first direction X parallel to the first surface 101 and covers the first insulating layer 121.

[0065] It can be understood that the first insulating layer 122 covers the inner wall of the source trench 121 and extends out of the source trench 121, and exceeds the source trench 121 in the direction Z, or, along the first direction X, at least one side boundary of the first insulating layer 122 is flush with the edge E of the source trench 121 or exceeds the edge E of the source trench 121, that is, the first insulating layer 122 covers the inner wall of the source trench 121, exceeds the source trench 121 in the direction Z, and covers the portion of the first surface 101 close to the source trench 121 along the first direction X. In some embodiments, as Figure 4 As shown, the specific steps of forming the filling layer and the insulating layer include the following steps S201 to S204:

[0066] Step S201: Fig. 9 As shown, an insulating film 16 is formed, and the insulating film 16 covers the inner wall of the source trench 121 and the first surface 101, and then Fig.10 As shown, a filling portion 17 covering the insulating film 16 is formed. Exemplarily, the filling portion 17 may be any one of silicon nitride (SiN), oxide (Oxide), carbon (Carbon), and silicon oxynitride (SiON).

[0067] Step S202: Fig.11 As shown, the side of the filling portion 17 away from the insulating film 16 is etched (Etch) to flatten the side of the filling portion 17 away from the insulating film 16, and then as shown in Fig.12 As shown, a mask layer 18 covering the filling portion 17 is formed, and along the first direction X, at least one side boundary of the mask layer 18 is flush with or exceeds the edge E of the source trench 121, that is, the projection of the mask layer 18 on the plane XY covers the projection of the source trench 121 on the plane XY, and then dry etching is used to etch the filling portion 17 with the mask layer 18 as a mask to form a Fig.13The filling layer 12 and the gate structure 11 are shown, wherein the filling layer 12 includes a first portion 123 located in the source trench 121, and a second portion 124 located on the side of the first surface 101 away from the second surface 102, the first portion 123 and the second portion 124 are formed simultaneously and are made of the same material, and the first portion 123 and the second portion 124 together constitute the filling layer 12 with a "boss" morphology.

[0068] Since the projection of the mask layer 18 on the plane XY covers the projection of the source trench 121 on the plane XY, the projection of the second portion 124 of the filling layer 12 formed by etching the filling portion 17 through the mask layer 18 on the plane XY also covers the projection of the source trench 121 on the plane XY, that is, at least one side boundary of the second portion 124 is flush with or exceeds the edge E of the source trench 121. After the filling layer 12 with a "boss" morphology is formed, the mask layer 18 is removed.

[0069] Step S203: Fig.14 As shown, after forming the filling layer 12 and the gate structure 13, an interlayer insulating film 151 is formed, and the interlayer insulating film 151 covers the filling layer 12 and the insulating film 16. The interlayer insulating film 151 and the insulating film 16 can be made of the same material, both of which can be silicon oxide.

[0070] Step S204: Fig.15 As shown, the filling layer 12 is used as an etching stop layer, and the interlayer insulating film 151 and the insulating film 16 are etched, and the part of the insulating film 16 covered by the filling layer 12 is retained. The insulating film 16 after etching is used as the first insulating layer 122 and the second insulating layer 112, and the interlayer insulating film 151 after etching is used as the interlayer insulating layer 15. Exemplarily, the process of etching the interlayer insulating film 151 adopts contact hole etching, that is, CT etching (Contact Etch), and the interlayer insulating layer 15 covers the gate structure 11 and exposes the second part 124 of the filling layer 12 as a "boss". Since the interlayer insulating film 151 and the insulating film 16 are made of the same material, the insulating film 16 will also be etched during the etching of the interlayer insulating film 16. In this process, the second part 124 of the filling layer 12 is used as a mask to etch the insulating film 16 to form the first insulating layer 122 and the second insulating layer 112.

[0071] In the embodiment provided in the present application, since the projection of the second portion 124 of the filling layer 12 on the plane XY covers the projection of the source groove 121 on the plane XY, in the process of etching the insulating film 16 using the second portion 124 as a mask, the first insulating layer 122 located between the source groove 121 and the filling layer 12 will not be over-etched, so that there is no gap between the source groove 121 and the filling layer 12, thereby solving the problem of stress concentration caused by the gap in the semiconductor device 1, thereby improving the reliability of the finally prepared semiconductor device.

[0072] Step S3: Fig.16 As shown, a source electrode 13 is formed on the first surface 101, the source electrode 13 is electrically connected to the first region 106 and the second region 107, and the interlayer insulating layer 15 is located between the source electrode 13 and the gate structure 11. Exemplarily, an ohmic contact layer 131 is also formed between the source electrode 13 and the semiconductor body, and the ohmic contact layer 131 can be any one of nickel (Ni), nickel titanium (Ni-Ti), nickel platinum (Ni-Pt), cobalt (Co), and nickel titanium (TiAl). The source electrode 13 is electrically connected to the first region 106 and the second region 12 through the ohmic contact layer 131.

[0073] Step S4: Fig.17 As shown, a drain 14 is formed on the second surface 102 .

[0074] Exemplarily, after forming the drain electrode 14, a protective layer 19 is formed on the side of the source electrode 13 away from the interlayer insulating layer 15 to form a Figure 1 The semiconductor device (Trench MOSFET) 1 shown in FIG. The protection layer 19 includes a stacked passivation (PA) layer and a polyimide (PI) layer, wherein the PA layer is used to protect the semiconductor device 1 from environmental influences, and the PI layer is used for electrical isolation to ensure the normal operation of the semiconductor device 1 .

[0075] By transmitting a turn-on voltage to the gate structure 11 , when the semiconductor device 1 is forward-conducting and the operating current is small, the operating current flows from the source 13 through the ohmic contact layer 131 , the first region 106 , the well region 105 , the epitaxial layer 104 and the silicon carbide substrate 103 to the drain 14 .

[0076] Since the P-type ion concentration in the second region 107 is higher than that in the well region 105 , more PN junctions are formed between the second region 107 and the epitaxial layer 104 . When the working current is large, the working current flows from the source 13 through the ohmic contact layer 131 , the second region 12 , the epitaxial layer 104 , and the silicon carbide substrate 103 to the drain 14 , thereby preventing the large working current from flowing through the well region 105 , thereby protecting the channel in the well region 105 .

[0077] In the preparation method provided in the embodiment of the present application, a source trench 121 is formed on the first surface 101 of the semiconductor body, and a first insulating layer 122 and a filling layer 12 are formed in the source trench 121, and the first insulating layer 122 is located between the filling layer 12 and the source trench 121, and along a first direction X parallel to the first surface 101, at least one side boundary of the first insulating layer 122 is flush with or exceeds the edge E of the source trench 121. The filling layer 12 includes a first portion 123 located in the source groove 121, and a second portion 124 located on a side of the first surface 101 away from the second surface 102, wherein at least one side boundary of the second portion 124 is flush with an edge E of the source groove 121 or exceeds the edge E of the source groove 12, that is, the projection of the second portion 124 on the second surface 102 at least covers the projection of the source groove 12 on the second surface 102, thereby protecting the first insulating layer 122 located between the first portion 123 and the source groove 121 from being over-etched, so that there is no gap between the filling layer 12 and the source groove 121, thereby solving the problem of stress concentration caused by the gap in the semiconductor device 1, thereby solving the problem of stress concentration on the semiconductor device 1 due to the gap, and further improving the reliability of the semiconductor device 1.

[0078] In another aspect, an embodiment of the present application further provides a power module, Fig.18 A schematic diagram of the structure of a power module provided in an embodiment of the present application.

[0079] See also Fig.18 The power module 2 includes a substrate 21 and the semiconductor device 1 in any of the above embodiments, and the substrate 21 is used to carry the semiconductor device 1.

[0080] Exemplarily, the power module 2 can be used as one of a power amplifier, a power converter, a power controller, a power management module, or a power regulator. The power amplifier is used to amplify the power of an electrical signal. The power converter is used to convert electrical energy from one form to another form. For example, the power converter can be an AC / DC converter or a DC / DC converter. The power controller is used to control the device of power flow. The power management module is used to manage the power supply to ensure that the power is stably and efficiently distributed to different parts of the electronic device. The power regulator is used to adjust the power output to meet the needs of a specific application.

[0081] On the other hand, an embodiment of the present application further provides a power conversion circuit, Fig.19 A schematic diagram of the structure of a power conversion circuit provided in an embodiment of the present application.

[0082] See also Fig.19The power conversion circuit 3 includes a circuit board 31 and a semiconductor device 1 in any of the above embodiments. The semiconductor device 1 is electrically connected to the circuit board 31. The power conversion circuit 3 can be used for current conversion, voltage conversion or power factor correction.

[0083] Exemplarily, the power conversion circuit 3 can be used as one of an AC / DC converter, an AC / AC converter, a DC / DC converter, a DC / AC inverter or a power factor correction (PFC) circuit, wherein the AC / DC converter is used to convert alternating current into direct current, the AC / AC converter is used to convert alternating current into alternating current, the DC / DC converter is used to convert direct current into direct current, the DC / AC inverter is used to convert direct current into alternating current, and the power factor correction circuit is used to improve the power factor of the power supply and reduce the harmonic pollution of the power grid.

[0084] In another aspect, an embodiment of the present application further provides a vehicle, Fig. 20 A schematic diagram of the structure of a vehicle provided in an embodiment of the present application.

[0085] See also Fig. 20 The vehicle 4 includes a load 41 and the power conversion circuit 3 in the above embodiment, and the power conversion circuit 3 is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power, and then input it into the load 41 to power the load 41.

[0086] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor body, the semiconductor body is set to a first conductivity type, including a first surface and a second surface arranged opposite to each other, the first surface is provided with a source trench, the source trench extends from the first surface into the semiconductor body; the semiconductor body also includes an insulating layer located on an inner wall of the source trench, the insulating layer also includes at least a portion extending from the inner wall of the source trench to outside the source trench; a gate structure extending from the first surface into the semiconductor body; a filling layer, comprising a first portion and a second portion connected to each other; the first portion is disposed in the source trench; the second portion is located on a side of the first surface away from the second surface, extends toward at least one side in a first direction parallel to the first surface, and covers the insulating layer; the material of the first portion is the same as that of the second portion; A source electrode, disposed on the first surface; The drain is disposed on the second surface.

2. The semiconductor device according to claim 1, wherein: Along the first direction, the boundary of the insulating layer is flush with or exceeds the edge of the source trench; Along a first direction parallel to the first surface, at least one side boundary of the second portion is flush with or exceeds an edge of the source trench.

3. The semiconductor device according to claim 2, characterized in that Along the first direction, the second portion includes a first side boundary and a second side boundary, the first side boundary is flush with or exceeds the edge of the source trench, and the second side boundary is located inside the edge of the source trench; The semiconductor device further includes an interlayer insulating layer, which is disposed between the first surface and the source electrode, and the interlayer insulating layer is in contact with the second side boundary.

4. The semiconductor device according to claim 2, characterized in that Along the first direction, two side boundaries of the second portion are flush with or exceed the edge of the source trench.

5. The semiconductor device according to claim 2, wherein: Along the first direction, when at least one side boundary of the second portion is flush with an edge of the source trench, a boundary of the second portion that is flush with the edge of the source trench coincides with a boundary of the insulating layer; Along the first direction, when at least one side boundary of the second portion exceeds an edge of the source trench, the boundary of the second portion exceeding the edge of the source trench coincides with a boundary of the insulating layer.

6. The semiconductor device according to claim 2, wherein: Along the first direction, at least one side boundary of the second portion exceeds the first portion, and a size range of the second portion exceeding the first portion is 10 nm to 2000 nm.

7. A method for preparing a semiconductor device, characterized in that: include: forming a semiconductor body, wherein the semiconductor body is set to a first conductivity type, the semiconductor body comprises a first surface and a second surface arranged opposite to each other, the first surface is further provided with a source trench and a gate trench, and the source trench extends from the first surface into the semiconductor body; The gate trench extends from the first surface into the semiconductor body; forming a gate structure, an insulating layer and a filling layer, wherein the gate structure is located in the gate trench; The insulating layer is located on the inner wall of the source trench, and the insulating layer also includes at least a portion extending from the inner wall of the source trench to the outside of the source trench; the filling layer includes a first portion and a second portion connected to each other, the first portion is located in the source trench, the second portion is located on a side of the first surface away from the second surface, the second portion extends toward at least one side in a first direction parallel to the first surface and covers the insulating layer; the material of the first portion is the same as the material of the second portion; forming a source electrode on the first surface; A drain electrode is formed on the second surface.

8. The preparation method according to claim 7, characterized in that: The filling layer and the insulating layer are formed, comprising: forming an insulating film and a filling portion, wherein the insulating film covers the inner wall of the source trench and the first surface, and the filling portion covers the insulating film; forming a mask layer covering the filling portion, wherein along the first direction, at least one side boundary of the mask layer is flush with or exceeds the edge of the source trench; The mask layer is used as a mask to etch the filling portion, and the etched filling portion serves as the filling layer.

9. The preparation method according to claim 8, characterized in that: After forming the filling layer, the preparation method further comprises: forming an interlayer insulating film, the interlayer insulating film covering the filling layer and the insulating film; The filling layer is used as an etching stop layer, and the interlayer insulating film and the insulating layer are etched, and the portion of the insulating film covered by the filling layer is retained. The insulating film after etching is used as the insulating layer, and the interlayer insulating film after etching is used as the interlayer insulating layer.

10. A power module, characterized in that: include: At least one semiconductor device according to any one of claims 1 to 6; A substrate is used to carry the semiconductor device.

11. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device according to any one of claims 1 to 6, wherein the semiconductor device is electrically connected to the circuit board.

12. A vehicle, characterized in that: include: A load and a power conversion circuit as claimed in claim 11, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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