Power semiconductor device and preparation method thereof

Abstract

The invention relates to the technical field of semiconductor devices, in particular to a power semiconductor device and a preparation method of the power semiconductor device. The power semiconductor device comprises a substrate, the substrate is provided with an active region, the active region comprises a source region and a drain region, a gate trench is formed between the source region and the drain region, and the gate trench is recessed from the upper surface of the substrate to the active region; the main grid electrode is located in the grid electrode groove, and the main grid electrode extends downwards from the upper surface of the grid electrode groove; and the insulating layer is filled between the inner wall of the gate trench and the main gate. The length of the drift region between the source region and the drain region is converted from the transverse size between the source region and the drain region to the perimeter of the gate trench, so that the transverse size of the power semiconductor device can be reduced while the BV is ensured, and the specific on-resistance (Rsp) of the power semiconductor device is reduced at the same time. The size of the power semiconductor device is reduced, and the optimal BV / Rsp compromise is realized.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular to a power semiconductor device and a method for preparing the power semiconductor device. Background Art

[0002] Power semiconductor devices, also known as power electronic devices, are high-power electronic devices mainly used in power conversion and control circuits of power equipment. For high current and high-frequency transistor applications, power semiconductor devices with low Qg (gate charge) and high robustness are required to achieve high efficiency in a small size range.

[0003] In the related art, a power semiconductor device is provided with a source, a drain and a main gate, and the main gate is located between the source and the drain. When the main gate is externally connected to a voltage, conduction between the source and the drain can be achieved.

[0004] However, for a target breakdown voltage (BV), the interval between the source and the drain cannot be infinitely reduced, resulting in the inability to effectively reduce the size of the power semiconductor device. Summary of the invention

[0005] Based on this, the present application provides a power semiconductor device and a method for preparing the power semiconductor device to solve the problem in the related art that the spacing between the source and the drain is limited by the BV, resulting in the inability to effectively reduce the size of the power semiconductor device.

[0006] In one aspect, the present application provides a power semiconductor device.

[0007] include:

[0008] A substrate having an active region, wherein the active region includes a source region and a drain region of a first doping type located on an upper surface of the substrate, a gate trench is formed between the source region and the drain region, and the gate trench is recessed from the upper surface of the substrate toward the active region;

[0009] A main gate is located in the gate trench, and the main gate extends downward from the upper surface of the gate trench;

[0010] The insulating layer is filled between the inner wall of the gate trench and the main gate.

[0011] In a possible implementation, the main gate is closer to the source region than to the drain region.

[0012] In a possible implementation, the method further includes:

[0013] A source electrode is disposed on the upper surface of the substrate and is electrically connected to the source region;

[0014] The drain is arranged on the upper surface of the substrate and is electrically connected to the drain region.

[0015] In a possible implementation, the power semiconductor device further includes at least one shielding gate, wherein the shielding gate is located in the gate trench;

[0016] The shielding grid is located at the bottom of the main grid and is spaced apart from the main grid;

[0017] The shielding gate is located on a side of the main gate close to the drain region.

[0018] In a possible implementation, a first distance exists between the shielding gate and an inner wall of the gate trench close to the source region;

[0019] A second distance exists between the shielding gate and the inner wall of the gate trench close to the drain region;

[0020] The first spacing is equal to the second spacing.

[0021] In a possible implementation, there are multiple shielding gates, and the multiple shielding gates are arranged at intervals along the thickness direction of the substrate.

[0022] In a possible implementation, the active region further includes a first doping region of a first doping type, and the first doping region is disposed around a side and a bottom of the gate trench.

[0023] In a possible implementation, the active region further includes a second doping region of a second doping type, and the second doping region is disposed around a sidewall and a bottom of the first doping region.

[0024] In a possible implementation, the active region further includes a heavily doped buffer region of the first doping type, the heavily doped buffer region is located at the bottom of the drain region, and the ion doping concentration of the heavily doped buffer region is lower than the ion doping concentration of the drain region.

[0025] In a possible implementation, the active region further includes a body region of the second doping type, the body region is located at the bottom of the source region, and the side edges of the body region and the side edges of the source region form a portion of the inner wall of the gate trench.

[0026] In a possible implementation manner, the cross section of the gate trench is one of a U-shape, a rectangle, and a trapezoid.

[0027] On the other hand, the present application also provides a method for preparing a power semiconductor device, comprising:

[0028] providing a substrate;

[0029] forming an active region in a substrate;

[0030] Forming a gate trench recessed toward the active area on the upper surface of the substrate;

[0031] filling an insulating layer in the gate trench;

[0032] forming a main gate in the insulating layer, the main gate extending from the upper surface of the gate trench to the inside thereof;

[0033] A source region and a drain region are formed on the upper surface of the active region, and a gate trench is located between the source region and the drain region.

[0034] In a possible implementation manner, before forming the main gate in the insulating layer, the method further includes:

[0035] forming a shielding gate in the insulating layer;

[0036] Wherein, the shielding grid is located at the bottom of the main grid and is spaced apart from the main grid;

[0037] The shielding gate is located on a side of the main gate close to the drain region.

[0038] In a possible implementation, the main gate is closer to the source region than to the drain region.

[0039] In a possible implementation, the method further includes:

[0040] Forming a source electrode on the upper surface of the substrate, wherein the source electrode is electrically connected to the source region;

[0041] A drain is formed on the upper surface of the substrate, wherein the drain is electrically connected to the drain region.

[0042] In a possible implementation, after forming the gate trench and before forming the source region and the drain region,

[0043] A first doping region is formed in the active region, and the first doping region is arranged around the side and bottom of the gate trench, wherein the doping concentration of the first doping region is greater than the doping concentration of the active region of the first doping type.

[0044] In a possible implementation manner, before forming the first doping region, the method further includes:

[0045] forming a second doping region in the active region, wherein the second doping region surrounds the sidewall and the bottom of the first doping region;

[0046] The first doping region and the second doping region have different ion doping types.

[0047] In a possible implementation, the method further includes:

[0048] A heavily doped buffer zone is formed in the active region, wherein the ion doping concentration of the heavily doped buffer zone is lower than the ion doping concentration of the drain region, wherein the drain region is located in the heavily doped buffer zone.

[0049] In a possible implementation, the method further includes:

[0050] A body region is formed in the active region, the body region is located at the bottom of the source region, and the side edges of the body region and the side edges of the source region form a part of the inner wall of the gate trench.

[0051] In a possible implementation, the body region is formed by ion implantation or ion implantation heating diffusion, and the gate-source charge of the power semiconductor device is reduced by adjusting the depth of the body region below the source region.

[0052] The present application provides a power semiconductor device and a method for preparing a power semiconductor device, wherein the power semiconductor device includes a substrate, a main gate and an insulating layer. A gate groove is formed between the source region and the drain region on the substrate, and the gate groove is recessed from the upper surface of the substrate to the active region. The main gate is located in the gate groove, and the main gate extends downward from the upper surface of the gate groove. The insulating layer is filled between the inner wall of the gate groove and the main gate. In this way, the thickness of the insulating layer in the gate groove is large, and a withstand voltage can be achieved. Compared with existing power semiconductor devices, the length of the drift region between the source region and the drain region is transformed from the lateral dimension between the source region and the drain region to the circumference of the gate groove, and the lateral dimension of the power semiconductor device can be reduced while ensuring BV, while reducing the specific on-resistance (Rsp) of the power semiconductor device, and reducing the size of the power semiconductor device while achieving the best BV / Rsp compromise. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0054] Figure 1 A cross-sectional structural diagram of a power semiconductor device in the related art;

[0055] Figure 2 for Figure 1 Schematic diagram of electric field distribution of the power semiconductor device shown;

[0056] Figure 3 The cross-sectional structure of the power semiconductor device provided in the embodiment of the present application Figure 1 ;

[0057] Figure 4 for Figure 3 Schematic diagram of electric field distribution of the power semiconductor device shown;

[0058] Figure 5 The cross-sectional structure of the power semiconductor device provided in the embodiment of the present application Figure 2 ;

[0059] Figure 6 The cross-sectional structure of the power semiconductor device provided in the embodiment of the present application Figure 3 ;

[0060] Figure 7 The cross-sectional structure of the power semiconductor device provided in the embodiment of the present application Figure 4 ;

[0061] Figure 8 The cross-sectional structure of the power semiconductor device provided in the embodiment of the present application Figure 5 ;

[0062] Fig. 9 The cross-sectional structure of the power semiconductor device provided in the embodiment of the present application Figure 6 ;

[0063] Fig.10 The cross-sectional structure of the power semiconductor device provided in the embodiment of the present application Figure 7 ;

[0064] Fig.11 The cross-sectional structure of the power semiconductor device provided in the embodiment of the present application Figure 8 ;

[0065] Fig.12 The cross-sectional structure of the power semiconductor device provided in the embodiment of the present application Figure 9 .

[0066] Description of reference numerals:

[0067] 100-substrate; 110-active region; 111-source region; 112-drain region; 113-gate trench; 114-first doping region; 115-second doping region; 116-heavily doped buffer region; 117-body region; 118-body contact region;

[0068] 210-main gate; 220-shielding gate; 230-insulating layer;

[0069] 300-source;

[0070] 400-Drain. DETAILED DESCRIPTION

[0071] In order to make the purpose, technical scheme and advantages of the present application clearer, the technical scheme in the embodiment of the present application will be described in more detail below in conjunction with the drawings in the preferred embodiments of the present application. In the drawings, the same or similar reference numerals throughout represent the same or similar parts or parts with the same or similar functions. The described embodiments are part of the embodiments of the present application, not all of the embodiments. The embodiments described below with reference to the drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limitations on the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application. The embodiments of the present application are described in detail below in conjunction with the drawings.

[0072] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, or it can be an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0073] In the description of the present application, it should be understood that the terms "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are orientations or positional relationships based on the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0074] The terms "lower", "front", "rear", "vertical", "horizontal", "top" and the like in the specification and claims of this application and the above-mentioned drawings are not necessarily used to describe a specific order or sequence.

[0075] In addition, the terms "below" and "before" in the terminology specification and claims and the above-mentioned drawings are not exclusive. For example, a process, method, system, product or display that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or are inherent to these processes, methods, products or displays.

[0076] In the prior art, such as Figure 1As shown, the power semiconductor device is provided with a source 300, a drain 400 and a main gate 210, and the source 300, the drain 400 and the main gate 210 are respectively arranged on the substrate 100 (bulk silicon) and the main gate 210 is located between the source 300 and the drain 400. The source 300 is electrically connected to the source region 111 on the substrate 100, and the drain 400 is electrically connected to the drain region 112 on the substrate 100. A lateral drift region is formed between the source region 111 and the drain region 112. When the main gate 210 is externally connected to a voltage, conduction between the source 300 and the drain 400 can be achieved. In power semiconductor devices, we need to focus on analog, low-voltage digital and high-voltage power supplies, etc. For analog, we need to enrich devices with outstanding analog precision. The scaling of digital CMOS benefits from the evolution of lithography technology. However, from the perspective of process node scaling, lateral high voltage (HV) and power devices will be limited by lateral geometric (constant field) scaling, which means that at the target BV, power semiconductor devices are limited by the peak electric field of bulk silicon and the size of power semiconductors cannot become smaller as the process nodes become more advanced.

[0077] like Figure 2 As shown, when the length of the lateral drift region of the power semiconductor device in the prior art is small, the electric field is highest in the drain region of the bulk silicon, the BV of the power semiconductor device is small, and breakdown is prone to occur.

[0078] After repeated thinking and verification, the inventors found that if a gate trench is set on the substrate, the main gate originally set on the substrate is set inside the gate trench, and an insulating layer (such as an oxide layer) is filled in the gate trench. Since the peak electric field of the insulating layer is greater than that of the bulk silicon and the thickness of the insulating layer in the gate trench is large, the withstand voltage can be achieved. The length of the drift region between the source region and the drain region is transformed from the lateral dimension between the source region and the drain region to the circumference of the gate trench, which can reduce the lateral dimension of the power semiconductor device while ensuring BV.

[0079] In view of this, the inventors have designed a power semiconductor device and a method for preparing the power semiconductor device. A gate trench is set on the substrate of the power semiconductor device, and the main gate is set inside the gate trench and extends downward from the upper surface of the gate trench. An insulating layer is filled in the remaining position of the gate trench. The withstand voltage is achieved by the insulating layer of the high peak electric field, and the length of the drift region of the power semiconductor device is transformed from the lateral length between the source region and the drain region to the circumference of the gate trench, reducing the space occupied by the drift region in the lateral direction of the power semiconductor device under the same BV, thereby reducing the size and Rsp of the power semiconductor device.

[0080] The technical solutions of the power semiconductor device and the method for manufacturing the power semiconductor device provided in the embodiments of the present application are described in detail below in conjunction with the accompanying drawings.

[0081] Reference Figures 3 to 8 As shown, the power semiconductor device provided in the embodiment of the present application includes a substrate 100, a main gate 210 and an insulating layer 230. The substrate 100 has an active area 110, and the active area 110 includes a source area 111 and a drain area 112 of a first doping type located on the upper surface of the substrate 100. A gate trench 113 is formed between the source area 111 and the drain area 112, and the gate trench 113 is recessed from the upper surface of the substrate 100 to the active area 110. The main gate 210 is located in the gate trench 113, and the main gate 210 extends downward from the upper surface of the gate trench 113. The insulating layer 230 is filled between the inner wall of the gate trench 113 and the main gate.

[0082] The power semiconductor device may be a LDMOS (Lateral Diffused Metal Oxide Semiconductor), such as NLDMOS or PLDMOS, which is not limited here. The source region 111 and the drain region 112 have the same ion doping type. When the power semiconductor device is an NLDMOS, the source region 111 and the drain region 112 are doped with N-type impurities respectively; when the power semiconductor device is a PLDMOS, the source region 111 and the drain region 112 are doped with P-type impurities respectively.

[0083] The following description takes the NLDMOS power semiconductor device as an example, but this is not intended to limit the scope of protection.

[0084] Exemplarily, the substrate 100 may be a P-type substrate, and the thickness of the substrate 100 may be set as required. An epitaxial layer may or may not be provided on the substrate 100. When an epitaxial layer is provided on the substrate 100, the epitaxial layer may be a P-type or an N-type, and the active region 110 may be provided on the epitaxial layer.

[0085] The main part of the active region 110 may be an N-type well (NWELL), which may be formed by doping N-type impurities in the substrate 100. The source region 111 and the drain region 112 may be formed by doping on the surface of the substrate 100, and the ion doping concentrations of the source region 111 and the drain region 112 are respectively greater than the ion doping concentration of the active region 110.

[0086] Exemplarily, the gate trench 113 can be formed using heat treatment and advanced etching processes, including anisotropy, isotropy, or a mixture of the two in different proportions. The gate trench 113 is recessed from the upper surface of the substrate 100 to the active area 110, that is, the opening of the gate trench 113 is located on the upper surface of the substrate 100. The perimeter of the gate trench 113 limits the length of the drift region between the source region 111 and the drain region 112, thereby ensuring the BV of the power semiconductor device. Under the target BV, the lateral size of the power semiconductor device is reduced, while the specific on-resistance of the power semiconductor device is reduced. The width of the gate trench 113 can be linearly reduced as the process node is reduced, and the width / depth / perimeter design of the gate trench 113 depends on achieving the best BV / Rsp compromise relationship within the smallest area.

[0087] Optionally, the main gate 210 may include a gate oxide and a polysilicon deposition attached to the gate oxide, and the thickness of the gate oxide may range from 20 angstroms to 400 angstroms, which may be set according to actual needs. The main gate 210 extends downward from the upper surface of the gate trench 113, that is, the top of the main gate 210 is located on the upper surface of the substrate 100, and the top of the main gate 210 may be connected to an external circuit.

[0088] For example, silicon dioxide can be used as the insulating layer 230. It can be understood that the dielectric constant of the insulating layer 230 is greater than the dielectric constant of the substrate 100, that is, the bulk silicon. Under the same withstand voltage requirement, the required width of the insulating layer 230 is smaller than that of the bulk silicon. The main gate 210 is closer to the source region 111 than the drain region 112, so that the thickness of the insulating layer 230 between the main gate 210 and the drain region 112 is larger, and the insulating layer 230 can achieve withstand voltage.

[0089] In the power semiconductor device provided in this embodiment, a gate trench 113 is formed between the source region 111 and the drain region 112 on the substrate 100, and the gate trench 113 is recessed from the upper surface of the substrate 100 to the active region 110. The main gate 210 is located in the gate trench 113, and the main gate 210 extends downward from the upper surface of the gate trench 113. The insulating layer 230 is filled between the inner wall of the gate trench 113 and the main gate 210. Compared with the existing power semiconductor device, the length of the drift region between the source region 111 and the drain region 112 is transformed from the lateral dimension between the source region 111 and the drain region 112 to the perimeter of the gate trench 113, and the target BV of the power semiconductor device is obtained while maintaining the lateral geometric dimension scaling of the power semiconductor device, thereby realizing the size reduction of the power semiconductor device, and the power semiconductor device can realize a small cell pitch, while reducing the specific on-resistance (Rsp) of the power semiconductor device, and reducing the size of the power semiconductor device while achieving the best BV / Rsp compromise.

[0090] like Figure 3-Figure 8As shown, the cross section of the gate trench 113 is one of U-shaped, rectangular, and trapezoidal.

[0091] When the cross section of the gate trench 113 is U-shaped, the opening of the U-shaped opening is located on the upper surface of the substrate 100. When the cross section of the gate trench 113 is trapezoidal, the upper base of the trapezoid is located on the upper surface of the substrate 100. Figure 7 As shown, the width of the upper base of the trapezoid can be greater than the width of the lower base of the trapezoid, such as Figure 8 As shown, the upper base width of the trapezoid can also be smaller than the lower base width of the trapezoid. The above arrangement can extend the effective length of the drift region.

[0092] Indicative, such as Figure 3-Figure 8 As shown, the main gate 210 is closer to the source region 111 than to the drain region 112 .

[0093] That is, the distance between the main gate 210 and the source region 111 is smaller than the distance between the main gate 210 and the drain region 112. The distance A between the main gate 210 and the inner wall of the gate trench 113 close to the drain region 112 can be adjusted according to the requirements of the device electric field distribution, and is not limited here.

[0094] Placing the main gate 210 closer to the source region 111 can better control the current flow from the source region 111 to the drain region 112, which helps to improve the control of carrier transmission in the channel, thereby improving the switching characteristics and reducing the on-resistance. Placing the main gate 210 closer to the source region 111 can reduce the parasitic capacitance between the main gate 210 and the drain region 112 to a certain extent.

[0095] In one embodiment, Figure 3-Figure 8 As shown, the power semiconductor device further includes a source 300 and a drain 400. The source 300 is disposed on the upper surface of the substrate 100 and is electrically connected to the source region 111. The drain 400 is disposed on the upper surface of the substrate 100 and is electrically connected to the drain region 112.

[0096] like Figure 3 As shown, the bottom end of the source 300 is connected to the source region 111 to achieve electrical conduction between the source 300 and the source region 111, and the bottom end of the drain 400 is connected to the drain region 112 to achieve electrical conduction between the drain 400 and the drain region 112. The power semiconductor device can be connected to an external circuit through the source 300 and the drain 400.

[0097] In one embodiment, Figure 5-Figure 8 As shown, the power semiconductor device further includes at least one shielding gate 220, which is located in the gate trench 113. The shielding gate 220 is located at the bottom of the main gate 210 and is spaced apart from the main gate 210. The shielding gate 220 is located on one side of the main gate 210 close to the drain region 112.

[0098] The number of shielding gates 220 may be one or more, the main gate 210 is configured to control the channel of the power semiconductor device, and the shielding gate 220 is configured to shield the high voltage electric field of the drain 400 of the power semiconductor device. Schematically, the main gate 210 and the shielding gate 220 are arranged alternately, and an insulating layer 230 is filled between the main gate 210 and the shielding gate 220. Optionally, the shielding gate 220 may be made of a conductive material.

[0099] Illustratively, those skilled in the art can adjust the BV of the power semiconductor device by adjusting the depth of the main gate 210 and the shielding gate 220 and the interval between the main gate 210 and the shielding gate 220. Optionally, a contact hole can be opened on the insulating layer 230, and the end of the contact hole extends to the shielding gate 220, and the shielding gate 220 can be externally connected to a potential through the contact hole.

[0100] In this embodiment, staggered main gates 210 and shielding gates 220 are arranged in the gate trench 113, so that the power semiconductor device has an adjustable voltage. Specifically, when the power semiconductor device is in the off state, the shielding gate 220 can be connected to a potential of 0V. When the power semiconductor device is in the on state, the shielding gate 220 can be connected to a fixed potential of 0V or a fixed potential greater than 0V, thereby reducing the Rsp of the power semiconductor device.

[0101] In addition, a staggered main gate 210 and shielding gate 220 are arranged in the gate trench 113, and the shielding gate 220 reduces the capacitive coupling between the main gate 210 and the drain 400. In addition, the shielding gate 220 changes the electric field distribution around the main gate 210 and reduces the electric field intensity in the direction of the drain 400. The above reasons greatly reduce the Qgd (Gate-to-Drain Charge) of the power semiconductor device.

[0102] In other embodiments, for semiconductor devices with low rated voltages, such as semiconductor devices with 40 V or less, the depth of the gate trench 113 may be smaller due to the increased drift length at the perimeter of the gate trench 113 in the semiconductor device. In this case, the shielding gate 220 of the semiconductor device may be merged with the main gate 210, or the shielding gate 220 may be omitted according to the needs of the target application.

[0103] In a specific embodiment, Figure 5-Figure 8 As shown, there is a first distance between the shielding gate 220 and the inner wall of the gate trench 113 close to the source region 111. There is a second distance between the shielding gate 220 and the inner wall of the gate trench 113 close to the drain region 112. The first distance is equal to the second distance.

[0104] That is to say, in the width direction of the gate groove 113, the shielding gate 220 is located in the middle of the gate groove 113, and the insulating layer 230 areas on both sides of the shielding gate 220 can be used as voltage-resistant areas. The size B of the first spacing and the second spacing can be adjusted according to the requirements of the shielding field area. Optionally, during the preparation of the power semiconductor device, the insulating layer 230 is first filled in the gate groove 113, a groove is set in the middle area of ​​the insulating layer 230, and the shielding gate 220 is formed inside the groove.

[0105] This structure sets the shielding gate 220 in the middle position in the width direction of the gate groove 113, which is convenient for setting a groove on the insulating layer 230, and then for forming the shielding gate 220 in the insulating layer 230, thereby improving the processing efficiency of the power semiconductor device.

[0106] In one possible implementation, Fig. 9 As shown, there are a plurality of shielding gates 220 , and the plurality of shielding gates 220 are arranged at intervals along the thickness direction of the substrate 100 .

[0107] During the preparation of the power semiconductor device, the length of each shielding gate 220 and the size of the interval between adjacent shielding gates 220 can be set according to the target BV and the gate-drain charge. The lengths of the plurality of shielding gates 220 can be the same or different, and are not limited here. It can be understood that each shielding gate 220 is located at the bottom of the main gate 210 and on the side of the main gate 210 close to the drain region 112.

[0108] Through the above configuration, the versatility of the power semiconductor device is improved, and the target BV and gate-drain charge of the power semiconductor device can be set by setting the number of shielding gates 220, the length of each shielding gate 220, and the size of the interval between adjacent shielding gates 220.

[0109] like Figure 3 and Figure 5-Figure 12 As shown, the active region 110 further includes a body region 117 of the second doping type. The body region 117 is located at the bottom of the source region 111 . The side edges of the body region 117 and the side edges of the source region 111 form a portion of the inner wall of the gate trench 113 .

[0110] Illustratively, the ion doping types of the body region 117 and the source region 111 are different. When the power semiconductor device is NLDMOS, the body region 117 is doped with P-type impurities; when the power semiconductor device is PLDMOS, the body region 117 is doped with N-type impurities.

[0111] When the active region 110 includes the first doping region 114, one end of the first doping region 114 away from the drain region 112 is connected to the body region 117, and when the active region 110 includes the second doping region 115, one end of the second doping region 115 away from the drain region 112 is connected to the body region 117. When the active region 110 includes the second doping region 115, the doping concentration of the body region 117 is greater than the doping concentration of the second doping region 115.

[0112] Figure 3 and Figure 5-Figure 12 As shown, the active region 110 also includes a body contact region 118 , which is arranged side by side with the source region 111 . The body contact region 118 and the body region 117 have the same ion doping type, and the ion doping concentration of the body contact region 118 is greater than the ion doping concentration of the body region 117 .

[0113] In one embodiment, Figure 5-Figure 12 As shown, the active region 110 further includes a first doping region 114 of a first doping type, and the first doping region 114 is disposed around the side and bottom of the gate trench 113 .

[0114] Among them, the ion doping type of the source region 111, the drain region 112 and the first doping region 114 is the same, that is, when the power semiconductor device is NLDMOS, the first doping region 114 is doped with N-type impurities, and when the power semiconductor device is PLDMOS, the first doping region 114 is doped with P-type impurities. The first doping region 114 can be formed by chain implantation. Schematically, the ion doping concentration of the first doping region 114 is less than the ion doping concentration of the drain region 112 and greater than the ion doping concentration of the active region 110. Optionally, one end of the first doping region 114 is electrically connected to the body contact region 118 through the body region 117.

[0115] Figure 5-Figure 12 As shown, the first doping region 114 forms a "U"-shaped region surrounding the gate trench 113. The width of the first doping region 114 can be set as required and is not limited here. It can be understood that the first doping region 114 forms at least part of the drift region.

[0116] This structure increases the ion doping concentration of the drift region between the source region 111 and the drain region 112 by providing the first doping region 114 , thereby reducing the Rsp of the power semiconductor device.

[0117] In a specific embodiment, Fig.11 and Fig.12 As shown, the active region 110 further includes a second doping region 115 of a second doping type, and the second doping region 115 is disposed around the sidewall and the bottom of the first doping region 114 .

[0118] The first doping region 114 and the second doping region 115 have different ion doping types. When the power semiconductor device is NLDMOS, P-type impurities are doped in the second doping region 115, and when the power semiconductor device is PLDMOS, N-type impurities are doped in the second doping region 115. The second doping region 115 can be formed by chain implantation. Fig.11 and Fig.12 It is shown that one end of the second doped region 115 is electrically connected to the body contact region 118 through the body region 117 .

[0119] Fig.11 and Fig.12 It is shown that the second doping region 115 forms a “U”-shaped region surrounding the first doping region 114 , and the width of the second doping region 115 can be set as required, which is not limited here.

[0120] By providing the second doping region 115 , the second doping region 115 and the first doping region 114 can deplete each other, and the power semiconductor device can achieve double RESURF (Reduced SURface Field) and increase the BV of the power semiconductor device.

[0121] In one embodiment, Fig.10 and Fig.12 As shown, the active region 110 further includes a heavily doped buffer region 116 of the first doping type. The heavily doped buffer region 116 is located at the bottom of the drain region 112 , and the ion doping concentration of the heavily doped buffer region 116 is lower than the ion doping concentration of the drain region 112 .

[0122] Illustratively, the heavily doped buffer region 116 may be formed into a drain drift region by doping ion implantation and / or thermal diffusion. For NLDMOS, an N-type drain drift region (NDD) is formed. Fig.10 and Fig.12 It is shown that the end surface of the heavily doped buffer region 116 may be connected to the gate trench 113. This embodiment does not limit the depth of the heavily doped buffer region 116, and those skilled in the art may set it as required.

[0123] When the active region 110 includes the first doped region 114 , one end of the first doped region 114 may be connected to the bottom of the heavily doped buffer region 116 ; when the active region 110 includes the second doped region 115 , one end of the second doped region 115 may be connected to the bottom of the heavily doped buffer region 116 .

[0124] In this embodiment, by providing the heavily doped buffer zone 116, when the power semiconductor device is subjected to high voltage, a relatively uniform electric field distribution can be formed in the heavily doped buffer zone 116, and the power semiconductor device is not prone to breakdown due to electric field concentration. At the same time, since the heavily doped buffer zone 116 has a relatively low resistivity, it can also effectively reduce the impedance of the flow path of the drain 400 current in the power semiconductor device, thereby reducing the Rsp of the power semiconductor device.

[0125] In this embodiment, the body region 117 can form a PN junction with the active region 110 or the first doped region 114. The side of the body region 117 and the side of the source region 111 form part of the inner wall of the gate trench 113, so that when the power semiconductor device is forward biased, the charge accumulated in the PN junction is confined to the side wall of the gate trench 113, and the spacing between the device gate trenches 113 near the side wall of the gate trench 113 and the width of the gate trench 113 are smaller than the distance between the source 300 and the drain 400 in the existing power semiconductor device. The carriers are confined to a narrow drift region space, and when the power semiconductor device is reverse recovered, the carriers are easily recombined to achieve a smaller Qrr (Reverse Recovered Charge). For power semiconductor devices with low Qrr, the reverse recovery current can be reduced and the switching power loss can be reduced. In addition, when the active region 110 includes the first doped region 114 and the side of the body region 117 forms a portion of the inner wall of the gate trench 113, the PN junction area is only the area of ​​the region where the bottom of the body region 117 is connected to the first doped region 114. The PN junction area can be reduced due to advanced process node scaling, which can further reduce the reverse recovery current and reduce the switching power loss.

[0126] It can be understood that the body region 117 forms a channel toward the side of the gate trench 113, and the power semiconductor device has a vertical or quasi-vertical channel, which facilitates reducing the lateral size of the power semiconductor device so that the power semiconductor device can have a small cell pitch.

[0127] It is worth mentioning that the channel of the power semiconductor device provided by this embodiment can be precisely controlled. Specifically, through advanced process implantation tools such as 55nm advanced node implantation machines, by longitudinal implantation, by utilizing the implantation energy difference between the body region 117 and the source region 111, the longitudinal implantation energy of ions can be precisely controlled. Compared with the existing body region 117 and source region 111 formed by double diffusion, the channel can be effectively shortened. The power semiconductor device can have a smaller Qgs (Gate-to-Source Charge) and channel length, so that the power semiconductor device can be used well at high frequencies.

[0128] The present application also provides a method for preparing a power semiconductor device, comprising:

[0129] A substrate 100 is provided.

[0130] The substrate 100 may be a P-type substrate or an N-type substrate, and an epitaxial layer may or may not be provided on the substrate 100 .

[0131] An active region 110 is formed in a substrate 100 .

[0132] Exemplarily, the active region 110 may be formed by ion implantation.

[0133] A gate trench 113 is formed on the upper surface of the substrate 100 and is recessed toward the active region 110 .

[0134] The gate trench 113 may be formed in the substrate 100 by heat treatment and / or etching.

[0135] An insulating layer 230 is filled in the gate trench 113 , and the material of the insulating layer 230 may be silicon dioxide.

[0136] A main gate 210 is formed in the insulating layer 230, and the main gate 210 extends from the upper surface of the gate trench 113 to the inside thereof.

[0137] Exemplarily, after the insulating layer 230 is filled, a portion of the insulating layer 230 can be removed by photolithography etching to form a groove, the opening of the groove is located on the upper surface of the gate trench 113, and the main gate 210 is formed inside the groove. The main gate 210 is inside the gate trench 113 and close to the source region 111.

[0138] A source region 111 and a drain region 112 are formed on the upper surface of the active region 110 , and a gate trench 113 is located between the source region 111 and the drain region 112 .

[0139] The source region 111 and the drain region 112 can be formed by ion implantation or ion implantation heating diffusion. The ion doping concentration of the source region 111 and the drain region 112 is greater than the ion doping concentration of the active region 110.

[0140] In the power semiconductor device manufactured by the above preparation method, the length of the drift region between the source region 111 and the drain region 112 is transformed from the lateral dimension between the source region 111 and the drain region 112 to the circumference of the gate trench 113, so that the lateral dimension of the power semiconductor device can be reduced while ensuring the BV, and the specific on-resistance (Rsp) of the power semiconductor device can be reduced, thereby reducing the size of the power semiconductor device while achieving the best BV / Rsp compromise.

[0141] In one embodiment, before forming the main gate 210 in the insulating layer 230, the method further includes:

[0142] The shield gate 220 is formed in the insulating layer 230 .

[0143] The shielding gate 220 is located at the bottom of the main gate 210 and is spaced apart from the main gate 210. The shielding gate 220 is located at a side of the main gate 210 close to the drain region 112.

[0144] Exemplarily, a portion of the insulating layer 230 may be filled in the gate trench 113, a first groove may be formed on the portion of the insulating layer 230, and the shielding gate 220 may be formed in the first groove. After the shielding gate 220 is formed, the remaining portion of the insulating layer 230 may be filled, a second groove may be formed on the remaining portion of the insulating layer 230, and the main gate 210 may be formed in the second groove.

[0145] By adopting the above-mentioned manufacturing method, a staggered main gate 210 and a shielding gate 220 are formed in the gate trench 113, so that the power semiconductor device has an adjustable voltage and the Qgd of the power semiconductor device is reduced.

[0146] In one embodiment, the main gate 210 is closer to the source region 111 than to the drain region 112 .

[0147] The distance A between the main gate 210 and the inner wall of the gate trench 113 close to the drain region 112 is greater than the distance between the main gate 210 and the inner wall of the gate trench 113 close to the source region 111 .

[0148] The distance A between the main gate 210 and the inner wall of the gate trench 113 close to the drain region 112 can be determined according to the requirements of the device electric field distribution, the second groove is determined according to the size of A, and then the main gate 210 is formed in the second groove.

[0149] The main gate 210 is closer to the source region 111 in the gate trench 113 , which can improve the switching characteristics and reduce the on-resistance, and is beneficial to reducing the parasitic capacitance between the main gate 210 and the drain region 112 .

[0150] In one embodiment, the method for preparing a power semiconductor device further includes: forming a source 300 on the upper surface of the substrate 100 , wherein the source 300 is electrically connected to the source region 111 ; forming a drain 400 on the upper surface of the substrate 100 , wherein the drain 400 is electrically connected to the drain region 112 .

[0151] For example, a metal layer may be deposited at a position on the upper surface of the substrate 100 corresponding to the source region 111 as the source 300, and a metal layer may be deposited at a position on the upper surface of the substrate 100 corresponding to the drain region 112 as the drain 400. The source 300 on the upper surface of the substrate 100 is electrically connected to the source region 111, and the drain 400 is electrically connected to the drain region 112. The power semiconductor device may be connected to an external circuit through the source 300 and the drain 400.

[0152] In one embodiment, after the gate trench 113 is formed and before the source region 111 and the drain region 112 are formed.

[0153] A first doping region 114 is formed in the active region 110, and the first doping region 114 surrounds the side and bottom of the gate trench 113. The doping concentration of the first doping region 114 is greater than the doping concentration of the active region 110 of the first doping type.

[0154] The first doping region 114 may be formed by chain implantation, and the first doping region 114 is connected to the source region 111 and the drain region 112 respectively.

[0155] By forming the first doping region 114 in the above manner, the ion doping concentration of the drift region between the source region 111 and the drain region 112 is increased, and the Rsp of the power semiconductor device is reduced.

[0156] In a specific embodiment, before forming the first doping region 114, the method for preparing a power semiconductor device further includes: forming a second doping region 115 in the active region 110, the second doping region 115 being arranged around the sidewall and the bottom of the first doping region 114. The first doping region 114 and the second doping region 115 have different ion doping types. The second doping region 115 can help increase the doping concentration of the first doping region 114 to form a first doping region 114 with a higher doping concentration, that is, in this example, since the second doping region 115 is formed first and then the first doping region 114 is formed, the doping concentration of the first doping region 114 is greater than the doping concentration of only forming the first doping region 114 in the above-mentioned embodiment.

[0157] Specifically, the second doping region 115 can be formed by chain implantation, and after the second doping region 115 is formed, the first doping region 114 is formed by chain implantation again. The ion types of the two chain implantations are different. After the first doping region 114 is formed, the second doping region 115 is surrounded by the sidewalls and the bottom of the first doping region 114.

[0158] By forming the second doping region 115 , the second doping region 115 and the first doping region 114 can deplete each other, and the power semiconductor device can achieve double RESURF (Reduced SURface Field) and increase the BV of the power semiconductor device.

[0159] In one embodiment, the method for preparing a power semiconductor device further includes:

[0160] A heavily doped buffer region 116 is formed in the active region 110 . The ion doping concentration of the heavily doped buffer region 116 is lower than the ion doping concentration of the drain region 112 . The drain region 112 is located in the heavily doped buffer region 116 .

[0161] Optionally, the heavily doped buffer region 116 may be formed by ion implantation or ion implantation heating diffusion. The heavily doped buffer region 116 may have the same ion doping type as the drain region 112. After the drain region 112 is formed in the active region 110, the ion doping concentration of the heavily doped buffer region 116 is lower than the ion doping concentration of the drain region 112.

[0162] The heavily doped buffer 116 prevents the power semiconductor device from being easily broken down by electric field concentration when it is subjected to high voltage. The heavily doped buffer 116 can also effectively reduce the impedance of the flow path of the drain 400 current in the power semiconductor device and reduce the Rsp of the power semiconductor device.

[0163] In one embodiment, the method for preparing a power semiconductor device further includes:

[0164] A body region 117 is formed in the active region 110 . The body region 117 is located at the bottom of the source region 111 . Sides of the body region 117 and the side of the source region 111 form a portion of the inner wall of the gate trench 113 .

[0165] The body region 117 may be formed by ion implantation or thermal diffusion. After the gate trench 113 is formed on the substrate 100, the sidewalls of the gate trench 113 are respectively connected to the body region 117 and the source region 111, so that the side edges of the body region 117 and the side edges of the source region 111 form part of the inner wall of the gate trench 113. When the power semiconductor device has the second doping region 115, the doping concentration of the body region 117 may be greater than the doping concentration of the second doping region 115.

[0166] By forming the body region 117, a PN junction can be formed between the body region 117 and the active region 110 or the first doped region 114. The side of the body region 117 and the side of the source region 111 form part of the inner wall of the gate trench 113, so that when the power semiconductor device is forward biased, the charge accumulated in the PN junction is confined near the side wall of the gate trench 113, the spacing between the device gate trenches 113 and the width of the gate trench 113 are smaller than the distance between the source 300 and the drain 400 in the existing power semiconductor device, the carriers are confined to a narrower drift region space, and when the power semiconductor device is reverse recovered, the carriers are easily recombined to achieve a smaller Qrr (Reverse Recovered Charge). For power semiconductor devices with low Qrr, the reverse recovery current can be reduced and the switching power loss can be reduced. In addition, when the active region 110 includes the first doped region 114 and the side of the body region 117 forms part of the inner wall of the gate trench 113, the PN junction area is only the area of ​​the region where the bottom of the body region 117 is connected to the first doped region 114, and the PN junction area can be reduced due to advanced process node scaling, which can further reduce the reverse recovery current and reduce the switching power loss. The body region 117 forms a channel toward the side of the gate trench 113, and the power semiconductor device has a vertical or quasi-vertical channel, which is convenient for reducing the size of the power semiconductor device, so that the power semiconductor device can have a small cell pitch.

[0167] In a specific embodiment, the body region 117 is formed by ion implantation or ion implantation heating diffusion, and the gate-source charge of the power semiconductor device is reduced by adjusting the depth of the body region 117 below the source region 111 .

[0168] Indicatively, an implantation machine at a 55nm advanced node can be used to implant ions to form the body region 117, with high control accuracy. The depth of the body region 117 can be precisely controlled, that is, the overlapping area of ​​the body region 117 beyond the source region 111 and the trench can be controlled, so that the gate-source charge (Qgs) and the channel of the power semiconductor device can be made very small, so that the power semiconductor device can be used well at high frequencies.

[0169] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A power semiconductor device, characterized in that: include: A substrate (100), the substrate (100) having an active region (110), the active region (110) comprising a source region (111) and a drain region (112) of a first doping type located on the upper surface of the substrate (100), a gate trench (113) formed between the source region (111) and the drain region (112), the gate trench (113) being recessed from the upper surface of the substrate (100) toward the active region (110); A main gate (210) is located in the gate trench (113), and the main gate (210) extends downward from the upper surface of the gate trench (113); An insulating layer (230), wherein the insulating layer (230) is filled between the inner wall of the gate trench (113) and the main gate.

2. The power semiconductor device according to claim 1, characterized in that: The main gate (210) is closer to the source region (111) than to the drain region (112).

3. The power semiconductor device according to claim 1, characterized in that: Also includes: A source electrode (300) is disposed on the upper surface of the substrate (100) and is electrically connected to the source region (111); The drain (400) is disposed on the upper surface of the substrate (100) and is electrically connected to the drain region (112).

4. The power semiconductor device according to claim 1, characterized in that: The power semiconductor device further comprises at least one shielding gate (220), wherein the shielding gate (220) is located in the gate trench (113); The shielding grid (220) is located at the bottom of the main grid (210) and is spaced apart from the main grid (210); The shielding gate (220) is located on a side of the main gate (210) close to the drain region (112).

5. The power semiconductor device according to claim 4, characterized in that: There is a first distance between the shielding gate (220) and the inner wall of the gate trench (113) close to the source region (111); A second distance exists between the shielding gate (220) and the inner wall of the gate trench (113) close to the drain region (112); The first interval is equal to the second interval.

6. The power semiconductor device according to claim 4, characterized in that: There are a plurality of shielding grid electrodes (220), and the plurality of shielding grid electrodes (220) are arranged at intervals along the thickness direction of the substrate (100).

7. The power semiconductor device according to claim 1, characterized in that: The active region (110) further comprises a first doping region (114) of a first doping type, wherein the first doping region (114) is arranged around the side and bottom of the gate trench (113).

8. The power semiconductor device according to claim 7, characterized in that: The active region (110) further comprises a second doping region (115) of a second doping type, wherein the second doping region (115) is arranged around the sidewall and the bottom of the first doping region (114).

9. The power semiconductor device according to claim 1, characterized in that: The active region (110) further comprises a heavily doped buffer region (116) of a first doping type, the heavily doped buffer region (116) being located at the bottom of the drain region (112), and the ion doping concentration of the heavily doped buffer region (116) being lower than the ion doping concentration of the drain region (112).

10. The power semiconductor device according to claim 1, characterized in that: The active region (110) further comprises a body region (117) of a second doping type, wherein the body region (117) is located at the bottom of the source region (111), and the side edges of the body region (117) and the side edges of the source region (111) form a portion of the inner wall of the gate trench (113).

11. The power semiconductor device according to any one of claims 1 to 10, characterized in that: The cross section of the gate trench (113) is one of a U-shape, a rectangle and a trapezoid.

12. A method for preparing a power semiconductor device, characterized in that: include: Providing a substrate (100); forming an active region (110) in the substrate (100); Forming a gate trench (113) on the upper surface of the substrate (100) so as to be recessed toward the active region (110); Filling an insulating layer (230) in the gate trench (113); forming a main gate (210) in the insulating layer (230), wherein the main gate (210) extends from the upper surface of the gate trench (113) to the interior thereof; A source region (111) and a drain region (112) are formed on the upper surface of the active region (110), and the gate trench (113) is located between the source region (111) and the drain region (112).

13. The preparation method according to claim 12, characterized in that: Before forming the main gate (210) in the insulating layer (230), the method further comprises: forming a shielding gate (220) in the insulating layer (230); The shielding grid (220) is located at the bottom of the main grid (210) and is spaced apart from the main grid (210); The shielding gate (220) is located on a side of the main gate (210) close to the drain region (112).

14. The preparation method according to claim 12, characterized in that: The main gate (210) is closer to the source region (111) than to the drain region (112).

15. The preparation method according to claim 12, characterized in that: The method further comprises: forming a source electrode (300) on the upper surface of the substrate (100), wherein the source electrode (300) is electrically connected to the source region (111); A drain electrode (400) is formed on the upper surface of the substrate (100), wherein the drain electrode (400) is electrically connected to the drain region (112).

16. The preparation method according to claim 12, characterized in that: After forming the gate trench (113) and before forming the source region (111) and the drain region (112), A first doping region (114) is formed in the active region (110), wherein the first doping region (114) surrounds the side and bottom of the gate trench (113), wherein the doping concentration of the first doping region (114) is greater than the doping concentration of the active region (110) of the first doping type.

17. The preparation method according to claim 16, characterized in that: Before forming the first doped region (114), the method further comprises: forming a second doping region (115) in the active region (110), wherein the second doping region (115) surrounds the sidewall and bottom of the first doping region (114); The first doping region (114) and the second doping region (115) have different ion doping types.

18. The preparation method according to claim 12, characterized in that: The method further comprises: A heavily doped buffer region (116) is formed in the active region (110), wherein the ion doping concentration of the heavily doped buffer region (116) is lower than the ion doping concentration of the drain region (112), wherein the drain region (112) is located in the heavily doped buffer region (116).

19. The preparation method according to claim 12, characterized in that: The method further comprises: A body region (117) is formed in the active region (110), the body region (117) is located at the bottom of the source region (111), and the side edges of the body region (117) and the side edges of the source region (111) form a portion of the inner wall of the gate trench (113).

20. The preparation method according to claim 19, characterized in that: The body region (117) is formed by ion implantation or ion implantation heating diffusion, and the gate-source charge of the power semiconductor device is reduced by adjusting the depth of the body region (117) located below the source region (111).

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