SiC MOSFET device and preparation method thereof

Abstract

The invention discloses a SiC MOSFET device, which comprises a gate electrode, a source electrode and a drain electrode, and is characterized in that the gate electrode is located on the front surface of a wafer and comprises a gate medium; the polycrystalline SiC conducting layer is located on the gate medium on the surface of the wafer and serves as a lower layer component of the gate electrode; the polycrystalline SiC surface alloy layer is positioned on the surface of the polycrystalline SiC conductive layer and is used for increasing the conductivity of the grid electrode; the source electrode is located on the front surface of the wafer and comprises source electrode surface alloy layers which are located on the two sides of the gate electrode and are electrically insulated from the gate electrode through isolation side walls, and the isolation side walls are insulating media; and the drain electrode is positioned on the back surface of the wafer. The method has the advantages that manufacturing steps can be reduced, and the machining process can be simplified.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a SiC MOSFET device and a preparation method thereof. Background Art

[0002] At present, SiC MOSFET devices basically follow the production method of Si devices, using polysilicon (Poly-Si) material as the gate material. The advantage of polysilicon material is that the process is simple and it is widely used in the semiconductor industry. The disadvantage is that the resistivity is relatively high. In particular, when the cell size is further reduced and the thickness of polysilicon is further reduced, the problem of high gate resistance is more obvious. In response to this phenomenon, the common solution in the industry is to use a double-layer gate material, that is, to grow a layer of metal (mainly tungsten metal in silicon devices) on the surface of polysilicon and react it to form a surface alloy, thereby reducing the gate resistance.

[0003] However, this method requires additional lithography and process steps, as well as corresponding manufacturing equipment, and is relatively cumbersome. Summary of the invention

[0004] In order to solve the above problems in the prior art, the present invention provides a SiC MOSFET device and a method for preparing the same.

[0005] First, the present application provides a SiC MOSFET device, including a gate electrode, a source electrode and a drain electrode: The gate electrode is located on the front side of the wafer and includes: Gate dielectric; A polycrystalline SiC conductive layer, located on the gate dielectric on the surface of the wafer, serving as a lower component of the gate electrode; A polycrystalline SiC surface alloy layer, located on the surface of the polycrystalline SiC conductive layer, is used to increase the conductivity of the gate; The source electrode is located on the front side of the wafer and includes: A source surface alloy layer, located on both sides of the gate electrode, and electrically insulated from the gate electrode by an isolation sidewall, wherein the isolation sidewall is an insulating medium; The drain electrode is located on the reverse side of the wafer.

[0006] In the above SiC MOSFET device, the polycrystalline SiC surface alloy layer and the source surface alloy layer are formed in the same process step.

[0007] In the above SiC MOSFET device, an interlayer dielectric layer is formed on the outer edge side of the gate electrode and the outer edge side of the source electrode.

[0008] The above-mentioned SiC MOSFET device also includes: A gate metal is located on the surface of the polycrystalline SiC gate surface alloy layer; A source metal is located on the surface of the source surface alloy layer, and the gate metal and the source metal are electrically isolated by the interlayer dielectric layer; Furthermore, the gate metal and the source metal are formed in the same step.

[0009] In the above SiC MOSFET device, the material of the metallic gate surface and the metallic source surface is SiC-Ni alloy.

[0010] The present application also proposes a method for preparing a SiC MOSFET device, comprising the following steps: Making a gate dielectric on the SiC epitaxial surface after the previous step processing; Depositing polycrystalline SiC on the surface of the gate dielectric and etching it to form a polycrystalline SiC conductive layer in the gate region as a lower component of the gate electrode; Making the isolation side wall includes: Growing an insulating dielectric layer on the surface of the wafer, wherein the growth range of the insulating dielectric layer covers and is larger than the range of the polycrystalline SiC conductive layer; Etching the insulating dielectric layer, the etching range and depth being until the surface of the polycrystalline SiC conductive layer and the surface of the SiC wafer used to make the source region are exposed, thereby forming the isolation sidewall composed of the insulating dielectric on the outer side of the polycrystalline SiC conductive layer; Depositing metal on the surface of the wafer, and using a secondary annealing process to form an alloy layer providing ohmic contact on the surface of the polycrystalline SiC conductive layer and the surface of the source region; An interlayer dielectric is grown on the surface of the polycrystalline SiC conductive layer and the surface of the source region, and then the interlayer dielectric is etched to expose a middle region between the surface of the polycrystalline SiC conductive layer and the surface of the source region.

[0011] The above-mentioned preparation method also includes depositing a dielectric layer and a surface metal on the alloy layer to finally form a gate and a source.

[0012] In the above-mentioned preparation method, the step of depositing polycrystalline SiC on the surface of the gate dielectric specifically comprises: Growing a layer of polycrystalline SiC on the surface of the wafer by CVD or PVD; The grown polycrystalline SiC is patterned using a dry etching process to form a gate electrode pattern.

[0013] In the above preparation method, the thickness of the polycrystalline SiC conductive layer is 1000~10000Å.

[0014] In the above preparation method, the polycrystalline SiC conductive layer has a polycrystalline type including 4H, 6H, 3C and any combination of the above types.

[0015] In the above preparation method, the thickness of the insulating medium layer is 4000~10000Å, and the insulating medium is SiO2.

[0016] In the above preparation method, the alloy layer is a SiC-Ni alloy layer.

[0017] Compared with the prior art, the present application uses polycrystalline SiC (Poly-SiC) material as the gate material of SiC MOSFET devices. The process method required to deposit metal on the surface of polycrystalline SiC material and form SiC-metal (such as SiC-Ni) alloy through annealing process is simple. Secondly, the present application introduces the isolation sidewall (insulating dielectric) process in the polycrystalline etching stage, and simultaneously forms the gate alloy layer on the surface of polycrystalline SiC and the source alloy layer on the surface of SiC source electrode through sub-alignment, eliminating the step of implementing the gate alloy process separately and simplifying the process flow. Therefore, the gate made of polycrystalline SiC material can obtain a smaller cell size and polycrystalline thickness. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1-10 According to some embodiments of the present application, a schematic diagram of step-by-step structural changes in manufacturing a polycrystalline SiC gate electrode is shown; Fig.11 According to some embodiments of the present application, a flow chart of a method for preparing a SiC MOSFET device is shown. DETAILED DESCRIPTION

[0019] Illustrative embodiments of the present application include, but are not limited to, trench gate power MOSFETs and methods of manufacturing the same.

[0020] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0021] The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used in this article refers to and includes any or all possible combinations of one or more associated listed items. "Include" or "include" and similar words mean that the elements or objects appearing in front of "include" or "include" cover the elements or objects listed after "include" or "include" and their equivalents, and do not exclude other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, and can include electrical connections, whether direct or indirect.

[0022] It should be understood that although the terms first, second, third, etc. may be used in the present application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0023] The following will be combined with the attached Figure 1-10 The embodiments of the present application are described in further detail. Figure 1-10 A schematic diagram of the step-by-step structural changes in making a polycrystalline SiC gate electrode is shown.

[0024] The present application is intended to improve the method for preparing the gate, and the preliminary steps for making a MOSFET device can be made using conventional steps currently or in the future. For example, the present application can be used in Figure 1 The processing is continued on the basis of the epitaxial wafer treated in the previous steps. The epitaxial wafer shown in the figure has completed the ion implantation processes such as P-WELL, source P+, ​​source N based on the SiC (silicon carbide) epitaxial wafer 1, and after the high temperature annealing process and the gate oxidation process, a silicon carbide oxide layer 2 is formed on the surface of the epitaxial wafer 1. The technical solution proposed in this application continues to process on the surface of the silicon carbide oxide layer 2. In the completed device, the silicon carbide oxide layer 2 is the gate dielectric of the gate electrode.

[0025] As described in the background technology section, SiC MOSFET devices in the prior art basically follow the Si device production method and use polycrystalline Si (Poly-Si) materials as gate materials. However, in the process of device miniaturization, the use of polycrystalline Si materials makes the problem of high gate resistance more prominent. The current solution is to manufacture double-layer gate materials, that is, grow a layer of metal (mainly W in Si devices) on the surface of polycrystalline Si to reduce gate resistance. However, the process steps for growing metals such as W and Ti on polycrystalline Si are relatively complicated, requiring operations such as drilling and injection, and requires special manufacturing equipment.

[0026] This application proposes to use polycrystalline SiC to make a gate electrode, and select Ni (or Ti) as a metal material combined with polycrystalline SiC, and make polycrystalline SiC and Ni or Ti react by secondary annealing to generate a polycrystalline SiC alloy layer on the surface of the gate. Since annealing is a commonly used processing equipment in semiconductor device manufacturing and the processing steps are simple, compared with the existing solutions mentioned above, this application simplifies the processing steps, avoids the purchase / use of special equipment to manufacture the gate, and reduces the manufacturing cost.

[0027] Specifically, Figure 2 As shown, a layer of polycrystalline SiC 3 is deposited on the surface of the silicon carbide oxide layer 2 by CVD. As mentioned above, the purpose of polycrystalline SiC is to manufacture gates. Figure 2 The coverage of the polycrystalline SiC 3 shown in FIG. 3 may be approximately equal to (slightly larger than) the area planned for manufacturing the gate. Further, Figure 2 The polycrystalline thickness of the polycrystalline SiC 3 shown in the figure is preferably between 1000 and 10000 Å, and the polycrystalline crystal form may include multiple crystal forms such as 4H, 6H, 3C, or a mixture of more than one crystal form.

[0028] Figure 3 The shown is Figure 2 The structure of polycrystalline SiC 3 after etching is shown in FIG. First, the surface of polycrystalline SiC 3 is patterned to clearly mark the planned gate area, and then etching is performed according to the pattern to obtain the structure shown in FIG. Figure 3 The polycrystalline SiC conductive layer 4 is indicated by the reference numeral 4. The lower layer of the polycrystalline SiC conductive layer 4 is the silicon carbide oxide layer 2. After etching, the polycrystalline SiC 3 outside the gate region (currently the polycrystalline SiC conductive layer 4) is completely etched, and the outer side of the polycrystalline SiC conductive layer 4 is exposed.

[0029] Figure 4-5 FIG. 4 shows the structural changes of the device when the isolation sidewall is manufactured on the outer side of the polycrystalline SiC conductive layer 4. Figure 4As shown, after the polycrystalline SiC conductive layer 4 is manufactured (i.e., there is a height difference on the surface of the wafer, and the gate protrudes from the surface of the wafer), a layer of insulating medium 5 is grown on the surface of the wafer, and the surface of the insulating medium 5 forms an undulating appearance with the shape of the gate being high and the source being low. Then, the insulating medium 5 is etched in the vertical direction, and the etching depth is the thickness of the growth of the insulating medium 5 in the previous step. Therefore, except for the insulating medium 5 on the side of the polycrystalline SiC conductive layer 4, the insulating medium 5 in other positions is etched away, and the remaining part of the insulating medium 5 forms the following Figure 5 The structure of the isolation sidewall 6 is shown. Those skilled in the art will appreciate that Figure 5 In the structure shown, the shorter parts on both sides of the gate region are usually the source regions (the source has not yet been made), and an insulating medium is separated between the gate and the source, which serves to block the flow of electrons between the gate and the source.

[0030] Furthermore, in some other embodiments, the etching depth may be the sum of the thickness of the insulating medium 5 and the thickness of the silicon carbide oxide layer 2, so that the dielectric in the source region is also etched away synchronously, and the source electrode (surface metal) may be fabricated synchronously later. At this time, the dielectric of the sidewall 6 is a double-layer structure, that is, the upper dielectric is the insulating medium 5, and the lower dielectric is the material of the silicon carbide oxide layer 2.

[0031] In this embodiment, the insulating medium 5 is preferably SiO 2 , the thickness of the insulating medium 5 is preferably between 4000 and 10000 Å. Figure 4 When the thickness of the insulating medium 5 is 5000Å, it is necessary to etch 5000Å in the vertical direction to form the following: Figure 5 The structure shown has a spacer 6 , but the source region and the gate region are not covered with an insulating dielectric (effect).

[0032] In the above processing steps, by growing the insulating medium in a large area (larger than the gate area) and vertically etching the insulating medium, the sidewalls are manufactured in the gate area relatively simply and accurately, achieving a higher manufacturing efficiency compared to the prior art.

[0033] Figure 6 The structure after gate and source surface metallization is simultaneously implemented in the same several steps is shown. Figure 5On the basis of the structure with the side wall 6 shown, Ni is deposited into the source region and the gate region respectively, and then annealed twice to allow Ni to fully react with the polycrystalline SiC on the surface, and at the same time form a gate alloy layer 7a and a source alloy layer 7b, that is, the surfaces of the gate and the source are metallized together in the same process step. The gate alloy layer 7a and the source alloy layer 7b serve as connecting layers between the surface metal of the gate and the source and the polycrystalline SiC conductive layer, which increases the conductivity of the gate / source and helps to improve the reliability and stability of the device. It is worth noting that in the prior art, since the gate is basically made of polycrystalline Si as a manufacturing material, a special step is required when manufacturing the gate alloy layer, and it is impossible to implement surface metallization treatment in the same process as the source. In the present application, the source region and the gate region react synchronously during annealing, so in Figure 6 In the structure diagram shown, the gate alloy layer 7a and the source alloy layer 7b are manufactured at the same time. That is to say, in the next step, the manufacturing of the gate and the source can continue to be synchronized, and there is no need to reprocess the manufacturing steps of the source when the gate is manufactured separately. That is, the technical solution proposed in this application can also simplify the manufacturing process of the source and improve the manufacturing efficiency of the device.

[0034] Figure 7-10 A schematic diagram showing the structures at each stage when the gate metal and source metal are subsequently manufactured. Figure 7 Shown in Figure 6 The structure shown in FIG. 1 is a structure after an interlayer dielectric (ILD) layer 8 is grown on the surface of the wafer. The interlayer dielectric layer 8 completely covers the gate alloy layer 7a, the source alloy layer 7b and the sidewall 6 to form a Figure 4 The gate region is higher than the source region. The interlayer dielectric layer 8 is used to separate the gate region and the source region, so that the gate region is insulated from the source regions on both sides. Figure 8 The structure after etching the interlayer dielectric layer 8 is shown. After etching, an interlayer dielectric opening 9 is formed. The depth of the interlayer dielectric opening 9 shown is the same as the thickness of the interlayer dielectric layer 8, exposing the gate alloy layer 7a and the source alloy layer 7b. After the subsequent process steps, the remaining interlayer dielectric becomes the spacer between the gate and the source, which is used to cut off the electron migration path between the gate and the source, that is, to ensure the insulation between the two. Fig. 9 Shown in Figure 8 The surface metal layer 10 fills the interlayer dielectric opening 9 and continues to be deposited until all source regions and gate regions are covered with a certain thickness. Then, the surface metal layer 10 is obtained by etching. Fig.10The final structure shown. In this step, the surface metal layer 10 connected as one is separated into the gate 12 and the source 11, so that there is no conductive path between the two. The metal gate 12 and source 11 can provide reliable connection points for the pins of the chip when the chip is packaged later.

[0035] The above schematic diagrams of a series of structural changes illustrate the process of using polycrystalline SiC as the gate material to make MOSFET devices in this application. When metallizing the gate surface, using polycrystalline SiC as the gate material can use a more common annealing process to catalyze the combination of metal Ni and the gate material, simplifying the manufacturing process and reducing manufacturing costs.

[0036] The following is passed Fig.11 The manufacturing steps are briefly described with reference to the flowchart of the SiC MOSFET device preparation method shown in FIG.

[0037] Step 101, deposit polycrystalline SiC on a SiC epitaxial wafer (wafer) that has completed conventional P-WELL, source P+, ​​sourceN ion implantation processes, and subsequent high-temperature annealing and gate oxidation processes. Specifically, a layer of polycrystalline SiC is grown on the SiC epitaxial wafer by CVD (chemical vapor deposition) and / or PVD (physical vapor deposition), and the deposition range of the polycrystalline SiC at least includes the gate region to be used to manufacture the gate. The grown polycrystalline SiC is then patterned, and the pattern accurately locates the gate region (in fact, the source region is usually etched out at the same time), and the pattern is etched by a dry etching process to form a polycrystalline SiC conductive layer on the gate region.

[0038] Step 102, making an isolation side wall, specifically includes: a. After the previous steps are completed, an insulating dielectric layer is grown on the surface of the SiC epitaxial wafer, and the growth range of the insulating dielectric layer covers and is larger than the polycrystalline SiC conductive layer. After the device is manufactured, the insulating dielectric exists at the bottom of the gate as a gate dielectric, isolating the current path between the polycrystalline SiC conductive layer and the epitaxial layer.

[0039] b. Patterning the insulating dielectric layer, and then etching the insulating dielectric layer according to the pattern, the etching range is larger than the polycrystalline SiC conductive layer and smaller than the insulating dielectric layer, so that the insulating dielectric layer covers the polycrystalline SiC conductive layer like a cap. The etching depth is until the upper surface of the polycrystalline SiC conductive layer is exposed, that is, the etching depth is greater than or equal to the thickness of the insulating dielectric layer, so as to form an isolation sidewall composed of insulating dielectric on the outer side of the polycrystalline SiC conductive layer; Step 103, using a secondary annealing process, an alloy layer is made on the surface of the polycrystalline SiC conductive layer and the surface of the source electrode, that is, a SiNi alloy layer is formed on the surface of SiC (the gate is polycrystalline SiC, and the source is single crystal SiC), and an ohmic contact electrode is prepared, which is conducive to the subsequent growth of metal for current extraction. In order to simplify the steps required for the metallization process, Ni is selected as the metal material of the alloy in this embodiment. SiC and Ni can react only at high temperature, that is, an alloy layer (metallization layer) can be formed only after annealing process.

[0040] In the prior art, polycrystalline Si is usually used in the same position. Those skilled in the art should know that under the premise of miniaturization of the device, its gate, source, etc. should also reduce the "footprint" accordingly. When using polycrystalline Si to make the gate, the reduction in gate size and thickness required for device miniaturization will cause its resistance to increase significantly. In order to reduce the gate resistance, it is necessary to add additional, repeated steps to deposit metal to reduce the gate resistance. The present application utilizes the characteristics of polycrystalline SiC that can be well combined with metal (Ni or Ti), and uses existing equipment and process steps to simultaneously perform high-temperature catalysis on the source and gate in the same step to form an alloy layer, thereby simplifying the process steps.

[0041] Annealing is an essential process step in the manufacturing process of MOSFET devices, so the metallization process in this embodiment does not require additional special equipment, and the original equipment can be directly used. Specifically, the secondary annealing process usually includes a low-temperature annealing and a high-temperature annealing, which can be performed according to the usual specifications, and this application will not go into details. An additional beneficial effect of this step is that the source can be metallized synchronously while the gate is metallized, which simplifies the process steps and improves production efficiency.

[0042] Step 104, deposit a dielectric layer and etch it to expose the area for making the gate and source. The remaining insulating material that has not been etched can be used to isolate the gate and source. This step corresponds to Figure 7-8 Schematic diagram of structural changes, please refer to the relevant Figure 7-8 Description.

[0043] Step 105, depositing surface metal and etching to finally form the gate and source. This step corresponds to Figure 9-10 Schematic diagram of structural changes, please refer to the relevant Figure 9-10 Description.

[0044] It should be noted that in the examples and description of this patent, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one" do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0045] Although the present application has been illustrated and described with reference to certain preferred embodiments thereof, it will be apparent to those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present application.

Claims

1. A SiC MOSFET device, comprising a gate electrode, a source electrode and a drain electrode, characterized in that: The gate electrode is located on the front side of the wafer and includes: Gate dielectric; A polycrystalline SiC conductive layer, located on the gate dielectric on the surface of the wafer, serving as a lower component of the gate electrode; A polycrystalline SiC surface alloy layer, located on the surface of the polycrystalline SiC conductive layer, is used to increase the conductivity of the gate; The source electrode is located on the front side of the wafer and includes: A source surface alloy layer, located on both sides of the gate electrode, and electrically insulated from the gate electrode by an isolation sidewall, wherein the isolation sidewall is an insulating medium; The drain electrode is located on the reverse side of the wafer.

2. The SiC MOSFET device according to claim 1, characterized in that: The polycrystalline SiC surface alloy layer and the source electrode surface alloy layer are formed in the same process step.

3. The SiC MOSFET device according to claim 1, characterized in that: An interlayer dielectric layer is formed on the outer edge side of the gate electrode and the outer edge side of the source electrode.

4. The SiC MOSFET device according to claim 3, characterized in that: Also includes: A gate metal is located on the surface of the polycrystalline SiC gate surface alloy layer; A source metal is located on the surface of the source surface alloy layer, and the gate metal and the source metal are electrically isolated by the interlayer dielectric layer; Furthermore, the gate metal and the source metal are formed in the same step.

5. The SiC MOSFET device according to claim 1, characterized in that: The material of the polycrystalline SiC surface alloy layer and the source electrode surface alloy layer is SiC-Ni alloy.

6. A method for preparing a SiC MOSFET device, characterized in that: The steps include: Making a gate dielectric on the SiC epitaxial surface after the previous step processing; Depositing polycrystalline SiC on the surface of the gate dielectric and etching it to form a polycrystalline SiC conductive layer in the gate region as a lower component of the gate electrode; Making the isolation side wall includes: Growing an insulating dielectric layer on the surface of the wafer, wherein the growth range of the insulating dielectric layer covers and is larger than the range of the polycrystalline SiC conductive layer; Etching the insulating dielectric layer, the etching range and depth being until the surface of the polycrystalline SiC conductive layer and the surface of the SiC wafer used to make the source region are exposed, thereby forming the isolation sidewall composed of the insulating dielectric on the outer side of the polycrystalline SiC conductive layer; Depositing metal on the surface of the wafer, and using a secondary annealing process to form an alloy layer providing ohmic contact on the surface of the polycrystalline SiC conductive layer and the surface of the source region; An interlayer dielectric is grown on the surface of the polycrystalline SiC conductive layer and the surface of the source region, and then the interlayer dielectric is etched to expose a middle region between the surface of the polycrystalline SiC conductive layer and the surface of the source region.

7. The preparation method according to claim 6, characterized in that: The method also includes depositing a dielectric layer and a surface metal on the alloy layer to finally form a gate and a source.

8. The preparation method according to claim 6, characterized in that: The depositing of polycrystalline SiC on the gate dielectric surface specifically comprises: Growing a layer of polycrystalline SiC on the surface of the wafer by CVD or PVD; The grown polycrystalline SiC is patterned using a dry etching process to form a gate electrode pattern.

9. The preparation method according to claim 6 or 8, characterized in that: The thickness of the polycrystalline SiC conductive layer is 1000-10000Å.

10. The preparation method according to claim 6 or 8, characterized in that: The polycrystalline SiC conductive layer may have a polycrystalline type of 4H, 6H, 3C, or any combination of the above types.

11. The preparation method according to claim 6, characterized in that: The thickness of the insulating medium layer is 4000-10000Å, and the insulating medium is SiO2.

12. The preparation method according to claim 6, characterized in that: The alloy layer is a SiC-Ni alloy layer.

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