Solar cell and method for manufacturing solar cell

Abstract

The invention provides a solar cell and a manufacturing method of the solar cell, and mainly relates to the technical field of photovoltaics. The solar cell comprises a silicon substrate with a first surface and a second surface which are opposite to each other in the thickness direction, and the first surface of the silicon substrate sequentially comprises a first tunneling oxide layer, a first lightly doped layer, a first transparent conductive layer, a first heavily doped layer and a first passivation layer from inside to outside, and the doping types of the first lightly doped layer and the first heavily doped layer are the same. The doping layer is divided into the lightly doped layer, the transparent conductive layer and the heavily doped layer, and by means of good conductivity and light transmission of the transparent conductive layer, the passivation performance and low contact resistance of the solar cell are ensured, the negative influence of parasitic current on the cell efficiency is reduced, and the cell efficiency is improved.

Description

Technical Field

[0001] The present application mainly relates to the field of photovoltaic technology, and in particular to a solar cell and a method for manufacturing a solar cell. Background Art

[0002] Tunnel Oxide Passivated Contact (TOPCon) cells can significantly reduce the recombination of electrons and holes due to the unique tunneling characteristics of their tunneling layer, greatly increasing the cell's opening voltage and current density.

[0003] The TOPCon cell with double-sided polysilicon structure deposits tunnel oxide layer and polysilicon (poly-Si) layer on both the front and back sides. The front and back sides are usually p-poly and n-poly, which improves the passivation effect of the front and back sides and increases the opening voltage. However, compared with crystalline silicon (C-Si), polysilicon has a certain disadvantage of large parasitic absorption, which reduces the current density of the cell and thus affects the cell efficiency. Summary of the invention

[0004] In order to solve the above technical problems, the present application provides a solar cell and a method for manufacturing a solar cell, which can reduce the parasitic absorption and contact resistance of the cell and improve the cell efficiency.

[0005] In a first aspect, the present application provides a solar cell, comprising:

[0006] A silicon substrate having a first surface and a second surface opposite to each other in a thickness direction;

[0007] The first surface of the silicon substrate includes, from inside to outside, a first tunneling oxide layer, a first lightly doped layer, a first transparent conductive layer, a first heavily doped layer and a first passivation layer, wherein the first lightly doped layer and the first heavily doped layer have the same doping type.

[0008] In a possible implementation manner, the thickness of the first transparent conductive layer is 10-40 nm.

[0009] In a possible implementation, the refractive index of the first transparent conductive layer is 1.9-2.2, and the sheet resistance is 18-100 ohm / sq.

[0010] In a possible implementation, the thickness of the first lightly doped layer is 10-30 nm; the thickness of the first heavily doped layer is 30-50 nm.

[0011] In a possible implementation, the doping concentration of the first doping impurity in the first lightly doped layer is 2E19-5E19 atoms / cm3, and the doping concentration of the first doping impurity in the first heavily doped layer is 6E19-1E20 atoms / cm3.

[0012] In one possible implementation, the second surface of the silicon substrate includes, from the inside to the outside, a second tunneling oxide layer, a second lightly doped layer, a second transparent conductive layer, a second heavily doped layer, and a second passivation layer, wherein the second lightly doped layer and the second heavily doped layer have the same doping type, and the second lightly doped layer and the first lightly doped layer have opposite doping types.

[0013] In a possible implementation manner, the thickness of the second transparent conductive layer is 10-40 nm.

[0014] In a possible implementation, the refractive index of the second transparent conductive layer is 1.9-2.2, and the sheet resistance is 18-100 ohm / sq.

[0015] In a possible implementation, the thickness of the second lightly doped layer is 10-50 nm; the thickness of the second heavily doped layer is 30-100 nm.

[0016] In a possible implementation, the doping concentration of the second doping impurity in the second lightly doped layer is 2E19-5E19 atoms / cm3, and the doping concentration of the second doping impurity in the second heavily doped layer is 6E19-1E20 atoms / cm3.

[0017] In a possible implementation, the doping type of the first lightly doped layer and the first heavily doped layer is P-type doping, and the doping type of the second lightly doped layer and the second heavily doped layer is N-type doping.

[0018] In a second aspect, the present application provides a method for manufacturing a solar cell, comprising:

[0019] Providing a silicon substrate having a first surface and a second surface opposite to each other in a thickness direction;

[0020] Forming a first tunneling oxide layer, a first lightly doped layer, a first transparent conductive layer and a first heavily doped layer in sequence on the first surface of the silicon substrate, wherein the first lightly doped layer and the first heavily doped layer have the same doping type;

[0021] forming a first passivation layer on a first surface of the silicon substrate, and forming a second passivation layer on a second surface of the silicon substrate;

[0022] A first electrode contacting the first heavily doped layer is formed on the first surface of the silicon substrate.

[0023] In a possible implementation manner, before forming a first passivation layer on the first surface of the silicon substrate and forming a second passivation layer on the second surface of the silicon substrate, the method further includes:

[0024] Forming a second tunneling oxide layer, a second lightly doped layer, a second transparent conductive layer and a second heavily doped layer in sequence on the second surface of the silicon substrate, wherein the second lightly doped layer and the second heavily doped layer have the same doping type, and the second lightly doped layer and the first lightly doped layer have opposite doping types;

[0025] After forming a first passivation layer on the first surface of the silicon substrate and forming a second passivation layer on the second surface of the silicon substrate, the method further includes:

[0026] A second electrode contacting the second heavily doped layer is formed on the second surface of the silicon substrate.

[0027] Compared with the prior art, this application has the following advantages:

[0028] The solar cell of the present application includes a silicon substrate having a first surface and a second surface opposite to each other in the thickness direction, wherein the first surface of the silicon substrate includes, from the inside to the outside, a first tunneling oxide layer, a first lightly doped layer, a first transparent conductive layer, a first heavily doped layer, and a first passivation layer, wherein the first lightly doped layer and the first heavily doped layer have the same doping type. The present application divides the doped layer into a lightly doped layer, a transparent conductive layer, and a heavily doped layer, and by virtue of the good conductivity and light transmittance of the transparent conductive layer, ensures the passivation performance and low contact resistance of the solar cell, while reducing the negative impact of parasitic current on the cell efficiency and improving the cell efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings are included to provide a further understanding of the present application. They are included and constitute a part of the present application. The accompanying drawings illustrate embodiments of the present application and together with the present specification serve to explain the principles of the present application. In the accompanying drawings:

[0030] Figure 1 is a schematic structural diagram of a solar cell provided in an embodiment of the present application;

[0031] Figure 2 is a schematic diagram of the structure of another solar cell provided in an embodiment of the present application;

[0032] Figure 3 is a schematic diagram of the structure of another solar cell provided in an embodiment of the present application;

[0033] Figure 4 is a schematic diagram of the structure of another solar cell provided in an embodiment of the present application;

[0034] Figure 5This is a schematic diagram of the structure of another solar cell provided in an embodiment of the present application.

[0035] In the figure: 100, silicon substrate; 111, first front passivation layer; 112, front anti-reflection layer; 121, back tunneling oxide layer; 122, back lightly doped layer; 123, back transparent conductive layer; 124, back heavily doped layer; 125, back passivation layer; 126, back first electrode; 127, back second electrode; 211, front doped layer; 212, second front passivation layer; 213, first front electrode; 226, first back electrode; 311, front tunneling oxide layer; 312, front lightly doped layer; 313, front transparent conductive layer; 314, front heavily doped layer Layer; 315, front passivation layer; 316, second front electrode; 321, back tunneling layer; 322, back doping layer; 324; second back electrode; 511, front silicon dioxide layer; 512, front lightly doped polysilicon layer; 513, front TCO layer; 514, front heavily doped polysilicon layer; 515, front silicon nitride layer; 516, third front electrode; 521, back silicon dioxide layer; 522, back lightly doped polysilicon layer; 523, back TCO layer; 524, back heavily doped polysilicon layer; 525, back silicon nitride layer; 526, third back electrode. DETAILED DESCRIPTION

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for the description of the embodiments. Obviously, the drawings described below are only some examples or embodiments of the present application. For ordinary technicians in this field, the present application can also be applied to other similar scenarios based on these drawings without creative work. Unless it is obvious from the language environment or otherwise explained, the same reference numerals in the figures represent the same structure or operation.

[0037] As shown in this application, unless the context clearly indicates an exception, the words "a", "an", "a kind" and / or "the" do not refer to the singular, but also include the plural. Generally speaking, the terms "include" and "comprise" only indicate the inclusion of the steps and elements that have been clearly identified, and these steps and elements do not constitute an exclusive list. The method or device may also include other steps or elements.

[0038] Unless otherwise specifically stated, the relative arrangement, numerical expressions and numerical values ​​of the parts and steps set forth in these embodiments do not limit the scope of the present application. Meanwhile, it should be understood that, for ease of description, the sizes of the various parts shown in the accompanying drawings are not drawn according to actual proportional relationships. The technology, methods and equipment known to those of ordinary skill in the relevant art may not be discussed in detail, but in appropriate cases, the technology, methods and equipment should be considered as a part of the specification. In all examples shown and discussed here, any specific value should be interpreted as being merely exemplary, rather than as a limitation. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters represent similar items in the following drawings, and therefore, once a certain item is defined in an accompanying drawing, it does not need to be further discussed in subsequent drawings.

[0039] In the description of the present application, it should be understood that the directions or positional relationships indicated by directional words such as "front, back, up, down, left, right", "lateral, vertical, perpendicular, horizontal" and "top, bottom" are usually based on the directions or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description. Unless otherwise specified, these directional words do not indicate or imply that the device or element referred to must have a specific direction or be constructed and operated in a specific direction, and therefore cannot be understood as limiting the scope of protection of the present application; the directional words "inside and outside" refer to the inside and outside relative to the contours of each component itself.

[0040] For ease of description, spatially relative terms such as "above", "above", "on the upper surface of", "above", etc. may be used here to describe the spatial positional relationship between a device or feature and other devices or features as shown in the figure. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Thus, the exemplary term "above" can include both "above" and "below". The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used here are interpreted accordingly.

[0041] In addition, it should be noted that the use of words such as "first" and "second" to define components is only for the convenience of distinguishing the corresponding components. If not otherwise stated, the above words have no special meaning and cannot be understood as limiting the scope of protection of this application. In addition, although the terms used in this application are selected from well-known and commonly used terms, some terms mentioned in the specification of this application may be selected by the applicant at his or her discretion, and their detailed meanings are explained in the relevant parts of the description of this article. In addition, it is required to understand this application not only by the actual terms used, but also by the meaning implied by each term.

[0042] It should be understood that when a component is referred to as being "on another component," "connected to another component," "coupled to another component," or "contacting another component," it may be directly on, connected to, coupled to, or contacting the other component, or there may be intervening components. In contrast, when a component is referred to as being "directly on another component," "directly connected to," "directly coupled to," or "directly contacting" another component, there are no intervening components. Similarly, when a first component is referred to as being "electrically in contact with" or "electrically coupled to" a second component, there is an electrical path between the first component and the second component that allows current to flow. The electrical path may include capacitors, coupled inductors, and / or other components that allow current to flow, even without direct contact between conductive components.

[0043] The solar cell of the embodiment of the present application includes a silicon substrate having a first surface and a second surface opposite to each other in the thickness direction, and at least one of the first surface and the second surface of the silicon substrate includes a tunneling oxide layer, a lightly doped layer, a transparent conductive layer, a heavily doped layer and a passivation layer in order from the inside to the outside, wherein the lightly doped layer and the heavily doped layer on the same surface have the same doping type, and the doping types of the doped layers on different surfaces are opposite. For P-type doping, the doping impurities may be boron, indium, gallium, etc.; for N-type doping, the doping impurities may be phosphorus, arsenic, antimony, etc. It should be noted that the first surface may be the front side of the solar cell, or the second surface may be the front side of the solar cell. When the solar cell is working, the front side faces the sun.

[0044] On the one hand, the outer heavily doped layer has a high surface concentration, and its doping concentration of impurities is about 6E19-1E20 atoms / cm 3 , it is easy for the slurry to form good contact, but the increase in doping concentration may lead to increased parasitic absorption, so it is necessary to control the thickness of the heavily doped layer. In some embodiments, the thickness of the heavily doped layer is about 30-100nm, such as 30-50nm. For example, the thickness of the heavily doped layer can be 30nm, 40nm, 50nm, 70nm, 80nm or 100nm.

[0045] On the other hand, the doping concentration of the bottom lightly doped layer is low, and its doping concentration of impurities is about 2E19-5E19 atoms / cm 3 In some embodiments, the thickness of the lightly doped layer is about 10-50 nm, such as 10-30 nm. For example, the thickness of the lightly doped layer may be 10 nm, 20 nm, 30 nm, 40 nm or 50 nm.

[0046] At the same time, the transparent conductive layer in the middle has good conductivity and light transmittance, which can ensure good contact resistance. The transparent conductive layer can be a transparent conductive oxide (TCO) film, such as a tin-doped indium oxide (ITO) film or a tungsten-doped indium oxide (IWO) film. In some embodiments, the thickness of the transparent conductive layer is about 10-40nm, the refractive index is about 1.9-2.2, and the square resistance is about 18-100ohm / sq.

[0047] The embodiment of the present application divides the doping layer into a lightly doped layer, a transparent conductive layer and a heavily doped layer, and utilizes the good conductivity and light transmittance of the transparent conductive layer to ensure the passivation performance and low contact resistance of the solar cell, while reducing the negative impact of parasitic current on battery efficiency and improving battery efficiency.

[0048] Figure 1 1 is a schematic diagram of the structure of a solar cell provided in an embodiment of the present application. In this embodiment, the solar cell may be a back contact (BC) type cell. The electrodes of a BC cell are all located on the back of the cell, and there is no grid line blocking the front, so the cell efficiency is high.

[0049] like Figure 1 As shown, the solar cell includes a silicon substrate 100, which can be an N-type silicon substrate or a P-type silicon substrate. The front side of the silicon substrate 100 includes a first front side passivation layer 111 and a front side anti-reflection layer 112 in order from the inside to the outside.

[0050] The back side of the silicon substrate 100 includes, from the inside to the outside, a back tunneling oxide layer 121, a back lightly doped layer 122, a back transparent conductive layer 123, a back heavily doped layer 124, and a back passivation layer 125. The back tunneling oxide layer 121 may be a silicon oxide layer, the back lightly doped layer 122 may be a lightly doped polysilicon layer, the back transparent conductive layer 123 may be a TCO film, the back heavily doped layer 124 may be a heavily doped polysilicon layer, and the back passivation layer 125 may be a silicon nitride layer.

[0051] The back side of the silicon substrate 100 further includes alternately distributed back first electrodes 126 and back second electrodes 127, one of which is a positive electrode and the other is a negative electrode. The back first electrode 126 and the back second electrode 127 are in contact with the back heavily doped layer 124 through the back passivation layer 125.

[0052] In some embodiments, the back lightly doped layer 122 and the back heavily doped layer 124 are phosphorus-doped layers, and the phosphorus doping concentration in the back lightly doped layer 122 is about 2E19-5E19 atoms / cm 3 The phosphorus doping concentration in the back heavily doped layer 124 is about 6E19-1E20 atoms / cm 3 For example, the thickness of the back lightly doped layer 122 is about 20 nm, the thickness of the back transparent conductive layer 123 is about 10 nm, the refractive index is about 1.9, and the thickness of the back heavily doped layer 124 is about 30 nm. It can be understood that the doping medium on the back of the silicon substrate 100 in this embodiment can also be other media such as indium and gallium.

[0053] The method for manufacturing a solar cell of this embodiment may include the following steps:

[0054] (1) A silicon substrate 100 is provided.

[0055] (2) A back tunneling oxide layer 121 , a back lightly doped layer 122 , a back transparent conductive layer 123 and a back heavily doped layer 124 are sequentially formed on the back side of the silicon substrate 100 .

[0056] For example, after cleaning the silicon substrate 100, a plasma enhanced chemical vapor deposition (PECVD) process is used to deposit a back tunneling oxide layer 121 and a back lightly doped layer 122 on the back side of the silicon substrate 100. Then, a physical vapor deposition (PVD) process is used to deposit a back transparent conductive layer 123 on the back side of the silicon substrate 100. A back heavily doped layer 124 is then deposited on the back side of the silicon substrate 100 using the PECVD process.

[0057] (3) A back passivation layer 125 is formed on the back surface of the silicon substrate 100 , and a first front passivation layer 111 is formed on the front surface of the silicon substrate 100 .

[0058] For example, a back passivation layer 125 may be formed on the back side of the silicon substrate 100 and a first front passivation layer 111 may be formed on the front side of the silicon substrate 100 using a PECVD process.

[0059] (4) A front anti-reflection layer 112 is formed on the front surface of the silicon substrate 100 , and a back first electrode 126 and a back second electrode 127 contacting the back heavily doped layer 124 are formed on the back surface of the silicon substrate 100 .

[0060] For example, the front anti-reflection layer 112 can be formed on the front side of the silicon substrate 100 using a PECVD process. Silver paste is printed on the back side of the silicon substrate 100 and sintered to form a back first electrode 126 and a back second electrode 127 contacting the back heavily doped layer 124.

[0061] In this embodiment, a back tunneling oxide layer 121, a back lightly doped layer 122, a back transparent conductive layer 123, a back heavily doped layer 124 and a back passivation layer 125 are formed on the back of the BC type battery to improve its back passivation performance, reduce contact resistance and parasitic absorption, and improve battery efficiency.

[0062] Figure 2 is a schematic diagram of the structure of another solar cell provided in an embodiment of the present application. In this embodiment, the solar cell may be a TOPCon cell. Figure 2 As shown, the solar cell includes a silicon substrate 100. The front side of the silicon substrate 100 includes a front doping layer 211 and a second front passivation layer 212 from the inside to the outside. The front doping layer 211 may be a doped polysilicon layer, and the second front passivation layer 212 may be a silicon nitride layer. The front side of the silicon substrate 100 also includes a first front electrode 213, which passes through the second front passivation layer 212 and contacts the front doping layer 211.

[0063] The back side of the silicon substrate 100 includes, from inside to outside, a back tunneling oxide 121, a back lightly doped layer 122, a back transparent conductive layer 123, a back heavily doped layer 124, and a back passivation layer 125. The back side of the silicon substrate 100 also includes a first back electrode 226, which passes through the back passivation layer 125 and contacts the back heavily doped layer 124.

[0064] In some embodiments, the front doped layer 211 is a boron doped layer, and the boron doping concentration in the front doped layer 211 is about 6E19-7E19 atoms / cm 3 The back lightly doped layer 122 and the back heavily doped layer 124 are phosphorus-doped layers. The phosphorus doping concentration in the back lightly doped layer 122 is approximately 2E19-4E19 atoms / cm 3 The phosphorus doping concentration in the back heavily doped layer 124 is about 7E19-1E20 atoms / cm 3 .

[0065] For example, the back lightly doped layer 122 has a thickness of about 40 nm, the back transparent conductive layer 123 has a thickness of about 20 nm and a refractive index of about 2, and the back heavily doped layer 124 has a thickness of about 50 nm.

[0066] The method for manufacturing a solar cell of this embodiment may include the following contents:

[0067] (1) A silicon substrate 100 is provided.

[0068] (2) A front doping layer 211 is formed on the front surface of the silicon substrate 100 .

[0069] For example, after cleaning the silicon substrate 100 , a front doping layer 211 is deposited on the front side of the silicon substrate 100 using a PECVD process.

[0070] (3) A back tunneling oxide layer 121 , a back lightly doped layer 122 , a back transparent conductive layer 123 and a back heavily doped layer 124 are sequentially formed on the back side of the silicon substrate 100 .

[0071] For example, a PECVD process may be used to deposit a back tunneling oxide layer 121 and a back lightly doped layer 122 on the back side of the silicon substrate 100. A physical vapor deposition (PVD) process is then used to deposit a back transparent conductive layer 123 on the back side of the silicon substrate 100. A back heavily doped layer 124 is then deposited on the back side of the silicon substrate 100 using a PECVD process.

[0072] (4) A second front passivation layer 212 is formed on the front surface of the silicon substrate 100 , and a back passivation layer 125 is formed on the back surface of the silicon substrate 100 .

[0073] For example, the second front passivation layer 212 may be deposited on the front side of the silicon substrate 100 , and the back side passivation layer 125 may be deposited on the back side of the silicon substrate 100 using a PECVD process.

[0074] (5) A first front electrode 213 contacting the front doped layer 211 is formed on the front surface of the silicon substrate 100 , and a first back electrode 226 contacting the back heavily doped layer 124 is formed on the back surface of the silicon substrate 100 .

[0075] For example, silver paste may be printed on the front and back sides of the silicon substrate 100 , and the first front electrode 213 and the first back electrode 226 may be formed after sintering.

[0076] In this embodiment, a back tunneling oxide layer 121, a back lightly doped layer 122, a back transparent conductive layer 123, a back heavily doped layer 124 and a back passivation layer 125 are formed on the back of the TOPCon battery to improve its back passivation performance, reduce contact resistance and parasitic absorption, and improve battery efficiency.

[0077] Figure 3 FIG. 1 is a schematic diagram of the structure of another solar cell provided in an embodiment of the present application. In this embodiment, the solar cell may be a TOPCon cell. Figure 3As shown, the solar cell includes a silicon substrate 100. The front side of the silicon substrate 100 includes a front tunneling oxide layer 311, a front lightly doped layer 312, a front transparent conductive layer 313, a front heavily doped layer 314, and a front passivation layer 315 from the inside to the outside. Among them, the front tunneling oxide layer 311 can be a silicon oxide layer, the front lightly doped layer 312 can be a lightly doped polysilicon layer, the front transparent conductive layer 313 can be a TCO film, the front heavily doped layer 314 can be a heavily doped polysilicon layer, and the front passivation layer 315 can be a silicon nitride layer. The front side of the silicon substrate 100 also includes a second front electrode 316, and the second front electrode 316 passes through the front passivation layer 315 and contacts the front heavily doped layer 314.

[0078] The back side of the silicon substrate 100 includes a back tunneling layer 321, a back doping layer 322 and a back passivation layer 125 in order from inside to outside. The back tunneling layer 321 may be a silicon oxide layer, and the back doping layer 322 may be a doped polysilicon layer. The back side of the silicon substrate 100 also includes a second back electrode 324, which passes through the back passivation layer 125 and contacts the back doping layer 322.

[0079] In some embodiments, the front lightly doped layer 312 and the front heavily doped layer 314 are phosphorus-doped layers, and the phosphorus doping concentration in the front lightly doped layer 312 is approximately 3E19-5E19 atoms / cm 3 The phosphorus doping concentration in the front heavily doped layer 314 is about 8E19-1E20 atoms / cm 3 The back doping layer 322 is a boron doping layer, and the boron doping concentration in the back doping layer 322 is about 6E19-8E19 atoms / cm 3 .

[0080] For example, the thickness of the front lightly doped layer 312 is about 30 nm, the thickness of the front transparent conductive layer 313 is about 30 nm, the refractive index is about 2.1, and the thickness of the front heavily doped layer 314 is about 40 nm.

[0081] The method for manufacturing a solar cell of this embodiment may include the following steps:

[0082] (1) A silicon substrate 100 is provided.

[0083] (2) A front tunneling oxide layer 311 , a front lightly doped layer 312 , a front transparent conductive layer 313 and a front heavily doped layer 314 are sequentially formed on the front surface of the silicon substrate 100 .

[0084] For example, after cleaning the silicon substrate 100, a front tunneling oxide layer 311 and a front lightly doped layer 312 are deposited on the front side of the silicon substrate 100 using a PECVD process. Then, a front transparent conductive layer 313 is deposited on the front side of the silicon substrate 100 using a PVD process. A front heavily doped layer 314 is deposited on the front side of the silicon substrate 100 using a PECVD process.

[0085] (3) A back tunneling layer 321 and a back doping layer 322 are sequentially formed on the back side of the silicon substrate 100 .

[0086] For example, the back tunneling layer 321 and the back doping layer 322 may be deposited on the back side of the silicon substrate 100 using a PECVD process.

[0087] (4) A front passivation layer 315 is formed on the front surface of the silicon substrate 100 , and a back passivation layer 125 is formed on the back surface of the silicon substrate 100 .

[0088] For example, the front passivation layer 315 may be deposited on the front side of the silicon substrate 100 , and the back passivation layer 125 may be deposited on the back side of the silicon substrate 100 using a PECVD process.

[0089] (5) A second front electrode 316 is formed on the front side of the silicon substrate 100 to contact the front heavily doped layer 314 , and a second back side electrode 324 is formed on the back side of the silicon substrate 100 to contact the back side doped layer 322 .

[0090] For example, silver paste may be printed on the front and back sides of the silicon substrate 100 , and then sintered to form the second front electrode 316 and the second back electrode 324 .

[0091] In this embodiment, a front tunneling oxide layer 311, a front lightly doped layer 312, a front transparent conductive layer 313, a front heavily doped layer 314 and a front passivation layer 315 are formed on the front side of the TOPCon battery, so as to improve the front passivation performance, reduce the contact resistance and parasitic absorption, and improve the battery efficiency.

[0092] Figure 4 FIG. 1 is a schematic diagram of the structure of another solar cell provided in an embodiment of the present application. In this embodiment, the solar cell may be a double-sided TOPCon cell. Figure 4 As shown, the solar cell includes a silicon substrate 100. The front side of the silicon substrate 100 includes, from the inside to the outside, a front tunneling oxide layer 311, a front lightly doped layer 312, a front transparent conductive layer 313, a front heavily doped layer 314, and a front passivation layer 315. The front side of the silicon substrate 100 also includes a second front electrode 316, which passes through the front passivation layer 315 and contacts the front heavily doped layer 314.

[0093] The back side of the silicon substrate 100 includes, from inside to outside, a back tunneling oxide 121, a back lightly doped layer 122, a back transparent conductive layer 123, a back heavily doped layer 124, and a back passivation layer 125. The back side of the silicon substrate 100 also includes a first back electrode 226, which passes through the back passivation layer 125 and contacts the back heavily doped layer 124.

[0094] In some embodiments, the front lightly doped layer 312 and the front heavily doped layer 314 are phosphorus-doped layers, and the phosphorus doping concentration in the front lightly doped layer 312 is approximately 2E19-5E19 atoms / cm 3 The phosphorus doping concentration in the front heavily doped layer 314 is about 6E19-1E20 atoms / cm 3 The back lightly doped layer 122 and the back heavily doped layer 124 are boron-doped layers. The boron doping concentration in the back lightly doped layer 122 is approximately 2E19-5E19 atoms / cm 3 The doping concentration of boron in the back heavily doped layer 124 is about 6E19-1E20 atoms / cm 3 .

[0095] For example, the thickness of the front lightly doped layer 312 is about 20 nm, the thickness of the front transparent conductive layer 313 is about 40 nm, the refractive index is about 2.2, and the thickness of the front heavily doped layer 314 is about 40 nm. The thickness of the back lightly doped layer 122 is about 30 nm, the thickness of the back transparent conductive layer 123 is about 40 nm, the refractive index is about 2.2, and the thickness of the back heavily doped layer 124 is about 60 nm.

[0096] The method for manufacturing a solar cell of this embodiment may include the following steps:

[0097] (1) A silicon substrate 100 is provided.

[0098] (2) A front tunneling oxide layer 311 , a front lightly doped layer 312 , a front transparent conductive layer 313 and a front heavily doped layer 314 are sequentially formed on the front surface of the silicon substrate 100 .

[0099] For example, after cleaning the silicon substrate 100, a front tunneling oxide layer 311 and a front lightly doped layer 312 are deposited on the front side of the silicon substrate 100 using a PECVD process. Then, a front transparent conductive layer 313 is deposited on the front side of the silicon substrate 100 using a PVD process. A front heavily doped layer 314 is deposited on the front side of the silicon substrate 100 using a PECVD process.

[0100] (3) A back tunneling oxide layer 121 , a back lightly doped layer 122 , a back transparent conductive layer 123 and a back heavily doped layer 124 are sequentially formed on the back side of the silicon substrate 100 .

[0101] For example, a PECVD process may be used to deposit a back tunneling oxide layer 121 and a back lightly doped layer 122 on the back side of the silicon substrate 100. A physical vapor deposition (PVD) process is then used to deposit a back transparent conductive layer 123 on the back side of the silicon substrate 100. A back heavily doped layer 124 is then deposited on the back side of the silicon substrate 100 using a PECVD process.

[0102] (4) A front passivation layer 315 is formed on the front surface of the silicon substrate 100 , and a back passivation layer 125 is formed on the back surface of the silicon substrate 100 .

[0103] For example, the front passivation layer 315 may be deposited on the front side of the silicon substrate 100 , and the back passivation layer 125 may be deposited on the back side of the silicon substrate 100 using a PECVD process.

[0104] (5) A second front electrode 316 is formed on the front side of the silicon substrate 100 to contact the front heavily doped layer 314 , and a first back side electrode 226 is formed on the back side of the silicon substrate 100 to contact the back heavily doped layer 124 .

[0105] For example, silver paste may be printed on the front and back sides of the silicon substrate 100 , and then sintered to form the second front electrode 316 and the first back electrode 226 .

[0106] In this embodiment, a tunneling oxide layer, a lightly doped layer, a transparent conductive layer, a heavily doped layer and a passivation layer are formed on the front and back sides of the TOPCon battery, so as to improve the passivation performance of the front and back sides, reduce the contact resistance and parasitic absorption, and improve the battery efficiency.

[0107] Figure 5 is a schematic diagram of the structure of another solar cell provided in an embodiment of the present application. In this embodiment, the solar cell may be a double-sided polycrystalline silicon TOPCon cell. Figure 5 As shown, the solar cell includes a silicon substrate 100. The front side of the silicon substrate 100 includes, from the inside to the outside, a front silicon dioxide layer 511, a front lightly doped polysilicon layer 512, a front TCO layer 513, a front heavily doped polysilicon layer 514, and a front silicon nitride layer 515. The front side of the silicon substrate 100 also includes a third front electrode 516, which passes through the front silicon nitride layer 515 and contacts the front heavily doped polysilicon layer 514.

[0108] The back side of the silicon substrate 100 includes, from the inside to the outside, a back silicon dioxide layer 521, a back lightly doped polysilicon layer 522, a back TCO layer 523, a back heavily doped polysilicon layer 524, and a back silicon nitride layer 525. The back side of the silicon substrate 100 also includes a third back electrode 526, which passes through the back silicon nitride layer 525 and contacts the back heavily doped polysilicon layer 524.

[0109] In some embodiments, the front lightly doped polysilicon layer 512 and the front heavily doped polysilicon layer 514 are boron-doped polysilicon layers, and the boron doping concentration in the front lightly doped polysilicon layer 512 is approximately 2E19-5E19 atoms / cm 3 The boron doping concentration in the front heavily doped polysilicon layer 514 is about 6E19-1E20atoms / cm 3 The back lightly doped polysilicon layer 522 and the back heavily doped polysilicon layer 524 are phosphorus-doped layers. The phosphorus doping concentration in the back lightly doped polysilicon layer 522 is approximately 2E19-5E19 atoms / cm 3 The phosphorus doping concentration in the back heavily doped polysilicon layer 524 is about 6E19-1E20 atoms / cm 3 .

[0110] For example, the thickness of the front lightly doped polysilicon layer 512 is about 10-30 nm, and the thickness of the front heavily doped polysilicon layer 514 is about 30-50 nm. The thickness of the front TCO layer 513 is about 10-40 nm, the refractive index is about 1.9-2.2, and the square resistance is about 18-100 ohm / sq. The thickness of the back lightly doped polysilicon layer 522 is about 10-50 nm, and the thickness of the back heavily doped polysilicon layer 524 is about 30-100 nm. The thickness of the back TCO layer 523 is about 10-40 nm, the refractive index is about 1.9-2.2, and the square resistance is about 18-100 ohm / sq.

[0111] The method for manufacturing a solar cell of this embodiment may include the following steps:

[0112] (1) Provide a silicon substrate 100. The silicon substrate 100 may be an N-type silicon wafer, and further, the silicon wafer may be textured on both sides.

[0113] (2) A front silicon dioxide layer 511 and a front lightly doped polysilicon layer 512 are sequentially formed on the front surface of the silicon substrate 100 .

[0114] For example, after cleaning the silicon substrate 100, a front silicon dioxide layer 511 with a thickness of about 1-2 nm is deposited on the front of the silicon substrate 100 using a plasma enhanced chemical vapor deposition (PECVD) process, and the specific implementation process is as follows: the laughing gas flow rate is between 9000-13000sccm, the deposition temperature is 420-450°C, the time is 120-400s, and the power is 9000-14000W. A front lightly doped polysilicon layer 512 with a thickness of about 10-30nm is deposited using a PECVD process, and the specific implementation process is as follows: the silane flow rate is 6000-9000sccm, the diborane flow rate is 200-300sccm, the power is 3000-10000w, and the time is 100-300s.

[0115] (3) A front TCO layer 513 is formed on the front surface of the silicon substrate 100 .

[0116] For example, a physical vapor deposition (PVD) process can be used to deposit a front TCO layer 513 with a thickness of about 10-40 nm on the front side of the silicon substrate 100. The specific implementation process is as follows: temperature is 200-250° C., argon flow rate is 300-600 sccm, water vapor flow rate is 3-6 sccm, oxygen flow rate is 6-10 sccm, and power is 3-6 Kw.

[0117] (4) A front heavily doped polysilicon layer 514 is formed on the front surface of the silicon substrate 100 .

[0118] For example, a PECVD process can be used to deposit a front heavily doped polysilicon layer 514 with a thickness of about 30-50 nm. The specific implementation process is as follows: silane flow rate is 6000-9000 sccm, diborane flow rate is 400-700 sccm, power is 6000-10000w, and time is 300-500s. Then the silicon substrate 100 is placed in a diffusion furnace for high temperature annealing (temperature is 930-960°C) for 15-30 minutes.

[0119] (5) The back side of the silicon substrate 100 is pickled and polished with an alkaline solution.

[0120] (6) A back silicon dioxide layer 521 and a back lightly doped polysilicon layer 522 are sequentially formed on the back side of the silicon substrate 100 .

[0121] For example, a PECVD process can be used to deposit a back silicon dioxide layer 521 with a thickness of about 1-2 nm, and the specific implementation process is as follows: the laughing gas flow rate is between 9000-13000sccm, the deposition temperature is 420-450°C, the time is 120-400s, and the power is 9000-14000W. A PECVD process is also used to deposit a back lightly doped polysilicon layer 522 with a thickness of about 10-50nm, and the specific implementation process is as follows: the silane flow rate is 6000-9000sccm, the phosphine flow rate is 200-300sccm, the power is 3000-10000w, and the time is 100-300s.

[0122] (7) A back TCO layer 523 is formed on the back surface of the silicon substrate 100 .

[0123] For example, a PVD process can be used to deposit a back TCO layer 523 with a thickness of about 10-40 nm on the back of the silicon substrate 100. The specific implementation process is as follows: temperature is 200-250° C., argon flow rate is 300-600 sccm, water vapor flow rate is 3-6 sccm, oxygen flow rate is 6-10 sccm, and power is 3-6 Kw.

[0124] (8) A back heavily doped polysilicon layer 524 is formed on the back side of the silicon substrate 100 .

[0125] For example, a PECVD process can be used to deposit a back heavily doped polysilicon layer 524 with a thickness of about 30-100 nm. The specific implementation process is as follows: the silane flow rate is 6000-9000 sccm, the phosphine flow rate is 400-700 sccm, the power is 6000-10000w, and the time is 300-500s. Then the silicon substrate 100 is placed in a diffusion furnace for high temperature annealing (temperature is 890-930°C) for 15-30min.

[0126] (9) Cleaning the silicon substrate 100.

[0127] (10) A front silicon nitride layer 515 is formed on the front surface of the silicon substrate 100 , and a back silicon nitride layer 525 is formed on the back surface of the silicon substrate 100 .

[0128] For example, the front silicon nitride layer 515 and the back silicon nitride layer 525 may be deposited using a PECVD process, wherein the process is specifically implemented as follows: temperature is 490-550° C., ammonia flow rate is 9000-16000 sccm, silane flow rate is 1300-2500 sccm, power is 9000-15000 W, and time is 100-600 s.

[0129] (11) Silver paste is printed on the front and back sides of the silicon substrate 100, and a third front electrode 516 and a third back electrode 526 are formed after sintering.

[0130] In this embodiment, a tunneling oxide layer, a lightly doped polysilicon layer, a transparent conductive layer, a heavily doped polysilicon layer and a passivation layer are formed on the front and back sides of the TOPCon battery, so as to improve the passivation performance of the front and back sides, reduce the contact resistance and parasitic absorption, and improve the battery efficiency.

[0131] The present application uses specific words to describe the embodiments of the present application. For example, "one embodiment", "an embodiment", and / or "some embodiments" refer to a certain feature, structure or characteristic related to at least one embodiment of the present application. Therefore, it should be emphasized and noted that "one embodiment" or "an embodiment" or "an alternative embodiment" mentioned twice or multiple times in different positions in this specification does not necessarily refer to the same embodiment. In addition, some features, structures or characteristics in one or more embodiments of the present application can be appropriately combined.

[0132] Similarly, it should be noted that in order to simplify the description of the disclosure of this application and thus help understand one or more embodiments of the invention, in the above description of the embodiments of the present application, multiple features are sometimes combined into one embodiment, figure or description thereof. However, this disclosure method does not mean that the subject of the present application requires more features than the features mentioned. In fact, the features of the embodiment are less than all the features of the single embodiment disclosed above.

[0133] In some embodiments, numbers describing the number of components and attributes are used. It should be understood that such numbers used in the description of the embodiments are modified by the modifiers "about", "approximately" or "substantially" in some examples. Unless otherwise specified, "about", "approximately" or "substantially" indicate that the numbers are allowed to vary by ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification are approximate values, which may change according to the required features of individual embodiments. In some embodiments, the numerical parameters should take into account the specified significant digits and adopt the general method of retaining the digits. Although the numerical domains and parameters used to confirm the breadth of the range in some embodiments of the present application are approximate values, in specific embodiments, the setting of such numerical values ​​is as accurate as possible within the feasible range.

[0134] Although the present application has been described with reference to the current specific embodiments, ordinary technicians in this technical field should recognize that the above embodiments are only used to illustrate the present application, and various equivalent changes or substitutions may be made without departing from the spirit of the present application. Therefore, as long as the changes and modifications to the above embodiments are within the essential spirit of the present application, they will fall within the scope of the present application.

Claims

1. A solar cell, characterized in that: include: A silicon substrate having a first surface and a second surface opposite to each other in a thickness direction; The first surface of the silicon substrate includes, from inside to outside, a first tunneling oxide layer, a first lightly doped layer, a first transparent conductive layer, a first heavily doped layer and a first passivation layer, wherein the first lightly doped layer and the first heavily doped layer have the same doping type.

2. The solar cell according to claim 1, wherein: The thickness of the first transparent conductive layer is 10-40 nm.

3. The solar cell according to claim 1, wherein: The refractive index of the first transparent conductive layer is 1.9-2.2, and the sheet resistance is 18-100 ohm / sq.

4. The solar cell according to claim 1, wherein: The thickness of the first lightly doped layer is 10-30 nm; the thickness of the first heavily doped layer is 30-50 nm.

5. The solar cell according to claim 1, wherein: The doping concentration of the first doping impurity in the first lightly doped layer is 2E19-5E19 atoms / cm 3 The doping concentration of the first doping impurity in the first heavily doped layer is 6E19-1E20 atoms / cm 3 .

6. The solar cell according to claim 1, wherein: The second surface of the silicon substrate includes, from inside to outside, a second tunneling oxide layer, a second lightly doped layer, a second transparent conductive layer, a second heavily doped layer, and a second passivation layer, wherein the second lightly doped layer and the second heavily doped layer have the same doping type, and the second lightly doped layer and the first lightly doped layer have opposite doping types.

7. The solar cell according to claim 6, characterized in that The thickness of the second transparent conductive layer is 10-40 nm.

8. The solar cell according to claim 6, wherein: The refractive index of the second transparent conductive layer is 1.9-2.2, and the sheet resistance is 18-100 ohm / sq.

9. The solar cell according to claim 6, wherein: The thickness of the second lightly doped layer is 10-50 nm; the thickness of the second heavily doped layer is 30-100 nm.

10. The solar cell according to claim 6, wherein: The doping concentration of the second doping impurity in the second lightly doped layer is 2E19-5E19 atoms / cm 3 The doping concentration of the second doping impurity in the second heavily doped layer is 6E19-1E20 atoms / cm 3 .

11. A method for manufacturing a solar cell, characterized in that: include: Providing a silicon substrate having a first surface and a second surface opposite to each other in a thickness direction; Forming a first tunneling oxide layer, a first lightly doped layer, a first transparent conductive layer and a first heavily doped layer in sequence on the first surface of the silicon substrate, wherein the first lightly doped layer and the first heavily doped layer have the same doping type; forming a first passivation layer on a first surface of the silicon substrate, and forming a second passivation layer on a second surface of the silicon substrate; A first electrode contacting the first heavily doped layer is formed on the first surface of the silicon substrate.

12. The method for manufacturing a solar cell according to claim 11, wherein: Before forming a first passivation layer on the first surface of the silicon substrate and forming a second passivation layer on the second surface of the silicon substrate, the method further includes: Forming a second tunneling oxide layer, a second lightly doped layer, a second transparent conductive layer and a second heavily doped layer in sequence on the second surface of the silicon substrate, wherein the second lightly doped layer and the second heavily doped layer have the same doping type, and the second lightly doped layer and the first lightly doped layer have opposite doping types; After forming a first passivation layer on the first surface of the silicon substrate and forming a second passivation layer on the second surface of the silicon substrate, the method further comprises: A second electrode contacting the second heavily doped layer is formed on the second surface of the silicon substrate.

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