Solar cell, preparation method thereof and photovoltaic module

Abstract

The invention provides a solar cell, a preparation method thereof and a photovoltaic module. The preparation method comprises the following steps that a tunneling oxide layer, a p + doped amorphous silicon carbide layer and a p + doped amorphous silicon layer are sequentially arranged on the back face of a silicon substrate in the direction away from the silicon substrate; grooves which are distributed at intervals and penetrate through the p + doped amorphous silicon layer are formed in the p + doped amorphous silicon layer, then channels are formed in the junctions of the grooves and the p + doped amorphous silicon layer, the tunneling oxide layer is divided into a P region and an N region, the p + doped amorphous silicon carbide layer and the p + doped amorphous silicon layer are arranged on the P region, and the p + doped amorphous silicon carbide layer is arranged on the N region; performing crystallization treatment, so that the p + doped amorphous silicon carbide layer and the p + doped amorphous silicon layer on the P region are respectively converted into a p + doped polycrystalline silicon carbide layer and a p + doped polycrystalline silicon layer, and the p + doped amorphous silicon carbide layer on the N region is converted into an n + doped polycrystalline silicon carbide layer; and performing post-treatment to obtain the solar cell.

Description

Technical Field

[0001] The present invention belongs to the technical field of photovoltaic module production and manufacturing, and specifically relates to a solar cell and a preparation method thereof, and a photovoltaic module. Background Art

[0002] The emitter and back passivation cell (PERC) technology is the mainstream cell technology on the market. The efficiency level of the mass-produced PERC cell can reach about 23.5%, but it is difficult to increase the cell efficiency to more than 24%. Since there is no light shielding on the front side of the IBC cell (cross back contact cell), the cell efficiency can reach more than 24.5%. If the passivation contact structure is superimposed, the efficiency can reach more than 26%, but the current preparation process of the IBC cell is complicated and has not become the mainstream route for large-scale mass production at this stage. It is generally believed that the next generation of PERC cell technology is N-type tunnel oxide passivation contact cell (TOPCon cell) or heterojunction cell and IBC cell technology. IBC cell technology can superimpose TOPCon or heterojunction structure, such as constructing TBC back contact solar cells (TOPCon-IBC cells), which combines the tunnel oxide passivation contact of TOPCon technology and the interdigital back contact structure of IBC technology, which can further improve the cell efficiency. Current TBC battery technology is mostly prepared by deposition or printing mask + wet etching or printing slurry diffusion. However, the wet etching process is complicated, the printing slurry will more or less have contamination problems and the process is also complicated, making it difficult to improve battery efficiency.

[0003] Therefore, how to simplify the process and further improve the photoelectric conversion efficiency of solar cells is a technical problem that needs to be solved urgently. Summary of the invention

[0004] In view of the deficiencies of the prior art, the purpose of the present invention is to provide a solar cell and a preparation method thereof and a photovoltaic module. The preparation method provided by the present invention has a simple process, a large process window, and strong mass production. During the crystallization process of the present invention, the p+ doped amorphous layer on the P region is converted into a p+ doped polycrystalline layer, and the p+ doped amorphous silicon carbide layer on the N region can be directly converted into an n+ doped polycrystalline silicon carbide layer, thereby forming an n-type and p-type tunnel passivation contact structure in one step, reducing the influence of the primary environment on the tunneling oxide layer.

[0005] In order to achieve the purpose of the invention, the present invention adopts the following technical solutions:

[0006] In a first aspect, the present invention provides a method for preparing a solar cell, the method comprising the following steps:

[0007] A tunneling oxide layer, a p+ doped amorphous silicon carbide layer and a p+ doped amorphous silicon layer are sequentially arranged on the back side of the silicon substrate in a direction away from the silicon substrate.

[0008] Grooves that are spaced apart and penetrate the p+ doped amorphous silicon layer are formed on the p+ doped amorphous silicon layer, and then a channel is formed at the junction of the grooves and the p+ doped amorphous silicon layer to separate the tunneling oxide layer into a P region and an N region, the p+ doped amorphous silicon carbide layer and the p+ doped amorphous silicon layer are arranged on the P region, and the p+ doped amorphous silicon carbide layer is arranged on the N region.

[0009] A crystallization treatment is performed so that the p+ doped amorphous silicon carbide layer and the p+ doped amorphous silicon layer located on the P region are converted into a p+ doped polycrystalline silicon carbide layer and a p+ doped polycrystalline silicon layer respectively, and the p+ doped amorphous silicon carbide layer on the N region is converted into an n+ doped polycrystalline silicon carbide layer.

[0010] Post-processing is performed to obtain the solar cell.

[0011] The preparation method provided by the present invention has a simple process, a large process window, and strong mass production capability. During the crystallization process, the p+ doped amorphous layer on the P region is converted into a p+ doped polycrystalline layer, and the p+ doped amorphous silicon carbide layer on the N region can be directly converted into an n+ doped polycrystalline silicon carbide layer, thereby forming an n-type and p-type tunnel passivation contact structure in one step, reducing the impact of the primary environment on the tunneling oxide layer; in the preparation method provided by the present invention, the P / N region is isolated by forming a channel, which can prevent the P / N region from being turned on in the subsequent process; in addition, the solar cell prepared based on the preparation method provided by the present invention has excellent photoelectric conversion efficiency.

[0012] Preferably, the tunnel oxide layer, the p+ doped amorphous silicon carbide layer and the p+ doped amorphous silicon layer are formed by plasma enhanced chemical vapor deposition (PECVD) methods respectively and independently.

[0013] Preferably, the tunnel oxide layer material comprises silicon oxide.

[0014] Preferably, the thickness of the tunnel oxide layer is 0.5 nm-2.5 nm, preferably 1 nm-2.5 nm.

[0015] Preferably, the concentration of doping elements in the p+ doped amorphous silicon carbide layer is 3×10 19 cm -3 -5×10 20 cm -3 .

[0016] Preferably, the p+ doped amorphous silicon carbide layer has a thickness of 30 nm-100 nm.

[0017] Preferably, the concentration of the doping element in the p+ doped amorphous silicon layer is 3×10 19 cm -3-5×10 20 cm -3 .

[0018] Preferably, the thickness of the p+ doped amorphous silicon layer is 50nm-200nm.

[0019] Preferably, the method for forming the groove comprises: forming a first mask layer on the outer surface of the p+ doped amorphous silicon layer, and sequentially performing patterned laser windowing and etching processes.

[0020] Preferably, the thickness of the first mask layer is 20 nm-100 nm.

[0021] Preferably, the laser for patterned laser window opening includes an ultraviolet picosecond laser or an ultraviolet picosecond laser.

[0022] Preferably, the etchant used for the etching process includes any one of KOH, NaOH or TMAH, or a combination of at least two of them.

[0023] Preferably, the width of the groove is 100 μm-1000 μm.

[0024] Preferably, the method for forming the groove comprises: sequentially forming an n+ doped amorphous silicon layer and a second mask layer on a surface of the silicon substrate on which the groove is formed, and sequentially performing patterned laser windowing and etching processes.

[0025] Preferably, the thickness of the n+ doped amorphous silicon layer is 30nm-100nm.

[0026] Preferably, the material of the second mask layer includes silicon oxide.

[0027] Preferably, the thickness of the second mask layer is 10 nm-50 nm.

[0028] Preferably, the width of the channel is 10 μm-60 μm.

[0029] Preferably, the crystallization treatment includes phosphorus diffusion and oxidation annealing treatments performed sequentially.

[0030] Preferably, the temperature of the phosphorus diffusion is 800°C-900°C.

[0031] Preferably, the atmosphere of the oxidation annealing treatment is an oxygen-containing atmosphere.

[0032] Preferably, the temperature of the oxidation annealing treatment is 900°C-1000°C.

[0033] Preferably, the front surface of the silicon substrate is a suede structure.

[0034] Preferably, after the phosphorus diffusion, a phosphorus-diffused lightly doped layer is formed on the front side of the silicon substrate.

[0035] Preferably, the surface phosphorus concentration of the phosphorus lightly doped layer is 5×10 17 cm -3 -5×10 20 cm -3 .

[0036] Preferably, the post-processing step comprises:

[0037] A back passivation layer and a back anti-reflection layer are sequentially stacked on one side of the silicon substrate where the n+ doped polycrystalline silicon carbide layer is formed, and a front passivation layer and a front anti-reflection layer are sequentially stacked on the front side of the silicon substrate.

[0038] A first back metal electrode and a second back metal electrode are formed in the P region and the N region respectively, so that one end of the first back metal electrode forms an ohmic contact with the p+ doped polycrystalline silicon layer, and the other end extends out of the back anti-reflection layer, and one end of the second back metal electrode forms an ohmic contact with the n+ doped polycrystalline silicon carbide layer, and the other end extends out of the back anti-reflection layer.

[0039] Preferably, the method for forming the back passivation layer and the front passivation layer comprises a thermal oxygen oxidation method or an atomic layer deposition method.

[0040] Preferably, the method for forming the back anti-reflection layer and the front anti-reflection layer comprises a plasma enhanced chemical vapor deposition method.

[0041] Preferably, the material of the back passivation layer and the front passivation layer includes silicon oxide and / or aluminum oxide.

[0042] Preferably, the material of the back anti-reflection layer and the front anti-reflection layer includes any one of silicon nitride, silicon oxynitride or silicon oxide, or a combination of at least two of them.

[0043] Preferably, the thickness of the back passivation layer and the front passivation layer is 2nm-10nm.

[0044] Preferably, the thickness of the back anti-reflection layer and the front anti-reflection layer is 60nm-150nm.

[0045] Preferably, the step of forming the first back metal electrode and the second back metal electrode comprises a metallization process and a sintering process performed sequentially.

[0046] Preferably, the materials of the first back metal electrode and the second back metal electrode include silver and / or aluminum.

[0047] Preferably, after the sintering process, a light injection annealing step is further performed.

[0048] In a second aspect, the present invention provides a solar cell, which is prepared by the preparation method described in the first aspect.

[0049] In a third aspect, the present invention provides a photovoltaic module, wherein the photovoltaic module comprises the solar cell described in the second aspect.

[0050] Compared with the prior art, the present invention has the following beneficial effects:

[0051] (1) The preparation method provided by the present invention has a simple process, a large process window, and strong mass production capability.

[0052] (2) In the preparation method provided by the present invention, the P / N regions are isolated by forming a channel, which can prevent the P / N regions from being turned on in the subsequent process; in addition, a front and back passivation layer is formed for the spaced non-diffused regions, which effectively reduces the interface recombination and ensures the passivation effect.

[0053] (3) During the oxidation annealing treatment, the p-type amorphous silicon carbide in contact with the n+ doped amorphous silicon layer can be directly converted into an n+ doped polycrystalline silicon carbide layer, thereby forming an n-type and p-type tunnel passivation contact structure in one step, reducing the impact of the primary environment on the tunnel oxide layer.

[0054] (4) The solar cell produced by the preparation method provided by the present invention has excellent photoelectric conversion efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 The present invention is a flow chart of a process for preparing a solar cell provided in one embodiment of the present invention.

[0056] Figure 2 This is a schematic diagram of the cell structure after step (1) of the preparation process of the solar cell provided in Example 1 of the present invention.

[0057] Figure 3 This is a schematic diagram of the cell structure after step (2) of the preparation process of the solar cell provided in Example 1 of the present invention.

[0058] Figure 4 This is a schematic diagram of the cell structure after step (3) of the preparation process of the solar cell provided in Example 1 of the present invention.

[0059] Figure 5 This is a schematic diagram of the cell structure after step (4) of the preparation process of the solar cell provided in Example 1 of the present invention.

[0060] Figure 6 This is a schematic diagram of the cell structure after step (5) of the preparation process of the solar cell provided in Example 1 of the present invention.

[0061] Figure 7 This is a schematic diagram of the cell structure after step (6) of the preparation process of the solar cell provided in Example 1 of the present invention.

[0062] Figure 8 This is a schematic diagram of the cell structure after step (7) of the preparation process of the solar cell provided in Example 1 of the present invention.

[0063] Among them, 1-n-type silicon wafer; 2-phosphorus-diffused lightly doped layer; 3-front passivation layer; 4-front anti-reflection layer; 5-tunneling oxide layer; 6'-p+ doped amorphous silicon carbide layer; 6-p+ doped polycrystalline silicon carbide layer; 7'-p+ doped amorphous silicon layer; 7-p+ doped polycrystalline silicon layer; 8'-n+ phosphorus-doped amorphous silicon layer; 8-n+ doped polycrystalline silicon carbide layer; 9-back passivation layer; 10-back anti-reflection layer; 11-first back metal electrode; 12-second back metal electrode; 13-first mask layer; 14-second mask layer; 15-PSG layer. DETAILED DESCRIPTION

[0064] The technical solution of the present invention is further described below by specific implementation methods. It should be understood by those skilled in the art that the embodiments are only to help understand the present invention and should not be regarded as specific limitations of the present invention.

[0065] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0066] In one embodiment, the present invention provides a method for preparing a solar cell, and the preparation process flow chart thereof is as follows: Figure 1 As shown, the preparation method comprises the following steps:

[0067] S101 . A tunneling oxide layer, a p+ doped amorphous silicon carbide layer and a p+ doped amorphous silicon layer are sequentially arranged on the back side of the silicon substrate in a direction away from the silicon substrate.

[0068] S102, forming grooves that are spaced apart and penetrate the p+ doped amorphous silicon layer on the p+ doped amorphous silicon layer, and then forming a channel at the junction of the grooves and the p+ doped amorphous silicon layer, separating the tunneling oxide layer into a P region and an N region, wherein the p+ doped amorphous silicon carbide layer and the p+ doped amorphous silicon layer are arranged on the P region, and the p+ doped amorphous silicon carbide layer is arranged on the N region.

[0069] S103, performing crystallization treatment, so that the p+ doped amorphous silicon carbide layer and the p+ doped amorphous silicon layer located on the P region are converted into a p+ doped polycrystalline silicon carbide layer and a p+ doped polycrystalline silicon layer respectively, and the p+ doped amorphous silicon carbide layer on the N region is converted into an n+ doped polycrystalline silicon carbide layer.

[0070] S104, performing post-processing to obtain the solar cell.

[0071] The preparation method provided by the present invention has a simple process, a large process window, and strong mass production capability. During the crystallization process, the p+ doped amorphous layer on the P region is converted into a p+ doped polycrystalline layer, and the p+ doped amorphous silicon carbide layer on the N region can be directly converted into an n+ doped polycrystalline silicon carbide layer, thereby forming an n-type and p-type tunnel passivation contact structure in one step, reducing the impact of the primary environment on the tunneling oxide layer; in the preparation method provided by the present invention, the P / N region is isolated by forming a channel, which can prevent the P / N region from being turned on in the subsequent process; in addition, the solar cell prepared based on the preparation method provided by the present invention has excellent photoelectric conversion efficiency.

[0072] In some embodiments, the silicon substrate is an n-type silicon wafer. Exemplarily, the n-type silicon wafer is a double-sided polished n-type silicon wafer.

[0073] In some embodiments, the tunnel oxide layer, the p+ doped amorphous silicon carbide layer and the p+ doped amorphous silicon layer are formed by plasma enhanced chemical vapor deposition (PECVD).

[0074] In some embodiments, the tunnel oxide layer material includes silicon oxide.

[0075] In some embodiments, the thickness of the tunnel oxide layer is 0.5 nm-2.5 nm, for example, 0.5 nm, 1 nm, 1.5 nm, 2 nm or 2.5 nm, etc., preferably 1 nm-2.5 nm.

[0076] It should be noted that the doping element in the p+ doped amorphous silicon carbide layer and the p+ doped amorphous silicon layer may be boron.

[0077] In some embodiments, the concentration of the doping element in the p+ doped amorphous silicon carbide layer is 3×10 19 cm -3-5×10 20 cm -3 , for example, it can be 3×10 19 cm -3 , 5×10 19 cm -3 , 1×10 20 cm -3 , 3×10 20 cm -3 or 5×10 20 cm -3 wait.

[0078] Furthermore, the thickness of the p+ doped amorphous silicon carbide layer is 30 nm-100 nm, for example, 30 nm, 50 nm, 70 nm or 90 nm.

[0079] Furthermore, the p+ doped amorphous silicon carbide layer is a single-layer film or at least two-layer films.

[0080] Preferably, the at least two film layers include an intrinsic layer and a doped layer, and the doped layer includes a lightly doped layer and / or a heavily doped layer.

[0081] Furthermore, the concentration of the doping element in the p+ doped amorphous silicon layer is 3×10 19 cm -3 -5×10 20 cm -3 , for example, it can be 3×10 19 cm -3 , 5×10 19 cm -3 , 1×10 20 cm -3 , 3×10 20 cm -3 or 5×10 20 cm -3 wait.

[0082] Furthermore, the thickness of the p+ doped amorphous silicon layer is 50 nm-200 nm, for example, 50 nm, 100 nm, 150 nm or 200 nm.

[0083] Furthermore, the method for forming the groove includes: forming a first mask layer on the outer surface of the p+ doped amorphous silicon layer, and sequentially performing patterned laser windowing and etching processes.

[0084] Furthermore, the material of the first mask layer includes silicon oxide.

[0085] Further, the thickness of the first mask layer is 20 nm-100 nm, for example, 20 nm, 40 nm, 60 nm, 80 nm or 100 nm.

[0086] Furthermore, the laser for performing the patterned laser window opening includes an ultraviolet picosecond laser or an ultraviolet picosecond laser.

[0087] Furthermore, the etchant used for the etching process includes any one of KOH, NaOH or TMAH, or a combination of at least two of them.

[0088] Furthermore, the width of the groove is 100 μm-1000 μm, for example, 100 μm, 300 μm, 500 μm, 700 μm, 900 μm or 1000 μm.

[0089] Furthermore, the method for forming the groove includes: forming an n+ doped amorphous silicon layer and a second mask layer on the surface of the side where the groove is formed on the silicon substrate, and performing patterned laser windowing and etching treatment in sequence. Exemplarily, in the process of patterned laser windowing, the laser used can be an ultraviolet picosecond laser or a green laser, etc., and the etching treatment method can be wet etching, etc. It should be noted that the doping element in the n+ doped amorphous silicon layer can be phosphorus.

[0090] Furthermore, the doping concentration of the doping element in the n+ doped amorphous silicon layer is 4×10 20 -2×10 21 cm -3 , for example, it can be 4×10 20 cm -3 , 6×10 20 cm -3 , 8×10 20 cm -3 , 1×10 21 cm -3 or 2×10 21 cm -3 wait.

[0091] Furthermore, the thickness of the n+ doped amorphous silicon layer is 30 nm-100 nm, for example, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm or 100 nm.

[0092] Furthermore, the n+ doped amorphous silicon layer is a single-layer film or at least two-layer films.

[0093] Furthermore, the at least two film layers include an intrinsic layer and a doped layer, and the doped layer includes a lightly doped layer and / or a heavily doped layer.

[0094] Furthermore, the growth method of the n+ doped amorphous silicon layer is a PECVD method.

[0095] Furthermore, the material of the second mask layer includes silicon oxide.

[0096] Furthermore, the thickness of the second mask layer is 10 nm-50 nm, for example, 10 nm, 20 nm, 30 nm, 40 nm or 50 nm.

[0097] Furthermore, the width of the channel is 10 μm-60 μm, for example, 10 μm, 20 μm, 30 μm, 40 μm, 50 μm or 60 μm.

[0098] Furthermore, the crystallization treatment includes phosphorus diffusion and oxidation annealing treatments performed sequentially.

[0099] Furthermore, in the phosphorus diffusion process, the phosphorus source used includes phosphorus oxychloride.

[0100] Furthermore, the temperature of the phosphorus diffusion is 800°C-900°C, for example, it can be 800°C, 820°C, 840°C, 860°C, 880°C or 900°C.

[0101] Furthermore, the atmosphere of the oxidation annealing treatment is an oxygen-containing atmosphere.

[0102] Furthermore, the gas in the oxygen-containing atmosphere includes oxygen and an inert gas. For example, the inert gas may be nitrogen or the like.

[0103] Further, the temperature of the oxidation annealing treatment is 900°C-1000°C, for example, it can be 900°C, 920°C, 940°C, 960°C, 980°C or 1000°C. In the present invention, if the temperature of the oxidation annealing treatment is too low, the activation is insufficient, the doping amount is too low, the contact is poor, and the passivation is poor; if the temperature of the oxidation annealing treatment is too high, the doping amount is too high, resulting in the destruction of the tunneling layer.

[0104] Furthermore, the front side of the silicon substrate is a suede structure.

[0105] Furthermore, after the phosphorus diffusion, a phosphorus-diffused lightly doped layer is formed on the front side of the silicon substrate.

[0106] Furthermore, the surface phosphorus concentration of the phosphorus lightly doped layer is 5×10 17 cm -3 -5×10 20 cm -3 , for example, it can be 5×10 17 cm -3 , 5×10 18 cm -3 , 5×10 19 cm -3 or 5×10 20 cm -3etc., preferably 1×10 18 -1×10 20 cm -3 wait.

[0107] Furthermore, the post-processing step includes:

[0108] A back passivation layer and a back anti-reflection layer are sequentially stacked on one side of the silicon substrate where the n+ doped polycrystalline silicon carbide layer is formed, and a front passivation layer and a front anti-reflection layer are sequentially stacked on the front side of the silicon substrate.

[0109] A first back metal electrode and a second back metal electrode are formed in the P region and the N region respectively, so that one end of the first back metal electrode forms an ohmic contact with the p+ doped polycrystalline silicon layer, and the other end extends out of the back anti-reflection layer, and one end of the second back metal electrode forms an ohmic contact with the n+ doped polycrystalline silicon carbide layer, and the other end extends out of the back anti-reflection layer.

[0110] Furthermore, the method for forming the back passivation layer and the front passivation layer includes a thermal oxidation method or an atomic layer deposition method (ALD method).

[0111] Furthermore, the method for forming the back anti-reflection layer and the front anti-reflection layer comprises a plasma enhanced chemical vapor deposition method.

[0112] Furthermore, the material of the back passivation layer and the front passivation layer includes silicon oxide and / or aluminum oxide.

[0113] Furthermore, the material of the back anti-reflection layer and the front anti-reflection layer includes any one of silicon nitride, silicon oxynitride or silicon oxide, or a combination of at least two of them.

[0114] Furthermore, the thickness of the back passivation layer and the front passivation layer is 2 nm-10 nm, for example, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm or 10 nm.

[0115] Furthermore, the thickness of the back anti-reflection layer and the front anti-reflection layer is 60nm-150nm, for example, 60nm, 80nm, 100nm, 110nm, 130nm or 150nm, etc., preferably 60-100nm.

[0116] Furthermore, the step of forming the first back metal electrode and the second back metal electrode includes a metallization process and a sintering process performed sequentially.

[0117] Furthermore, the metallization treatment method includes any one of screen printing, laser transfer or electroplating.

[0118] Furthermore, the peak temperature of the sintering process is 650-750°C, for example, 650°C, 700°C or 750°C.

[0119] Furthermore, the materials of the first back metal electrode and the second back metal electrode include silver and / or aluminum.

[0120] Furthermore, after the sintering process, a light injection annealing step is performed.

[0121] In another embodiment, the present invention provides a solar cell, which is prepared by the preparation method described above.

[0122] The solar cell includes a silicon substrate, and a discontinuously distributed tunneling oxide layer is arranged on the back side of the silicon substrate along a direction away from the silicon substrate, and the tunneling oxide layer is divided into a plurality of P regions and a plurality of N regions, and the P regions and the N regions are alternately arranged in sequence; a p+ doped layer is arranged on the plurality of P regions, and the p+ doped layer includes a p+ doped polycrystalline silicon carbide layer and a p+ doped polycrystalline silicon layer along a direction away from the tunneling oxide layer; and an n+ doped polycrystalline silicon carbide layer is arranged on the plurality of N regions along a direction away from the tunneling oxide layer.

[0123] A back passivation layer and a back anti-reflection layer are provided on a surface of the p+ doped polycrystalline silicon layer away from the tunneling oxide layer and a surface of the n+ doped polycrystalline silicon carbide layer away from the tunneling oxide layer.

[0124] A first groove is partially opened on the back passivation layer and the back anti-reflection layer arranged on the p+ doped polycrystalline silicon layer, and a first back metal electrode is arranged in the first groove, and one end of the first back metal electrode forms an ohmic contact with the p+ doped polycrystalline silicon layer, and the other end extends out of the back anti-reflection layer; a second groove is partially opened on the back passivation layer and the back anti-reflection layer arranged on the n+ doped polycrystalline silicon carbide layer, and a second back metal electrode is arranged in the second groove, and one end of the second back metal electrode forms an ohmic contact with the n+ doped polycrystalline silicon carbide layer, and the other end extends out of the back anti-reflection layer.

[0125] Exemplarily, the solar cell is, for example, a TBC back contact solar cell.

[0126] Preferably, a phosphorus-diffused lightly doped layer, a front passivation layer and a front anti-reflection layer are sequentially arranged on the front side of the silicon substrate in a direction away from the silicon substrate.

[0127] Preferably, the front surface of the silicon substrate is a suede structure.

[0128] Preferably, the silicon substrate is an n-type silicon wafer.

[0129] Preferably, the resistivity of the n-type silicon wafer is 0.3Ω·cm-7Ω·cm, for example, it can be 0.3Ω·cm, 0.5Ω·cm, 1Ω·cm, 2Ω·cm, 3Ω·cm, 4Ω·cm, 5Ω·cm, 6Ω·cm or 7Ω·cm, etc., preferably 0.5-3.5Ω·cm.

[0130] Preferably, the diffusion sheet resistance of the phosphorus lightly doped layer is 200Ω / sq-500Ω / sq, for example, it may be 200Ω / sq, 300Ω / sq, 400Ω / sq or 500Ω / sq.

[0131] In another embodiment, the present invention provides a photovoltaic module, wherein the photovoltaic module comprises the solar cell as described above.

[0132] The numerical range described in the present invention not only includes the point values ​​listed above, but also includes any point values ​​between the above numerical ranges that are not listed. Due to space limitations and for the sake of simplicity, the present invention no longer exhaustively lists the specific point values ​​included in the range.

[0133] Example 1

[0134] like Figures 2 to 8 As shown, this embodiment provides a method for preparing a solar cell, and the preparation method comprises the following steps:

[0135] (1) Growth of p+ doped layer: an n-type silicon wafer 1 with a resistivity of 1.5 Ω·cm is subjected to alkali polishing to remove the mechanical damage layers on the front and back sides, and then is cleaned by an RCA cleaning method. Subsequently, a non-interrupted tunneling oxide layer, a p+ doped amorphous silicon carbide layer, a p+ doped amorphous silicon layer and a first mask layer 13 are sequentially grown on the back side of the n-type silicon wafer 1 by a PECVD method.

[0136] The p+ doped amorphous silicon carbide layer and the p+ doped amorphous silicon layer are collectively referred to as the p+ doped layer; the material of the non-interrupted tunneling oxide layer is silicon oxide with a thickness of 1.5 nm; the doping element in the non-interrupted p+ doped amorphous silicon carbide layer is boron with a doping concentration of 1×10 20 cm -3 The thickness is 60nm, including an intrinsic amorphous silicon carbide layer with a thickness of 20nm and a p-type lightly doped amorphous silicon carbide layer with a thickness of 40nm; the doping element in the non-interrupted p+ doped polysilicon layer is boron, and the doping concentration is 1×10 20 cm -3 , with a total thickness of 120 nm; the material of the first mask layer 13 is silicon oxide, with a thickness of 40 nm.

[0137] (2) Grooving: Patterned laser windowing is performed using an ultraviolet picosecond laser, and the laser windowing area is etched using KOH to remove the first mask layer and the p+ doped amorphous silicon layer in the laser windowing area, forming spaced grooves with a width of 600 μm.

[0138] (3) Growing an n+ doped layer: Using the PECVD method, a 50 nm thick n+ phosphorus-doped amorphous silicon layer and a 20 nm thick second mask layer 14 are sequentially grown on the first mask layer 13 treated in step (1) and on the p+ doped amorphous silicon carbide layer in the groove.

[0139] The material of the second mask layer 14 is silicon oxide.

[0140] (4) Setting up channels and texturing: Using a laser with a wavelength of 532 nm to perform laser window opening at the junction of the P / N regions, and wet-etching the second mask layer 14, n+ phosphorus-doped amorphous silicon layer 8', p+ doped amorphous silicon layer 7', p+ doped amorphous silicon carbide layer 6' and tunneling oxide layer 5 at the laser window opening to form a channel with a width of 30 μm to disconnect and isolate the P / N regions. At the same time, texturing is performed on the front side of the n-type silicon wafer 1, and the second mask layer 14 is removed by cleaning.

[0141] The channel penetrates the tunneling oxide layer 5 , the p+ doped amorphous silicon carbide layer 6 ′, the p+ doped amorphous silicon layer 7 ′, the n+ phosphorus doped amorphous silicon layer 8 ′ and the second mask layer 14 at the junction of the P / N regions.

[0142] (5) Crystallization treatment: At 840°C, phosphorus oxychloride is used as a phosphorus source to perform phosphorus diffusion on the n-type silicon wafer 1 after the texturing in step (2), thereby forming a phosphorus-diffused lightly doped layer 2 on the front side, and then an oxidation annealing treatment is performed in an oxygen-containing atmosphere composed of nitrogen and oxygen. The oxidation annealing process is a gradient annealing process, including a primary annealing at a temperature of 910°C and a secondary annealing at a temperature of 940°C, so that the p+ doped amorphous silicon carbide layer 6', the p+ doped amorphous silicon layer 7' and the n+ phosphorus-doped amorphous silicon layer 8' on the back side are respectively converted into a p+ doped polycrystalline silicon carbide layer 6, a p+ doped polycrystalline silicon layer 7 and a PSG layer 13, and at the same time, the p+ doped amorphous silicon carbide layer 6 connected to the n+ phosphorus-doped amorphous silicon layer 8' is converted into an n+ doped polycrystalline silicon carbide layer 8; wherein the surface phosphorus concentration of the phosphorus-diffused lightly doped layer 2 is 1×10 19 cm -3 .

[0143] (6) Removing the PSG layer: The PSG layer 15 is removed by using hydrofluoric acid, and then the RCA cleaning method is used to remove the first mask layer 13.

[0144] (7) Surface modification and electrode preparation: A front passivation layer 3 and a back passivation layer 9 with a thickness of 3.5 nm and made of silicon oxide are grown on the front and back sides of the n-type silicon wafer 1 after being treated in step (6) by thermal oxidation, and then a silicon nitride layer, a silicon oxynitride layer and a silicon oxide layer are grown in sequence on the passivation layers on the front and back sides of the n-type silicon wafer 1 by PECVD as the front anti-reflection layer 4 and the back anti-reflection layer 10.

[0145] Then, silver paste is printed on the N region and the P region of the back side of the n-type silicon wafer 1 by screen printing to form patterned metal electrodes respectively, and then the metal electrodes are contact-treated at 750°C to obtain a first back metal electrode 11 and a second back metal electrode 12, and one end of the first back metal electrode 22 forms an ohmic contact with the p+ doped polycrystalline silicon layer 7, and one end of the second back metal electrode 12 forms an ohmic contact with the n+ doped polycrystalline silicon carbide layer 8, and then post-processing is performed by light injection annealing to finally obtain the solar cell.

[0146] This embodiment provides a solar cell, and its structural schematic diagram is as follows Figure 7 As shown, the solar cell includes an n-type silicon wafer 1, and a discontinuously distributed tunneling oxide layer 5 is arranged on the back side of the n-type silicon wafer 1 along a direction away from the n-type silicon wafer 1, the tunneling oxide layer 5 is divided into a plurality of P regions and a plurality of N regions, and the P regions and the N regions are alternately arranged in sequence, a p+ doped layer is arranged on the plurality of P regions, and the p+ doped layer includes a p+ doped polycrystalline silicon carbide layer 6 and a p+ doped polycrystalline silicon layer 7 along a direction away from the tunneling oxide layer 5, and an n+ doped polycrystalline silicon carbide layer 8 is arranged on the plurality of N regions along a direction away from the tunneling oxide layer 5.

[0147] The doping element in the n+ doped polycrystalline silicon carbide layer 8 includes phosphorus, and the doping concentration is 1×10 21 cm -3 , with a thickness of 60 nm, the thickness of the n+ doped polycrystalline silicon carbide layer 8 is the same as that of the p+ doped polycrystalline silicon carbide layer 6 .

[0148] A back passivation layer 9 and a back anti-reflection layer 10 are provided on the surface of the p+ doped polysilicon layer 7 away from the tunneling oxide layer 5, the discontinuous region (i.e., the channel) between the P-region tunneling oxide layer and the N-region tunneling oxide layer, and the surface of the n+ doped polycrystalline silicon carbide layer 8 away from the tunneling oxide layer 5; wherein the material of the back passivation layer 9 is silicon oxide with a thickness of 3.5nm; the back anti-reflection layer 10 includes a silicon nitride layer, a silicon oxynitride layer and a silicon oxide layer with a thickness of 100nm.

[0149] A first groove is partially opened in the back passivation layer 9 and the back anti-reflection layer 10 arranged on the p+ doped polysilicon layer 7, and a first back metal electrode 11 is arranged in the first groove, and one end of the first back metal electrode 11 forms an ohmic contact with the p+ doped polysilicon layer 7, and the other end extends out of the back anti-reflection layer 10; a second groove is partially opened in the back passivation layer 9 and the back anti-reflection layer 10 arranged on the n+ doped polycrystalline silicon carbide layer 8, and a second back metal electrode 12 is arranged in the second groove, and one end of the second back metal electrode 12 forms an ohmic contact with the n+ doped polycrystalline silicon carbide layer 8, and the other end extends out of the back anti-reflection layer 10; wherein, the material of the first back metal electrode 11 is silver, and the material of the second back metal electrode 12 is silver.

[0150] The front side of the n-type silicon wafer 1 is a suede structure, and a phosphorus diffusion lightly doped layer 2, a front passivation layer 3 and a front anti-reflection layer 4 are sequentially arranged on the front side along a direction away from the n-type silicon wafer 1; wherein the phosphorus diffusion lightly doped layer 2 has a diffusion square resistance of 400Ω / sq and a junction depth of 100nm; the front anti-reflection layer 4 includes a silicon nitride layer, a silicon oxynitride layer and a silicon oxide layer, and has a thickness of 80nm.

[0151] Example 2

[0152] This embodiment provides a method for preparing a solar cell, the method comprising the following steps:

[0153] (1) An n-type silicon wafer with a resistivity of 1 Ω·cm is subjected to alkali polishing to remove the mechanical damage layer on the front and back sides, and then is cleaned by an RCA cleaning method. Subsequently, a tunneling oxide layer, a p+ doped amorphous silicon carbide layer, a p+ doped amorphous silicon layer, and a first mask layer are grown in sequence on the back side of the n-type silicon wafer by a PECVD method.

[0154] The tunnel oxide layer is made of silicon oxide with a thickness of 0.5 nm. The doping element in the p+ doped amorphous silicon carbide layer is boron with a doping concentration of 3×10 19 cm -3 , with a thickness of 30nm; the doping element in the p+ doped polysilicon layer is boron, with a doping concentration of 3×10 19 cm -3 , with a thickness of 50nm; the material of the first mask layer is silicon oxide, with a thickness of 20nm.

[0155] (2) Using an ultraviolet picosecond laser to perform patterned laser windowing, and using KOH to etch the laser windowing area, so that the first mask layer and the p+ doped amorphous silicon layer in the laser windowing area are removed to form spaced grooves, the width of which is 100 μm.

[0156] (3) Using the PECVD method, a 30 nm thick n+ phosphorus-doped amorphous silicon layer and a 10 nm thick second mask layer are sequentially grown on the first mask layer treated in step (1) and on the p+ doped amorphous silicon carbide layer in the groove.

[0157] Wherein, the material of the second mask layer is silicon oxide.

[0158] (4) A 532nm wave laser is used to perform laser window opening at the junction of the P / N region, and the second mask layer, n+ phosphorus-doped amorphous silicon layer, p+ doped amorphous silicon carbide layer and tunneling oxide layer at the laser window opening are wet etched to form a channel with a width of 10μm to disconnect and isolate the P / N region. At the same time, the front side of the n-type silicon wafer is textured and cleaned to remove the second mask layer.

[0159] The channel penetrates the tunneling oxide layer at the junction of the P / N regions, the p+ doped amorphous silicon carbide layer, the n+ phosphorus doped amorphous silicon layer and the second mask layer.

[0160] (5) At 800°C, phosphorus oxychloride is used as a phosphorus source to perform phosphorus diffusion on the n-type silicon wafer after the texturing in step (2), thereby forming a phosphorus-diffused lightly doped layer on the front side, and then an oxidation annealing treatment is performed in an oxygen-containing atmosphere composed of nitrogen and oxygen. The oxidation annealing process is a gradient annealing process, including a primary annealing at a temperature of 900°C and a secondary annealing at a temperature of 970°C, so that the p+ doped amorphous silicon carbide layer, the p+ doped amorphous silicon layer and the n+ phosphorus doped amorphous silicon layer on the back side are respectively converted into a p+ doped polycrystalline silicon carbide layer, a p+ doped polycrystalline silicon layer and a PSG layer, and at the same time, the p+ doped amorphous silicon carbide layer connected to the n+ phosphorus doped amorphous silicon layer is converted into an n+ doped polycrystalline silicon carbide layer.

[0161] The surface phosphorus concentration of the phosphorus-doped layer is 5×10 17 cm -3 .

[0162] (6) The PSG layer is removed by using hydrofluoric acid, and then the RCA cleaning method is used to remove the first mask layer.

[0163] (7) A passivation layer made of silicon oxide and having a thickness of 2 nm is grown on the front and back sides of the n-type silicon wafer after being treated in step (4) by a thermal oxygen oxidation method, and then a silicon nitride layer, a silicon oxynitride layer and a silicon oxide layer are grown in sequence on the passivation layer on the front and back sides of the n-type silicon wafer by a PECVD method as an anti-reflection layer.

[0164] Then, silver paste is printed on the N region of the back side of the n-type silicon wafer treated in step (5), and silver aluminum paste is printed on the P region by screen printing to form patterned metal electrodes respectively, and then the metal electrodes are contact-treated at 730° C. to obtain a first back metal electrode and a second back metal electrode, wherein one end of the first back metal electrode forms an ohmic contact with the p+ doped polycrystalline silicon layer, and one end of the second back metal electrode forms an ohmic contact with the n+ doped polycrystalline silicon carbide layer, and then post-processed by light injection annealing to finally obtain the solar cell.

[0165] The present embodiment provides a solar cell, the solar cell comprising an n-type silicon wafer, a discontinuously distributed tunneling oxide layer being arranged on the back side of the n-type silicon wafer in a direction away from the n-type silicon wafer, the tunneling oxide layer being divided into a plurality of P regions and a plurality of N regions, and the P regions and the N regions being arranged alternately in sequence, a p+ doped layer being arranged on the plurality of P regions, the p+ doped layer comprising a p+ doped polycrystalline silicon carbide layer and a p+ doped polycrystalline silicon layer in a direction away from the tunneling oxide layer, and an n+ doped polycrystalline silicon carbide layer being arranged on the plurality of N regions in a direction away from the tunneling oxide layer.

[0166] The doping elements in the n+ doped polycrystalline silicon carbide layer include phosphorus, and the doping concentration is 4×10 20 cm -3 , with a thickness of 30 nm, the thickness of the n+ doped polycrystalline silicon carbide layer is the same as that of the p+ doped polycrystalline silicon carbide layer.

[0167] A back passivation layer and a back anti-reflection layer are provided on the surface of the p+ doped polycrystalline silicon layer away from the tunneling oxide layer, the discontinuous region (i.e., the channel) between the P-region tunneling oxide layer and the N-region tunneling oxide layer, and the surface of the n+ doped polycrystalline silicon carbide layer away from the tunneling oxide layer; wherein the material of the back passivation layer is aluminum oxide with a thickness of 2nm; the back anti-reflection layer includes a silicon nitride layer, a silicon oxynitride layer and a silicon oxide layer with a thickness of 60nm.

[0168] A first groove is partially opened on the back passivation layer and the back anti-reflection layer arranged on the p+ doped polycrystalline silicon layer, a first back metal electrode is arranged in the first groove, one end of the first back metal electrode forms an ohmic contact with the p+ doped polycrystalline silicon layer, and the other end extends out of the back anti-reflection layer; a second groove is partially opened on the back passivation layer and the back anti-reflection layer arranged on the n+ doped polycrystalline silicon carbide layer, a second back metal electrode is arranged in the second groove, one end of the second back metal electrode forms an ohmic contact with the n+ doped polycrystalline silicon carbide layer, and the other end extends out of the back anti-reflection layer; wherein the material of the first back metal electrode is silver, and the material of the second back metal electrode is silver.

[0169] The front side of the n-type silicon wafer is a suede structure, and a phosphorus diffusion lightly doped layer, a front passivation layer and a front anti-reflection layer are sequentially arranged on the front side along the direction away from the n-type silicon wafer; among which, the diffusion square resistance of the phosphorus diffusion lightly doped layer is 500Ω / sq; the front anti-reflection layer includes a silicon nitride layer, a silicon oxynitride layer and a silicon oxide layer, and the thickness is 60nm.

[0170] Example 3

[0171] This embodiment provides a method for preparing a solar cell, the method comprising the following steps:

[0172] (1) An n-type silicon wafer with a resistivity of 2 Ω·cm is subjected to alkali polishing to remove the mechanical damage layer on the front and back sides, and then is cleaned by an RCA cleaning method. Subsequently, a tunneling oxide layer, a p+ doped amorphous silicon carbide layer, a p+ doped amorphous silicon layer, and a first mask layer are grown in sequence on the back side of the n-type silicon wafer by a PECVD method.

[0173] The tunnel oxide layer is made of silicon oxide with a thickness of 3 nm. The doping element in the p+ doped amorphous silicon carbide layer is boron with a doping concentration of 5×10 20 cm -3 , with a thickness of 100nm; the doping element in the p+ doped polysilicon layer is boron, and the doping concentration is 5×10 20 cm -3 , with a thickness of 200nm; the material of the first mask layer is silicon oxide, with a thickness of 100nm.

[0174] (2) Using an ultraviolet picosecond laser to perform patterned laser windowing, and using KOH to etch the laser windowing area, so that the first mask layer and the p+ doped amorphous silicon layer in the laser windowing area are removed to form spaced grooves, the width of which is 1000 μm.

[0175] (3) Using the PECVD method, a 100 nm thick n+ phosphorus-doped amorphous silicon layer and a 50 nm thick second mask layer are grown in sequence on the first mask layer treated in step (1) and on the p+ doped amorphous silicon carbide layer in the groove.

[0176] Wherein, the material of the second mask layer is silicon oxide.

[0177] (4) A 532nm wave laser is used to perform laser window opening at the junction of the P / N region, and the second mask layer, n+ phosphorus-doped amorphous silicon layer, p+ doped amorphous silicon carbide layer and tunneling oxide layer at the laser window opening are wet etched to form a channel with a width of 60μm to disconnect and isolate the P / N region. At the same time, the front side of the n-type silicon wafer is textured and cleaned to remove the second mask layer.

[0178] The channel penetrates the tunneling oxide layer at the junction of the P / N regions, the p+ doped amorphous silicon carbide layer, the n+ phosphorus doped amorphous silicon layer and the second mask layer.

[0179] (5) At 900°C, phosphorus oxychloride is used as a phosphorus source to perform phosphorus diffusion on the n-type silicon wafer after the texturing in step (2), thereby forming a phosphorus-diffused lightly doped layer on the front side, and then an oxidation annealing treatment is performed in an oxygen-containing atmosphere composed of nitrogen and oxygen. The oxidation annealing process is a gradient annealing process, including a primary annealing at a temperature of 930°C and a secondary annealing at a temperature of 1000°C, so that the p+ doped amorphous silicon carbide layer, the p+ doped amorphous silicon layer and the n+ phosphorus doped amorphous silicon layer on the back side are respectively converted into a p+ doped polycrystalline silicon carbide layer, a p+ doped polycrystalline silicon layer and a PSG layer, and at the same time, the p+ doped amorphous silicon carbide layer connected to the n+ phosphorus doped amorphous silicon layer is converted into an n+ doped polycrystalline silicon carbide layer.

[0180] The surface phosphorus concentration of the phosphorus-doped layer is 5×10 20 cm -3 .

[0181] (6) The PSG layer is removed by using hydrofluoric acid, and then the RCA cleaning method is used to remove the first mask layer.

[0182] (7) A passivation layer made of silicon oxide and having a thickness of 10 nm is grown on the front and back sides of the n-type silicon wafer after being treated in step (4) by a thermal oxygen oxidation method, and then a silicon nitride layer, a silicon oxynitride layer and a silicon oxide layer are grown in sequence on the passivation layer on the front and back sides of the n-type silicon wafer by a PECVD method as an anti-reflection layer.

[0183] Then, silver paste is printed on the N region of the back side of the n-type silicon wafer treated in step (5), and silver aluminum paste is printed on the P region by screen printing to form patterned metal electrodes respectively, and then the metal electrodes are contact-treated at 520° C. to obtain a first back metal electrode and a second back metal electrode, wherein one end of the first back metal electrode forms an ohmic contact with the p+ doped polycrystalline silicon layer, and one end of the second back metal electrode forms an ohmic contact with the n+ doped polycrystalline silicon carbide layer, and then post-processed by light injection annealing to finally obtain the TBC back contact solar cell.

[0184] The present embodiment provides a solar cell, the solar cell comprising an n-type silicon wafer, a discontinuously distributed tunneling oxide layer being arranged on the back side of the n-type silicon wafer in a direction away from the n-type silicon wafer, the tunneling oxide layer being divided into a plurality of P regions and a plurality of N regions, and the P regions and the N regions being arranged alternately in sequence, a p+ doped layer being arranged on the plurality of P regions, the p+ doped layer comprising a p+ doped polycrystalline silicon carbide layer and a p+ doped polycrystalline silicon layer in a direction away from the tunneling oxide layer; and an n+ doped polycrystalline silicon carbide layer being arranged on the plurality of N regions in a direction away from the tunneling oxide layer.

[0185] The doping elements in the n+ doped polycrystalline silicon carbide layer include phosphorus, and the doping concentration is 2×10 21 cm -3 , with a thickness of 100 nm; the thickness of the n+ doped polycrystalline silicon carbide layer is the same as that of the p+ doped polycrystalline silicon carbide layer.

[0186] A back passivation layer and a back anti-reflection layer are provided on the surface of the p+ doped polycrystalline silicon layer away from the tunneling oxide layer, the discontinuous region (i.e., the channel) between the P-region tunneling oxide layer and the N-region tunneling oxide layer, and the surface of the n+ doped polycrystalline silicon carbide layer away from the tunneling oxide layer; wherein the material of the back passivation layer is silicon oxide with a thickness of 10nm; the back anti-reflection layer includes a silicon nitride layer, a silicon oxynitride layer and a silicon oxide layer with a thickness of 90nm.

[0187] A first groove is partially opened on the back passivation layer and the back anti-reflection layer arranged on the p+ doped polycrystalline silicon layer, a first back metal electrode is arranged in the first groove, one end of the first back metal electrode forms an ohmic contact with the p+ doped polycrystalline silicon layer, and the other end extends out of the back anti-reflection layer; a second groove is partially opened on the back passivation layer and the back anti-reflection layer arranged on the n+ doped polycrystalline silicon carbide layer, a second back metal electrode is arranged in the second groove, one end of the second back metal electrode forms an ohmic contact with the n+ doped polycrystalline silicon carbide layer, and the other end extends out of the back anti-reflection layer; wherein the material of the first back metal electrode is silver, and the material of the second back metal electrode is silver.

[0188] The front side of the n-type silicon wafer is a suede structure, and a phosphorus diffusion lightly doped layer, a front passivation layer and a front anti-reflection layer are sequentially arranged on the front side along the direction away from the n-type silicon wafer; among which, the diffusion square resistance of the phosphorus diffusion lightly doped layer is 200Ω / sq; the back anti-reflection layer includes a silicon nitride layer, a silicon oxynitride layer and a silicon oxide layer, and the thickness is 90nm.

[0189] Example 4

[0190] The difference between this embodiment and embodiment 1 is that the thickness of the tunnel oxide layer is 5 nm.

[0191] The rest of the preparation methods and parameters were the same as those in Example 1.

[0192] Example 5

[0193] The difference between this embodiment and embodiment 1 is that the total thickness of the p+ doped polycrystalline silicon carbide layer is 20 nm.

[0194] The rest of the preparation methods and parameters were the same as those in Example 1.

[0195] Example 6

[0196] The difference between this embodiment and embodiment 1 is that the total thickness of the p+ doped polycrystalline silicon carbide layer is 120 nm.

[0197] The rest of the preparation methods and parameters were the same as those in Example 1.

[0198] Example 7

[0199] The difference between this embodiment and embodiment 1 is that the thickness of the p+ doped polysilicon layer is 30 nm.

[0200] The rest of the preparation methods and parameters were the same as those in Example 1.

[0201] Example 8

[0202] The difference between this embodiment and embodiment 1 is that the thickness of the p+ doped polysilicon layer is 220 nm.

[0203] The rest of the preparation methods and parameters were the same as those in Example 1.

[0204] Example 9

[0205] The difference between this embodiment and embodiment 1 is that the temperature of the oxidation annealing treatment in step (5) is 800°C.

[0206] The rest of the preparation methods and parameters were the same as those in Example 1.

[0207] Example 10

[0208] The difference between this embodiment and embodiment 1 is that the temperature of the oxidation annealing treatment in step (5) is 1200°C.

[0209] The rest of the preparation methods and parameters were the same as those in Example 1.

[0210] Comparative Example 1

[0211] The difference between this comparative example and Example 1 is that the growth of the p+ doped amorphous silicon layer is not performed in step (1).

[0212] The rest of the preparation methods and parameters were the same as those in Example 1.

[0213] Comparative Example 2

[0214] The difference between this comparative example and Example 1 is that the growth of the p+ doped amorphous silicon carbide layer is not performed in step (1).

[0215] The rest of the preparation methods and parameters were the same as those in Example 1.

[0216] Comparative Example 3

[0217] The difference between this comparative example and Example 1 is that wet etching is not performed in step (4).

[0218] The rest of the preparation methods and parameters were the same as those in Example 1.

[0219] Performance Testing

[0220] The photoelectric performance of the TBC back contact solar cells prepared in the above examples and comparative examples was tested under the following conditions: light intensity 1000 W / m 2 , test temperature 25±2℃.

[0221] The test results are shown in Table 1.

[0222] Table 1

[0223]

[0224] analyze:

[0225] As can be seen from the above, the TBC back-contact solar cell provided by the present invention solves the problem of low efficiency caused by the interface recombination between the metal electrode and the silicon substrate and the problem of conduction leakage between PNs, and has excellent photoelectric conversion efficiency.

[0226] It can be seen from Example 1 and Example 4 that if the thickness of the tunnel oxide layer is too thick, the doping concentration of the P region and the N region into the silicon substrate will be too low, the string resistance is high and the contact is poor.

[0227] It can be seen from Example 1 and Example 5-Example 6 that if the thickness of the p+ doped polycrystalline silicon carbide layer is too small, the metal electrodes in the P region and the N region are easily burned through, directly contacting the silicon substrate, destroying the tunneling layer, and affecting the passivation and contact; if the thickness of the p+ doped polycrystalline silicon carbide layer is too large, the parasitic absorption is high and the current is low.

[0228] It can be seen from Example 1 and Example 7-Example 8 that if the thickness of the p+ doped polysilicon layer is too small, the metal electrodes in the P region are easily burned through, directly contacting the silicon substrate, destroying the tunneling layer, and affecting the passivation and contact; if the thickness of the p+ doped polysilicon layer is too large, the parasitic absorption is high and the current is low.

[0229] It can be seen from Example 1 and Example 9-Example 10 that if the oxidation annealing temperature is too low, the activation is insufficient, the doping amount is too low, and the contact is poor; if the oxidation annealing temperature is too high, the doping is too heavy, the doping elements diffuse through, the tunneling layer is destroyed, and the passivation is poor.

[0230] It can be seen from Example 1 and Comparative Example 1 that if the p+ doped polysilicon layer is not provided, the metal electrodes in the P region are easily burned through, directly contacting the silicon substrate, destroying the tunneling layer, and affecting passivation and contact.

[0231] It can be seen from Example 1 and Comparative Example 2 that if the p+ doped polycrystalline silicon carbide layer is not provided, the metal electrodes in the P region and the N region are easily burned through, directly contacting the silicon substrate, destroying the tunneling layer, and affecting passivation and contact.

[0232] It can be seen from Example 1 and Comparative Example 3 that if the sidewalls of the n+ doped polycrystalline silicon carbide layer and the p+ doped layer are closely attached, the P region and the N region are directly connected, and electrons and holes are directly recombined, which is extremely inefficient.

[0233] The applicant declares that the present invention illustrates the process method of the present invention through the above-mentioned embodiments, but the present invention is not limited to the above-mentioned process steps, that is, it does not mean that the present invention must rely on the above-mentioned process steps to be implemented. Those skilled in the art should understand that any improvement of the present invention, equivalent replacement of the raw materials selected by the present invention, addition of auxiliary components, selection of specific methods, etc., all fall within the protection scope and disclosure scope of the present invention.

Claims

1. A method for preparing a solar cell, characterized in that: The preparation method comprises the following steps: A tunneling oxide layer, a p+ doped amorphous silicon carbide layer and a p+ doped amorphous silicon layer are sequentially arranged on the back side of the silicon substrate in a direction away from the silicon substrate; Forming grooves on the p+ doped amorphous silicon layer that are spaced apart and penetrate the p+ doped amorphous silicon layer, and then forming a channel at the junction of the grooves and the p+ doped amorphous silicon layer, so as to separate the tunneling oxide layer into a P region and an N region, wherein the p+ doped amorphous silicon carbide layer and the p+ doped amorphous silicon layer are arranged on the P region, and the p+ doped amorphous silicon carbide layer is arranged on the N region; Performing a crystallization process so that the p+ doped amorphous silicon carbide layer and the p+ doped amorphous silicon layer located on the P region are converted into a p+ doped polycrystalline silicon carbide layer and a p+ doped polycrystalline silicon layer respectively, and the p+ doped amorphous silicon carbide layer on the N region is converted into an n+ doped polycrystalline silicon carbide layer; Post-processing is performed to obtain the solar cell.

2. The preparation method according to claim 1, characterized in that: The tunneling oxide layer, the p+ doped amorphous silicon carbide layer and the p+ doped amorphous silicon layer are formed by plasma enhanced chemical vapor deposition method respectively and independently; Preferably, the tunnel oxide layer material comprises silicon oxide; Preferably, the thickness of the tunnel oxide layer is 0.5 nm-2.5 nm, preferably 1 nm-2.5 nm; Preferably, the concentration of doping elements in the p+ doped amorphous silicon carbide layer is 3×10 19 cm -3 -5×10 20 cm -3 ; Preferably, the thickness of the p+ doped amorphous silicon carbide layer is 30nm-100nm; Preferably, the concentration of the doping element in the p+ doped amorphous silicon layer is 3×10 19 cm -3 -5×10 20 cm -3 ; Preferably, the thickness of the p+ doped amorphous silicon layer is 50nm-200nm.

3. The preparation method according to claim 1 or 2, characterized in that: The groove forming method comprises: forming a first mask layer on the outer surface of the p+ doped amorphous silicon layer, and sequentially performing patterned laser window opening and etching processes; Preferably, the thickness of the first mask layer is 20nm-100nm; Preferably, the laser for patterned laser windowing includes an ultraviolet picosecond laser or a green picosecond laser; Preferably, the etchant used for the etching process includes any one of KOH, NaOH or TMAH or a combination of at least two thereof; Preferably, the width of the groove is 100 μm-1000 μm.

4. The preparation method according to any one of claims 1 to 3, characterized in that The method for forming the groove comprises: sequentially forming an n+ doped amorphous silicon layer and a second mask layer on a surface of a side of the silicon substrate where the groove is formed, and sequentially performing patterned laser windowing and etching processes; Preferably, the thickness of the n+ doped amorphous silicon layer is 30nm-100nm; Preferably, the material of the second mask layer includes silicon oxide; Preferably, the thickness of the second mask layer is 10nm-50nm; Preferably, the width of the channel is 10 μm-60 μm.

5. The preparation method according to any one of claims 1 to 4, characterized in that: The crystallization treatment includes phosphorus diffusion and oxidation annealing treatments performed in sequence; Preferably, the temperature of the phosphorus diffusion is 800°C-900°C; Preferably, the atmosphere of the oxidation annealing treatment is an oxygen-containing atmosphere; Preferably, the temperature of the oxidation annealing treatment is 900°C-1000°C.

6. The preparation method according to claim 5, characterized in that: The front side of the silicon substrate is a suede structure; Preferably, after the phosphorus diffusion, a phosphorus-diffused lightly doped layer is formed on the front side of the silicon substrate; Preferably, the surface phosphorus concentration of the phosphorus lightly doped layer is 5×10 17 cm -3 -5×10 20 cm -3 ; Preferably, the post-processing step comprises: A back passivation layer and a back anti-reflection layer are sequentially stacked on the side of the silicon substrate where the n+ doped polycrystalline silicon carbide layer is formed, and a front passivation layer and a front anti-reflection layer are sequentially stacked on the front side of the silicon substrate; A first back metal electrode and a second back metal electrode are formed in the P region and the N region respectively, so that one end of the first back metal electrode forms an ohmic contact with the p+ doped polycrystalline silicon layer, and the other end extends out of the back anti-reflection layer, and one end of the second back metal electrode forms an ohmic contact with the n+ doped polycrystalline silicon carbide layer, and the other end extends out of the back anti-reflection layer.

7. The preparation method according to claim 6, characterized in that: The method for forming the back passivation layer and the front passivation layer includes a thermal oxidation method or an atomic layer deposition method; Preferably, the method for forming the back anti-reflection layer and the front anti-reflection layer comprises a plasma enhanced chemical vapor deposition method; Preferably, the materials of the back passivation layer and the front passivation layer include silicon oxide and / or aluminum oxide; Preferably, the material of the back anti-reflection layer and the front anti-reflection layer includes any one of silicon nitride, silicon oxynitride or silicon oxide, or a combination of at least two thereof; Preferably, the thickness of the back passivation layer and the front passivation layer is 2nm-10nm; Preferably, the thickness of the back anti-reflection layer and the front anti-reflection layer is 60nm-150nm.

8. The preparation method according to claim 6 or 7, characterized in that: The step of forming the first back metal electrode and the second back metal electrode comprises a metallization process and a sintering process performed in sequence; Preferably, the materials of the first back metal electrode and the second back metal electrode include silver and / or aluminum; Preferably, after the sintering process, a light injection annealing step is further performed.

9. A solar cell, characterized in that: The solar cell is prepared by the preparation method according to any one of claims 1 to 8.

10. A photovoltaic module, characterized in that: The photovoltaic module comprises the solar cell according to claim 9.

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