High-voltage LED chip and preparation method thereof

Abstract

The application discloses a high-voltage LED chip and a preparation method thereof. The preparation method comprises the following steps: coating a positive photoresist on the side of an epitaxial layer far from a substrate; providing a first mask, adjusting the position of the first mask, so that the light transmission area of the first mask corresponds to the preset position of the non-bridge area, and performing exposure treatment, so that the non-bridge area forms an inclined surface with a steep angle; providing a second mask, the second mask has a plurality of light transmission areas with different sizes, adjusting the position of the second mask, so that the light transmission area of the second mask corresponds to the preset position of the bridge area, and performing n times of photoetching by using the plurality of light transmission areas with different sizes of the second mask, so that the bridge area forms an inclined surface with a gentle angle, wherein n is an integer greater than or equal to 1; and performing development treatment and etching treatment. The preparation method of the application effectively increases the light-emitting area, is beneficial to electrode bridging, and makes the obtained high-voltage LED chip have good light-emitting efficiency and light-emitting brightness.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a high-voltage LED chip and a preparation method thereof. BACKGROUND

[0002] An LED (Light Emitting Diode) is a kind of semiconductor light emitting device capable of converting electric energy into light energy. With the development and progress of LED chip manufacturing technology, LED chips have gradually become a new mainstream lighting light source after incandescent lamps and fluorescent lamps, and have advantages such as small size, fast response, long service life, environmental protection and energy saving, and are widely used in the fields of lighting, display screens and the like.

[0003] LED chips can be generally divided into two categories: normal-pressure LED chips and high-voltage LED chips. In a limited packaging bracket space, it is difficult to form a high-power lamp bead by connecting a plurality of normal-pressure chips in series, especially wire bonding. Therefore, high-voltage LED chips have emerged as the times require. A high-voltage LED chip is formed by connecting a plurality of PN junctions through a chip process. A normal-pressure LED chip is generally referred to as a 3V chip, while a high-voltage LED chip has various types such as 6V, 9V, 12V and 18V. The structure of the high-voltage LED chip is composed of a substrate, an epitaxial layer and a chip layer. The epitaxial layer generally includes an N-type semiconductor, a quantum well layer and a P-type semiconductor. The chip structure is sequentially composed of a current blocking layer, a transparent conductive layer, an electrode and a passivation layer from bottom to top. Specifically, the high-voltage LED chip is divided into a plurality of PN junctions by an isolation groove to form a plurality of PN junctions, as shown in Figure 1 The isolation groove is formed by combining a positive photoresist and a mask, and has a gentle angle, generally <50°, as shown in Figure 2 The purpose is to facilitate electrode bridging to realize the series connection between a plurality of PN junctions. However, the isolation groove process in the existing high-voltage LED chip is formed by one photoresist and one photoetching, and the bridging portion must have a steep angle to facilitate metal bridging, otherwise the electrode will be broken, which also causes the angle of the isolation groove in other non-bridging areas to be relatively steep, that is, the upper width of the isolation groove is large, which sacrifices the epitaxial layer, resulting in a small light emitting area and affecting the brightness of the chip. SUMMARY

[0004] The technical problem to be solved by the present application is to provide a high-voltage LED chip and a preparation method thereof, which reduces the etching area of the epitaxial layer in the isolation groove etching process, and makes the formed isolation groove simultaneously consider electrode connection and light emitting area.

[0005] In order to solve the above technical problem, the first aspect of the present application provides a preparation method of a high-voltage LED chip, comprising:

[0006] An epitaxial layer is arranged on a substrate, the epitaxial layer comprising at least an N-type semiconductor, a quantum well and a P-type semiconductor;

[0007] The epitaxial layer is etched to expose the N-type semiconductor layer to form a cutting path;

[0008] A photoetching and etching process is performed at the position of the cutting path to form an isolation groove, the isolation groove comprising a non-bridge region and a bridge region;

[0009] The photoetching and etching process at the position of the cutting path to form the isolation groove comprises:

[0010] (1) applying a positive photoresist to the side of the epitaxial layer away from the substrate;

[0011] (2) providing a first mask plate, adjusting the position of the first mask plate so that the light-transmitting region of the first mask plate corresponds to the preset position of the non-bridge region, and performing an exposure process to form an inclined surface with a steep angle in the non-bridge region;

[0012] (3) providing a second mask plate, adjusting the position of the second mask plate so that the light-transmitting region of the second mask plate corresponds to the preset position of the bridge region, the light-transmitting region of the second mask plate having a plurality of sub-light-transmitting regions of different sizes, and performing n times of photoetching using the plurality of sub-light-transmitting regions of different sizes of the second mask plate to form an inclined surface with a gentle angle in the bridge region, wherein n is an integer greater than or equal to 1;

[0013] (4) performing a developing process to form a non-bridge structure with a steep angle and a bridge structure with a gentle angle;

[0014] (5) performing an etching process to form a non-bridge region with a steep angle and a bridge region with a gentle angle.

[0015] As an improvement of the above-mentioned scheme, the value of n is positively correlated with the inclination angle of the bridge region.

[0016] As an improvement of the above-mentioned scheme, the non-bridge region passes through the center of the bridge region, and the width of the light-transmitting region of the second mask plate in the first photoetching is d1; when n>1, the width of the light-transmitting region of the second mask plate in the nth photoetching is d n , d n =2bn+d1, wherein b=1-3.

[0017] As an improvement of the above-mentioned scheme, in the n times of photoetching, the horizontal distance between the bridge region formed in the first photoetching and the non-bridge region is c1;

[0018] When n>1, the horizontal distance between the bridge region formed in the nth photoetching and the non-bridge region is c n ,

[0019] cn =an+c1, wherein a=3-15.

[0020] As an improvement of the above scheme, 3≤c≤25μm; 10≤d≤50μm;

[0021] The width of the light transmission area of the first mask is 1μm-10μm.

[0022] As an improvement of the above scheme, in step (3), the exposure amount of the exposure process in the n times of photolithography is J, and the value of J decreases with the increase of the value of n;

[0023] In step (2), the exposure amount of the exposure process is K, and K>J.

[0024] As an improvement of the above scheme, the coating thickness of the positive photoresist is T;

[0025] In step (3), when n>1, the exposure amount of the exposure process in the first photolithography is J1, and the exposure amount of the exposure process in the n times of photolithography is J n , J n =J1-m(n-1), wherein m=20-300;

[0026] In step (2), the exposure amount of the exposure process is K, and K>J1.

[0027] As an improvement of the above scheme, J1 n <T*50; J

[0028] The thickness of the epitaxial layer is H, and T≥H*2 is satisfied.

[0029] As an improvement of the above scheme, the angle of the isolation groove of the non-bridge area is θ1, and θ1>70°, and the angle of the isolation groove of the bridge area is θ2, and θ2≤50°.

[0030] The second aspect of the present application further provides a high-voltage LED chip prepared by the preparation method of the high-voltage LED chip.

[0031] The present application has the following beneficial effects:

[0032] In the present application, the isolation groove is divided into a bridging area and a non-bridging area, and the bridging area and the non-bridging area are exposed by different photolithography processes. Specifically, the epitaxial layer of the LED chip is photolithographically processed by using a first mask and a second mask, so that the inclination angles of the bridging area and the non-bridging area are controllable. The angle of the non-bridging area is relatively steep, and the angle of the bridging area is relatively gentle. Compared with the isolation groove structure of the traditional high-voltage LED chip, the light-emitting area is effectively increased, and the electrode bridging is facilitated, so that the obtained high-voltage LED chip has good light-emitting efficiency and light-emitting brightness.

[0033] In addition, in the present application, the photolithography process of one-time photoresist coating, multiple exposure processing and unified development processing is combined with the etching process to prepare the isolation groove. The preparation process is simple, and to some extent, the damage of the N-type semiconductor layer caused by the long-time use of the mask is avoided, and the influence on the reliability of the high-voltage LED chip is small. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 : Schematic diagram of the planar structure of the isolation groove of the high-voltage LED chip in the prior art;

[0035] Figure 2 : Schematic diagram of the cross-section of the isolation groove of the high-voltage LED chip in the prior art;

[0036] Figure 3 : Schematic diagram of the planar structure of the isolation groove of the high-voltage LED chip in the present application;

[0037] Figure 4 : Schematic diagram of the cross-section of the non-bridging area isolation groove of the high-voltage LED chip in the present application;

[0038] Figure 5 : Schematic diagram of the cross-section of the bridging area isolation groove of the high-voltage LED chip in the present application;

[0039] Figure 6 : Schematic diagram of the structure of the first mask in the present application;

[0040] Figure 7 : Schematic diagram of the photolithography forming the non-bridging area isolation groove;

[0041] Figure 8 : Schematic diagram of the structure of the second mask in the present application;

[0042] Figure 9 : Figure 8 : Schematic diagram of the structure of the photomask of the light transmission area;

[0043] Figure 10 : Schematic diagram of the first photolithography forming the bridging area isolation groove;

[0044] Figure 11: Schematic view of the bridge region isolation groove after the second photoetching;

[0045] Figure 12 : Schematic view of the bridge structure after development;

[0046] Figure 13 : Schematic view of the non-bridge structure after development;

[0047] Reference signs:

[0048] 1 - substrate; 2 - epitaxial layer; 3 - isolation groove; 31 - bridge region; 32 - non-bridge region; 4 - positive photoresist; 5 - first mask; 6 - second mask; 61 - light transmission region; A1 - first sub-light transmission region; A2 - second sub-light transmission region; A3 - third sub-light transmission region. DETAILED DESCRIPTION

[0049] In order to make the object, technical scheme and advantages of the present application more clear, the present application will be further described in detail with specific examples.

[0050] To solve the above problems, the present application provides a preparation method of high-voltage LED chip, comprising:

[0051] An epitaxial layer 2 is arranged on the substrate 1, and the epitaxial layer 2 at least comprises an N-type semiconductor, a quantum well and a P-type semiconductor;

[0052] The epitaxial layer 2 is etched to expose the N-type semiconductor layer, forming a cutting channel;

[0053] Photoetching and etching treatment are performed at the position of the cutting channel to form an isolation groove 3, and the isolation groove 3 comprises a non-bridge region 32 and a bridge region 31;

[0054] The photoetching and etching treatment at the position of the cutting channel to form the isolation groove 3 comprises:

[0055] (1) The epitaxial layer 2 is coated with a positive photoresist 4 away from one side of the substrate 1;

[0056] (2) A first mask 5 is provided, the position of the first mask 5 is adjusted so that the light transmission region of the first mask 5 corresponds to the preset position of the non-bridge region 32, and exposure treatment is performed so that the non-bridge region 32 forms an inclined surface with a steep angle;

[0057] (3) A second mask 6 is provided, the position of the second mask 6 is adjusted so that the light transmission region 61 of the second mask 6 corresponds to the preset position of the bridge region 31, and the light transmission region 61 of the second mask 6 has a plurality of sub-light transmission regions of different sizes, n times of photoetching is performed using the plurality of sub-light transmission regions of different sizes of the second mask 6, so that the bridge region 31 forms an inclined surface with a gentle angle, wherein n is an integer greater than or equal to 1;

[0058] (4) developing treatment is performed to form the non-bridge structure with steep angle and the bridge structure with gentle angle;

[0059] (5) etching treatment is performed to form the non-bridge area 32 with steep angle and the bridge area 31 with gentle angle.

[0060] In the present application, the isolation groove 3 is divided into the bridge area 31 and the non-bridge area 32, and the bridge area 31 and the non-bridge area 32 are exposed by different photolithography processes. Specifically, the first mask 5 and the second mask 6 are used for photolithography of the epitaxial layer 2 of the LED chip, so that the inclination angles of the bridge area 31 and the non-bridge area 32 can be controlled respectively. The structure of the isolation groove 3 is formed, in which the angle of the non-bridge area 32 is relatively steep and the angle of the bridge area 31 is relatively gentle. Compared with the traditional isolation groove 3 structure of the high-voltage LED chip, the light-emitting area is effectively increased, and the electrode bridging is also facilitated. In addition, in the present application, the photolithography process of one-time photoresist coating, multiple exposure treatment and unified development treatment is combined with the etching process to prepare the isolation groove 3. The preparation process is simple, and to some extent, the damage of the N-type semiconductor layer caused by the long-time use of the mask is avoided, and the influence on the reliability of the high-voltage LED chip is small.

[0061] The following will be specifically described for each step:

[0062] S1, an epitaxial layer 2 is arranged on a substrate 1, and the epitaxial layer 2 at least includes an N-type semiconductor, a quantum well and a P-type semiconductor;

[0063] Preferably, the substrate 1 can be one of a sapphire substrate, a SiO2 sapphire composite substrate, a silicon substrate, a silicon carbide substrate, a gallium nitride substrate and a zinc oxide substrate; more preferably, the substrate 1 is a sapphire substrate.

[0064] Preferably, the N-type semiconductor layer includes but is not limited to an N-type GaN layer, the P-type semiconductor layer includes but is not limited to a P-type GaN layer, and the quantum well includes but is not limited to an InGaN / AlGaN superlattice structure. The actual requirements can be reasonably adjusted.

[0065] Further, the thickness of the epitaxial layer 2 is H, and 4≤H≤7μm. The thickness of the epitaxial layer 2 is exemplarily 4μm, 4.5μm, 5μm, 5.5μm, 6μm, 6.5μm or 7μm, but is not limited thereto.

[0066] S2, etching is performed on the epitaxial layer 2 to expose the N-type semiconductor layer to form a cutting path;

[0067] In this step, the epitaxial layer 2 can be etched by a process combining photolithography and dry etching, and the etching depth is to expose the N-type semiconductor layer, so as to facilitate the preparation of the cutting path and the formation of the position connected to the negative electrode. Preferably, the etching depth is 0.8-2 μm.

[0068] S3, performing photolithography and etching treatment at the cutting path position to form an isolation groove 3, the isolation groove 3 including a non-bridge region 32 and a bridge region 31;

[0069] Please refer to Figures 3-5 The isolation groove 3 can divide the epitaxial layer 2 of the LED chip into multiple PN junctions, and realize the series connection between different PN junctions by electrodes to form a high-voltage LED chip. The depth of the isolation groove 3 is equal to the depth of the epitaxial layer 2, so that when performing photolithography and etching treatment at the cutting path position, the epitaxial layer 2 needs to be etched to expose the substrate 1, so as to ensure the electrical isolation between the light emitting units and improve the electrical performance and reliability of the LED chip.

[0070] Specifically, the photolithography and etching treatment at the cutting path position to form the isolation groove 3 includes:

[0071] (1) coating a positive photoresist 4 on the side of the epitaxial layer 2 away from the substrate 1;

[0072] In this step, the coating thickness of the positive photoresist 4 is related to the thickness of the epitaxial layer 2. In the photolithography process, the positive photoresist 4 with a suitable thickness can provide good etching resistance and sufficient contrast in the developing process, so as to accurately define the pattern in the etching process and not damage the underlying epitaxial layer 2. Preferably, the coating thickness of the positive photoresist 4 is T, which satisfies T≥H*2. If the T value is too high, it will affect the light penetration and the resolution of the pattern, and cannot ensure the accurate transfer of the pattern. In some specific and preferred embodiments, 8≤T≤20 μm, and the T value is exemplarily 8 μm, 10 μm, 12 μm, 14 μm, 16 μm, 18 μm, or 20 μm, but is not limited thereto.

[0073] (2) providing a first mask plate 5, adjusting the position of the first mask plate 5 so that the light transmission area of the first mask plate 5 corresponds to the preset position of the non-bridge region 32, and performing exposure treatment to form an inclined surface with a steep angle in the non-bridge region 32;

[0074] In this step, the first mask plate 5 (the shaded part is the light shielding area, and the other part is the light transmission area) is used for exposure treatment, as shown in Figure 6 The pattern on the first mask plate 5 can be transferred to the positive photoresist 4 layer, as shown in Figure 7

[0075] ​Preferably, the width of the light-transmitting area of ​​the first mask 5 is 1 μm to 10 μm, that is, the upper width of the non-bridged area 32 in the isolation trench 3 is 1 μm to 10 μm. It should be noted that the steep angle of the non-bridged area 32 in this application refers to an angle between the inclined surface and the horizontal line greater than 60°. Preferably, the isolation trench angle of the non-bridged area 32 is θ1, where θ1 is greater than 70°. This reduces the etching area of ​​the epitaxial layer 2, thereby increasing the light-emitting area of ​​the high-voltage LED chip and improving the luminous efficiency.

[0076] Furthermore, when performing the exposure process at the isolation trench 3 in the non-bridging region 32, the purpose is to separate the epitaxial layer 2 into several PN junctions, thereby exposing the substrate 1. Therefore, the exposure dose during the photolithography process must be sufficiently large to completely develop the positive photoresist 4. The exposure dose during the exposure process is K, and the value of K is related to the coating thickness T of the positive photoresist 4. In some specific and preferred embodiments, K ≥ T * 80. The unit of the exposure dose K during the exposure process is millijoule (mJ).

[0077] (3) providing a second mask 6, adjusting the position of the second mask 6 so that the light-transmitting area 61 of the second mask 6 corresponds to the preset position of the bridge area 31, wherein the light-transmitting area 61 of the second mask 6 has a plurality of sub-light-transmitting areas of different sizes, performing n times of photolithography using the plurality of sub-light-transmitting areas of different sizes of the second mask 6, so that the bridge area 31 forms an inclined surface with a gentle angle, wherein n ≥ 1 and is an integer;

[0078] In this step, the design of the second mask 6 is as follows: Figure 8 As shown (the shaded portion is the shading area, and the other portion is the light-transmitting area 61), the light-transmitting area 61 corresponds to the preset position of the bridge area 31, and the non-bridge area 32 passes through the center of the bridge area 31. Specifically, please refer to 9. Each light-transmitting area 61 in the second mask 6 has a plurality of sub-light-transmitting areas of different sizes (each box is a complete light-transmitting area 61), such as the first sub-light-transmitting area A1, the second sub-light-transmitting area A2, and the third sub-light-transmitting area A3, and the sizes increase in equal gradients. By adjusting the sizes of the sub-light-transmitting areas 61 at the preset positions of the bridge area 31 and performing exposure processing respectively, an inclined surface with a gentle angle can be formed in the bridge area 31. In the specific implementation process, as the n value increases, the size of the light-transmitting area 61 gradually increases, which is conducive to the formation of the inclined surface of the bridge area 31.

[0079] Further, when n = 1, i.e. the wafer is subjected to one-time photolithography and etching with the second mask 6 as a shield, the bridging area 31 of the isolation groove 3 is obtained, at this time, the size of the light transmission area 61 of the second mask 6 can be selected according to actual requirements. When n > 1, i.e. the wafer needs to be subjected to multiple times of photolithography with the second mask 6 as a shield, and finally etching to form the bridging area 31 of the isolation groove 3. The value of n is positively correlated with the inclination angle of the bridging area 31, the greater the value of n, the greater the inclination angle of the bridging area 31, and the more inclined the inclined surface of the bridging area 31. It should be noted that the gentle angle of the bridging area 31 in the present application refers to the included angle between the inclined surface and the horizontal line being less than 60°, preferably, the angle of the isolation groove 3 of the bridging area 31 is θ2, θ2≤50°, it can be understood that the inclination angle and the angle θ2 of the isolation groove 3 of the bridging area 31 are complementary angles.

[0080] Optionally, referring to Figure 9 , the width of the first sub-light transmission area A1 of the second mask 6 is adjusted to d1 during the first time photolithography, when n > 1, the width of the light transmission area of the second mask during the nth time photolithography is d n , d n = 2bn + d1, wherein b = 1 ~ 3, b is exemplarily 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, etc. In some specific and preferred embodiments, 10 ≤ d1 ≤ 50 μm, d1 is exemplarily 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, etc.; the horizontal distance between the bridging area formed by the first time photolithography and the non-bridging area is c1; when n > 1, the horizontal distance between the bridging area formed by the nth time photolithography and the non-bridging area is c n , c n = an + c1, wherein a = 3 ~ 15, a is exemplarily 3 μm, 5 μm, 10 μm, 15 μm, etc. In some specific and preferred embodiments, 3 ≤ c1 ≤ 25 μm, c1 is exemplarily 3 μm, 5 μm, 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, etc. It should be noted that the length refers to the distance along the electrode bridging direction, and the width refers to the distance perpendicular to the electrode bridging direction.

[0081] Further, in step (3), the isolation groove 3 of the bridging area 31 is subjected to multiple times of photolithography, and during the exposure process, it is ensured that the positive photoresist 4 cannot be fully exposed, so that the remaining part of the positive photoresist 4 can be reserved outside the epitaxial layer 2. The purpose of the exposure process in step (2) is different, therefore, in step (3), the exposure amount of the exposure process during n times of photolithography is J, which satisfies K > J.

[0082] Furthermore, when n>1, the J value decreases as the n value increases, which can be a linear decrease, a gradient decrease, or an irregular decrease according to the thickness of the positive photoresist 4. More preferably, the exposure amount of the first photolithography process is J1, K>J1, and the exposure amount of the nth photolithography process is J n , J n =J1-m(n-1), where m=20~300(n-1), the exposure amount during the last photolithography is J n The value cannot be too large to ensure that the thickness of the positive photoresist 4 is thick enough to protect the epitaxial layer 2 from being etched. Examples of m include 20, 50, 70, 100, 120, 150, 170, 200, 220, 250, 270, 300, etc. At the same time, the value of J is also related to the coating thickness T of the positive photoresist 4. In some specific and preferred embodiments, J1<T*50; J n ≤T*100 / 5. It should be noted that the unit of the exposure value J during the exposure process is millijoule (mJ).

[0083] See also Figures 10-11 , taking n=2 as an example for explanation.

[0084] In step (3), provide Figure 8 and Figure 9 The second mask 6 shown in FIG. 1 is used to determine the position of the isolation trench 3 in the bridge area 31 with the position of the isolation trench 3 in the non-bridge area 32 as the center. Then, the position of the second mask 6 is adjusted so that the smallest light-transmitting area A1 corresponds to the preset position of the bridge area 31. Figure 10 Then, the position of the second mask 6 is adjusted so that the second light-transmitting area A2 with a larger size corresponds to the preset position of the bridge area 31, as shown in FIG. Figure 11 As shown, a second exposure process is performed to complete the second photolithography, that is, the final photolithography.

[0085] (4) performing a development process to form a non-bridging structure with a steep angle and a bridging structure with a gentle angle;

[0086] In this step, the positive photoresist 4 layer that has been subjected to multiple exposure treatments in steps (2) and (3) is developed to generate a product soluble in a developer in the light-transmitting portion of the positive photoresist 4 in the first mask 5 and the second mask 6. The product is then dissolved and removed after the development treatment, thereby forming a pattern on the epitaxial layer 2 with the first mask 5 and the second mask 6 as shielding, i.e., a non-bridge structure with a steep angle and a bridge structure with a gentle angle. The bridge structure with a gentle angle after development is as shown in FIG. Figure 12 As shown, the non-bridging structure with a steep angle after development is as shown in Figure 13 shown.

[0087] (5) etching treatment is performed to form the non-bridge region 32 with steep angle and the bridge region 31 with gentle angle.

[0088] In this step, etching is performed with the developed positive photoresist 4 as a mask to expose the substrate 1, and the pattern on the positive photoresist 4 is transferred to the epitaxial layer 2 to form the non-bridge region 32 with steep angle and the bridge region 31 with gentle angle. The structure of the isolation groove 3 of the non-bridge region 32 with steep angle is shown in FIG. 4, and the structure of the isolation groove 3 of the bridge region 31 with gentle angle is shown in FIG. 5. Figure 4 Figure 5 Figure 4 Figure 5 As can be seen, the angle of the bridge isolation groove 3 is more inclined, which is conducive to electrode bridging of the bridge region 31. Meanwhile, the inclination of the non-bridge region 32 is small, which is conducive to increasing the light-emitting area of the high-voltage LED chip and thus improving the light-emitting efficiency of the high-voltage LED chip. Alternatively, dry etching such as reactive ion etching and high-density plasma etching can be selected for etching treatment.

[0089] Optionally, the method for preparing the high-voltage LED chip further comprises: preparing a current blocking layer on the obtained high-voltage LED chip.

[0090] In this step, the method for preparing the current blocking layer comprises: depositing a current blocking layer material on the obtained high-voltage LED chip, and then performing photolithography and etching to obtain the current blocking layer.

[0091] Preferably, the material of the current blocking layer includes but is not limited to SiO2, and the thickness of the current blocking layer is 350-450 nm. The deposition mode is preferably plasma-enhanced chemical vapor deposition (PECVD), and the etching mode is preferably wet etching.

[0092] Optionally, the method for preparing the high-voltage LED chip further comprises: preparing a transparent conductive layer on the obtained high-voltage LED chip.

[0093] In this step, the method for preparing the transparent conductive layer comprises: depositing a transparent conductive material on the obtained high-voltage LED chip, and then performing photolithography and etching to obtain the transparent conductive layer.

[0094] Preferably, the material of the transparent conductive layer includes but is not limited to ITO, and the thickness of the transparent conductive layer is 40-80 nm. The deposition mode is preferably plasma-enhanced chemical vapor deposition (PECVD), and the etching mode is preferably wet etching.

[0095] Optionally, the method for preparing the high-voltage LED chip further comprises: preparing an electrode on the obtained high-voltage LED chip.

[0096] ​​​In the step, the preparation method of the electrode comprises: coating a metal electrode layer on the high-voltage LED chip, and then performing photolithography to obtain the electrode.

[0097] Preferably, the coating can be performed by using a metal coating device.

[0098] Optionally, the preparation method of the high-voltage LED chip further comprises: preparing a passivation layer on the obtained high-voltage LED chip.

[0099] In the step, the preparation method of the passivation layer comprises: depositing a passivation layer material on the high-voltage LED chip, and then performing photolithography and etching to obtain the passivation layer.

[0100] Preferably, the material of the passivation layer comprises but is not limited to SiO2, the thickness of the passivation layer is 200-300 nm, the deposition mode is preferably plasma enhanced chemical vapor deposition (PECVD), and the etching mode is preferably wet etching.

[0101] Correspondingly, the application also provides a high-voltage LED chip prepared by the above preparation method.

[0102] The application will be further described below with specific examples:

[0103] Example 1

[0104] The embodiment provides a high-voltage LED chip, and a preparation method thereof is as follows:

[0105] S1, depositing an epitaxial layer on a sapphire substrate, the epitaxial layer comprising an N-type semiconductor, a quantum well and a P-type semiconductor; the thickness H of the epitaxial layer is 5.5 μm;

[0106] S2, etching the epitaxial layer by photolithography and dry etching to expose the N-type semiconductor layer with an etching depth of 1 μm, to form a cutting path and a position for connecting a negative electrode;

[0107] S3, performing photolithography and etching treatment at the cutting path position to form an isolation groove, the isolation groove comprising a non-bridge region and a bridge region; the specific steps are as follows:

[0108] (1) coating a positive photoresist on the side of the epitaxial layer away from the substrate;

[0109] In the step, the coating thickness T of the positive photoresist is 11 μm;

[0110] (2) using a first mask plate as shown in Figure 6 to shield, so that the light transmission region of the first mask plate corresponds to the preset position of the non-bridge region, and performing exposure treatment, so that the isolation groove of the non-bridge region forms an inclined surface with a steep angle, as shown in Figure 7 .

[0111] In this step, the width of the light-transmitting region in the first mask is 3 μm, and the exposure amount K is 1100 mJ.

[0112] (3) The second mask shown in FIG. 3 is used as a shield to make the smallest first sub-light-transmitting region A1 correspond to the preset position of the bridge region, as shown in FIG. 4, and a first exposure process is performed to complete the first photolithography and form the first inclined surface structure of the isolation groove of the bridge region. Figure 8 Figure 9 The second mask shown in FIG. 3 is used as a shield to make the smallest first sub-light-transmitting region A1 correspond to the preset position of the bridge region, as shown in FIG. 4, and a first exposure process is performed to complete the first photolithography and form the first inclined surface structure of the isolation groove of the bridge region. Figure 10

[0113] In this step, the exposure amount J1 of the first exposure process is 400 mJ, c = 6 μm, and d = 25 μm. The positive photoresist in this region is not fully photolithographed, and after development, the positive photoresist still protects the epitaxial layer, but is not thick enough to completely protect the epitaxial layer, and part of the epitaxial layer is etched during dry etching.

[0114] Subsequently, the position of the second mask is adjusted to make the larger first sub-light-transmitting region A2 correspond to the preset position of the bridge region, as shown in FIG. 5, and a second exposure process is performed to complete the second photolithography, i.e., the last photolithography, so that the isolation groove of the bridge region forms an inclined surface with a gentle angle. Figure 11

[0115] In this step, the exposure amount J2 of the second exposure process is 100 mJ, where a = 5 μm and b = 1 μm. The photoresist in this region is not fully photolithographed, and after development, the photoresist is thick enough to completely protect the epitaxial layer from dry etching.

[0116] (4) The wafer after the above photolithography is developed, and the structure of the non-bridge region with an abrupt angle after development is shown in FIG. 6, and the structure of the bridge region with a gentle angle after development is shown in FIG. 7. Figure 12 Figure 13 (5) The wafer after the above development is dry etched to form the structure of the isolation groove of the non-bridge region with an abrupt angle, as shown in FIG. 8, and the structure of the isolation groove of the bridge region with a gentle angle, as shown in FIG. 9.

[0117] (5) The wafer after the above development is dry etched to form the structure of the isolation groove of the non-bridge region with an abrupt angle, as shown in FIG. 8, and the structure of the isolation groove of the bridge region with a gentle angle, as shown in FIG. 9. Figure 4 Figure 5

[0118] S4. The positive photoresist is removed, and SiO2 material with a thickness of 400 nm is deposited on the above structure by PECVD, followed by photolithography and wet etching to prepare a current blocking layer.

[0119] S5. ITO transparent conductive layer material with a thickness of 60 nm is deposited on the above structure, and a transparent conductive layer is prepared by photolithography and wet etching.

[0120] ​​​​​​S6. On the above structure, electrodes are prepared by photolithography and metal coating equipment;

[0121] S7. Deposit SiO2 material on the above structure by PECVD to a thickness of 230 nm, and then perform photolithography and wet etching to prepare a passivation layer.

[0122] Example 2

[0123] This embodiment provides a high-voltage LED chip, and its preparation method is basically the same as that of embodiment 1, except that:

[0124] by Figure 8 and Figure 9 The second mask shown is shielded so that the first light-transmitting sub-area A1 with the smallest size corresponds to the preset position of the bridge area, and a first exposure process is performed to complete the first photolithography to form the first slope structure of the isolation trench in the bridge area;

[0125] In this step, the exposure dose of the first exposure process is J1 = 400mJ, c = 6μm; d = 25μm. The positive photoresist in this area is not fully lithographed. After development, there is still positive photoresist protecting the epitaxial layer here, but it is not enough to completely protect the epitaxial layer. During dry etching, part of the epitaxial layer is etched;

[0126] Subsequently, the position of the second mask is adjusted so that the first light-transmitting sub-area A2 with a larger size corresponds to the preset position of the bridge area, and a second exposure process is performed to form a second inclined surface structure of the isolation trench in the bridge area;

[0127] In this step, the exposure dose of the second exposure process is J2 = 250mJ, a = 5μm; b = 1μm. The positive photoresist in this area is not fully lithographed. After development, there is still positive photoresist protecting the epitaxial layer here, but it is not enough to completely protect the epitaxial layer. During dry etching, part of the epitaxial layer is etched;

[0128] Finally, the position of the second mask is adjusted so that the larger first sub-light-transmitting area A3 corresponds to the preset position of the bridge area, and a third exposure process is performed to complete the third and final photolithography, so that the isolation trench in the bridge area forms a gently inclined surface.

[0129] In this step, the exposure amount of the third exposure treatment is J3=100mJ, where a=5μm and b=1μm. The photoresist in this area is not fully photoetched, and there is still photoresist here after development. The photoresist is thick enough to completely protect the epitaxial layer from dry etching.

[0130] Example 3

[0131] This embodiment provides a high-voltage LED chip, and its preparation method is basically the same as that of embodiment 1, except that:

[0132] The exposure amount of the first exposure process is J1=400mJ, c=6μm; d=25μm;

[0133] The exposure amount of the second exposure process is J2=200 mJ, a=5 μm; b=1 μm.

[0134] Example 4

[0135] This embodiment provides a high-voltage LED chip, and its preparation method is basically the same as that of embodiment 1, except that:

[0136] In step (1), the coating thickness of the positive photoresist is T=13 μm.

[0137] control group

[0138] by Figure 1 The high-voltage LED chip shown is a control group, that is, in this comparative example, the isolation grooves in the bridge area and the isolation grooves in the non-bridge area are completed by using one photoresist and one photolithography process.

[0139] Performance Testing

[0140] The high-voltage LED chip obtained in the embodiment was tested for its luminous brightness, non-bridge area angle, and bridge area angle under 30 mA. The test results are shown in Table 1 below.

[0141] Table 1 Performance test results of the embodiment and the control group

[0142]

[0143] It can be seen from the above results that compared with the control group, in Example 1, the angle of the flying bridge area becomes larger, and the luminous area is increased, so the luminous brightness is brighter than the control group; compared with Example 1, Example 2 adds a photolithography process, which can make the angle of the bridge area more oblique, so the luminous area in the bridge area is slightly reduced, and the brightness is slightly reduced; in Example 3, the exposure amount of J2 is increased, and it is easier to obtain a bridge area with a large inclination angle, thereby reducing the luminous area and reducing the brightness; in Example 4, the photoresist layer becomes thicker, but the exposure energy remains unchanged, which makes the photoresist angle more difficult to be oblique, so the angle of the bridge area is slightly increased, which prompts a slight increase in the luminous area, and then the luminous brightness is also slightly brighter.

[0144] It can be seen that, in the present application, the isolation groove is divided into a bridging region and a non-bridging region, the epitaxial layer of the LED chip is photoetched by using the first mask and the second mask, the design of the light-transmitting region of the second mask, the thickness of the positive photoresist, the thickness of the epitaxial layer, and the exposure amount of the exposure treatment are combined, the isolation groove structure with a relatively steep angle of the non-bridging region and a relatively gentle angle of the bridging region is formed, the light-emitting area is effectively increased, the light-emitting efficiency is greatly improved, and the formed isolation groove structure is beneficial to electrode bridging, so that the obtained high-voltage LED chip has stable light-emitting brightness under the same current condition.

[0145] The above only discloses a preferred embodiment of the present application, and of course cannot limit the scope of the present application, so equivalent changes made according to the claims of the present application still fall within the scope of the present application.

Claims

1. A method of fabricating a high voltage LED chip, characterized by, The application relates to a method for manufacturing a semiconductor wafer, and comprises the following steps: An epitaxial layer is arranged on a substrate, and the epitaxial layer comprises at least an N-type semiconductor, a quantum well and a P-type semiconductor; The epitaxial layer is etched to expose the N-type semiconductor layer, and a cutting path is formed; Photoetching and etching treatment are performed at the position of the cutting path to form an isolation groove, and the isolation groove comprises a non-bridge region and a bridge region; The photoetching and etching treatment performed at the position of the cutting path to form the isolation groove comprises the following steps: (1) a positive photoresist is coated on the side of the epitaxial layer away from the substrate; (2) a first mask is provided, the position of the first mask is adjusted so that the light-transmitting region of the first mask corresponds to the preset position of the non-bridge region, and exposure treatment is performed so that the non-bridge region forms an inclined surface with a steep angle; (3) a second mask is provided, the position of the second mask is adjusted so that the light-transmitting region of the second mask corresponds to the preset position of the bridge region, the light-transmitting region of the second mask comprises a plurality of sub-light-transmitting regions with different sizes, n times of photoetching is performed by using the plurality of sub-light-transmitting regions with different sizes of the second mask, and the bridge region forms an inclined surface with a gentle angle, wherein n is an integer greater than or equal to 1; (4) development treatment is performed to form a non-bridge structure with a steep angle and a bridge structure with a gentle angle; (5) etching treatment is performed to form a non-bridge region with a steep angle and a bridge region with a gentle angle.

2. The method for preparing a high-voltage LED chip according to claim 1, wherein: The value of n is positively correlated with the inclination angle of the bridge region.

3. The method for preparing a high-voltage LED chip according to claim 1, wherein: The non-bridge region passes through the center of the bridge region, and the width of the light-transmitting region of the second mask in the first photoetching is d1; When n>1, the width of the light transmission area of the second mask in the nth photoetching is d n , d n =2bn+d1, wherein b=1 μm~3 μm.

4. The method for preparing a high-voltage LED chip according to claim 3, wherein: The horizontal distance between the bridge region formed in the first photoetching and the non-bridge region is c1; when n>1, the horizontal distance between the bridge region and the non-bridge region formed by the n th photoetching is c n , c n =an+c1, wherein a=3μm~15μm.

5. The method of producing a high voltage LED chip according to claim 3 or 4, wherein 3<=c1<=25 mu m; 10<=d1<=50 mu m; The width of the light-transmitting region of the first mask is 1-10 mu m.

6. The method for preparing a high-voltage LED chip according to claim 1, wherein: In step (3), the exposure amount of the exposure treatment in the n times of photoetching is J, and the value of J decreases with the increase of the value of n; In step (2), the exposure amount of the exposure treatment is K, and K>J.

7. The method for preparing a high-voltage LED chip according to claim 6, wherein: The coating thickness of the positive photoresist is T; In step (3), when n>1, the exposure amount of the first photolithography process is J1, and the exposure amount of the nth photolithography process is J n , J n =J1-m(n-1), where m=20mJ~300mJ; In step (2), the exposure amount of the exposure treatment is K, and K>J1.

8. The method for preparing a high-voltage LED chip according to claim 7, wherein: J1 < T*50; J n ≤ T*100 / 5; K ≥ T*80; The thickness of the epitaxial layer is H, and T>=H*2 is satisfied.

9. The method of claim 1 to 4, wherein The angle of the isolation groove of the non-bridge region is theta1, and theta1>70 DEG; the angle of the isolation groove of the bridge region is theta2, and theta2<=50 DEG.

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