Testing device of interlocking detection system and electronic equipment

Abstract

The invention discloses a testing device of an interlocking detection system and electronic equipment, and the device is characterized in that a first controlled end of a first relay, a second controlled end of a fourth relay and one end of a resistor are connected with one end of an interlocking loop, a third controlled end of the first relay is connected with a first controlled end of a third relay, and a first control end of the third relay receives a first signal; a first controlled end of the second relay is connected with the other end of the interlocking loop, a second controlled end of the second relay is connected with a first controlled end of the fourth relay, and a first control end of the second relay receives a second signal; a second controlled end of the third relay is connected with the power supply, a third controlled end is grounded, and a first control end receives a third signal; a third controlled end of the fourth relay is connected with the other end of the resistor, a first control end of the fourth relay receives a fourth signal, and second control ends of all relays are grounded; and then the state of the interlocking loop is simulated through the first signal, the second signal, the third signal and the fourth signal, so that the detection efficiency and accuracy are improved.

Description

A test device and electronic equipment for an interlock detection system Technical Field

[0001] The present application relates to the technical field of electric vehicles, and in particular to a testing device and electronic equipment for an interlock detection system. Background Art

[0002] The high-voltage systems of new energy pure electric vehicles typically contain voltages exceeding 400V. During driving or DC charging, operating currents can reach hundreds of amperes. Therefore, appropriate safety technologies are required to monitor the vehicle's high-voltage system to reduce the probability of risk. To ensure the proper operation of the high-voltage interlock detection system, reliability testing of new energy vehicles requires constructing a high-voltage interlock fault to test the interlock function's ability to detect abnormal conditions.

[0003] In current practical applications, high-voltage interlock fault injection is achieved by connecting two contactors, where the first contactor is used to open the interlock circuit, and the second contactor is used to short the interlock circuit to the ground and the power supply. However, this solution cannot simulate the common fault of increased interlock circuit impedance.

[0004] Summary of the Invention

[0005] The present application provides a testing device and electronic equipment for an interlock detection system, which are used to improve detection efficiency and accuracy.

[0006] In a first aspect, the present application provides a test device for an interlock detection system, which includes: a first relay, a second relay, a third relay, a fourth relay and a resistor, wherein the first controlled end of the first relay, the second controlled end of the fourth relay and one end of the resistor are connected to one end of the interlock loop, the third controlled end of the first relay is connected to the first controlled end of the third relay, the first control end of the first relay receives a first signal, the second control end of the first relay is grounded, and the interlock loop is a loop detected by the interlock detection system; the first controlled end of the second relay is connected to the other end of the interlock loop, the second controlled end of the second relay is connected to the first controlled end of the fourth relay, the first control end of the second relay receives a second signal, and the second control end of the second relay is grounded; the second controlled end of the third relay is connected to a power supply, the third controlled end of the third relay is grounded, the first control end of the third relay receives a third signal, and the second control end of the third relay is grounded; the third controlled end of the fourth relay is connected to the other end of the resistor, the first control end of the fourth relay receives a fourth signal, and the second control end of the fourth relay is grounded; the first signal, the second signal, the third signal and the fourth signal are used to simulate the state of the interlock loop.

[0007] In the above aspects, by adjusting the levels of the first signal, the second signal, the third signal and the fourth signal, the connection mode of the controlled end inside each low-voltage relay is changed, thereby simulating the state of the interlocking loop, thereby realizing the testing of the function and performance of the interlocking detection system and improving the detection efficiency and accuracy.

[0008] In one possible implementation, when the first signal, the second signal, the third signal, and the fourth signal are at a low level, the state of the interlock loop is a normal state; when the first signal, the second signal, and the third signal are at a low level, and the fourth signal is at a high level, the state of the interlock loop is a state in which the impedance increases; when the first signal and the third signal are at a high level, and the second signal and the fourth signal are at a low level, the state of the interlock loop is a short-circuit state to the ground; when the first signal is at a high level, and the second signal, the third signal, and the fourth signal are at a low level, the state of the interlock loop is a short-circuit state to the power supply; when the first signal, the third signal, and the fourth signal are at a low level, and the second signal is at a high level, the state of the interlock loop is an open state.

[0009] In the above possible implementation manner, the first signal, the second signal, the third signal and the fourth signal can be used to simulate the test scenarios of open circuit, short circuit to ground, short circuit to power supply and increased loop resistance, thereby improving simulation efficiency.

[0010] In a possible implementation, the device further includes an operating unit configured to receive a user's command to adjust the levels of the first signal, the second signal, the third signal, and the fourth signal.

[0011] In the above possible implementation manner, the user can adjust the first signal, the second signal, the third signal and the fourth signal on the operation unit to improve the user experience.

[0012] In a possible implementation, the device further includes a feedback unit configured to display the levels of the first signal, the second signal, the third signal, and the fourth signal adjusted by the operating unit, as well as a status of the interlocking loop.

[0013] In the above possible implementation manner, the adjusted levels of the first signal, the second signal, the third signal, and the fourth signal and the state of the interlocking loop are displayed in real time, thereby improving detection efficiency and user experience.

[0014] In a possible implementation, the device further includes a monitoring unit, which is configured to monitor a detection result of the interlock detection system.

[0015] In the above possible implementation manner, the detection result of the monitoring interlock detection system can be compared with the simulation state in a timely manner.

[0016] In a possible implementation, the device further includes a storage unit configured to store instructions of the device.

[0017] In a possible implementation, the device further includes a control unit configured to adjust levels of the first signal, the second signal, the third signal, and the fourth signal according to an adjustment command from a user.

[0018] In one possible implementation, the first relay is a double-throw low-voltage relay or a normally open low-voltage relay, the second relay is a double-throw low-voltage relay or a normally closed low-voltage relay, and the third relay and the fourth relay are double-throw low-voltage relays.

[0019] The second aspect of the present application provides a testing device for an interlock detection system, which includes: a first relay, a second relay, a third relay and an adjustable resistor, wherein the first controlled end of the first relay and the adjustment end of the adjustable resistor are connected to one end of the interlock loop, the second controlled end of the first relay is connected to the second controlled end of the second relay, the third controlled end of the first relay is connected to the first controlled end of the third relay, the first control end of the first relay receives a first signal, the second control end of the first relay is grounded, and the interlock loop is a loop detected by the interlock detection system; the first controlled end of the second relay is connected to the other end of the interlock loop, the third controlled end of the second relay is connected to the other end of the adjustable resistor, the first control end of the second relay receives a second signal, and the second control end of the second relay is grounded; the second controlled end of the third relay is connected to a power supply, the third controlled end of the third relay is grounded, the first control end of the third relay receives a third signal, and the second control end of the third relay is grounded; the resistance values ​​of the first signal, the second signal, the third signal and the adjustable resistor are used to adjust the state of the interlock loop.

[0020] In the above-mentioned second aspect, by adjusting the levels of the first signal, the second signal and the third signal, the connection mode of the controlled end inside each low-voltage relay is changed, and the resistance value of the adjustable resistor is adjusted to simulate the state of the interlocking loop, thereby realizing the testing of the function and performance of the interlocking detection system and improving the detection efficiency and accuracy.

[0021] In one possible implementation, when the first signal, the second signal, and the third signal are low levels, and the resistance of the adjustable resistor is any value, the state of the interlocking loop is a normal state; when the first signal and the third signal are low levels, the second signal is high levels, and the resistance of the adjustable resistor is any value greater than 0, the state of the interlocking loop is a state in which the impedance increases; when the first signal, the second signal, and the third signal are high levels, and the resistance of the adjustable resistor is in a short-circuit state, the state of the interlocking loop is a short-circuit state to ground; when the first signal and the second signal are high levels, the third signal is low levels, and the adjustable resistor is in a short-circuit state, the state of the interlocking loop is a short-circuit state to the power supply; when the first signal and the third signal are low levels, the second signal is high levels, and the adjustable resistor is in an open-circuit state, the state of the interlocking loop is an open-circuit state.

[0022] In a possible implementation, the device further includes an operating unit configured to receive a user's command to adjust the levels of the first signal, the second signal, and the third signal, and a command to adjust the resistance value of the adjustable resistor.

[0023] In a possible implementation, the device further includes a feedback unit configured to display the levels of the first signal, the second signal, the third signal, and the fourth signal adjusted by the operating unit, as well as the resistance value of the adjustable resistor and the state of the interlocking loop.

[0024] In a possible implementation, the device further includes a monitoring unit, which is configured to monitor a detection result of the interlock detection system.

[0025] In a possible implementation, the device further includes a storage unit configured to store instructions of the device.

[0026] In a possible implementation, the device further includes a control unit configured to adjust the levels of the first signal, the second signal, and the third signal, and the resistance of the adjustable resistor according to an adjustment command from a user.

[0027] In a possible implementation manner, the first relay, the second relay, and the third relay are double-throw low-voltage relays.

[0028] A third aspect of the present application provides an electronic device, which includes a testing device for an interlock detection system as described in the first aspect or any embodiment of the first aspect, or the second aspect or any embodiment of the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] FIG1 is a schematic structural diagram of a high-voltage interlock detection system provided in an embodiment of the present application;

[0030] FIG2 is a schematic structural diagram of a test device for an interlock detection system provided in an embodiment of the present application;

[0031] FIG3 is a schematic diagram of a normal connection state provided by an embodiment of the present application;

[0032] FIG4 is a schematic diagram of a connection in a high impedance state provided by an embodiment of the present application;

[0033] FIG5 is a schematic diagram of a connection in a short-circuit state to ground provided by an embodiment of the present application;

[0034] FIG6 is a schematic diagram of a connection to a power supply short circuit state provided by an embodiment of the present application;

[0035] FIG7 is a schematic diagram of an open circuit connection according to an embodiment of the present application;

[0036] FIG8 is a schematic structural diagram of another testing device provided in an embodiment of the present application;

[0037] FIG9 is a schematic structural diagram of another detection device provided in an embodiment of the present application;

[0038] FIG10 is another schematic diagram of a normal state connection provided by an embodiment of the present application;

[0039] FIG11 is a schematic diagram of another connection state of increased impedance provided by an embodiment of the present application;

[0040] FIG12 is another schematic diagram of a connection in a short-circuit state to ground provided by an embodiment of the present application;

[0041] FIG13 is another schematic diagram of a connection to a power supply short circuit state provided by an embodiment of the present application;

[0042] FIG14 is another schematic diagram of an open circuit state connection according to an embodiment of the present application;

[0043] FIG15 is a schematic structural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0044] The embodiments of the present application provide a testing device and electronic equipment for an interlock detection system, which are used to improve detection efficiency and accuracy.

[0045] The following describes the embodiments of the present application in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present application, rather than all the embodiments. Those skilled in the art will appreciate that with the development of technology and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0046] The terms "first," "second," and the like in the specification and claims of this application and in the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions, e.g., a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to these processes, methods, products, or apparatus.

[0047] The high-voltage system of a new energy pure electric vehicle generally has a high voltage of more than 400V. The operating current during driving or DC charging can reach hundreds of amperes. Therefore, it is necessary to configure corresponding safety technical means to monitor the high-voltage system of the vehicle to reduce the probability of risk. Please refer to Figure 1. As shown in Figure 1, a structural schematic diagram of a high-voltage interlock detection system provided by an embodiment of the present application is shown. The system 10 includes an on-board charger (OBC) 101, a direct current / direct current (DCDC) converter 102, a front motor controller (FMCU) 103, a battery management system (BMS) 104, a vehicle control unit (VCU) 105, a power distribution unit (PDU) 106 and a rear motor control unit (RMCU) 107.

[0048] The high-voltage system of an electric vehicle is generally equipped with one or more high-voltage interlock detection systems. A typical detection circuit is shown in the figure above, which includes two high-voltage interlock detection circuits, where the two interlock circuit monitoring units are VCU and RMCU respectively.

[0049] The OBC is used to charge the electric vehicle's battery. The high-voltage DC power provided by the battery is converted to low-voltage DC power by the DC-DC converter and supplied to the FMCU to power the electric vehicle. The BMS is a functional unit that monitors the battery and manages charge and discharge, ensuring that the battery remains within a safe and controllable state. The high-voltage terminals of these high-voltage components and circuits are connected to the electric vehicle's DC bus, forming a high-voltage circuit. This circuit is subject to vibration and impact during driving, posing a safety risk. The high-voltage interlock system monitors these signs and provides an alarm to the VCU before power is lost, giving the vehicle system time to take countermeasures.

[0050] Among them, the PDU can also input AC power to the battery of the electric vehicle, the BMS monitors the battery and manages charging and discharging, and the RMCU can monitor the circuit.

[0051] Currently, in the high-voltage interlocking circuit of the high-voltage interlocking system, the above-mentioned high-voltage devices and circuits are connected to each other through high-voltage connectors and cables. The high-voltage connector integrates the HVIL interface, such as HVIL_P and HVIL_N connected to the VCU or RMCU.

[0052] To ensure the proper operation of the high-voltage interlock detection system, reliability testing of new energy vehicles requires constructing a high-voltage interlock fault to test the interlock function's ability to detect abnormal conditions. In current applications, this fault is injected by connecting two contactors: the first to open the interlock circuit, and the second to short the interlock circuit to ground and the power supply. However, this approach cannot simulate common faults caused by increased interlock circuit impedance.

[0053] To solve the above problems, an embodiment of the present application provides a testing device for an interlock detection system, which is described as follows.

[0054] Please refer to Figure 2, as shown in Figure 2 is a structural schematic diagram of a test device for an interlock detection system provided in an embodiment of the present application, the device includes: a first relay, a second relay, a third relay, a fourth relay and a resistor, the first controlled end of the first relay, the second controlled end of the fourth relay and one end of the resistor are connected to one end of the interlock loop, the third controlled end of the first relay is connected to the first controlled end of the third relay, the first control end of the first relay receives a first signal, the second control end of the first relay is grounded, and the interlock loop is a loop detected by the interlock detection system; the first controlled end of the second relay is connected to the other end of the interlock loop, the second controlled end of the second relay is connected to the first controlled end of the fourth relay, the first control end of the second relay receives a second signal, and the second control end of the second relay is grounded; the second controlled end of the third relay is connected to the power supply, the third controlled end of the third relay is grounded, the first control end of the third relay receives a third signal, and the second control end of the third relay is grounded; the third controlled end of the fourth relay is connected to the other end of the resistor, the first control end of the fourth relay receives a fourth signal, and the second control end of the fourth relay is grounded; the first signal, the second signal, the third signal and the fourth signal are used to simulate the state of the interlock loop.

[0055] The first relay, the second relay, the third relay, and the fourth relay are double-throw low-voltage relays as an example. In the figure, A1 and A2 are the control terminals of the double-throw low-voltage relay, and 11, 12, and 14 are the controlled terminals of the double-throw low-voltage relay, that is, the first controlled terminal is 11, the second controlled terminal is 12, and the third controlled terminal is 14. The first control terminal is A1, and the second control terminal is A2. In the initial state, that is, when the control terminal A1 of each low-voltage relay is low level (0), the controlled terminals 11 and 12 are connected, and 11 and 14 are disconnected; when A1 is high level (1), 11 and 12 are disconnected, and 11 and 14 are connected. The resistor device can be a sliding resistor or a resistor array to simulate different sizes of loop impedance, or it can be a single-resistance resistor.

[0056] Taking the VCU in the high-voltage interlock detection system as an example, which is responsible for detecting the interlock status, during testing, one end of the interlock loop is HVIL_N, and the other end of the interlock loop is HVIL_P.

[0057] The embodiment of the present application can adjust the level of the A1 terminal of the first relay, the second relay, the third relay, and the fourth relay to change the connection of 11, 12, and 14 of each low-voltage relay, thereby simulating different states of the interlock circuit. The details are as follows:

[0058] 1) In the initial state, the control end of each low-voltage relay is at a low level. At this time, the two pins HVIL_N and HVIL_P of the interlocking circuit are connected and turned on through the second relay and the fourth relay. Please refer to Figure 3. As shown in Figure 3, it is a normal state connection diagram provided by the embodiment of the present application. The 11th and 12th ends of the first relay are connected, and the 11th and 14th ends of the first relay are disconnected. The 11th and 12th ends of the second relay are connected, and the 11th and 14th ends of the second relay are disconnected. The 11th and 12th ends of the third relay are connected, and the 11th and 14th ends of the third relay are disconnected. The 11th and 12th ends of the fourth relay are connected, and the 11th and 14th ends of the fourth relay are disconnected. At this time, HVIL_N is connected to HVIL_P connected to the 11th end of the second relay through the 12th end of the fourth relay. At this time, the state of the simulated interlocking circuit is normal. As shown in Table 1:

[0059] Table 1

[0060]

[0061] 2) When it is necessary to inject a fault with increased impedance into the interlocking loop, the A1 port of the fourth relay is pulled high. At this time, the two pins HVIL_N and HVIL_P of the interlocking loop are connected and conducted through the second and fourth relays and the resistor. Please refer to Figure 4. As shown in Figure 4, it is a connection diagram of the impedance increased state provided by the embodiment of the present application. The 11 ends and 12 ends of the first relay are connected, the 11 ends and 14 ends of the first relay are disconnected, the 11 ends and 12 ends of the second relay are connected, the 11 ends and 14 ends of the second relay are disconnected, the 11 ends and 12 ends of the third relay are connected, the 11 ends and 14 ends of the third relay are disconnected, the 11 ends and 12 ends of the fourth relay are disconnected, and the 11 ends and 14 ends of the fourth relay are connected. At this time, HVIL_N is connected to the 14 end of the fourth relay through the resistor, and is correspondingly connected to HVIL_P connected to the 11 end of the second relay. At this time, the state of the simulated interlocking loop is the impedance increased state, as shown in Table 2:

[0062] Table 2

[0063]

[0064] Optionally, during the test, the variable resistor may be an adjustable resistor, and the resistance value of the adjustable resistor is adjusted to achieve simulation of different impedances on the loop.

[0065] 3) When it is necessary to inject a short-circuit fault to the interlocking circuit, the A1 ports of the first and third relays are pulled high. At this time, the two pins HVIL_N and HVIL_P of the interlocking circuit are connected and turned on through the second and fourth relays, and are short-circuited to the low-voltage power supply ground through the first and third relays. Please refer to Figure 5. As shown in Figure 5, it is a schematic diagram of the connection state of the short-circuit to ground provided in an embodiment of the present application. The 11th and 12th terminals of the first relay are disconnected, the 11th and 14th terminals of the first relay are connected, the 11th and 12th terminals of the second relay are connected, and the 11th and 12th terminals of the first relay are connected. Terminals 11 and 14 of the second relay are disconnected, terminals 11 and 12 of the third relay are disconnected, terminals 11 and 14 of the third relay are connected, terminals 11 and 12 of the fourth relay are connected, and terminals 11 and 14 of the fourth relay are disconnected. At this time, HVIL_N is connected to HVIL_P connected to terminal 11 of the second relay through terminal 12 of the fourth relay, and HVIL_N is connected to terminal 14 of the third relay that is grounded through terminal 11 of the first relay. At this time, the state of the simulated interlock circuit is a short circuit to ground, as shown in Table 3:

[0066] Table 3

[0067]

[0068] 4) When it is necessary to inject a short circuit fault to the interlock circuit, the A1 port of the first relay is pulled high. At this time, the two pins HVIL_N and HVIL_P of the interlock circuit are connected and conducted through the second and fourth relays, and are short-circuited with the positive electrode of the low-voltage power supply through the first and third relays. Please refer to Figure 6. As shown in Figure 6, it is a schematic diagram of the connection state of the power supply short circuit provided by the embodiment of the present application. The 11th and 12th terminals of the first relay are disconnected, the 11th and 14th terminals of the first relay are connected, the 11th and 12th terminals of the second relay are connected, and the 2nd relay is connected. Terminals 11 and 14 of the electrical appliance are disconnected, terminals 11 and 12 of the third relay are connected, terminals 11 and 14 of the third relay are disconnected, terminals 11 and 12 of the fourth relay are connected, and terminals 11 and 14 of the fourth relay are disconnected. At this time, HVIL_N is connected to HVIL_P connected to terminal 11 of the second relay through terminal 12 of the fourth relay, and HVIL_N is connected to terminal 12 of the third relay connected to the power supply through terminal 11 of the first relay. At this time, the state of the simulated interlock circuit is a short circuit state to the power supply, as shown in Table 4:

[0069] Table 4

[0070]

[0071] 5) When it is necessary to inject an open circuit fault into the interlocking loop, the A1 port of the second relay is pulled high. At this time, the two pins HVIL_N and HVIL_P of the interlocking loop will be in an open circuit state. Please refer to Figure 7. As shown in Figure 7, it is a schematic diagram of the open circuit state connection provided by an embodiment of the present application. The 11 and 12 ends of the first relay are connected, the 11 and 14 ends of the first relay are disconnected, the 11 and 12 ends of the second relay are disconnected, the 11 and 14 ends of the second relay are connected, the 11 and 12 ends of the third relay are connected, the 11 and 14 ends of the third relay are disconnected, the 11 and 12 ends of the fourth relay are connected, and the 11 and 14 ends of the fourth relay are disconnected. At this time, HVIL_N cannot be connected to HVIL_P, and the state of the simulated interlocking loop is an open circuit state, as shown in Table 5:

[0072] Table 5

[0073]

[0074] In summary, the switching of the high-voltage interlock circuit state is achieved by controlling the low-voltage relay state, which are normal, increased loop impedance, short circuit to ground, short circuit to power supply, and open circuit. The low-voltage relay A1 signals in each state are shown in Table 6 below:

[0075]

[0076] Since terminal 12 of the first relay and terminal 14 of the second relay do not need to be used, in order to save costs, the first relay can be replaced with a normally open low-voltage relay and the second relay can be replaced with a normally closed low-voltage relay.

[0077] To achieve control of the relay or resistor in the above-mentioned device and to build a good human-machine delivery process in the test, please refer to 8. As shown in FIG8, it is a structural schematic diagram of another test device provided in an embodiment of the present application. In this case, the aforementioned low-voltage relay and resistor together constitute the execution unit 801. The embodiment of the present application can add other functional units, optionally:

[0078] 1) In an embodiment of the present application, an operation unit 802 may be provided to identify the test intention of the tester, such as receiving the user's adjustment command for the first signal, the second signal, the third signal, and the fourth signal, where the adjustment command may be a command generated by the user using an input control such as a button or knob.

[0079] 2) This embodiment of the present application may also include a feedback unit 803 to display the input signals of each low-voltage relay and the status of the interlock circuit. The display result may be a table showing the different simulation states described above, making it easier for the user to adjust the signal level. The feedback unit may be composed of an LCD display, an LED light, or a buzzer.

[0080] 3) This embodiment of the present application may also include a monitoring unit 804 to monitor the interlock detection system's test results, such as obtaining the VCU's monitoring results, thereby coordinating with the feedback unit to verify whether its high-voltage interlock detection function is functioning properly. Furthermore, the feedback unit may simultaneously display both the simulation status and the monitoring status, and report an error when the simulation and monitoring status differ, thereby improving the user experience. Optionally, the monitoring unit may also be used to calibrate or set the initial state of the interlock detection system.

[0081] 4) The embodiment of the present application may further include a storage unit 805 that can store instructions of the device of the embodiment of the present application, such as storing automated execution instructions or test results of the interlock detection system.

[0082] 5) The embodiment of the present application may also be provided with a control unit 806 to collect the adjustment commands of the operation unit 802 so as to drive the above-mentioned low-voltage relay to realize simulation of different states of different high-voltage interlocking circuits, and may also control the feedback unit 803 to simultaneously display the simulation state and the monitoring state. Optionally, the control unit 806 may also automatically drive the execution unit to perform automated testing according to the scenario preset in its storage unit 805, and store the execution results or transmit them through the monitoring unit or store them in the storage unit 805. Optionally, the execution unit may be used alone as a test method or test device, and cooperate with other test equipment, such as digital space (dSPACE) hardware in the loop (HIL), to realize testing of the high-voltage interlocking detection system.

[0083] The embodiment of the present application realizes the construction of open circuit, short circuit to ground, short circuit to power supply and increased loop resistance test scenarios by adjusting the first signal, the second signal, the third signal and the fourth signal based on the connection method of the aforementioned relays and resistors, thereby testing the functions and performance of the interlock detection system and improving the detection efficiency and accuracy.

[0084] In the above embodiment, four low-voltage relays are used. In order to save the number of low-voltage relays, please refer to Figure 9. As shown in Figure 9, it is a structural schematic diagram of another detection device provided in an embodiment of the present application. The device replaces the four low-voltage relays with three double-throw low-voltage relays, such as a first relay, a second relay, a third relay and an adjustable resistor. The first controlled end of the first relay and the adjustment end of the adjustable resistor are connected to one end of the interlocking loop, the second controlled end of the first relay is connected to the second controlled end of the second relay, and the third controlled end of the first relay is connected to the first controlled end of the third relay. The first control end of the first relay receives the first signal, and the second control end of the first relay is grounded. The interlocking loop is a loop detected by the interlocking detection system; the first controlled end of the second relay is connected to the other end of the interlocking loop, the third controlled end of the second relay is connected to the other end of the adjustable resistor, the first control end of the second relay receives the second signal, and the second control end of the second relay is grounded; the second controlled end of the third relay is connected to the power supply, the third controlled end of the third relay is grounded, the first control end of the third relay receives the third signal, and the second control end of the third relay is grounded; the resistance values ​​of the first signal, the second signal, the third signal and the adjustable resistor are used to adjust the state of the interlocking loop.

[0085] The first relay, the second relay, and the third relay are double-throw low-voltage relays. In FIG9 , A1 and A2 are control terminals of the double-throw low-voltage relays, and 11, 12, and 14 are controlled terminals of the double-throw low-voltage relays, that is, the first controlled terminal is 11, the second controlled terminal is 12, and the third controlled terminal is 14. The first control terminal is A1, and the second control terminal is A2. In the initial state, that is, when the control terminal A1 of each low-voltage relay is at a low level (0), the controlled terminals 11 and 12 are connected, and 11 and 14 are disconnected; when A1 is at a high level (1), 11 and 12 are disconnected, and 11 and 14 are connected.

[0086] Taking the VCU in the high-voltage interlock detection system as an example, which is responsible for detecting the interlock status, during testing, one end of the interlock loop is HVIL_N, and the other end of the interlock loop is HVIL_P.

[0087] The embodiment of the present application can adjust the voltage level of the A1 terminal of the first relay, the second relay, and the third relay to change the connection of 11, 12, and 14 of each low-voltage relay, and adjust the resistance value of the adjustable resistor to simulate different states of the interlock circuit. The details are as follows:

[0088] 1) In the initial state, the control end of each relay is at a low level. At this time, the two pins HVIL_N and HVIL_P of the interlocking circuit are connected and conducted through the first relay and the second relay. Please refer to Figure 10. As shown in Figure 10, it is another normal state connection diagram provided by an embodiment of the present application. The 11th and 12th ends of the first relay are connected, and the 11th and 14th ends of the first relay are disconnected. The 11th and 12th ends of the second relay are connected, and the 11th and 14th ends of the second relay are disconnected. The 11th and 12th ends of the third relay are connected, and the 11th and 14th ends of the third relay are disconnected. The resistance value of the adjustable resistor can be any value. At this time, HVIL_N is connected to HVIL_P connected to the 11th end of the second relay through the 11th end of the first relay. At this time, the state of the simulated interlocking circuit is normal. As shown in Table 7:

[0089] Table 7

[0090]

[0091] 2) When it is necessary to inject a fault with increased impedance into the interlocking loop, the A1 port of the second relay is pulled high, and the resistance value of the resistor is adjusted to an appropriate size (such as 10 ohms). At this time, the two pins HVIL_N and HVIL_P of the interlocking loop are connected and turned on through the second relay and the resistor. Please refer to Figure 11. As shown in Figure 11, it is another impedance increased state connection diagram provided by an embodiment of the present application. The 11th and 12th ends of the first relay are connected, the 11th and 14th ends of the first relay are disconnected, the 11th and 12th ends of the second relay are disconnected, the 11th and 14th ends of the second relay are connected, the 11th and 12th ends of the third relay are connected, and the 11th and 14th ends of the third relay are disconnected. The resistance value of the adjustable resistor can be any value greater than 0, such as 10 ohms. At this time, HVIL_N is connected to the 14th end of the second relay through the adjustable resistor, and then connected to HVIL_P connected to the 11th end of the second relay. At this time, the state of the simulated interlocking loop is the impedance increased state. As shown in Table 8:

[0092] Table 8

[0093]

[0094] 3) When it is necessary to inject a short-circuit fault to the interlocking circuit, the A1 ports of the first, second, and third relays are all pulled high, and the resistor short-circuit block is adjusted. At this time, the two pins HVIL_N and HVIL_P of the interlocking circuit are connected and turned on through the second relay, and are short-circuited to the low-voltage power supply ground through the first and third relays. Please refer to Figure 12. As shown in Figure 12, another short-circuit state connection diagram provided in an embodiment of the present application is shown. Terminals 11 and 12 of the first relay are disconnected, terminals 11 and 14 of the first relay are connected, and terminal 11 of the second relay is turned on. The terminals 11 and 14 of the second relay are disconnected, the terminals 11 and 12 of the third relay are connected, the terminals 11 and 12 of the third relay are disconnected, the terminals 11 and 14 of the third relay are connected, and the resistance of the adjustable resistor is set to a short-circuit state. At this time, HVIL_N is equivalent to being directly connected to the terminal 14 of the second relay, and then connected to HVIL_P connected to the terminal 11 of the second relay. HVIL_N is connected to the terminal 14 of the third relay through the terminal 11 of the first relay. Since the terminal 14 of the third relay is grounded, the state of the simulated interlock circuit at this time is a short-circuit state to ground. As shown in Table 9:

[0095] Table 9

[0096]

[0097] 4) When it is necessary to inject a short-circuit fault into the interlocking circuit, the A1 ports of the first and second relays are pulled high, and the resistor short-circuit block is adjusted. At this time, the two pins HVIL_N and HVIL_P of the interlocking circuit are connected and turned on through the second relay, and are short-circuited with the positive pole of the low-voltage power supply through the first and third relays. Please refer to Figure 13. As shown in Figure 13, another schematic diagram of the connection state of the power supply short circuit provided by the embodiment of the present application is shown. The 11th and 12th terminals of the first relay are disconnected, the 11th and 14th terminals of the first relay are connected, and the 11th terminal of the second relay is turned on. The terminals 11 and 14 of the second relay are connected, the terminals 11 and 12 of the third relay are connected, and the terminals 11 and 14 of the third relay are disconnected. The resistance of the adjustable resistor is set to a short-circuit state. At this time, HVIL_N is equivalent to being directly connected to the terminal 14 of the second relay, and then connected to HVIL_P connected to the terminal 11 of the second relay. HVIL_N is connected to the terminal 12 of the third relay through the terminal 11 of the first relay. Since the terminal 14 of the third relay is connected to the power supply, the state of the simulated interlock circuit at this time is a short-circuit state to the power supply. As shown in Table 10:

[0098] Table 10

[0099]

[0100] 5) When it is necessary to inject an open circuit fault into the interlocking loop, the A1 port of the second relay is pulled high and the resistor open block is adjusted. At this time, the two pins HVIL_N and HVIL_P of the interlocking loop will be in an open circuit state. Please refer to Figure 14. As shown in Figure 14, another open circuit state connection diagram provided by an embodiment of the present application is shown. The 11 and 12 ends of the first relay are connected, the 11 and 14 ends of the first relay are disconnected, the 11 and 12 ends of the second relay are disconnected, the 11 and 14 ends of the second relay are connected, the 11 and 12 ends of the third relay are connected, and the 11 and 14 ends of the third relay are disconnected. The resistance value of the adjustable resistor is set to an open circuit state. At this time, HVIL_N is connected to the 14 end of the second relay through the adjustable resistor, and then connected to the HVIL_P connected to the 11 end of the second relay. Since the adjustable resistor is in an open circuit state, HVIL_N and HVIL_P are disconnected. At this time, the state of the simulated interlocking loop is an open circuit state. As shown in Table 11:

[0101] Table 11

[0102]

[0103] In summary, the switching of the high-voltage interlock circuit state is achieved by controlling the relay state and the resistor value, which are normal, increased loop impedance, short circuit to ground, short circuit to power supply, and open circuit. The states of the low-voltage relay and adjustable resistor in each state are shown in Table 12 below:

[0104] Table 12

[0105]

[0106] In order to realize the control of the relay or resistor in the above-mentioned device and to build a good human-machine delivery process in the test, the aforementioned low-voltage relay and adjustable resistor together constitute the execution unit. The embodiment of the present application can add the operation unit, feedback unit, detection unit, storage unit and control unit in Figure 8, which will not be repeated here.

[0107] The embodiment of the present application realizes the construction of open circuit, short circuit to ground, short circuit to power supply and increased loop resistance test scenarios by adjusting the levels of the first signal, the second signal and the third signal and the resistance value of the adjustable resistor based on the connection method of the aforementioned relay and resistor, thereby testing the function and performance of the interlock detection system and improving the detection efficiency and accuracy.

[0108] Please refer to Figure 15, which is a schematic diagram of a possible structure of an electronic device 150 provided in an embodiment of the present application. The electronic device 150 can be a signal processor, which can include the detection device 1501 of the interlock detection system shown in any one of Figures 2 to 14.

[0109] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0110] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0111] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0112] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0113] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

Claims

1. A test device for an interlock detection system, characterized in that: include: a first relay, a second relay, a third relay, a fourth relay, and a resistor, The first controlled end of the first relay, the second controlled end of the fourth relay, and one end of the resistor are connected to one end of an interlocking circuit, the third controlled end of the first relay is connected to the first controlled end of the third relay, the first control end of the first relay receives a first signal, the second control end of the first relay is grounded, and the interlocking circuit is a circuit detected by the interlocking detection system; The first controlled end of the second relay is connected to the other end of the interlocking circuit, the second controlled end of the second relay is connected to the first controlled end of the fourth relay, the first control end of the second relay receives the second signal, and the second control end of the second relay is grounded; The second controlled end of the third relay is connected to the power supply, the third controlled end of the third relay is grounded, the first control end of the third relay receives the third signal, and the second control end of the third relay is grounded; The third controlled end of the fourth relay is connected to the other end of the resistor, the first control end of the fourth relay receives the fourth signal, and the second control end of the fourth relay is grounded; The first signal, the second signal, the third signal, and the fourth signal are used to simulate a state of the interlock loop.

2. The device according to claim 1, characterized in that When the first signal, the second signal, the third signal and the fourth signal are at a low level, the state of the interlock loop is a normal state; When the first signal, the second signal and the third signal are at a low level and the fourth signal is at a high level, the state of the interlock loop is a state of increased impedance; When the first signal and the third signal are at a high level, and the second signal and the fourth signal are at a low level, the state of the interlock circuit is a short-circuit state to ground; When the first signal is at a high level, and the second signal, the third signal, and the fourth signal are at a low level, the state of the interlock circuit is a short-circuit state to the power supply; When the first signal, the third signal, and the fourth signal are at a low level, and the second signal is at a high level, the interlock loop is in an open state.

3. The device according to claim 1 or 2, characterized in that The device further includes an operating unit configured to receive a user's command for adjusting the levels of the first signal, the second signal, the third signal, and the fourth signal.

4. The device according to any one of claim 3, characterized in that The device further includes a feedback unit configured to display the levels of the first signal, the second signal, the third signal, and the fourth signal adjusted by the operating unit, and a state of the interlocking loop.

5. The device according to any one of claims 1 to 4, characterized in that: The device further comprises a monitoring unit, which is used to monitor the detection result of the interlock detection system.

6. The device according to any one of claims 1 to 5, characterized in that The device further includes a storage unit configured to store instructions of the device.

7. The device according to claim 3, characterized in that The device further includes a control unit configured to adjust the levels of the first signal, the second signal, the third signal, and the fourth signal according to an adjustment command from the user.

8. The device according to any one of claims 1 to 7, characterized in that The first relay is a double-throw low-voltage relay or a normally open low-voltage relay, the second relay is a double-throw low-voltage relay or a normally closed low-voltage relay, and the third relay and the fourth relay are double-throw low-voltage relays.

9. A test device for an interlock detection system, characterized in that: include: The first relay, the second relay, the third relay and the adjustable resistor, The first controlled end of the first relay and the adjustment end of the adjustable resistor are connected to one end of an interlocking loop, the second controlled end of the first relay is connected to the second controlled end of the second relay, the third controlled end of the first relay is connected to the first controlled end of the third relay, the first control end of the first relay receives a first signal, the second control end of the first relay is grounded, and the interlocking loop is a loop detected by the interlocking detection system; The first controlled end of the second relay is connected to the other end of the interlocking circuit, the third controlled end of the second relay is connected to the other end of the adjustable resistor, the first control end of the second relay receives a second signal, and the second control end of the second relay is grounded; The second controlled end of the third relay is connected to the power supply, the third controlled end of the third relay is grounded, the first control end of the third relay receives the third signal, and the second control end of the third relay is grounded; The first signal, the second signal, the third signal and the resistance value of the adjustable resistor are used to adjust the state of the interlock loop.

10. The device according to claim 9, characterized in that When the first signal, the second signal and the third signal are at a low level and the resistance of the adjustable resistor is any value, the state of the interlock circuit is a normal state; When the first signal and the third signal are at a low level, the second signal is at a high level, and the resistance of the adjustable resistor is any value greater than 0, the state of the interlocking loop is a state of increased impedance; When the first signal, the second signal and the third signal are at a high level and the resistance value of the adjustable resistor is in a short-circuit state, the state of the interlocking loop is a short-circuit state to ground; When the first signal and the second signal are at a high level, the third signal is at a low level, and the adjustable resistor is in a short-circuit state, the state of the interlock circuit is a short-circuit state to the power supply; When the first signal and the third signal are at a low level, the second signal is at a high level, and the adjustable resistor is in an open state, the state of the interlock loop is an open state.

11. The device according to claim 9 or 10, characterized in that The device further includes an operating unit configured to receive a user's command to adjust the levels of the first signal, the second signal, and the third signal, and a command to adjust the resistance value of the adjustable resistor.

12. The device according to any one of claims 11, characterized in that The device further includes a feedback unit configured to display the levels of the first signal, the second signal, and the third signal adjusted by the operating unit, as well as the resistance value of the adjustable resistor and the state of the interlocking loop.

13. The device according to any one of claims 9 to 12, characterized in that The device further comprises a monitoring unit, which is used to monitor the detection result of the interlock detection system.

14. The device according to any one of claims 9 to 13, characterized in that The device further includes a storage unit configured to store instructions of the device.

15. The device according to claim 11, characterized in that The device further includes a control unit configured to adjust the levels of the first signal, the second signal, and the third signal, and the resistance value of the adjustable resistor according to an adjustment command from the user.

16. The device according to any one of claims 9 to 15, characterized in that The first relay, the second relay, and the third relay are double-throw low-voltage relays.

17. An electronic device, characterized in that: The electronic device comprises a testing device for an interlock detection system according to any one of claims 1 to 16.

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