Semiconductor device

Abstract

One embodiment of the present invention provides a semiconductor device having a novel structure. The semiconductor device includes: a first arithmetic device including a register; and a second arithmetic device including a storage circuit, a layer selection circuit, and an arithmetic circuit. The first arithmetic device and the second arithmetic device are provided in an element layer in which a plurality of second element layers are laminated on a first element layer. The register includes a flip-flop and a data retention circuit. The flip-flop and the operational circuit are arranged in the first element layer. The data retention circuit is disposed in each of the plurality of second element layers on the first element layer including the flip-flop. The memory circuit and the layer selection circuit are provided in each of a plurality of second element layers on a first element layer including the arithmetic circuit.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device and the like.

[0002] Note that one embodiment of the present invention is not limited to the above-mentioned technical field. The technical field of one embodiment of the invention disclosed in this specification, etc., relates to an object, method or manufacturing method. In addition, one embodiment of the present invention relates to a process, a machine, a product or a composition of matter. Therefore, more specifically, as examples of the technical field of one embodiment of the present invention disclosed in this specification, semiconductor devices, display devices, light-emitting devices, power storage devices, storage devices (memory devices), driving methods of these devices or manufacturing methods of these devices can be cited. Background Art

[0003] Technical development is underway for a semiconductor device capable of holding charges corresponding to data by combining a transistor using an oxide semiconductor for a channel formation region (hereinafter referred to as an OS transistor) and a transistor using silicon for a channel formation region (hereinafter referred to as a Si transistor).

[0004] By providing the semiconductor device with a structure for saving (also referred to as retaining, storing, or backing up) or loading (also referred to as regenerating, restoring, or rebuilding) a program or data held in a trigger or the like, low power consumption can be achieved by power gating or the like. Therefore, it has been applied to semiconductor devices including a CPU (central processing unit) or the like (for example, refer to Patent Document 1).

[0005] In the CPU, a series of processes (tasks) are executed by successively executing processes corresponding to a program or data.

[0006] Data required for CPU processing or data obtained through the processing is sent and received between the peripheral circuit and the CPU. As the peripheral circuit, various peripheral circuits are used according to user requirements. As the peripheral circuit, for example, a DRAM (Dynamic Random Access Memory) interface, PCI (Peripheral Component Interface), DMA (Direct Memory Access), network interface, audio interface, etc. can be cited.

[0007] When executing multiple tasks, each task is divided into smaller processing units and the processing units of each task are executed sequentially, so that multiple tasks are executed simultaneously. In order to execute this processing, multiple register banks (general register groups) are prepared, and the register banks are switched according to each task to execute the task.

[0008] Furthermore, when the program is transferred from the main routine to the subroutine, the processing of the subroutine is executed after the register bank is switched, and after the processing of the subroutine is completed, the register bank is switched to the original register bank, and then the processing of the main routine is executed. [Prior technical literature] [Patent Document]

[0009] [Patent Document 1] Japanese Patent Application Publication No. 2013-9297 Summary of the invention Technical problem to be solved by the invention

[0010] In a CPU or other computing device, when a register library is insufficient during complex processing, the data of the register corresponding to the task needs to be written to an external memory device first, and when the task is executed again, the data is written back to the register from the external memory device. In this case, energy is consumed by writing and writing back data between the external memory device and the register. By preparing a large number of register libraries, the power consumption between the external memory device and the register can be suppressed, but this will lead to an increase in the circuit layout area.

[0011] In addition, in a computing device that performs computing processing that simulates a neural network, computing using a data group of weight data is performed. When the weight data is stored in an external memory device, when switching different data groups of weight data to perform computing processing, the access frequency to the external memory device increases, thereby consuming energy for writing and writing back data between the external memory device and the computing circuit. In addition, when accessing the external memory device, it is difficult to switch the weight data in a short time.

[0012] One of the purposes of one embodiment of the present invention is to provide a novel semiconductor device, etc. Another purpose of one embodiment of the present invention is to provide a semiconductor device, etc. having a novel structure and having an advantage in low power consumption. Another purpose of one embodiment of the present invention is to provide a semiconductor device, etc. having a novel structure and having excellent computing performance.

[0013] Note that the purpose of one embodiment of the present invention is not limited to the above-mentioned purpose. The above-mentioned purpose does not prevent the existence of other purposes. Other purposes are purposes that are not mentioned above but will be described in the following description. Those skilled in the art can derive and appropriately extract the purposes not mentioned above from the description of the specification or drawings, etc. Note that one embodiment of the present invention achieves at least one of the above-mentioned purpose and / or other purposes. Solutions to technical problems

[0014] One embodiment of the present invention is a semiconductor device, comprising: a first operating device including a register; and a second operating device including a storage circuit, a layer selection circuit and an operating circuit, wherein the first operating device and the second operating device are arranged in an element layer formed by stacking multiple second element layers on a first element layer, the first element layer is provided with a first transistor containing silicon in a semiconductor layer having a channel formation region, and the second element layer is provided with a second transistor containing an oxide semiconductor in a semiconductor layer having a channel formation region, the register includes a trigger and a data holding circuit, the trigger and the operating circuit are arranged in the first element layer, the data holding circuit is arranged in each layer of the multiple second element layers on the first element layer including the trigger, and the storage circuit and the layer selection circuit are arranged in each layer of the multiple second element layers on the first element layer including the operating circuit.

[0015] In a semiconductor device of one embodiment of the present invention, it is preferred that an input terminal of the trigger is electrically connected to each of the output terminals of the data holding circuit, an output terminal of the trigger is electrically connected to each of the input terminals of the data holding circuit, and the data holding circuit has a function of maintaining data corresponding to a task performed by the first computing device by making the second transistor non-conductive.

[0016] In the semiconductor device of one embodiment of the present invention, preferably, the memory circuit includes a memory cell electrically connected to the write word line and the read word line, and the layer selection circuit has a function of outputting a signal supplied to the write word line and the read word line.

[0017] In a semiconductor device of one embodiment of the present invention, preferably, storage circuits provided in different second element layers each include weight data used in arithmetic processing based on a neural network, and the weight data input to the arithmetic circuit is switched by a layer selection circuit.

[0018] In the semiconductor device according to one embodiment of the present invention, preferably, the data holding circuit has a region overlapping with the flip-flop when viewed from a planar perspective.

[0019] In the semiconductor device according to one embodiment of the present invention, preferably, the memory circuit has a region overlapping with the arithmetic circuit when viewed in plan.

[0020] In the semiconductor device according to one embodiment of the present invention, the oxide semiconductor preferably includes In, Ga, and Zn.

[0021] In the semiconductor device according to one embodiment of the present invention, preferably, the arithmetic circuit has a function of performing a product-sum operation.

[0022] Note that other aspects of the present invention are described in the description and drawings of the embodiment modes described below. Effects of the Invention

[0023] One embodiment of the present invention can provide a novel semiconductor device, etc. Another embodiment of the present invention can provide a semiconductor device with a novel structure that is superior in terms of low power consumption, etc. Another embodiment of the present invention can provide a semiconductor device with a novel structure that is excellent in computing performance, etc.

[0024] Note that the description of these effects does not prevent the existence of other effects. In addition, one mode of the present invention does not need to have all the above effects. In addition, effects other than the above can be known and extracted from the description of the specification, drawings, claims, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figures 1A to 1C A diagram illustrating a structural example of a semiconductor device. Figure 2A and Figure 2B A diagram illustrating a structural example of a semiconductor device. Figure 3A and Figure 3B A diagram illustrating a structural example of a semiconductor device. FIG. 4A to FIG. 4E A diagram illustrating a structural example of a semiconductor device. Figure 5 A diagram illustrating a structural example of a semiconductor device. Fig. 6A and Figure 6B A diagram illustrating a structural example of a semiconductor device. Fig. 7A and Figure 7B A diagram illustrating a structural example of a semiconductor device. FIG. 8A to FIG. 8C A diagram illustrating a structural example of a semiconductor device. Fig. 9 A diagram illustrating a structural example of a semiconductor device. FIG. 10A to FIG. 10C A diagram illustrating a structural example of a semiconductor device. Fig.11 A diagram illustrating a structural example of a semiconductor device. Fig.12 A diagram illustrating a structural example of a semiconductor device. FIG. 13A to FIG. 13C A diagram illustrating a structural example of a semiconductor device. Fig.14 A diagram illustrating a structural example of a semiconductor device. Fig.15 A diagram illustrating a structural example of a memory device. Fig.16A A diagram illustrating a structural example of a memory device. Fig. 16B is a diagram illustrating an equivalent circuit of a memory device. Fig.17 A diagram illustrating a structural example of a memory device. Fig.18A A diagram illustrating a structural example of a memory device. Fig.18B is a diagram illustrating an equivalent circuit of a memory device. Fig.19A and Fig.19B It is a diagram showing an example of an electronic component. Fig. 20A and Fig. 20B is a diagram showing an example of an electronic device, FIG. 20C to FIG. 20E This is a diagram showing an example of a large computer. Fig.21 is a diagram showing an example of space equipment. Fig. 22 is a diagram showing an example of a secondary storage system that may be used in a data center. Fig.23 It is a diagram for explaining the structure of the embodiment. Fig.24 It is a diagram for explaining the structure of the embodiment. Fig.25 It is a diagram for explaining the structure of the embodiment. Fig.26 It is a diagram for explaining the structure of the embodiment. Fig. 27 It is a diagram for explaining the structure of the embodiment. Fig.28 It is a diagram for explaining the structure of the embodiment. Fig.29 It is a diagram for explaining the structure of the embodiment. Fig.30 It is a diagram for explaining the structure of the embodiment. Fig.31 It is a diagram for explaining the structure of the embodiment. Fig.32 It is a diagram for explaining the structure of the embodiment. Fig.33A and Fig.33B It is a diagram for explaining the structure of the embodiment. Fig.34 It is a diagram for explaining the structure of the embodiment. Fig.35 It is a diagram for explaining the structure of the embodiment. Fig.36A and Fig.36B It is a diagram for explaining the structure of the embodiment. FIG. 37A to FIG. 37C It is a diagram for explaining the structure of the embodiment. FIG. 38A to FIG. 38CIt is a diagram for explaining the structure of the embodiment. Fig.39 It is a diagram for explaining the structure of the embodiment. Fig.40 It is a diagram for explaining the structure of the embodiment. Modes for Carrying Out the Invention

[0026] The following describes the embodiments with reference to the accompanying drawings. It should be noted that a person skilled in the art can easily understand that the embodiments can be implemented in a variety of different forms, and the methods and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the embodiments shown below.

[0027] In the drawings, the size, thickness of the layer or the area are sometimes exaggerated for the sake of clarity. Therefore, the present invention is not limited to the dimensions in the drawings. In addition, in the drawings, ideal examples are schematically shown, so the present invention is not limited to the shapes or numerical values ​​shown in the drawings.

[0028] In addition, in this specification, etc., unless otherwise specified, the off-state current refers to the drain current when the transistor is in the off state (also called the non-conducting state or the blocking state). Unless otherwise specified, in an n-channel transistor, the off state refers to the voltage V between the gate and the source. gs Below the threshold voltage V th (In a p-channel transistor, V gs Higher than V th ) status.

[0029] In this specification, metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (Oxide Semiconductor, also referred to as OS). For example, when a metal oxide is used in the active layer of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, an OS transistor can be referred to as a transistor containing a metal oxide or an oxide semiconductor.

[0030] (Implementation Method 1) In this embodiment mode, a structural example of a semiconductor device is described.

[0031] <Configuration Example of Semiconductor Device 10> The semiconductor device described in one embodiment of the present invention is used as a SoC (System on Chip) in which a plurality of computing devices, memory devices, and the like are tightly coupled.

[0032] Figure 1A 1 is a block diagram schematically showing a semiconductor device 10 for explaining one embodiment of the present invention. Figure 1B is a block diagram further schematically showing the top surface of the semiconductor device 10. In addition, Figure 1C Yes Description Figure 1A , Figure 1B The diagram shows an example of the structure of the device layer that can be composed of each component shown.

[0033] Note that in this specification, in order to explain the arrangement of each component, the X direction, Y direction, and Z direction are sometimes specified. Figure 1A , Figure 1B In the schematic diagram shown, an X direction, a Y direction, and a Z direction are sometimes defined to explain the arrangement of components constituting the semiconductor device 10. The X direction, the Y direction, and the Z direction are perpendicular or substantially perpendicular to each other.

[0034] In addition, Figure 1A , Figure 1B In the schematic diagram shown, in order to facilitate understanding of the configuration of the components constituting the semiconductor device 10, the components are shown to be separated from each other. The components arranged in the same layer are preferably formed by the same process, but are not limited to this. For example, components formed by different processes may be integrated using bonding technology or the like.

[0035] Figure 1A , Figure 1B The semiconductor device 10 shown includes a computing device (also referred to as a first computing device) 100 , a computing device (also referred to as a second computing device) 200 , a memory device 300 , and a peripheral circuit 400 .

[0036] Figure 1A , Figure 1B The semiconductor device 10 shown has a structure in which a different element layer (element layer 30) is stacked on an element layer 20. For example, Figure 1C As shown, the element layer 20 is stacked with the element layer 30 ( Figure 1C Four component layers 30[1] to 30[4] are shown.

[0037] Note that Figure 1C, the first element layer 30 is represented as element layer 30[1], the second element layer 30 is represented as element layer 30[2], and the third element layer 30 is represented as element layer 30[3]. In addition, the k-th element layer 30 (k is an integer greater than or equal to 2) is represented as element layer 30[k]. Note that in this embodiment, when describing matters related to the plurality of element layers 30 as a whole, or when showing matters common to each layer of the plurality of element layers 30, sometimes only "element layer 30" is mentioned. The same applies to the components to which the symbols describing the plurality of components are attached.

[0038] The computing device 100 has a function of executing an operating system, controlling data, executing various operations, executing programs, and other general processing like a CPU. The computing device 100 includes a register 110 that has a function of storing data during the computing process.

[0039] The computing device 200 includes a plurality of PEs (Processing Elements, also called computing circuits), which have the function of performing special processing such as image processing or product-sum operations. In addition to the computing circuit (not shown), the computing device 200 also includes a storage circuit 210 and layer selection circuits 220 and 230 that have the function of storing weight data used for computing processing.

[0040] like Figure 1C As shown, the register 110 , the storage circuit 210 , and the layer selection circuits 220 and 230 have a structure in which element layers 30 [ 1 ] to 30 [ 4 ] including transistors 31 are provided on an element layer 20 including a transistor 21 .

[0041] The transistor 21 includes silicon in a semiconductor layer 22 having a channel formation region. A transistor including silicon in a semiconductor layer having a channel formation region like the transistor 21 is referred to as a Si transistor. In addition, the transistor 31 includes an oxide semiconductor in a semiconductor layer 32 having a channel formation region. A transistor including an oxide semiconductor in a semiconductor layer having a channel formation region like the transistor 31 is referred to as an OS transistor.

[0042] As the Si transistor, it is particularly preferable to use silicon having high crystallinity, such as single crystal silicon or polycrystalline silicon, because this can achieve high field effect mobility and higher speed operation.

[0043] As metal oxides applied to OS transistors, for example, indium oxide, gallium oxide and zinc oxide can be cited. In addition, the metal oxide preferably contains two or three selected from indium, element M and zinc. In addition, element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten and magnesium. In particular, element M is preferably selected from one or more of aluminum, gallium, yttrium and tin.

[0044] In particular, as the metal oxide film, an oxide containing indium (In), gallium (Ga) and zinc (Zn) (also referred to as IGZO) is preferably used. Alternatively, an oxide containing indium, tin and zinc (also referred to as ITZO) is preferably used. Alternatively, an oxide containing indium, gallium, tin and zinc is preferably used. Alternatively, an oxide containing indium (In), aluminum (Al) and zinc (Zn) (also referred to as IAZO) is preferably used. Alternatively, an oxide containing indium (In), aluminum (Al), gallium (Ga) and zinc (Zn) (also referred to as IAGZO) is preferably used. Alternatively, an oxide containing indium (In), gallium (Ga), zinc (Zn) and tin (Sn) (also referred to as IGZTO) is preferably used.

[0045] In addition, the metal oxide used in the OS transistor may also include two or more metal oxide layers with different compositions. For example, a stacked structure of a first metal oxide layer having a composition of In:M:Zn=1:3:4 [atomic ratio] or a similar composition and a second metal oxide layer having a composition of In:M:Zn=1:1:1 [atomic ratio] or a similar composition disposed on the first metal oxide layer is preferably used.

[0046] Furthermore, for example, a stacked-layer structure of any one selected from indium oxide, indium gallium oxide, and IGZO and any one selected from IAZO, IAGZO, and ITZO may be employed.

[0047] In addition, the metal oxide used for the OS transistor preferably has crystallinity. Examples of crystalline oxide semiconductors include CAAC (c-axis-aligned crystalline)-OS and nc (nanocrystalline)-OS. By using crystalline oxide semiconductors, a semiconductor device with high reliability can be provided.

[0048] The memory device 300 includes a storage layer 310 for storing data input and output to and from the computing device 100 or the computing device 200 .

[0049] The storage layer 310 included in the memory device 300 is preferably, for example, NOSRAM. Figure 1AThe memory layer 310 is shown to be stacked and provided on the drive circuit and the like provided in the element layer 20 in the same manner as the element layers 30 [ 1 ] to 30 [ 4 ]. The memory layer 310 is a layer including memory cells of the NOSRAM.

[0050] "NOSRAM (registered trademark)" is the abbreviation of "Nonvolatile Oxide Semiconductor Random Access Memory (RAM)". NOSRAM refers to a memory in which the storage unit is a two-transistor type (2T) or three-transistor type (3T) gain unit and the transistor is an OS transistor. The OS transistor flows a current between the source and the drain in the off state, that is, the leakage current is extremely small. NOSRAM can be used as a non-volatile memory by utilizing the characteristic of extremely small leakage current to keep the charge corresponding to the data in the storage unit. In particular, NOSRAM can be read out without destroying the retained data (non-destructive readout), so it is suitable for arithmetic processing that only repeatedly performs multiple data read operations. NOSRAM can increase the data capacity by stacking, so it can be used as a large-scale cache memory, main memory (main memory), and auxiliary memory (storage memory) to achieve high performance of semiconductor devices.

[0051] As a structure that can be used for the storage layer 310, in addition to NOSRAM, DOSRAM including OS transistors can also be used. DOSRAM (registered trademark) is an abbreviation of "Dynamic Oxide Semiconductor RAM" and refers to a RAM including a 1T (transistor) 1C (capacitor) type memory cell. DOSRAM is a DRAM formed using OS transistors, and is a memory that temporarily stores information sent from the outside. DOSRAM is a memory that utilizes the low off-state current characteristic of OS transistors.

[0052] The peripheral circuit 400 includes an interface circuit with an external circuit, for example, a DRAM (Dynamic Random Access Memory) interface, a PCI (Peripheral Component Interface), a DMA (Direct Memory Access), a network interface, an audio interface, and the like.

[0053] The semiconductor device 10 is used as a so-called SoC in which arithmetic devices 100 and 200 such as a CPU and a GPU are tightly coupled with a memory device 300. This structure can shorten the length of wiring between devices for data transmission, thereby suppressing heat generation and power consumption increase.

[0054] <Configuration Example of Register 110> Figure 2A It is shown Figure 1A , etc. are circuit diagrams of a configuration example of a register 110. The register 110 includes a scan trigger 120 (volatile register) and a plurality of data holding circuits 130[1] to 130[k] (k is an integer greater than or equal to 2). The number of k may correspond to the number of layers of the element layer 30. The scan trigger 120 includes a selector 121 and a trigger 122. In addition, the register 110 includes a transistor 132.

[0055] Signals BK[1] to BK[k] are signals for controlling the saving (also referred to as retention, storage, or backup) of data held by the flip-flop 122 in the scan flip-flop 120. By saving the data, the data held by the flip-flop 122 is held in any one of the data holding circuits 130[1] to 130[k]. The signal BK is sometimes referred to as a backup signal.

[0056] The signals RE[1] to RE[k] are signals for controlling the loading (also referred to as regeneration, restoration, or reconstruction) of data held by any one of the data holding circuits 130[1] to 130[k]. By loading the data, the data held by any one of the data holding circuits 130[1] to 130[k] is held in the flip-flop 122 in the scan flip-flop 120. The signal RE is sometimes referred to as a restoration signal.

[0057] The signal SE is a switching signal of the selector 121. The clock signal CLK is a signal for operating the flip-flop 122.

[0058] The register 110 holds data input from the terminal D or data input from the terminal SD of the scan flip-flop 120 in the scan flip-flop 120, and outputs the data from the terminal Q according to the clock signal CLK. The data of the scan flip-flop 120 output from the terminal Q is stored in any one of the data holding circuits 130[1] to 130[k]. The data of any one of the data holding circuits 130[1] to 130[k] is loaded from the terminal SD of the scan flip-flop 120.

[0059] The data holding circuits 130 [ 1 ] to 130 [ k ] can independently store or load data. In other words, the scan flip-flops 120 in multiple states generated by task switching can be stored in the data holding circuits 130 [ 1 ] to 130 [ k ] respectively.

[0060] The scan trigger 120 may be formed of Si transistors. The scan trigger 120 may be provided in the element layer 20. The data holding circuits 130[1] to 130[k] may be formed of OS transistors and capacitors. The data holding circuits 130[1] to 130[k] may be provided in each layer of the element layers 30[1] to 30[k] including OS transistors.

[0061] The selector 121 has a function of transmitting a signal from the terminal D or the terminal SD to the scan flip-flop 120 according to the signal SE. The terminal D supplies data input from outside the register 110. The terminal SD supplies: data input from any one of the data holding circuits 130[1] to 130[k]; or data input from the terminal SD_IN that supplies scan trial data. The data input from the terminal SD_IN is supplied through the transistor 132 whose conduction state or non-conduction state is controlled by the signal BK[0].

[0062] exist Figure 2A In the figure, a D flip-flop is shown as the flip-flop 122, but the present invention is not limited to this. A flip-flop prepared in a standard circuit library can be applied. The transistor of the flip-flop 122 is a Si transistor, and a circuit such as an inverting loop can hold a data. The flip-flop 122 holds the input terminal D according to the clock signal CLK. F The data is stored in the output terminal Q F Output to terminal Q.

[0063] As described above, the data holding circuits 130[1] to 130[k] are provided in each of the element layers 30[1] to 30[k] on the element layer 20 provided with the scan trigger 120. By adopting this structure, a plurality of data holding circuits 130 can be provided in the region where the scan trigger 120 is formed, and thus even if a plurality of data holding circuits 130 are assembled in the register 110, the area overhead of the register 110 can preferably be zero.

[0064] Furthermore, since the data holding circuits 130[1] to 130[k] have an overlapping area with the scan flip-flop 120, the distance between the scan flip-flop 120 and the data holding circuits 130[1] to 130[k] electrically connected to the scan flip-flop 120 can be shortened. Therefore, the wiring can have a structure that suppresses power consumption required for charging and discharging.

[0065] The data holding circuits 130[1] to 130[k] each include a transistor 133, a transistor 134, and a capacitor 135. The other electrode of the capacitor 135 is connected to the wiring CL. The transistor 133 is provided between the capacitor 135 and the terminal Q. The transistor 134 is provided between the capacitor 135 and the terminal SD. Nodes SN[1] to SN[k] represent one electrode of the capacitor 135 of each of the plurality of data holding circuits 130[1] to 130[k].

[0066] Transistors 133 and 134 are OS transistors. Transistors 133 and 134 have a back gate structure. By supplying a constant voltage to the back gates of transistors 133 and 134, the transistor characteristics can be controlled. Since the OS transistor is characterized by an extremely small off-state current, the voltage drop of nodes SN[1] to SN[k] can be suppressed, and there is almost no power consumption when retaining data, so the data retention circuits 130[1] to 130[k] each have non-volatility. The data is rewritten by charging and discharging the capacitor 135, so that the data retention circuits 130[1] to 130[k] are not limited in the number of rewrites in principle, and data can be written and read with low energy.

[0067] When all transistors of the data holding circuits 130[1] to 130[k] are OS transistors, as shown in FIG. Figure 2B As shown in FIG. 1 , a data holding circuit 130 may be stacked on a scan flip-flop 120 formed of a silicon CMOS circuit. Figure 2B In the embodiment of the present invention, the transistor 132 is provided in the same layer as the transistor 133 and the transistor 134. The transistor 132 is not limited to an OS transistor. As the transistor 132, an OS transistor or a Si transistor can be used.

[0068] Compared to the scan trigger 120, the number of elements in the data holding circuits 130[1] to 130[k] is very small, so there is no need to change the circuit structure and layout of the scan trigger 120 in order to stack the data holding circuits 130[1] to 130[k]. In other words, the versatility of the data holding circuits 130[1] to 130[k] is very high. In addition, because the data holding circuits 130[1] to 130[k] can be set in the area where the scan trigger 120 is formed, even if a plurality of data holding circuits 130[1] to 130[k] are assembled, the area overhead can be zero. The energy required to hold data in the data holding circuits 130[1] to 130[k] is small, so data can be saved or loaded frequently in the computing device 100.

[0069] By providing the data holding circuits 130[1] to 130[k], although the parasitic capacitance generated by the transistor 133 is added to the node Q, it is smaller than the parasitic capacitance generated by the logic circuit connected to the node Q, and thus does not affect the operation of the scan flip-flop 120. In other words, even if a plurality of data holding circuits 130[1] to 130[k] are provided, the performance of the register 110 is not substantially degraded.

[0070] In the data holding circuits 130[1] to 130[k], the OS transistor is used as a switch. In the OS transistor, which is an n-channel transistor, by setting the signal supplied to the gate to a high level (hereinafter indicated as = "H"), the source and the drain can be turned on (on), and by setting the signal supplied to the gate to a low level (hereinafter indicated as = "L"), the source and the drain can be turned off (off). In addition, in the selector 121, by setting the signal SE to a high level (hereinafter indicated as = "H"), the signal of the terminal SD is selected, and by setting the signal SE to a low level (hereinafter indicated as = "L"), the signal of the terminal D is selected.

[0071] For example, in the data holding circuits 130[1] to 130[k], by setting the signal BK[1] to "H", the data held by the flip-flop 122 can be written to the node SN[1] of the data holding circuit 130[1]. Similarly, by setting BK[2] to "H", BK[3] to "H", and BK[4] to "H", the data of the flip-flop 122 can be written to the nodes SN[2], SN[3], and SN[4] of the data holding circuits 130[2] to 130[4], respectively. In addition, by setting RE[1] to "H" and SE to "H", the data of the node SN[1] of the data holding circuit 130[1] can be written back to the flip-flop 122. Similarly, by setting RE[2] = "H", RE[3] = "H", and RE[4] = "H", the data of nodes SN[2], node SN[3], and node SN[4] of data holding circuits 130[2] to 130[4] can be written back to trigger 122 respectively.

[0072] For illustration purposes only Figure 2A To explain the operation of register 110, Figure 3A FIG. 2 shows a structure when the number of data holding circuits 130 is four, that is, k=4. Figure 3A , nodes SN[1] to SN[4] that hold data in the data holding circuit 130 (data holding circuits 130[1] to 130[4]) included in the data holding circuit 130 are shown. Figure 3A, signals BK[1] to BK[4] and signals RE[1] to RE[4] that control data holding circuits 130[1] to 130[4] are shown.

[0073] Figure 3B Show instructions Figure 3A An example of a timing diagram of the operation of the register 110 is shown. Figure 3B In , T0 to T7 represent time. Figure 3B , a clock signal CLK, a terminal D, a terminal Q, a signal BK[1], a signal BK[2], a signal RE[1], a signal RE[2], a node SN[1], a node SN[2], and a signal SE supplied to the selector 121 are shown. The flip-flop 122 stores the input terminal D in synchronization with the rising edge of the clock signal CLK (the waveform converted from the L level to the H level). F The data is output from the output terminal Q F Output the data.

[0074] also, FIG. 4A to FIG. 4E It is used to illustrate Figure 3B A schematic diagram of the operation of register 110 is shown in the timing diagram. Figure 4A Scan trigger 120 and data holding circuits 130[1] to 130[4] are shown. Figure 4B , Figure 4C , Figure 4D as well as Figure 4E Show Figure 3B The data at times T1, T3, T5, and T7 are input and output to the scan flip-flop 120 and the data holding circuits 130[1] to 130[4].

[0075] At time T0, in synchronization with the rising edge of the clock signal CLK, the scan flip-flop 120 stores the data D0 and outputs the data from the output terminal Q F The data D0 is output. The terminal D is supplied with data D1.

[0076] At time T1, in synchronization with the rising edge of the clock signal CLK, the scan flip-flop 120 stores the data D1 supplied to the terminal D and outputs the data D1 from the output terminal Q F The data D1 is output. At time T1, the data D1 of the scan flip-flop 120 is held in the data holding circuit 130[1] by setting the signal BK[1] = "H", the signal RE[1] = "L", and the signal SE = "L" (see Figure 4B ). Terminal D is supplied with data D2.

[0077] At time T2, in synchronization with the rising edge of the clock signal CLK, the scan flip-flop 120 stores the data D2 supplied to the terminal D and outputs the data D2 from the output terminal Q FThe data D2 is outputted. The terminal D is supplied with data D3.

[0078] At time T3, in synchronization with the rising edge of the clock signal CLK, the scan flip-flop 120 stores the data D3 supplied to the terminal D and outputs the data D3 from the output terminal Q F The data D3 is output. At time T3, the data D3 of the scan flip-flop 120 is held in the data holding circuit 130[2] by setting the signal BK[2] = "H", the signal RE[2] = "L", and the signal SE = "L" (see Figure 4C ). Terminal D is supplied with data D4.

[0079] At time T4, in synchronization with the rising edge of the clock signal CLK, the scan flip-flop 120 stores the data D4 supplied to the terminal D and outputs the data D4 from the output terminal Q F The data D4 is output. The terminal D is supplied with data D5.

[0080] At time T5, in synchronization with the rising edge of the clock signal CLK, the scan flip-flop 120 stores the data D5 supplied to the terminal D and outputs the data D5 from the output terminal Q. F At time T5, by setting BK[1] = "L", RE[1] = "H", and SE = "H", the data D1 held by the data holding circuit 130[1] can be written back to the scan flip-flop 120 (see Figure 4D ). Terminal D is supplied with data D6.

[0081] At time T6, in synchronization with the rising edge of the clock signal CLK, the scan flip-flop 120 stores the data D6 supplied to the terminal D and outputs the data D6 from the output terminal Q F The data D6 is output. The terminal D is supplied with data D7.

[0082] At time T7, in synchronization with the rising edge of the clock signal CLK, the scan flip-flop 120 stores the data D7 supplied to the terminal D and outputs the data D7 from the output terminal Q. F At time T7, by setting BK[2] = "L", RE[2] = "H", and SE = "H", the data D3 held by the data holding circuit 130[2] can be written back to the scan flip-flop 120 (see Figure 4E ). Terminal D is supplied with data D8.

[0083] As reference Figure 3B and FIG. 4B to FIG. 4EAs described above, the data of the interrupted task can be saved and the data of the restarted task can be loaded. In one embodiment of the present invention, the data saved according to the switching of the tasks can be stored in a plurality of data holding circuits. By adopting this structure, the data can be saved and loaded according to the switching of the plurality of tasks when the plug signal is input, so that the program processing can be executed sequentially. Therefore, the data processing can be performed more efficiently.

[0084] Figure 5 is to use Figure 3A The register 110 shown and the reference Figure 3B The following is a timing diagram of the operation of the register 110 for explaining the operation of task switching.

[0085] At time Ta, the data of the scan flip-flop 120 is stored in the data holding circuit 130[1] (saved in 130[1]) while the computing device 100 is executing task 1, and then the data of the data holding circuit 130[2] is written back to the scan flip-flop 120 (loaded from 130[2]). In this way, the state of task 1 is saved, and task 1 is switched to task 2 while task 2 is executable.

[0086] At time Tb, while the computing device 100 is executing task 2, the data of the scan flip-flop 120 is stored in the data holding circuit 130[2] (saved in 130[2]), and then the data of the data holding circuit 130[3] is written back to the scan flip-flop 120 (loaded from 130[3]). In this way, the state of task 2 is saved, and task 2 is switched to task 3 in a state where task 3 can be executed.

[0087] At time Tc, the data of the scan flip-flop 120 is stored in the data holding circuit 130[3] (saved in 130[3]) while the computing device 100 is executing task 3, and then the data of the data holding circuit 130[1] is written back to the scan flip-flop 120 (loaded from 130[1]). Here, the data written back to the scan flip-flop 120 from the data holding circuit 130[1] is the data stored from the scan flip-flop 120 to the data holding circuit 130[1] at time Ta. That is, the execution of task 1 up to time Ta can be restarted. In this way, the state of task 3 is saved, and task 3 is switched to task 3 while task 1 is executable.

[0088] The above structure can provide a semiconductor device including a computing device that can set a large number of registers to reduce power consumption. In addition, when switching tasks, the processing of the previous task can be restarted, thereby providing a semiconductor device including a computing device with improved computing performance.

[0089] The computing device with registers included in the semiconductor device of this embodiment can restart the processing of the original task based on the interrupted data even if another task is inserted and another task is inserted during the program processing according to the task. Because the data for restarting the processing of the task is held in the register in the computing device, it is not necessary to access the stacking area of ​​the external memory such as SRAM or DRAM to save or load the data. Therefore, even if the processing is switched from the current task to a different task due to the task insertion, the processing of saving or loading the data accompanying the switching task can be efficiently performed without causing delays such as memory access.

[0090] <Configuration Example of Storage Circuit 210 and Layer Selection Circuits 220 and 230> Fig. 6A and Figure 6B 2 is a schematic diagram for explaining a configuration example of a storage circuit 210 and layer selection circuits 220 and 230 included in a computing device 200 according to one embodiment of the present invention. Fig. 7A and Figure 7B 2 is a diagram for explaining a configuration example of a storage unit included in the storage circuit 210. FIG. 8A to FIG. 8C 1 and 2 are diagrams for explaining a circuit configuration example and an operation example of the layer selection circuits 220 and 230. Note that in the following description, for ease of understanding, the number of element layers 30[1] to 30[k] is four, that is, k=4.

[0091] like Fig. 6A As shown, a plurality of blocks are shown as the storage circuit 210. Note that Fig. 6A In one example, four stacked blocks (blocks of stacked memory circuits 210 [1] to 210 [4]) correspond to the memory circuit 210. In addition, Fig. 6A The four stacked blocks are shown arranged four side by side in the X direction.

[0092] The memory circuits 210[1] to 210[4] of each element layer each include a plurality of memory cells MC provided in the element layers 30[1] to 30[4] (see Figure 6B ).

[0093] As the memory cell MC, a memory cell including an OS transistor can be used. For example, Fig. 7A The circuit structure example of NOSRAM is shown. Fig. 7A The illustrated memory cell MC exemplifies a NOSRAM including transistors M1 to M3 and a capacitor C.

[0094] Fig. 7AWiring WWL, wiring RWL, wiring WBL, wiring RBL, and wiring PL connected to the elements possessed by the memory cell MC are shown. Wiring WWL is used as a wiring for a write word line. Wiring RWL is used as a wiring for a read word line. Wiring WBL is used as a wiring for a write bit line. Wiring RBL is used as a wiring for a read bit line. Wiring PL is used as a wiring for a capacitor line. Wiring PL can be used as a wiring for transmitting a potential supplied to the back gate of the transistor M1.

[0095] like Figure 7B As shown, about Fig. 7A The memory cells MC shown are arranged in the Y direction in the stacked element layers 30[1] to 30[4], and are electrically connected to the same wiring WBL and wiring RBL. Figure 7B FIG. 1 is a schematic diagram of a stacked memory cell MC as a NOSRAM including an OS transistor. By stacking the memory cells MC side by side, it is possible to realize Fig. 6A The memory circuit 210 shown is a stacked memory circuit 210 [ 1 ] to 210 [ 4 ] .

[0096] like Figure 6B and Figure 7B As shown, the memory cells MC included in each of the memory circuits 210[1] to 210[4] are arranged in the same layer as the layer selection circuits 220 and 230 included in each of the element layers 30[1] to 30[4]. Fig. 6A , Figure 6B and Figure 7B In the figure, the layer selection circuits 220 and 230 provided in the element layers 30 [ 1 ] to 30 [ 4 ] are referred to as layer selection circuits 220 [ 1 ] to 220 [ 4 ] and 230 [ 1 ] to 230 [ 4 ].

[0097] like Fig. 6A As shown, the computing device 200 includes a write word line driver 221, a read word line driver 231, and a computing circuit 211. Note that Figure 6B The figure shows that a write word line driver 221, a read word line driver 231, and an operation circuit 211 are provided in the element layer 20. Figure 6B The diagram shows a state where layer selection circuits 220 [ 1 ] to 220 [ 4 ] and 230 [ 1 ] to 230 [ 4 ] are provided in element layers 30 [ 1 ] to 30 [ 4 ].

[0098] In the layer selection circuits 220[1] to 220[4], the signals output to the wirings WWLout[1] to WWLout[4] are controlled by controlling the signals output to the wirings WWLin by the write word line driver 221. The wirings WWLout[1] to WWLout[4] correspond to the wirings WWL connected to the memory cells MC provided in the element layers 30[1] to 30[4]. The signals output to the wirings WWLout[1] to WWLout[4] are signals for controlling the writing of data signals from the wirings WBL extending in the Z direction to the memory cells MC. Fig. 6A and Figure 6B As shown, the layer selection circuits 220 [ 1 ] to 220 [ 4 ] may be arranged in an overlapping manner in the Z direction.

[0099] In the layer selection circuits 230[1] to 230[4], the signals output to the wirings RWLout[1] to RWLout[4] are controlled by controlling the signals output to the wirings RWLin by the read word line driving unit 231. The wirings RWLout[1] to RWLout[4] correspond to the wirings RWL connected to the memory cells MC provided in the element layers 30[1] to 30[4]. The signals output to the wirings RWLout[1] to RWLout[4] are signals for controlling the reading of data signals from the wirings RBL extending in the Z direction to the memory cells MC. Fig. 6A , Figure 6B and Figure 7B As shown, the layer selection circuits 230 [ 1 ] to 230 [ 4 ] may be arranged in an overlapping manner in the Z direction.

[0100] Fig. 8A 2 is a circuit diagram for explaining an example of a circuit structure that can be used for the layer selection circuits 220 and 230. The layer selection circuits 220 and 230 include transistors ML1, ML2, and ML3. Like the transistors included in the memory cell MC, the transistors ML1 to ML3 are OS transistors provided in the stacked element layers 30[1] to 30[4].

[0101] The gate of transistor ML2 is electrically connected to one of the source and drain of transistor ML1. One of the source and drain of transistor ML2 is electrically connected to one of the source and drain of transistor ML3 and wiring WWLout or wiring RWLout (WWLout / RWLout in the drawings) corresponding to wiring WWL or wiring RWL provided in element layers 30[1] to 30[4]. The other of the source and drain of transistor ML2 is electrically connected to wiring WWLin or wiring RWLin (WWLin or RWLin in the drawings) connected to write word line driver 221 or read word line driver 231. The other of the source and drain of transistor ML1 is electrically connected to wiring supplied with potential VLD (high power supply potential). The gate of transistor ML1 is electrically connected to wiring supplied with signal LSEL. The gate of transistor ML3 is electrically connected to wiring supplied with signal LSELB. The other of the source and drain of transistor ML3 is electrically connected to wiring supplied with potential VLS (low power supply potential). In addition, a region electrically connecting the gate of the transistor ML2 and one of the source and the drain of the transistor ML1 is sometimes referred to as a node FN1.

[0102] Figure 8C A structural example of a plurality of memory cells MC connected to the layer selection circuits 220 and 230 via the wiring WWL and the wiring RWL is shown. Figure 8C The plurality of memory cells MC shown are simultaneously selected by signals output from the layer selection circuits 220 and 230. Therefore, by controlling the output signals of the layer selection circuits 220 and 230, data can be written and read from the memory circuits 210 provided in the respective element layers 30 simultaneously.

[0103] Note that the structure of the layer selection circuits 220 and 230 is not limited to Fig. 8A For example, a capacitor may be provided between the gate of the transistor ML2 and one of the source and the drain of the transistor ML1.

[0104] The layer selection circuits 220 and 230 have a function of outputting any one of the signal and the potential VLS supplied to the wiring WWLin or the wiring RWLin to the wiring WWLout or the wiring RWLout in accordance with the signal LSEL and the signal LSELB.

[0105] Figure 8B 2 is a timing chart for explaining an example of the operation of the layer selection circuits 220 and 230.

[0106] Figure 8BThe timing chart shows the potential (H level or L level) of the signal LSEL, the signal LSELB, and the signal supplied to the wiring WWLin or the wiring RWLin at each operation time, and also shows the potential change of each of the node FN1 and the wiring WWLout or the wiring RWLout.

[0107] Note that in the following description of the operation example, the potential VLD is a potential equal to the H level of the signal LSEL and the signal LSELB, and the potential VLS is a potential equal to the L level of the signal LSEL and the signal LSELB.

[0108] Immediately before entering time TL1, the signal LSEL is set to L level and the signal LSELB is set to H level. At this time, since the transistor ML1 is in the on state, the potential of the node FN1 becomes L level. Therefore, the transistor ML2 is in the non-conductive state and the transistor ML3 is in the on state. Therefore, regardless of whether the signal supplied to the wiring WWLin or the wiring RWLin is at the H level or the L level, the potential of the wiring WWLout or the wiring RWLout becomes L level (potential VLS).

[0109] At time TL1, the signal LSEL becomes H level, and the signal LSELB becomes L level. At this time, the potential of the node FN1 rises to a potential obtained by subtracting the threshold voltage of the transistor ML1 from the H level (potential VLD), and the transistor ML1 becomes non-conductive. As a result, the transistor ML2 becomes conductive, and the transistor ML3 becomes non-conductive. Therefore, the potential of the wiring WWLout or the wiring RWLout becomes L level (the signal supplied to the wiring WWLin or the wiring RWLin at time TL1).

[0110] At time TL2, the signal supplied to the wiring WWLin or the wiring RWLin becomes H level. As a result, a current flows from the wiring WWLin or the wiring RWLin to the wiring WWLout or the wiring RWLout through the transistor ML2, thereby increasing the potential of the wiring WWLout or the wiring RWLout. At this time, since the transistor ML1 is in a non-conducting state, the capacitive coupling of the gate capacitance of the transistor ML2 causes the potential of the node FN1 to increase. Therefore, the potential difference between the gate and the source of the transistor ML2 is maintained, that is, the conductive state of the transistor ML2 is maintained. Therefore, the potential of the wiring WWLout or the wiring RWLout becomes H level (the signal supplied to the wiring WWLin or the wiring RWLin at time TL2).

[0111] In this way, in the layer selection circuits 220 and 230, by configuring a bootstrap circuit in which a gate capacitance is provided between the gate and the source of the transistor ML2, when the signal supplied to the wiring WWLin or the wiring RWLin becomes an H level, the on state of the transistor ML2 is maintained, and an H level can be output to the wiring WWLout or the wiring RWLout. Note that the gate capacitance of the transistor ML2 is sometimes referred to as a "bootstrap capacitance".

[0112] In the computing device 200, by controlling the signal LSEL and the signal LSELB supplied to the layer selection circuits 220[1] to 220[4] or the layer selection circuits 230[1] to 230[4], any one of the storage circuits 210[1] to 210[4] can be selected and the signal supplied to the wiring WWLin or the wiring RWLin can be output to the wiring WWLout or the wiring RWLout.

[0113] For example, when the signal LSEL and the signal LSELB supplied to the layer selection circuit 220[1] are set to the H level and the L level, respectively, and the signal LSEL and the signal LSELB supplied to the layer selection circuits 220[2] to 220[4] are set to the L level and the H level, respectively, the signal supplied from the write word line driver 221 to the wiring WWLin is output to the wiring WWLout[1] through the layer selection circuit 220[1].

[0114] In the computing device 200, it is necessary to provide wiring used as a word line for each of the element layer 20 and the element layers 30[1] to 30[4], but the number of wirings can be reduced by adopting a structure in which a layer selection circuit is provided in each element layer. In addition, the computing device 200 can suppress the increase in the area of ​​the write word line driver 221 and the read word line driver 231 caused by the increase in the number of layers of the element layers 30[1] to 30[4]. That is, the computing device 200 can increase the number of layers of the element layers 30[1] to 30[4] provided with the storage circuit without increasing the area overhead, thereby improving the density of the storage cell MC (memory density).

[0115] Next, a structural example of the operation circuit 211 is described. The operation circuit 211 has a function of performing a product-sum operation. The operation device 200 including the operation circuit 211 is sometimes called an accelerator or a GPU (Graphics Processing Unit). A memory cell MC such as NOSRAM or DOSRAM can be stacked on the operation circuit 211. That is, on the substrate provided with the element layer 20 including Si transistors, a layer including OS transistors can be stacked in the vertical direction.

[0116] For example, the arithmetic circuit 211 can perform parallel processing of row and column operations in graphic processing, parallel processing of product-sum operations in neural networks, parallel processing of floating-point operations in scientific and technological calculations, and the like.

[0117] For example, Fig. 9 The memory cells MC[1] to MC[4] shown in the figure can use a memory cell including an OS transistor such as NOSRAM. Fig. 9 The circuit structure of the memory cells MC[1] to MC[4] shown is equivalent to a NOSRAM of a three-transistor (3T) gain unit. NOSRAM can be used as a nonvolatile memory by retaining the charge corresponding to the data in the memory cell using the characteristic of extremely small leakage current.

[0118] For example, Fig. 9 The illustrated operation circuit 211 includes a readout circuit 241 to which a signal of the wiring RBL is supplied, a bit product sum operator 242 , an accumulator 243 , a latch circuit 244 , and an encoding circuit 245 which outputs an output signal Q.

[0119] Each circuit constituting the operation circuit 211 includes Si transistors and can be provided in the element layer 20. The memory cell MC includes OS transistors and can be provided in the element layers 30[1] to 30[4]. Fig. 7A , Figure 7B As shown, the element layer 20 and the element layers 30[1] to 30[4] can be stacked in such a manner that the regions where the circuits are provided overlap. The wiring RBL connecting the operation circuit 211 and the memory cell MC is provided in a direction (z direction) perpendicular to the surface of the substrate where the element layer 20 is provided. The wiring RWL can be provided in an opening in the insulating layer and can be micro-processed. Therefore, compared with wiring using silicon through-hole electrodes, etc., the wiring RWL can reduce parasitic capacitance. As a result, the power consumption required for charging and discharging the wiring can be reduced, thereby achieving low power consumption.

[0120] By adopting Fig. 9 The circuit structure shown as a special product-sum operation can reduce the circuit area, thereby achieving low power consumption by miniaturizing the circuit area.

[0121] FIG. 10A to FIG. 10C This is a schematic diagram for explaining a structure in which the memory circuit 210 provided in each of the plurality of element layers 30 [ 1 ] to 30 [ 4 ] stores different data and the data is read or written by switching the layer selection circuit.

[0122] In the memory circuit 210 , the data stored in each element layer 30 is weight data used for the product-sum operation. Fig. 10AThe memory circuit 210 [ 1 ] included in the first-layer element layer 30 [ 1 ] stores weight data NN1 . Fig. 10A The figure shows how the storage circuit 210 [ 2 ] included in the second-layer element layer 30 [ 2 ] stores weight data NN2 . Fig. 10A The figure shows how the storage circuit 210 [ 3 ] included in the third-layer element layer 30 [ 3 ] stores weight data NN3 . Fig. 10A The memory circuit 210 [ 4 ] included in the fourth-layer element layer 30 [ 4 ] is shown storing weight data NN4 .

[0123] By performing switching control using the layer selection circuit 220, the data group of weight data stored in the storage circuits 210[1] to 210[4] is written from the operation circuit 211 to the storage cell MC of the storage circuit 210. In addition, by performing switching control using the layer selection circuit 230, the weight data is read from the storage cell MC of the storage circuit 210 to the operation circuit 211.

[0124] For example, in Fig. 10B In the embodiment, the weight data NN2 of the storage circuit 210[2] can be updated by controlling the layer selection circuit 220 in such a way as to output a signal to the wiring WWLout[2]. Fig. 10B In the example, by controlling the layer selection circuit 230 to output a signal to the wiring RWLout[1], the weight data NN1 of the storage circuit 210[1] can be read to the operation circuit 211.

[0125] In addition, Fig. 10C In the embodiment, the weight data NN1 of the storage circuit 210[1] can be updated by controlling the layer selection circuit 220 in such a way that a signal is output to the wiring WWLout[1]. Fig. 10C In the example, by controlling the layer selection circuit 230 to output a signal to the wiring RWLout[4], the weight data NN4 of the storage circuit 210[4] can be read out to the operation circuit 211.

[0126] like Fig. 10B , Fig. 10C As shown, by controlling the layer selection circuits 220 and 230, the weight data can be written and read to different storage circuits 210. That is, by having such a structure, in the operation processing imitating the neural network, the switching order of the weight data can be executed by switching the layer selection circuits 220 and 230.

[0127] Fig.116 and 6 . 6 is a timing chart for explaining the simultaneous execution of the switching of tasks in the computing device 100 and the switching of weight data in the computing process imitating the neural network in the computing device 200 .

[0128] At time Ta, the computing device 100 stores the data of the scan trigger 120 in the data holding circuit 130[1] (saves to 130[1]) while executing task 1, and then writes the data of the data holding circuit 130[2] back to the scan trigger 120 (loads from 130[2]). In this way, the state of task 1 is saved, and task 1 is switched to task 2 in the state where task 2 can be executed. At the same time, the computing device 200 reads the weight data NN2 from the storage unit of the storage circuit 210[2], and switches the computing process based on the first neural network to the computing process based on the second neural network.

[0129] At time Tb, while the computing device 100 is executing task 2, the data of the scan trigger 120 is stored in the data holding circuit 130[2] (saved in 130[2]), and then the data of the data holding circuit 130[3] is written back to the scan trigger 120 (loaded from 130[3]). In this way, the state of task 2 is saved, and task 2 is switched to task 3 in the state where task 3 can be executed. At the same time, the computing device 200 reads the weight data NN3 from the storage unit of the storage circuit 210[3], and switches the computing process based on the second neural network to the computing process based on the third neural network.

[0130] At time Tc, while the computing device 100 is executing Task 3, the data of the scan trigger 120 is stored in the data holding circuit 130[3] (saved in 130[3]), and then the data of the data holding circuit 130[1] is written back to the scan trigger 120 (loaded from 130[1]). Here, the data written back from the data holding circuit 130[1] to the scan trigger 120 is the data stored from the scan trigger 120 to the data holding circuit 130[1] at time Ta. That is, the execution of Task 1 until time Ta can be restarted. In this way, the state of Task 3 is saved, and Task 3 is switched to Task 3 while Task 1 is executable. At the same time, the computing device 200 reads out the weight data NN1 from the storage unit of the storage circuit 210[1], and switches the operation processing based on the third neural network to the operation processing based on the first neural network.

[0131] For example, the first neural network performs number recognition, thereby realizing a structure for performing number recognition as a first task. In addition, the second neural network performs animal recognition, thereby realizing a structure for confirming the presence of a pet as a second task. In addition, the third neural network performs vehicle recognition, thereby realizing a structure for confirming the presence or absence of a visitor as a third task.

[0132] The above structure can provide a semiconductor device that can set a large number of registers to reduce power consumption. In addition, when switching tasks, the processing of the previous task can be restarted, thereby providing a semiconductor device with improved computing performance. In addition, a semiconductor device that supports multiple neural networks and has improved computing performance can be provided.

[0133] This embodiment mode can be implemented in combination with other embodiment modes described in this specification as appropriate.

[0134] (Implementation Method 2) In this embodiment, a transistor structure applicable to the semiconductor device described in the above embodiment is described. As an example, a structure in which transistors having different electrical characteristics are stacked is described. By adopting this structure, the degree of freedom in designing the semiconductor device can be increased. In addition, by stacking transistors having different electrical characteristics, the integration of the semiconductor device can be increased.

[0135] Fig.12 A partial cross-sectional structure of a semiconductor device is shown. Fig.12 The semiconductor device shown includes a transistor 550 , a transistor 500 , and a capacitor 600 . Fig.13A is a cross-sectional view of the transistor 500 in the channel length direction, Fig. 13B is a cross-sectional view of the transistor 500 in the channel width direction, Fig. 13C 2 is a cross-sectional view in the channel width direction of the transistor 550. For example, the transistor 500 corresponds to the Si transistor described in the above embodiment, and the transistor 550 corresponds to the OS transistor.

[0136] exist Fig.12 In the embodiment, the transistor 500 is disposed above the transistor 550 , and the capacitor 600 is disposed above the transistor 550 and the transistor 500 .

[0137] The transistor 550 is provided on a substrate 311 and includes a conductor 316, an insulator 315, a semiconductor region 313 formed of a portion of the substrate 311, and a low resistance region 314a and a low resistance region 314b functioning as a source region or a drain region.

[0138] like Fig. 13C As shown, in the transistor 550, the conductor 316 covers the top surface and the side surface in the channel width direction of the semiconductor region 313 via the insulator 315. In this way, by making the transistor 550 have a Fin-type structure, the effective channel width increases, thereby improving the on-state characteristics of the transistor 550. In addition, since the effect of the electric field of the gate electrode can be enhanced, the off-state characteristics of the transistor 550 can be improved.

[0139] Furthermore, transistor 550 may be either a p-channel transistor or an n-channel transistor.

[0140] The channel formation region of the semiconductor region 313 or the region near it, the low resistance region 314a and the low resistance region 314b used as the source region or the drain region preferably include semiconductors such as silicon-based semiconductors, and more preferably include single crystal silicon. In addition, it can also be formed using materials including Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenic), etc. Silicon that controls the effective mass by subjecting the lattice to stress to change the interplanar spacing can be used. In addition, the transistor 550 can also be a HEMT (High Electron Mobility Transistor) using GaAs and GaAlAs, etc.

[0141] The low resistance regions 314 a and 314 b contain, in addition to the semiconductor material used for the semiconductor region 313 , an element imparting n-type conductivity such as arsenic and phosphorus or an element imparting p-type conductivity such as boron.

[0142] As the conductor 316 serving as the gate electrode, a conductive material such as a semiconductor material such as silicon, a metal material, an alloy material, or a metal oxide material containing an element imparting n-type conductivity such as arsenic and phosphorus or an element imparting p-type conductivity such as boron can be used.

[0143] In addition, since the material of the conductor determines the work function, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, materials such as titanium nitride or tantalum nitride are preferably used as the conductor. In order to have both conductivity and embeddability, a stack of metal materials such as tungsten or aluminum is preferably used as the conductor, and tungsten is particularly preferred in terms of heat resistance.

[0144] Alternatively, the transistor 550 may be formed using a SOI (Silicon on Insulator) substrate or the like.

[0145] In addition, as SOI substrates, there can be used: SIMOX (Separation by Implanted Oxygen) substrates formed by forming an oxide layer in a region at a certain depth from the surface and eliminating defects generated in the surface layer after oxygen ion implantation in a mirror-polished thin slice, and SOI substrates formed by the smart peeling method or ELTRAN method (registered trademark: Epitaxial Layer Transfer) in which a semiconductor substrate is split by growing tiny gaps formed by hydrogen ion implantation through heat treatment. A transistor formed using a single crystal substrate includes a single crystal semiconductor in a channel formation region.

[0146] An insulator 320 , an insulator 322 , an insulator 324 , and an insulator 326 are stacked in this order so as to cover the transistor 550 .

[0147] As the insulator 320 , the insulator 322 , the insulator 324 , and the insulator 326 , for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or aluminum nitride can be used.

[0148] Note that in this specification, silicon oxynitride refers to a material containing more oxygen than nitrogen in its composition, and silicon nitride oxide refers to a material containing more nitrogen than oxygen in its composition. Note that in this specification, aluminum oxynitride refers to a material containing more oxygen than nitrogen, and aluminum nitride oxide refers to a material containing more nitrogen than oxygen.

[0149] The insulator 322 may also be used as a planarization film for planarizing a step caused by the transistor 550 disposed thereunder, etc. For example, in order to improve the planarity of the top surface of the insulator 322, the top surface may be planarized by a planarization process such as chemical mechanical polishing (CMP).

[0150] As the insulator 324 , a film having a barrier property that can prevent hydrogen, impurities, and the like from diffusing from the substrate 311 , the transistor 550 , or the like into a region where the transistor 500 is provided is preferably used.

[0151] As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by a CVD method can be used. Here, hydrogen sometimes diffuses into a semiconductor element having an oxide semiconductor such as transistor 500, resulting in a decrease in the characteristics of the semiconductor element. Therefore, it is preferred to provide a film that inhibits the diffusion of hydrogen between transistor 500 and transistor 550. Specifically, the film that inhibits the diffusion of hydrogen refers to a film with a small amount of hydrogen released.

[0152] The amount of hydrogen released can be measured, for example, by thermal desorption spectroscopy (TDS). For example, when the amount of hydrogen released is converted to the amount per unit area of ​​the insulator 324 when the film surface temperature in the TDS analysis is in the range of 50°C to 500°C, the amount of hydrogen released from the insulator 324 is 1×10 16 atoms / cm 2 Below, preferably 5×10 15 atoms / cm 2 The following is enough.

[0153] Note that the dielectric constant of the insulator 326 is preferably lower than that of the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably lower than 4, more preferably lower than 3. For example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced.

[0154] In addition, conductors 328 and 330 connected to capacitor 600 and transistor 500 are embedded in insulators 320, 322, 324, and 326. In addition, conductors 328 and 330 have the function of plugs or wiring. Note that the same symbol is sometimes used to represent a plurality of conductors having the function of plugs or wiring. In addition, in this specification, wiring and a plug connected to wiring may also be one component. That is, a part of a conductor is sometimes used as wiring, and a part of a conductor is sometimes used as a plug.

[0155] As the material of each plug and wiring (conductor 328, conductor 330, etc.), a single layer or a laminate of a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used. It is preferred to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is preferably used. Alternatively, a low-resistance conductive material such as aluminum or copper is preferably used. By using a low-resistance conductive material, the wiring resistance can be reduced.

[0156] Alternatively, a wiring layer may be provided on the insulator 326 and the conductor 330. Fig.12 In the embodiment of the present invention, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. Furthermore, a conductor 356 is formed between the insulator 350, the insulator 352, and the insulator 354. The conductor 356 has a function of a plug or wiring connected to the transistor 550. The conductor 356 can be made of the same material as the conductor 328 and the conductor 330.

[0157] In addition, similar to the insulator 324, the insulator 350 preferably uses an insulator having a barrier property to hydrogen, for example. In addition, the conductor 356 preferably includes a conductor having a barrier property to hydrogen. In particular, the conductor having a barrier property to hydrogen is formed in the opening portion of the insulator 350 having a barrier property to hydrogen. By adopting this structure, the transistor 550 can be separated from the transistor 500 using a barrier layer, thereby suppressing the diffusion of hydrogen from the transistor 550 to the transistor 500.

[0158] Note that as a conductor having a barrier property against hydrogen, for example, tantalum nitride or the like is preferably used. Furthermore, by stacking tantalum nitride and tungsten having high conductivity, it is possible to maintain the conductivity as a wiring and suppress the diffusion of hydrogen from the transistor 550. At this time, the tantalum nitride layer having a barrier property against hydrogen is preferably in contact with the insulator 350 having a barrier property against hydrogen.

[0159] Alternatively, a wiring layer may be provided on the insulator 354 and the conductor 356. Fig.12 In the embodiment, an insulator 360, an insulator 362, and an insulator 364 are stacked in this order. In addition, a conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364. The conductor 366 has a function of a plug or wiring. In addition, the conductor 366 can use the same material as the conductor 328 and the conductor 330.

[0160] In addition, similar to the insulator 324, the insulator 360 preferably uses an insulator having a barrier property to hydrogen. In addition, the conductor 366 preferably includes a conductor having a barrier property to hydrogen. In particular, the conductor having a barrier property to hydrogen is formed in the opening portion of the insulator 360 having a barrier property to hydrogen. By adopting this structure, the transistor 550 can be separated from the transistor 500 using a barrier layer, thereby suppressing the diffusion of hydrogen from the transistor 550 to the transistor 500.

[0161] Alternatively, a wiring layer may be provided on the insulator 364 and the conductor 366. Fig.12 In the embodiment, an insulator 370, an insulator 372, and an insulator 374 are stacked in this order. In addition, a conductor 376 is formed in the insulator 370, the insulator 372, and the insulator 374. The conductor 376 has a function of a plug or wiring. In addition, the conductor 376 can use the same material as the conductor 328 and the conductor 330.

[0162] In addition, similar to the insulator 324, the insulator 370 preferably uses an insulator having a barrier property to hydrogen. In addition, the conductor 376 preferably includes a conductor having a barrier property to hydrogen. In particular, the conductor having a barrier property to hydrogen is formed in the opening portion of the insulator 370 having a barrier property to hydrogen. By adopting this structure, the transistor 550 can be separated from the transistor 500 using a barrier layer, thereby suppressing the diffusion of hydrogen from the transistor 550 to the transistor 500.

[0163] Alternatively, a wiring layer may be provided on the insulator 374 and the conductor 376. Fig.12In the embodiment, an insulator 380, an insulator 382, ​​and an insulator 384 are stacked in this order. In addition, a conductor 386 is formed in the insulator 380, the insulator 382, ​​and the insulator 384. The conductor 386 has a function of a plug or wiring. In addition, the conductor 386 can use the same material as the conductor 328 and the conductor 330.

[0164] In addition, similar to the insulator 324, the insulator 380 preferably uses an insulator having a barrier property to hydrogen. In addition, the conductor 386 preferably includes a conductor having a barrier property to hydrogen. In particular, the conductor having a barrier property to hydrogen is formed in the opening portion of the insulator 380 having a barrier property to hydrogen. By adopting this structure, the transistor 550 can be separated from the transistor 500 using a barrier layer, so that the diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0165] In the above description, the wiring layer including the conductor 356, the wiring layer including the conductor 366, the wiring layer including the conductor 376, and the wiring layer including the conductor 386 are described, but the semiconductor device according to the present embodiment is not limited thereto. The number of wiring layers similar to the wiring layer including the conductor 356 may be three or less, and the number of wiring layers similar to the wiring layer including the conductor 356 may be five or more.

[0166] An insulator 510, an insulator 512, an insulator 514, and an insulator 516 are sequentially stacked on the insulator 384. As any of the insulators 510, 512, 514, and 516, a substance having a barrier property against oxygen, hydrogen, and the like is preferably used.

[0167] For example, a film having a barrier property that prevents hydrogen, impurities, and the like from diffusing from the substrate 311 or a region where the transistor 550 is provided to a region where the transistor 500 is provided is preferably used as the insulator 510 and the insulator 514. Therefore, the insulator 510 and the insulator 514 can be made of the same material as the insulator 324.

[0168] As an example of a film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used. Here, hydrogen sometimes diffuses into a semiconductor element having an oxide semiconductor such as transistor 500, resulting in a decrease in the characteristics of the semiconductor element. Therefore, it is preferred to provide a film that inhibits the diffusion of hydrogen between transistor 550 and transistor 500.

[0169] For example, as a film having a barrier property against hydrogen, the insulator 510 and the insulator 514 are preferably made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0170] In particular, aluminum oxide has a high barrier effect of preventing oxygen and impurities such as hydrogen and moisture that cause changes in the electrical characteristics of the transistor from penetrating. Therefore, during and after the manufacturing process of the transistor, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500. In addition, aluminum oxide can suppress the release of oxygen from the oxide constituting the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0171] For example, the insulator 512 and the insulator 516 can use the same material as the insulator 320. In addition, by using a material with a low dielectric constant for the insulator, the parasitic capacitance generated between wirings can be reduced. For example, the insulator 512 and the insulator 516 can use a silicon oxide film, a silicon oxynitride film, or the like.

[0172] In addition, a conductor 518 or a conductor (for example, the conductor 503) constituting the transistor 500 is embedded in the insulator 510, the insulator 512, the insulator 514, and the insulator 516. The conductor 518 is used as a plug or wiring connected to the capacitor 600 or the transistor 550. The conductor 518 can be made of the same material as the conductor 328 and the conductor 330.

[0173] In particular, the conductor 518 in the region in contact with the insulator 510 and the insulator 514 is preferably a conductor having a barrier property to oxygen, hydrogen, and water. With this structure, the transistor 550 can be separated from the transistor 500 by a layer having a barrier property to oxygen, hydrogen, and water, thereby suppressing the diffusion of hydrogen from the transistor 550 into the transistor 500.

[0174] The transistor 500 is provided above the insulator 516 .

[0175] like Fig.13A and Fig. 13B As shown, transistor 500 includes a conductor 503 configured in a manner of embedding insulator 514 and insulator 516, an insulator 520 configured on insulator 516 and conductor 503, an insulator 522 configured on insulator 520, an insulator 524 configured on insulator 522, an oxide 530a configured on insulator 524, an oxide 530b configured on oxide 530a, a conductor 542a and a conductor 542b configured separately from each other on oxide 530b, an insulator 580 configured on conductor 542a and conductor 542b and forming an opening in a manner overlapping between conductor 542a and conductor 542b, an insulator 545 configured on the bottom and side surfaces of the opening, and a conductor 560 configured on the formation surface of insulator 545.

[0176] In addition, if Fig.13A and Fig. 13BAs shown in FIG. 5 , an insulator 544 is preferably disposed between the oxide 530a, the oxide 530b, the conductor 542a, the conductor 542b, and the insulator 580. Fig.13A and Fig. 13B As shown in FIG. 5 , the conductor 560 preferably includes a conductor 560a disposed inside the insulator 545 and a conductor 560b disposed in a manner embedded inside the conductor 560a. Fig.13A and Fig. 13B As shown, an insulator 574 is preferably arranged on the insulator 580 , the conductor 560 , and the insulator 545 .

[0177] Note that in this specification and the like, the oxide 530 a and the oxide 530 b may be collectively referred to as an oxide 530 .

[0178] In the transistor 500, two layers of oxide 530a and oxide 530b are stacked in the channel forming region and its vicinity, but the present invention is not limited thereto. For example, the oxide 530b may have a single layer structure or a stacked structure of three or more layers.

[0179] In addition, in the transistor 500, the conductor 560 has a two-layer structure, but the present invention is not limited to this. For example, the conductor 560 may also have a single-layer structure or a stacked structure of three or more layers. Note that Fig.12 and Fig.13A The structure of the transistor 500 shown is only an example and is not limited to the above structure, and an appropriate transistor can be used according to the circuit structure or driving method.

[0180] Here, the conductor 560 is used as the gate electrode of the transistor, and the conductor 542a and the conductor 542b are used as the source electrode or the drain electrode. As described above, the conductor 560 is set in a manner embedded in the opening of the insulator 580 and in the area sandwiched between the conductor 542a and the conductor 542b. The configuration of the conductor 560, the conductor 542a, and the conductor 542b is selected in a self-aligned manner according to the opening of the insulator 580. In other words, in the transistor 500, the gate electrode can be configured in a self-aligned manner between the source electrode and the drain electrode. Thus, the conductor 560 can be formed in a manner without providing room for alignment, so that the occupied area of ​​the transistor 500 can be reduced. Thus, miniaturization and high integration of semiconductor devices can be achieved.

[0181] Furthermore, since the conductor 560 is formed in a self-aligned manner in the region between the conductor 542a and the conductor 542b, the conductor 560 does not include a region overlapping with the conductor 542a or the conductor 542b. Thus, the parasitic capacitance formed between the conductor 560 and the conductors 542a and 542b can be reduced. Therefore, the switching speed of the transistor 500 can be increased, so that the transistor 500 can have high frequency characteristics.

[0182] Conductor 560 is sometimes used as a first gate (also called a top gate) electrode. Conductor 503 is sometimes used as a second gate (also called a bottom gate) electrode. In this case, the threshold voltage of transistor 500 can be controlled by independently changing the potential supplied to conductor 503 without linking it with the potential supplied to conductor 560. In particular, by supplying a negative potential to conductor 503, the threshold voltage of transistor 500 can be made to exceed 0V to reduce the off-state current. Therefore, compared with when no negative potential is applied to conductor 503, when a negative potential is applied to conductor 503, the drain current when the potential applied to conductor 560 is 0V can be reduced.

[0183] The conductor 503 is arranged to overlap the oxide 530 and the conductor 560. Therefore, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated by the conductor 560 and the electric field generated by the conductor 503 are connected to each other, and a channel formation region formed in the oxide 530 can be covered.

[0184] In this specification, etc., the structure of a transistor in which the electric field of the first gate electrode electrically surrounds the channel forming region is called a surrounded channel (S-channel) structure. In addition, the S-channel structure disclosed in this specification, etc. has a structure different from the Fin-type structure and the planar structure. On the other hand, the S-channel structure disclosed in this specification, etc. can also be regarded as a kind of Fin-type structure. In this specification, etc., the Fin-type structure refers to a structure in which the gate electrode is configured in a manner of surrounding at least two or more surfaces of the channel (specifically, two surfaces, three surfaces or four surfaces, etc.). By adopting the Fin-type structure and the S-channel structure, a transistor with improved resistance to short channel effects can be realized. In other words, a transistor that is not prone to short channel effects can be realized.

[0185] By adopting a transistor having the above-mentioned S-channel structure, the channel formation region can be electrically surrounded. In addition, the S-channel structure can also be said to be substantially equal to the GAA (Gate All Around: full surround gate) structure or the LGAA (Lateral Gate All Around: lateral full surround gate) structure because it electrically surrounds the channel formation region. By making the transistor have an S-channel structure, a GAA structure or a LGAA structure, the channel formation region formed at or near the interface between the oxide 530 and the gate insulator can be set in the entire bulk of the oxide 530. Therefore, the current density flowing through the transistor can be increased, so it can be expected that the on-state current of the transistor or the field effect mobility of the transistor can be improved.

[0186] In addition, the conductor 503 has the same structure as the conductor 518, and the conductor 503a is formed in contact with the inner wall of the opening of the insulator 514 and the insulator 516, and the conductor 503b is formed on the conductor 503a in a manner embedded in the opening. In addition, in the transistor 500, the conductor 503a and the conductor 503b are stacked, but the present invention is not limited to this. For example, the conductor 503 may have a single-layer structure or a stacked structure of three or more layers.

[0187] Here, as the conductor 503a, it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (not allowing the above impurities to pass through easily). In addition, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) (not allowing the above oxygen to pass through easily). In this specification, the function of suppressing the diffusion of impurities or oxygen refers to the function of suppressing the diffusion of any one or all of the above impurities and the above oxygen.

[0188] For example, by providing the conductor 503a with a function of suppressing the diffusion of oxygen, a decrease in conductivity due to oxidation of the conductor 503b can be suppressed.

[0189] In addition, when the conductor 503 also has a wiring function, it is preferable to use a conductive material with high conductivity whose main component is tungsten, copper or aluminum as the conductor 503b. In addition, although the conductor 503 composed of a stack of conductors 503a and 503b is shown in this embodiment, the conductor 503 may also have a single-layer structure.

[0190] The insulator 520 , the insulator 522 , and the insulator 524 are used as a second gate insulating film.

[0191] Here, the insulator 524 in contact with the oxide 530 preferably contains oxygen exceeding the stoichiometric composition. This oxygen is easily released from the film by heating. In this specification, etc., the oxygen released by heating is sometimes referred to as "excess oxygen". That is, it is preferred that a region containing excess oxygen (also referred to as "excess oxygen region") is formed in the insulator 524. By providing the insulator containing excess oxygen in contact with the oxide 530, the oxygen vacancies (V O : oxygen vacancy), thereby improving the reliability of the transistor 500. In addition, when hydrogen enters the oxygen vacancy of the oxide 530, the defect (hereinafter, sometimes referred to as V O H) is used as a donor to generate electrons as carriers. In addition, sometimes electrons as carriers are generated because part of the hydrogen is bonded to the oxygen bonded to the metal atom. Therefore, transistors using oxide semiconductors containing a large amount of hydrogen tend to have a normally-on characteristic. In addition, since hydrogen in oxide semiconductors is easily moved due to heat, electric field, etc., when oxide semiconductors contain a large amount of hydrogen, the reliability of the transistor may be reduced. In one embodiment of the present invention, it is preferred to minimize the V O H and become high purity intrinsic or substantially high purity intrinsic. In this way, in order to obtain such V O For an oxide semiconductor with sufficiently reduced H, it is important to: remove impurities such as water and hydrogen in the oxide semiconductor (sometimes referred to as dehydration or dehydrogenation treatment); and supply oxygen to the oxide semiconductor to fill oxygen vacancies (sometimes referred to as oxidation treatment). O An oxide semiconductor in which impurities such as H are sufficiently reduced is used for a channel formation region of a transistor, and can provide stable electrical characteristics.

[0192] Specifically, as an insulator having an excess oxygen region, an oxide material from which a portion of oxygen is released by heating is preferably used. An oxide from which oxygen is released by heating means that the amount of oxygen released in terms of oxygen atoms in TDS (Thermal Desorption Spectroscopy) analysis is 1.0×10 18 atoms / cm 3 Above, preferably 1.0×10 19 atoms / cm 3 More preferably, 2.0×10 19 atoms / cm 3 Above, or 3.0×10 20 atoms / cm 3Furthermore, the surface temperature of the film when performing the above-mentioned TDS analysis is preferably in the range of 100° C. to 700° C., or 100° C. to 400° C.

[0193] In addition, any one or more of heat treatment, microwave treatment, or RF treatment may be performed in such a manner that the insulator having the excess oxygen region and the oxide 530 are in contact with each other. By performing this treatment, water or hydrogen in the oxide 530 can be removed. For example, a reaction occurs in the oxide 530 in which VoH bonding is severed, in other words, a “V O H→Vo+H" reaction can be dehydrogenated. A part of the hydrogen generated at this time is sometimes bonded to oxygen and removed from the oxide 530 or the insulator near the oxide 530 as H2O. In addition, a part of the hydrogen is sometimes doped by the conductors 542a and 542b.

[0194] In addition, as the above-mentioned microwave treatment, for example, it is preferred to use a device including a power supply for generating high-density plasma or a device including a power supply for applying RF to one side of the substrate. For example, by using a gas containing oxygen and a high-density plasma, a high-density oxygen radical can be generated, and by applying RF to one side of the substrate, the oxygen radical generated by the high-density plasma can be efficiently introduced into the oxide 530 or an insulator near the oxide 530. In addition, in the above-mentioned microwave treatment, the pressure is 133 Pa or more, preferably 200 Pa or more, and more preferably 400 Pa or more. In addition, as the gas introduced into the device for performing microwave treatment, for example, oxygen and argon are used, and the oxygen flow ratio (O2 / (O2+Ar)) is 50% or less, preferably 10% or more and 30% or less.

[0195] In addition, in the manufacturing process of transistor 500, it is preferred to perform heat treatment in a state where the surface of oxide 530 is exposed. The heat treatment can be performed, for example, at a temperature of 100°C or higher and 450°C or lower, more preferably 350°C or higher and 400°C or lower. In addition, the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas or an atmosphere containing an oxidizing gas of 10 ppm or higher, 1% or higher, or 10% or higher. For example, the heat treatment is preferably performed in an oxygen atmosphere. Thus, oxygen can be supplied to oxide 530 to reduce oxygen vacancies (V O ). In addition, the heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen or an inert gas, and then the heat treatment may be performed in an atmosphere of an oxidizing gas containing 10 ppm or more, 1% or more, or 10% or more to fill the oxygen that has been separated. Alternatively, the heat treatment may be performed in an atmosphere of an oxidizing gas containing 10 ppm or more, 1% or more, or 10% or more, and then the heat treatment may be performed continuously in an atmosphere of nitrogen or an inert gas.

[0196] In addition, by performing an oxidation treatment on the oxide 530, the supplied oxygen can fill the oxygen vacancies in the oxide 530. In other words, the reaction of "Vo+O→null" can be promoted. Furthermore, by reacting the hydrogen remaining in the oxide 530 with the supplied oxygen, the hydrogen can be removed as H2O (dehydration). Thus, the hydrogen remaining in the oxide 530 can be suppressed from re-bonding with the oxygen vacancies to form V. O H.

[0197] When the insulator 524 has an excess oxygen region, the insulator 524 preferably has a function of suppressing diffusion of oxygen (for example, oxygen atoms, oxygen molecules, etc.) (making it difficult for the oxygen to permeate).

[0198] When the insulator 522 has a function of suppressing diffusion of oxygen, impurities, and the like, it is preferable because oxygen included in the oxide 530 does not diffuse toward the insulator 520. In addition, reaction between the conductor 503 and oxygen included in the insulator 524 or the oxide 530 can be suppressed.

[0199] As the insulator 522, for example, a single layer or a stack of insulators containing so-called high-k materials such as aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3) or (Ba, Sr)TiO3 (BST) is preferably used. When miniaturization and high integration of transistors are performed, problems such as off-state current sometimes occur due to the thin film of the gate insulating film. By using a high-k material as an insulator used as a gate insulating film, the gate potential when the transistor is operating can be reduced while maintaining the physical thickness.

[0200] In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium as an insulating material having a function of suppressing the diffusion of impurities and oxygen (not allowing the above oxygen to pass easily). As an insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. are preferably used. When the insulator 522 is formed using such a material, the insulator 522 is used as a layer that suppresses the release of oxygen from the oxide 530 or the entry of impurities such as hydrogen into the oxide 530 from the surrounding part of the transistor 500.

[0201] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator. In addition, the insulator may be nitrided. In addition, silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the insulator.

[0202] The insulator 520 preferably has thermal stability. For example, silicon oxide and silicon oxynitride are preferred because they have thermal stability. In addition, by combining an insulator of a high-k material with silicon oxide or silicon oxynitride, an insulator 520 having a laminated structure with thermal stability and a high relative dielectric constant can be formed.

[0203] In addition, Fig.13A and Fig. 13B In the transistor 500, the insulator 520, the insulator 522, and the insulator 524 are shown as the second gate insulating film having a three-layer stacked structure, but the second gate insulating film may also have a single-layer structure, a two-layer structure, or a stacked structure of four or more layers. In this case, the stacked structure is not limited to being made of the same material, and a stacked structure made of different materials may be used.

[0204] In the transistor 500 , a metal oxide that functions as an oxide semiconductor is used as the oxide 530 including a channel formation region.

[0205] The metal oxide used as the oxide semiconductor may be formed by a sputtering method or an ALD (Atomic Layer Deposition) method. The metal oxide used as the oxide semiconductor will be described in detail in other embodiments.

[0206] The metal oxide used as the channel formation region in the oxide 530 preferably has a band gap of 2 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0207] In the oxide 530 , when the oxide 530 a is provided below the oxide 530 b , diffusion of impurities from a structure formed below the oxide 530 a to the oxide 530 b can be suppressed.

[0208] In addition, the oxide 530 preferably has a structure of multiple oxide layers in which the atomic number ratios of the metal atoms are different from each other. Specifically, the atomic number ratio of the element M in the constituent elements of the metal oxide used for the oxide 530a is preferably greater than the atomic number ratio of the element M in the constituent elements of the metal oxide used for the oxide 530b. In addition, the atomic number ratio of the element M relative to In in the metal oxide used for the oxide 530a is preferably greater than the atomic number ratio of the element M relative to In in the metal oxide used for the oxide 530b. In addition, the atomic number ratio of In in the metal oxide used for the oxide 530b is preferably greater than the atomic number ratio of In in the metal oxide used for the oxide 530a.

[0209] It is preferred that the energy of the conduction band bottom of oxide 530a be higher than that of the conduction band bottom of oxide 530b. In other words, the electron affinity of oxide 530a is preferably lower than that of oxide 530b.

[0210] Here, in the junction of oxide 530a and oxide 530b, the energy level of the conduction band bottom changes smoothly. In other words, the above situation can also be expressed as the energy level of the conduction band bottom of the junction of oxide 530a and oxide 530b continuously changes or continuously joins. For this reason, it is preferable to reduce the defect state density of the mixed layer formed at the interface between oxide 530a and oxide 530b.

[0211] Specifically, by making the oxide 530a and the oxide 530b contain a common element (as a main component) in addition to oxygen, a mixed layer with a low defect state density can be formed. For example, when the oxide 530b is an In-Ga-Zn oxide, it is preferable to use In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide, etc. as the oxide 530a.

[0212] At this time, the main path of the carrier is oxide 530b. By making oxide 530a have the above structure, the defect state density at the interface between oxide 530a and oxide 530b can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the on-state current of transistor 500 can be increased.

[0213] Conductors 542a and 542b serving as a source electrode and a drain electrode are provided on the oxide 530b. As the conductors 542a and 542b, metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, alloys containing the above metal elements as components, or alloys combining the above metal elements are preferably used. For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, and the like are preferably used. In addition, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel are conductive materials that are not easily oxidized or materials that maintain conductivity even when absorbing oxygen, so they are preferred. Metal nitride films such as tantalum nitride have barrier properties against hydrogen or oxygen, so they are more preferred.

[0214] In addition, although Fig.13AAlthough the single-layer structure of the conductor 542a and the conductor 542b is shown, a stacked structure of two or more layers may be adopted. For example, it is preferable to stack a tantalum nitride film and a tungsten film. In addition, a titanium film and an aluminum film may be stacked. In addition, a two-layer structure of stacking an aluminum film on a tungsten film, a two-layer structure of stacking a copper film on a copper-magnesium-aluminum alloy film, a two-layer structure of stacking a copper film on a titanium film, and a two-layer structure of stacking a copper film on a tungsten film may also be adopted.

[0215] In addition, a three-layer structure may be used in which an aluminum film or a copper film is stacked on a titanium film or a titanium nitride film and a titanium film or a titanium nitride film is formed thereon, a three-layer structure may be used in which an aluminum film or a copper film is stacked on a molybdenum film or a molybdenum nitride film and a molybdenum film or a molybdenum nitride film is formed thereon, etc. In addition, a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

[0216] In addition, if Fig.13A As shown, sometimes, a region 543a and a region 543b are formed as a low resistance region at the interface between the oxide 530 and the conductor 542a (conductor 542b) and in the vicinity thereof. In this case, the region 543a is used as one of the source region and the drain region, and the region 543b is used as the other of the source region and the drain region. In addition, a channel formation region is formed in a region sandwiched between the region 543a and the region 543b.

[0217] The oxygen concentration of the region 543a (region 543b) may be reduced by providing the above-mentioned conductor 542a (conductor 542b) in contact with the oxide 530. In addition, a metal compound layer containing a metal contained in the conductor 542a (conductor 542b) and a component of the oxide 530 may be formed in the region 543a (region 543b). In this case, the carrier concentration of the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low resistance region.

[0218] The insulator 544 is provided so as to cover the conductors 542 a and 542 b and suppress oxidation of the conductors 542 a and 542 b. In this case, the insulator 544 may be provided so as to cover the side surface of the oxide 530 and to be in contact with the insulator 524.

[0219] The insulator 544 can be made of a metal oxide containing one or more metals selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, or magnesium. Alternatively, the insulator 544 can be made of silicon nitride oxide or silicon nitride.

[0220] In particular, as the insulator 544, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc., which are insulators containing oxides of one or both of aluminum and hafnium, are preferably used. In particular, hafnium aluminate has higher heat resistance than hafnium oxide film. Therefore, it is not easy to crystallize in the heat treatment of the subsequent process, so it is preferred. In addition, insulator 544 does not necessarily need to be provided when conductor 542a and conductor 542b are composed of a material having oxidation resistance or a material whose conductivity does not significantly decrease even when oxygen is absorbed. It can be appropriately designed according to the required transistor characteristics.

[0221] By including the insulator 544, it is possible to suppress the diffusion of impurities such as water and hydrogen contained in the insulator 580 into the oxide 530b. In addition, it is possible to suppress the oxidation of the conductors 542a and 542b by excess oxygen contained in the insulator 580.

[0222] The insulator 545 is used as a first gate insulating film. The insulator 545 is preferably formed using an insulator that contains excess oxygen and releases oxygen by heating, similarly to the insulator 524 described above.

[0223] Specifically, silicon oxide containing excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, and silicon oxide having pores can be used. In particular, silicon oxide and silicon oxynitride are preferred because they have thermal stability.

[0224] By providing an insulator containing excess oxygen as the insulator 545, oxygen can be effectively supplied to the channel formation region of the oxide 530b from the insulator 545. In addition, as with the insulator 524, it is preferable to reduce the concentration of impurities such as water and hydrogen in the insulator 545. The thickness of the insulator 545 is preferably not less than 1 nm and not more than 20 nm.

[0225] In addition, in order to efficiently supply the excess oxygen contained in the insulator 545 to the oxide 530, a metal oxide may be provided between the insulator 545 and the conductor 560. The metal oxide preferably suppresses the diffusion of oxygen from the insulator 545 to the conductor 560. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of excess oxygen from the insulator 545 to the conductor 560 is suppressed. In other words, the amount of excess oxygen supplied to the oxide 530 can be suppressed from decreasing. In addition, the oxidation of the conductor 560 due to the excess oxygen can be suppressed. As the metal oxide, a material that can be used for the insulator 544 can be used.

[0226] In addition, like the second gate insulating film, the insulator 545 may also have a stacked structure. When miniaturization and high integration of transistors are performed, sometimes the thinning of the gate insulating film leads to problems such as off-state current. Therefore, by using the insulator used as the gate insulating film to have a stacked structure of a high-k material and a material with thermal stability, the gate potential of the transistor during operation can be reduced while maintaining the physical thickness. In addition, a stacked structure with thermal stability and a high relative dielectric constant can be achieved.

[0227] exist Fig.13A and Fig. 13B In the embodiment, the conductor 560 serving as the first gate electrode has a two-layer structure, but may have a single-layer structure or a stacked-layer structure of three or more layers.

[0228] As the conductor 560a, it is preferred to use a conductive material having the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), copper atoms, etc. In addition, it is preferred to use a conductive material having the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.). By making the conductor 560a have the function of suppressing the diffusion of oxygen, it is possible to suppress the decrease in conductivity caused by the oxidation of the conductor 560b due to the oxygen contained in the insulator 545. As a conductive material having the function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium or ruthenium oxide, etc. are preferably used. In addition, as the conductor 560a, an oxide semiconductor that can be applied to the oxide 530 can be used. In this case, by forming the conductor 560b by sputtering, the resistance value of the conductor 560a can be reduced to make it a conductor. It can be called an OC (Oxide Conductor) electrode.

[0229] As the conductor 560b, a conductive material mainly composed of tungsten, copper or aluminum is preferably used. Since the conductor 560b is also used as wiring, it is preferable to use a conductor with high conductivity. The conductor 560b may also have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive materials may be used.

[0230] The insulator 580 is preferably disposed on the conductor 542a and the conductor 542b via the insulator 544. The insulator 580 preferably has an excess oxygen region. For example, the insulator 580 preferably includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide with pores, or resin. In particular, silicon oxide and silicon oxynitride are thermally stable and therefore are preferred. In particular, silicon oxide and silicon oxide with pores are preferred because they are easy to form an excess oxygen region in the subsequent process.

[0231] The insulator 580 preferably has an excess oxygen region. By providing the insulator 580 that releases oxygen by heating, the oxygen in the insulator 580 can be efficiently supplied to the oxide 530. In addition, it is preferable to reduce the concentration of impurities such as water and hydrogen in the insulator 580.

[0232] The opening of the insulator 580 is formed so as to overlap with the region between the conductor 542a and the conductor 542b. Thus, the conductor 560 is provided so as to be embedded in the opening of the insulator 580 and in the region between the conductor 542a and the conductor 542b.

[0233] When miniaturizing semiconductor devices, it is necessary to shorten the gate length, but it is necessary to prevent the conductivity of the conductor 560 from decreasing. For this reason, when the thickness of the conductor 560 is increased, the conductor 560 may have a shape with a high aspect ratio. In this embodiment, since the conductor 560 is provided so as to be embedded in the opening of the insulator 580, even if the conductor 560 has a shape with a high aspect ratio, the conductor 560 does not collapse during the process.

[0234] The insulator 574 is preferably provided in contact with the top surface of the insulator 580, the top surface of the conductor 560, and the top surface of the insulator 545. By forming the insulator 574 by sputtering, an excess oxygen region can be formed in the insulator 545 and the insulator 580. Thus, oxygen can be supplied to the oxide 530 from the excess oxygen region.

[0235] For example, as the insulator 574, a metal oxide containing one or two or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like can be used.

[0236] In particular, aluminum oxide has high barrier properties and can inhibit the diffusion of hydrogen and nitrogen even in a thin film of 0.5 nm to 3.0 nm. Therefore, aluminum oxide formed by sputtering can be used as an oxygen supply source while also functioning as a barrier film for impurities such as hydrogen.

[0237] Furthermore, an insulator 581 serving as an interlayer film is preferably provided over the insulator 574. As with the insulator 524 and the like, the concentration of impurities such as water and hydrogen in the insulator 581 is preferably reduced.

[0238] In addition, the conductors 540a and 540b are arranged in the openings formed in the insulator 581, the insulator 574, the insulator 580, and the insulator 544. The conductors 540a and 540b are provided so as to face each other via the conductor 560. The conductors 540a and 540b have the same structure as the conductors 546 and 548 described later.

[0239] An insulator 582 is provided on the insulator 581. The insulator 582 is preferably made of a material having a barrier property against oxygen, hydrogen, and the like. Therefore, the insulator 582 can be made of the same material as the insulator 514. For example, the insulator 582 is preferably made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0240] In particular, aluminum oxide has a high barrier effect of preventing oxygen and impurities such as hydrogen and moisture that cause changes in the electrical characteristics of the transistor from penetrating. Therefore, during and after the manufacturing process of the transistor, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500. In addition, aluminum oxide can suppress the release of oxygen from the oxide constituting the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0241] In addition, an insulator 586 is provided on the insulator 582. As the insulator 586, the same material as the insulator 320 can be used. In addition, by using a material with a low dielectric constant as these insulators, the parasitic capacitance generated between the wirings can be reduced. For example, as the insulator 586, a silicon oxide film or a silicon oxynitride film can be used.

[0242] In addition, the conductor 546 and the conductor 548 are embedded in the insulator 520 , the insulator 522 , the insulator 524 , the insulator 544 , the insulator 580 , the insulator 574 , the insulator 581 , the insulator 582 , and the insulator 586 .

[0243] The conductor 546 and the conductor 548 are used as plugs or wirings connected to the capacitor 600, the transistor 500, or the transistor 550. The conductor 546 and the conductor 548 can be made of the same material as the conductor 328 and the conductor 330.

[0244] In addition, after forming the transistor 500, an opening may be formed around the transistor 500, and an insulator having a high barrier to hydrogen or water may be formed to cover the opening. By wrapping the transistor 500 with the above-mentioned high barrier insulator, it is possible to prevent moisture and hydrogen from entering from the outside. Alternatively, multiple transistors 500 may be wrapped with an insulator having a high barrier to hydrogen or water. In addition, in the case of forming an opening around the transistor 500, for example, when an opening is formed to reach the insulator 522 or the insulator 514 and the above-mentioned high barrier insulator is formed in contact with the insulator 522 or the insulator 514, it can also serve as a part of the manufacturing process of the transistor 500, so it is preferred. In addition, as an insulator having a high barrier to hydrogen or water, for example, the same material as the insulator 522 or the insulator 514 can be used.

[0245] The transistors that can be used in the present invention are not limited to Fig.13A and Fig. 13BThe transistor 500 shown. For example, it is also possible to use Fig.14 A transistor 500 having a structure as shown. Fig.14 The transistor 500 is shown with Fig.13A and Fig. 13B The transistor shown is different in that an insulator 555 is used and the conductor 542a (conductor 542a1 and conductor 542a2) and the conductor 542b (conductor 542b1 and conductor 542b2) have a stacked-layer structure.

[0246] The conductor 542a has a laminated structure of a conductor 542a1 and a conductor 542a2 on the conductor 542a1, and the conductor 542b has a laminated structure of a conductor 542b1 and a conductor 542b2 on the conductor 542b1. The conductors 542a1 and 542b1 in contact with the oxide 530b are preferably conductors that are not easily oxidized, such as metal nitrides. Thus, the conductors 542a and 542b can be prevented from being excessively oxidized by oxygen contained in the oxide 530b. In addition, the conductors 542a2 and 542b2 are preferably conductors such as metal layers having higher conductivity than the conductors 542a1 and 542b1. Thus, the conductors 542a and 542b can be used as wiring or electrodes with high conductivity. In this manner, a semiconductor device can be provided in which the conductors 542a and 542b serving as wiring or electrodes are provided in contact with the top surface of the oxide 530 serving as an active layer.

[0247] As the conductors 542a1 and 542b1, metal nitrides are preferably used, for example, nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing tantalum and aluminum, nitrides containing titanium and aluminum, etc. are preferably used. In one embodiment of the present invention, nitrides containing tantalum are particularly preferably used. In addition, for example, ruthenium, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. can also be used. These materials are conductive materials that are not easily oxidized or materials that maintain conductivity even if they absorb oxygen, so they are preferred.

[0248] The electrical conductivity of the conductor 542a2 and the conductor 542b2 is preferably higher than that of the conductor 542a1 and the conductor 542b1. For example, the thickness of the conductor 542a2 and the conductor 542b2 is preferably greater than that of the conductor 542a1 and the conductor 542b1. As the conductor 542a2 and the conductor 542b2, the conductor that can be used for the conductor 560b described above can be used. By adopting the above structure, the resistance of the conductor 542a2 and the conductor 542b2 can be reduced.

[0249] For example, tantalum nitride or titanium nitride can be used as the conductor 542a1 and the conductor 542b1, and tungsten can be used as the conductor 542a2 and the conductor 542b2.

[0250] like Fig.14 As shown in FIG. 1 , when viewed from a cross section in the channel length direction of the transistor 500, the distance between the conductor 542a1 and the conductor 542b1 is smaller than the distance between the conductor 542a2 and the conductor 542b2. By adopting this structure, the distance between the source and the drain can be further shortened, and the channel length can be shortened accordingly. Therefore, the frequency characteristics of the transistor 500 can be improved. In this way, by miniaturizing the semiconductor device, a semiconductor device with improved operating speed can be provided.

[0251] The insulator 555 is preferably an insulator that is not easily oxidized, such as a nitride. The insulator 555 is formed in a manner that contacts the side surface of the conductor 542a2 and the side surface of the conductor 542b2, and has the function of protecting the conductor 542a2 and the conductor 542b2. Since the insulator 555 is exposed to an oxidizing atmosphere, it is preferably an inorganic insulator that is not easily oxidized. In addition, since the insulator 555 contacts the conductor 542a2 and the conductor 542b2, it is preferably an inorganic insulator that is not easily oxidized by the conductors 542a2 and 542b2. Therefore, the insulator 555 is preferably an insulating material that has a barrier property against oxygen. For example, silicon nitride can be used as the insulator 555.

[0252] Openings are formed in the insulator 580 and the insulator 544, and the insulator 555 is formed so as to be in contact with the side walls of the openings. The conductor 542a1 and the conductor 542b1 are separated using a mask, thereby forming Fig.14 The transistor 500 shown in FIG. 1 is a transistor 500. Here, the opening overlaps the region between the conductor 542a2 and the conductor 542b2. In addition, a portion of the conductor 542a1 and the conductor 542b1 protrude into the opening. Therefore, the insulator 555 is in contact with the top surface of the conductor 542a1, the top surface of the conductor 542b1, the side surface of the conductor 542a2, and the side surface of the conductor 542b2 in the opening. In addition, the insulator 545 is in contact with the top surface of the oxide 530 in the region between the conductor 542a1 and the conductor 542b1.

[0253] Preferably, after the conductor 542a1 is separated from the conductor 542b1, a heat treatment is performed in an oxygen-containing atmosphere before the insulator 545 is deposited. Thus, oxygen is supplied to the oxide 530a and the oxide 530b, thereby reducing oxygen vacancies. Furthermore, by forming the insulator 555 in contact with the side of the conductor 542a2 and the side of the conductor 542b2, the conductor 542a2 and the conductor 542b2 can be prevented from being excessively oxidized. Thus, the electrical characteristics and reliability of the transistor can be improved. In addition, the uneven electrical characteristics of a plurality of transistors formed on the same substrate can be suppressed.

[0254] like Fig.14 As shown, in the transistor 500 , the insulator 524 may be formed in an island shape. Here, the side end of the insulator 524 may be substantially aligned with the oxide 530 .

[0255] like Fig.14 As shown in FIG. 5 , in the transistor 500, the insulator 522 may be in contact with the insulator 516 and the conductor 503. In other words, it is also possible not to set Fig.13A and Fig. 13B Insulator 520 is shown.

[0256] Next, a capacitor 600 is provided above the transistor 500 . The capacitor 600 includes a conductor 610 , a conductor 620 , and an insulator 630 .

[0257] Furthermore, a conductor 612 may be provided over the conductor 546 and the conductor 548. The conductor 612 is used as a plug or wiring connected to the transistor 500. The conductor 610 is used as an electrode of the capacitor 600. Alternatively, the conductor 612 and the conductor 610 may be formed at the same time.

[0258] As the conductor 612 and the conductor 610, a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing the above elements as a component (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film), etc. can be used. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon oxide, etc. can also be used.

[0259] In this embodiment, the conductor 612 and the conductor 610 have a single-layer structure, but the present invention is not limited thereto and they may have a stacked structure of two or more layers. For example, a conductor having high tightness to the conductor having a barrier property and the conductor having a high conductivity may be formed between the conductor having a barrier property and the conductor having a high conductivity.

[0260] The conductor 620 is provided so as to overlap the conductor 610 via the insulator 630. Conductive materials such as metal materials, alloy materials, and metal oxide materials can be used as the conductor 620. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is particularly preferable. When the conductor 620 is formed simultaneously with other components such as a conductor, a low-resistance metal material such as Cu (copper) or Al (aluminum) can be used.

[0261] An insulator 640 is provided on the conductor 620 and the insulator 630. The insulator 640 can be made of the same material as the insulator 320. In addition, the insulator 640 can be used as a planarization film that covers the uneven shape thereunder.

[0262] By adopting this structure, miniaturization or high integration of a semiconductor device using a transistor including an oxide semiconductor can be achieved.

[0263] As a substrate for a semiconductor device that can be used in one embodiment of the present invention, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, a metal substrate (for example, a stainless steel substrate, a substrate containing a stainless steel foil, a tungsten substrate, a substrate containing a tungsten foil, etc.), a semiconductor substrate (for example, a single crystal semiconductor substrate, a polycrystalline semiconductor substrate or a compound semiconductor substrate), an SOI (SOI: Silicon on Insulator) substrate, etc. can be used. In addition, a heat-resistant plastic substrate that can withstand the processing temperature of this embodiment can also be used. As an example of a glass substrate, barium borosilicate glass, aluminosilicate glass, aluminoborosilicate glass or soda-lime glass can be cited. In addition, crystallized glass, etc. can also be used.

[0264] In addition, as a substrate, a flexible substrate, a laminated film, paper or a base film containing a fibrous material can be used. As a flexible substrate, a laminated film, a base film, etc., the following examples can be cited. For example, plastics represented by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether sulfone (PES), and polytetrafluoroethylene (PTFE) can be cited. Or, as an example, synthetic resins such as acrylic resins can be cited. Or, as an example, polypropylene, polyester, polyvinyl fluoride or polyvinyl chloride can be cited. Or, as an example, polyamide, polyimide, aramid resin, epoxy resin, inorganic vapor-deposited film, paper, etc. can be cited. In particular, by using semiconductor substrates, single crystal substrates or SOI substrates to manufacture transistors, it is possible to manufacture transistors with small deviations in characteristics, size or shape, high current capacity and small size. When the above-mentioned transistors are used to form a circuit, low power consumption of the circuit or high integration of the circuit can be achieved.

[0265] In addition, a flexible substrate may be used as a substrate, and transistors, resistors and / or capacitors may be directly formed on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate and the transistors, resistors and / or capacitors. The peeling layer may be used in a case where a part or all of a semiconductor device is manufactured on the peeling layer, and then the semiconductor device is separated from the substrate and transferred to another substrate. In this case, the transistors, resistors and / or capacitors may be transferred to a substrate with low heat resistance or a flexible substrate. In addition, as the above-mentioned peeling layer, for example, a laminated structure of an inorganic film of a tungsten film and a silicon oxide film, a structure in which an organic resin film such as polyimide is formed on a substrate, or a silicon film containing hydrogen may be used.

[0266] That is, after forming a semiconductor device on one substrate, the semiconductor device can be transferred to another substrate. As the substrate to which the semiconductor device is transferred, not only the above-mentioned substrate on which a transistor can be formed can be used, but also paper substrates, glass paper substrates, aramid film substrates, polyimide film substrates, stone substrates, wood substrates, cloth substrates (including natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester) or regenerated fibers (acetate, cuprammonium, rayon, regenerated polyester)), leather substrates, rubber substrates, etc. can be used. By using such a substrate, it is possible to manufacture a flexible semiconductor device, manufacture a semiconductor device that is not easily damaged, improve heat resistance, and reduce weight or thickness.

[0267] By providing a semiconductor device on a flexible substrate, it is possible to provide a semiconductor device that is less likely to be damaged while suppressing an increase in weight.

[0268] Fig.12 The structure of transistor 550 shown is only an example and is not limited to the above structure, and an appropriate transistor can be used according to the circuit structure, driving method, etc. For example, when the semiconductor device is a unipolar circuit with only OS transistors (transistors of the same polarity such as only n-channel transistors), transistor 550 can have the same structure as transistor 500.

[0269] The configuration, structure, method, and the like described in this embodiment mode can be used in combination with the configuration, structure, method, and the like described in other embodiments and examples as appropriate.

[0270] (Implementation 3) In this embodiment, a cross-sectional structure example of an element layer having stacked OS transistors that can be used in a memory device, a data holding circuit, a storage circuit, etc. is described. In this embodiment, an example of a cross-sectional schematic diagram of a circuit structure that can be used in a DOSRAM, a NOSRAM, etc. is described.

[0271] Fig.15An example of a cross-sectional structure when a circuit structure using DOSRAM is shown. Fig.15 An example is shown in which element layers 700 [ 1 ] to 700 [ 4 ] are stacked on the element layer 701 .

[0272] also, Fig.15 An example of the transistor 550 included in the element layer 701 is shown. As the transistor 550, the transistor 550 described in the above embodiment mode can be applied.

[0273] also, Fig.15 The transistor 550 shown is just an example, and an appropriate transistor may be used according to the circuit structure or driving method without being limited to the structure.

[0274] A wiring layer having an interlayer film, wiring, plugs, etc. may also be provided between the component layer 701 and the component layer 700 or between the k-th component layer 700 and the k+1-th component layer 700. In addition, in the present embodiment, the k-th component layer 700 is sometimes referred to as the component layer 700[k], and the k+1-th component layer 700 is sometimes referred to as the component layer 700[k+1]. Here, k is an integer greater than 1 and less than N. In addition, in the present embodiment, when referred to as "k+α (α is an integer greater than 1)" or "k-α", the solutions of "k+α" and "k-α" are each integer greater than 1 and less than N.

[0275] In addition, the wiring layer may be provided in a plurality of layers according to the design. In addition, in this specification, a wiring and a plug electrically connected to the wiring may also be one component. That is, a part of a conductor may be used as a wiring, and a part of a conductor may be used as a plug.

[0276] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked as interlayer films on the transistor 550. In addition, a conductor 328 or the like is embedded in the insulator 320 and the insulator 322. In addition, a conductor 330 or the like is embedded in the insulator 324 and the insulator 326. In addition, the conductor 328 and the conductor 330 are used as contact plugs or wirings.

[0277] In addition, the insulator used as the interlayer film can be used as a planarization film that covers the concavo-convex shape thereunder. For example, in order to improve the flatness of the top surface of the insulator 320, planarization can also be achieved by a planarization process using a CMP method or the like.

[0278] Alternatively, a wiring layer may be provided on the insulator 326 and the conductor 330. Fig.15In the embodiment, an insulator 350, an insulator 357, an insulator 352, and an insulator 354 are sequentially stacked on the insulator 326 and the conductor 330. Furthermore, a conductor 356 is formed in the insulator 350, the insulator 357, and the insulator 352. The conductor 356 is used as a contact plug or a wiring.

[0279] The insulator 514 included in the element layer 700[1] is provided on the insulator 354. In addition, the conductor 358 is embedded in the insulator 514 and the insulator 354. The conductor 358 is used as a contact plug or wiring. For example, the wiring BL and the transistor 550 are electrically connected through the conductor 358, the conductor 356, and the conductor 330.

[0280] Fig.16A An example of a cross-sectional structure of the element layer 700[k] is shown. Fig. 16B yes Fig.16A Equivalent circuit diagram of . Fig.16A An example is shown in which one wiring BL is electrically connected to two element cells MC.

[0281] Fig.15 and Fig.16A The memory cell MC shown includes a transistor M1 and a capacitor C. As the transistor M1 , for example, the transistor 500 shown in the above embodiment can be used.

[0282] In this embodiment, a modified example of the transistor 500 is described as the transistor M1. Specifically, the transistor M1 is different from the transistor 500 in that the conductors 542a and 542b extend beyond the ends of the metal oxide 531 (the metal oxide 531a and the metal oxide 531b).

[0283] also, Fig.15 and Fig.16A The memory cell MC shown includes a conductor 156 serving as one terminal of the capacitor C, an insulator 153 serving as a dielectric, and a conductor 160 (conductor 160a and conductor 160b) serving as the other terminal of the capacitor C. The conductor 156 is electrically connected to a portion of the conductor 542b. In addition, the conductor 160 is connected to the wiring PL (in Fig.16A (not shown) electrical connection.

[0284] Capacitor C is formed in an opening portion provided by removing a portion of insulator 574, insulator 580, and insulator 554. Since conductor 156, insulator 580, and insulator 554 are formed along the side surface of the opening portion, they are preferably deposited using ALD or CVD.

[0285] In addition, as the conductor 156 and the conductor 160, a conductor that can be used for the conductor 505 or the conductor 560 can be used. For example, as the conductor 156, titanium nitride deposited by the ALD method can be used. In addition, as the conductor 160a, titanium nitride deposited by the ALD method can be used, and as the conductor 160b, tungsten deposited by the CVD method can be used. In addition, when the adhesion between tungsten and the insulator 153 is sufficiently high, a single layer film of tungsten deposited by the CVD method can also be used as the conductor 160.

[0286] As the insulator 153, it is preferred to use an insulator composed of a high dielectric constant (high-k) material (a material with a relatively high dielectric constant). For example, as an insulator composed of a high dielectric constant material, an oxide, an oxynitride, an oxynitride or a nitride containing one or more metal elements selected from aluminum, hafnium, zirconium and gallium can be used. In addition, the above-mentioned oxide, oxynitride, oxynitride or nitride may also contain silicon. In addition, an insulating layer composed of the above-mentioned materials may also be stacked. As the insulator 153, for example, a three-layer stacked structure of zirconium oxide, aluminum oxide and zirconium oxide can be cited. In addition, the three-layer stacked structure may also be referred to as ZrO xa \AlO xb \ZrO xc (ZAZ). The above xa, xb and xc are all arbitrary units.

[0287] For example, as an insulator composed of a high dielectric constant material, aluminum oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, an oxide containing silicon and zirconium, an oxynitride containing silicon and zirconium, an oxide containing hafnium and zirconium, an oxynitride containing hafnium and zirconium, etc. can be used. By using such a high dielectric constant material, the thickness of the insulator 153 can be increased to a degree that can suppress the off-state current, and the electrostatic capacitance of the capacitor element C can be fully ensured.

[0288] In addition, it is preferred to stack an insulating layer composed of the above-mentioned materials, and it is preferred to use a laminated structure of a high dielectric constant material and a material whose insulation resistance is higher than that of the high dielectric constant material. For example, as an insulator 153, an insulating film stacked with zirconium oxide, aluminum oxide and zirconium oxide can be used. In addition, for example, an insulating film stacked with zirconium oxide, aluminum oxide, zirconium oxide and aluminum oxide can be used. In addition, for example, an insulating film stacked with hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide and aluminum oxide can be used. By stacking an insulator with relatively high insulation resistance such as aluminum oxide, the insulation resistance can be improved to suppress the electrostatic destruction of the capacitor element C.

[0289] Fig.17An example of a cross-sectional structure when a circuit structure of a memory cell using NOSRAM is shown. Fig.17 Too Fig.15 In addition, Fig.18A An example of a cross-sectional structure of the element layer 700[k] is shown. Fig.18B yes Fig.18A Equivalent circuit diagram of .

[0290] Fig.17 and Fig.18A The illustrated memory cell MC includes a transistor M1, a transistor M2, and a transistor M3 on an insulator 514. In addition, a conductor 215 is provided on the insulator 514. The conductor 215 can be formed simultaneously with the conductor 505 using the same material and the same process.

[0291] also, Fig.17 and Fig.18A The transistor M2 and the transistor M3 shown in the figure share an island-shaped metal oxide 531. In other words, a portion of the island-shaped metal oxide 531 is used as a channel formation region of the transistor M2, and another portion is used as a channel formation region of the transistor M3. In addition, the source of the transistor M2 and the drain of the transistor M3 or the drain of the transistor M2 and the source of the transistor M3 are shared. Therefore, compared with the case where the transistor M2 and the transistor M3 are provided separately, the occupied area of ​​the transistor is small.

[0292] In addition, Fig.17 and Fig.18A In the illustrated memory cell MC, an insulator 287 is provided on an insulator 581, and a conductor 161 is embedded in the insulator 287. Furthermore, on the insulator 287 and the conductor 161, an insulator 514 of the element layer 700[k+1] is provided.

[0293] exist Fig.17 and Fig.18A In the embodiment, the conductor 215 of the element layer 700[k+1] is used as one terminal of the capacitor C, the insulator 514 of the element layer 700[k+1] is used as a dielectric of the capacitor C, and the conductor 161 is used as the other terminal of the capacitor C. In addition, the other of the source and the drain of the transistor M1 is electrically connected to the conductor 161 through a contact plug, and the gate of the transistor M2 is electrically connected to the conductor 161 through another contact plug.

[0294] This embodiment mode can be implemented in combination with other embodiment modes described in this specification as appropriate.

[0295] (Implementation 4) In this embodiment, a transistor including an oxide semiconductor in a channel formation region (OS transistor) is described. In addition, in the description of the OS transistor, a comparison with a transistor including silicon in a channel formation region (also referred to as a Si transistor) is briefly described.

[0296] [OS Transistor] It is preferable to use an oxide semiconductor with a low carrier concentration for the OS transistor. For example, the carrier concentration of the channel formation region of the oxide semiconductor is 1×10 18 cm -3 Below, preferably below 1×10 17 cm -3 , more preferably less than 1×10 16 cm -3 , and more preferably less than 1×10 13 cm -3 , and further preferably less than 1×10 10 cm -3 , and is 1×10 -9 cm -3 In the case of reducing the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film can be reduced to reduce the defect state density. In this specification, etc., a state in which the impurity concentration is low and the defect state density is low is referred to as high-purity intrinsic or substantially high-purity intrinsic. In addition, an oxide semiconductor with a low carrier concentration is sometimes referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0297] Since high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors have a low defect state density, they sometimes have a low trap state density. In addition, it takes a long time for the charges captured by the trap states of the oxide semiconductor to disappear, and sometimes they act like fixed charges. Therefore, sometimes the electrical characteristics of a transistor in which a channel formation region is formed in an oxide semiconductor with a high trap state density are unstable.

[0298] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the nearby film. As impurities, hydrogen, nitrogen, etc. can be cited. Note that impurities in oxide semiconductors refer to, for example, elements other than the main components that constitute the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be said to be an impurity.

[0299] In an OS transistor, when impurities and oxygen vacancies exist in the channel formation region of an oxide semiconductor, the electrical characteristics are easily changed and reliability may be reduced. In addition, in an OS transistor, hydrogen enters the oxygen vacancies in the oxide semiconductor to form defects (hereinafter sometimes referred to as V OH), electrons that become carriers may be generated. In addition, when V O When the voltage is V, the donor concentration in the channel formation region may increase. As the donor concentration in the channel formation region increases, the threshold voltage may become uneven. Therefore, when oxygen vacancies are included in the channel formation region of the oxide semiconductor, the transistor may have a normally-on characteristic (a characteristic in which a channel exists and current flows in the transistor even when no voltage is applied to the gate electrode). Therefore, in the channel formation region of the oxide semiconductor, it is preferable to minimize impurities, oxygen vacancies, and V. O H.

[0300] In addition, the band gap of the oxide semiconductor is preferably larger than the band gap of silicon (typically 1.1 eV), preferably 2 eV or more, more preferably 2.5 eV or more, and more preferably 3.0 eV or more. By using an oxide semiconductor with a larger band gap than silicon, the off-state current (also called Ioff) of the transistor can be reduced.

[0301] For example, in Si transistors, as the miniaturization of transistors progresses, short channel effects (Short Channel Effect: also called SCE) appear. Therefore, miniaturization of Si transistors is difficult. One of the reasons for the short channel effect is that the band gap of silicon is small. On the other hand, in OS transistors, oxide semiconductors, which are semiconductor materials with large band gaps, are used, so the short channel effect can be suppressed. In other words, OS transistors are transistors with no short channel effect or very little short channel effect.

[0302] The short channel effect refers to the degradation of electrical characteristics that occurs with the miniaturization of transistors (reduction of channel length). Specific examples of the short channel effect include a reduction in threshold voltage, an increase in subthreshold swing value (sometimes recorded as S value), and an increase in leakage current. Here, the S value refers to the change in gate voltage in the subthreshold region that changes the drain current value by one digit with a fixed drain voltage.

[0303] As an indicator of resistance to short channel effects, characteristic length is widely used. Characteristic length refers to an indicator of the curvature of the potential in the channel formation region. The smaller the characteristic length, the more rapidly the potential rises, so it can be said that the ability to resist short channel effects is high.

[0304] OS transistors are accumulation-type transistors, and Si transistors are inversion-type transistors. Therefore, compared with Si transistors, the characteristic length between the source region and the channel formation region and the characteristic length between the drain region and the channel formation region in OS transistors are smaller. Therefore, OS transistors have a higher ability to resist short channel effects than Si transistors. That is, when you want to manufacture transistors with a small channel length, OS transistors are more suitable than Si transistors.

[0305] Even when the carrier concentration of the oxide semiconductor is reduced to the point where the channel formation region is i-type or substantially i-type, the conduction band bottom of the channel formation region is also lowered due to the conduction-band-lowering (CBL) effect in the short channel transistor, so the energy difference of the conduction band bottom between the source region or the drain region and the channel formation region is likely to be reduced to more than 0.1 eV and less than 0.2 eV. Thus, the OS transistor can be regarded as having n + / n - / n + The accumulation type junction-less transistor structure or n + / n - / n + The accumulation type non-junction transistor structure, in which the channel formation region is n - Type region, source region and drain region are n + Type area.

[0306] When the above structure is used as an OS transistor, good electrical characteristics can be achieved even if the semiconductor device is miniaturized or highly integrated. For example, even if the gate length of the OS transistor is less than 20nm, less than 15nm, less than 10nm, less than 7nm or less than 6nm and more than 1nm, more than 3nm or more than 5nm, good electrical characteristics can be obtained. On the other hand, in Si transistors, it is sometimes difficult to have a gate length of less than 20nm or less than 15nm due to the occurrence of a short channel effect. Therefore, compared with Si transistors, OS transistors are more suitable for use as transistors with a small channel length. The gate length is the length of the gate electrode in the direction of the carrier movement channel formation region when the transistor is working, and is the width of the bottom surface of the gate electrode in the top view of the transistor.

[0307] In addition, by miniaturizing the OS transistor, the high-frequency characteristics of the transistor can be improved. Specifically, the cutoff frequency of the transistor can be increased. When the gate length of the OS transistor is within the above range, for example, at room temperature, the cutoff frequency of the transistor can be above 50 GHz, preferably above 100 GHz, and more preferably above 150 GHz.

[0308] As described above, the OS transistor has advantages superior to the Si transistor, such as a small off-state current and the ability to manufacture a transistor with a small channel length.

[0309] The configuration, structure, method, and the like described in this embodiment mode can be used in combination with the configuration, structure, method, and the like described in other embodiments mode and the like as appropriate.

[0310] (Implementation method 5) In this embodiment, electronic components, electronic devices, mainframe computers, space equipment, and data centers (also referred to as DC) that can use the semiconductor device described in the above embodiment are described. Electronic components, electronic devices, mainframe computers, space equipment, and data centers that use a semiconductor device in one embodiment of the present invention are effective in achieving high performance such as low power consumption.

[0311] [Electronic components] Fig.19A A perspective view of a substrate (circuit board 704 ) on which electronic components 709 are mounted is shown. Fig.19A The electronic component 709 shown includes a semiconductor device 710 within a mold 711. Fig.19A 709 is partially omitted to show the inside. The electronic component 709 includes a land 712 on the outside of the mold 711. The land 712 is electrically connected to the electrode pad 713, and the electrode pad 713 is electrically connected to the semiconductor device 710 through the lead 714. The electronic component 709 is mounted on the printed circuit board 702, for example. By combining a plurality of these electronic components and electrically connecting them on the printed circuit board 702, the circuit board 704 is completed.

[0312] In addition, the semiconductor device 710 includes a driving circuit layer 715 and an element layer 716. The element layer 716 has a structure in which a plurality of memory cell arrays are stacked. The structure in which the driving circuit layer 715 and the element layer 716 are stacked can adopt a monolithic stacked structure. In the monolithic stacked structure, it is possible to connect the layers without using through-electrode technologies such as TSV (Through Silicon Via) and bonding technologies such as Cu-Cu direct bonding. When the driving circuit layer 715 and the element layer 716 are stacked in a monolithic manner, for example, a so-called on-chip memory structure in which a memory is directly formed on a processor can be realized. By adopting the on-chip memory structure, high-speed operation of the interface portion between the processor and the memory can be achieved.

[0313] In addition, by adopting an on-chip memory structure, the size of the connection wiring can be reduced compared to the technology using through-electrodes such as TSV, so the number of pins can be increased. By increasing the number of pins, parallel operation can be performed, thereby increasing the bandwidth of the memory (also called memory bandwidth).

[0314] In addition, it is preferred that multiple memory cell arrays in the element layer 716 are formed using OS transistors, and the multiple memory cell arrays are stacked in a monolithic manner. When multiple memory cell arrays are stacked in a monolithic manner, either or both of the bandwidth of the memory and the access delay of the memory can be improved. The bandwidth refers to the amount of data transmitted per unit time, and the access delay refers to the time between accessing and starting the exchange of data. When Si transistors are used in the element layer 716, it is more difficult to realize a monolithic stacked structure compared to OS transistors. Therefore, in a monolithic stacked structure, OS transistors are superior to Si transistors.

[0315] In addition, the semiconductor device 710 may be referred to as a bare chip. In this specification, etc., a bare chip refers to a chip obtained by forming a circuit pattern on a disc-shaped substrate (also called a wafer) in the manufacturing process of a semiconductor chip, for example, and cutting it into rectangular small pieces. As semiconductor materials that can be used for bare chips, for example, silicon (Si), silicon carbide (SiC) or gallium nitride (GaN) can be cited. For example, a bare chip obtained from a silicon substrate (also called a silicon wafer) is sometimes called a silicon chip.

[0316] then, Fig.19B The electronic component 730 is a perspective view. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi Chip Module). In the electronic component 730, an interposer 731 is provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 are provided on the interposer 731.

[0317] The electronic component 730 shows an example of using the semiconductor device 710 as a high bandwidth memory (HBM). In addition, the semiconductor device 735 can be used in an integrated circuit such as a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), or an FPGA (Field Programmable Gate Array).

[0318] The package substrate 732 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 731 may be, for example, a silicon interposer or a resin interposer.

[0319] The interposer 731 has a plurality of wirings and has the function of electrically connecting a plurality of integrated circuits with different terminal spacings. The plurality of wirings are composed of a single layer or a plurality of layers. In addition, the interposer 731 has the function of electrically connecting the integrated circuit disposed on the interposer 731 to the electrode disposed on the package substrate 732. Therefore, the interposer is sometimes also referred to as a "rewiring substrate" or "intermediate substrate". In addition, sometimes a through electrode is provided in the interposer 731, and the integrated circuit is electrically connected to the package substrate 732 through the through electrode. In addition, in the case of using a silicon interposer, TSV can also be used as a through electrode.

[0320] In HBM, many wirings need to be connected to achieve a wide memory bandwidth. For this reason, it is required that fine wirings can be formed at a high density on the interposer on which the HBM is mounted. Therefore, a silicon interposer is preferably used as the interposer on which the HBM is mounted.

[0321] In addition, in SiP and MCM using silicon interposers, the reliability degradation caused by the difference in expansion coefficient between the integrated circuit and the interposer is not easy to occur. In addition, since the surface flatness of the silicon interposer is high, the connection between the integrated circuit arranged on the silicon interposer and the silicon interposer is not easy to occur. It is particularly preferred to use the silicon interposer for 2.5D packaging (2.5D mounting) in which a plurality of integrated circuits are arranged horizontally and configured on the interposer.

[0322] On the other hand, when a plurality of integrated circuits with different terminal pitches are electrically connected using silicon interposers and TSV, etc., a space such as the width of the terminal pitch is required. Therefore, when the size of the electronic component 730 is to be reduced, the width of the terminal pitch becomes a problem, and it is sometimes difficult to set up a large number of wirings required to achieve a wider memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferred. In addition, a composite structure combining a memory cell array stacked using TSV and a memory cell array stacked in a monolithic manner can also be used.

[0323] In addition, a heat sink (heat sink plate) may be provided so as to overlap with the electronic component 730. When a heat sink is provided, it is preferable to make the heights of the integrated circuits provided on the interposer 731 consistent. For example, in the electronic component 730 shown in this embodiment, it is preferable to make the heights of the semiconductor device 710 and the semiconductor device 735 consistent.

[0324] In order to mount the electronic component 730 on another substrate, an electrode 733 may be provided on the bottom of the package substrate 732 . Fig.19BAn example of forming the electrode 733 using solder balls is shown. By arranging solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrode 733 can be formed using conductive needles. By arranging conductive needles in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0325] The electronic component 730 can be mounted on other substrates by various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0326] [Electronic equipment] then, Fig. 20A A perspective view of electronic device 6500 is shown. Fig. 20A The electronic device 6500 shown is a portable information terminal that can be used as a smartphone. The electronic device 6500 includes a housing 6501, a display unit 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509. The control device 6509 includes, for example, any one or more selected from a CPU, a GPU, and a storage device. The semiconductor device of one embodiment of the present invention can be used for the display unit 6502, the control device 6509, and the like.

[0327] Fig. 20B The electronic device 6600 shown is an information terminal that can be used as a notebook personal computer. The electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display unit 6615, a control device 6616, etc. The control device 6616 includes, for example, any one or more selected from a CPU, a GPU, and a storage device. A semiconductor device of one embodiment of the present invention can be used for the display unit 6615, the control device 6616, etc. In addition, by using a semiconductor device of one embodiment of the present invention for the above-mentioned control device 6509 and the control device 6616, power consumption can be reduced, so it is preferred.

[0328] [Mainframe computer] then, Fig. 20CA perspective view of a mainframe computer 5600 is shown. Fig. 20C In the illustrated mainframe computer 5600, a plurality of rack-mounted computers 5620 are housed in a rack 5610. The mainframe computer 5600 may also be referred to as a supercomputer.

[0329] Computer 5620 may have, for example, Fig.20D The structure of the stereogram is shown. Fig.20D In the embodiment, the computer 5620 includes a motherboard 5630, and the motherboard 5630 includes a plurality of slots 5631 and a plurality of connection terminals. A personal computer card 5621 is inserted into the slot 5631. The personal computer card 5621 includes connection terminals 5623, 5624, and 5625, which are connected to the motherboard 5630.

[0330] Fig.20E The personal computer card 5621 shown is an example of a processing board including a CPU, a GPU, a storage device, etc. The personal computer card 5621 has a board 5622. In addition, the board 5622 includes a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that Fig.20E Semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 are shown. For description of these semiconductor devices, refer to the description of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 described below.

[0331] The connection terminal 5629 has a shape that can be inserted into the slot 5631 of the motherboard 5630, and is used as an interface for connecting the personal computer card 5621 and the motherboard 5630. Examples of the standard of the connection terminal 5629 include PCIe and the like.

[0332] The connection terminals 5623, 5624, and 5625 can be used as interfaces for supplying power to the personal computer card 5621 or inputting signals, for example. In addition, for example, they can be used as interfaces for outputting signals calculated by the personal computer card 5621, for example. Examples of the specifications of the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). In addition, when video signals are output from the connection terminals 5623, 5624, and 5625, HDMI (registered trademark) and the like can be cited as the specifications.

[0333] The semiconductor device 5626 includes a terminal (not shown) for inputting and outputting a signal. By inserting the terminal into a socket (not shown) included in the board 5622 , the semiconductor device 5626 and the board 5622 can be electrically connected.

[0334] The semiconductor device 5627 includes a plurality of terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring included in the board 5622 by reflow soldering. Examples of the semiconductor device 5627 include FPGA, GPU, and CPU. For example, the electronic component 730 can be used as the semiconductor device 5627.

[0335] The semiconductor device 5628 includes a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring included in the board 5622 by reflow soldering. As the semiconductor device 5628, for example, a memory device can be cited. As the semiconductor device 5628, for example, the electronic component 709 can be used.

[0336] The mainframe computer 5600 can be used as a parallel computer. By using the mainframe computer 5600 as a parallel computer, for example, large-scale calculations required for learning and inference of artificial intelligence can be performed.

[0337] [Space Equipment] The semiconductor device of one embodiment of the present invention can be applied to space equipment such as equipment for processing and storing information.

[0338] A semiconductor device according to one embodiment of the present invention may include an OS transistor. The OS transistor has a small change in electrical characteristics due to exposure to radiation. In other words, it has high resistance to radiation, so it can be appropriately used in an environment where radiation may be incident. For example, an OS transistor can be appropriately used when used in outer space.

[0339] exist Fig.21 In FIG. 6 , an artificial satellite 6800 is shown as an example of a space device. The artificial satellite 6800 includes a main body 6801, a solar cell panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Fig.21 An example is shown in which the outer space includes the planet 6804. Note that the outer space refers to, for example, an altitude of 100 km or more, but the outer space described in this specification may also include the thermosphere, mesosphere, and stratosphere.

[0340] In addition, although Fig.21Although not shown in the figure, a battery management system (also called BMS) or a battery control circuit may be provided in the secondary battery 6805. When an OS transistor is used for the above-mentioned battery management system or battery control circuit, power consumption is low and high reliability is achieved even in outer space, so it is preferable.

[0341] In addition, outer space is an environment where the radiation dose is more than 100 times that of the ground. Examples of radiation include: electromagnetic waves (electromagnetic radiation) represented by X-rays and gamma rays; and particle radiation represented by alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, muon rays, etc.

[0342] When sunlight shines on the solar cell panel 6802, the power required for the artificial satellite 6800 to operate is generated. However, for example, when sunlight does not shine on the solar cell panel or when the amount of sunlight shining on the solar cell panel is small, the amount of power generated is reduced. Therefore, there is a possibility that the power required for the artificial satellite 6800 to operate may not be generated. In order to operate the artificial satellite 6800 even when the generated power is small, it is preferable to provide a secondary battery 6805 in the artificial satellite 6800. In addition, the solar cell panel is sometimes referred to as a solar cell module.

[0343] The artificial satellite 6800 can generate a signal. The signal is transmitted through the antenna 6803, and a receiver on the ground or other artificial satellites can receive the signal. By receiving the signal transmitted by the artificial satellite 6800, the position of the receiver receiving the signal can be measured. Thus, the artificial satellite 6800 can constitute a satellite positioning system.

[0344] In addition, the control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is composed of, for example, any one or more selected from a CPU, a GPU, and a storage device. In addition, as the control device 6807, a semiconductor device of one embodiment of the present invention is preferably used. Compared with Si transistors, the electrical characteristics of OS transistors due to radiation exposure change is small. In other words, OS transistors have high reliability and can be used appropriately even in an environment where radiation may be incident.

[0345] In addition, the artificial satellite 6800 may include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 may have a function of detecting sunlight reflected from an object on the ground. Alternatively, by including a thermal infrared sensor, the artificial satellite 6800 may have a function of detecting thermal infrared rays released from the ground. Thus, the artificial satellite 6800 may be used as an earth observation satellite, for example.

[0346] Note that although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited to this. For example, a semiconductor device according to one embodiment of the present invention can be suitably applied to space equipment such as a spacecraft, a space capsule, and a space probe.

[0347] As described above, OS transistors have superior effects compared to Si transistors, such as being able to achieve a wider memory bandwidth and having high radiation resistance.

[0348] [Data Center] For example, a semiconductor device of one embodiment of the present invention can be applied to an auxiliary storage system used in a data center or the like. A data center is required to ensure data invariance and to perform long-term data management. When performing long-term data management, it is necessary to enlarge facilities, such as installing auxiliary storage and servers for storing huge amounts of data, ensuring a stable power supply to maintain data, or ensuring cooling equipment required for maintaining data.

[0349] By using a semiconductor device of one embodiment of the present invention in an auxiliary storage system used in a data center, it is possible to reduce the power required for data retention and miniaturize the semiconductor device for retaining data. Therefore, it is possible to miniaturize the auxiliary storage system, miniaturize the power supply for retaining data, and reduce the scale of cooling equipment. As a result, it is possible to save space in the data center.

[0350] In addition, the power consumption of the semiconductor device of one embodiment of the present invention is low, so the heat generation of the circuit can be reduced. As a result, the negative impact of the heat generation on the circuit itself, the peripheral circuits and the modules can be reduced. In addition, by using the semiconductor device of one embodiment of the present invention, a data center that can operate stably even in a high temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0351] Fig. 22 A secondary storage system that may be used in a data center is shown. Fig. 22 The auxiliary storage system 7000 shown includes a plurality of servers 7001sb as a host 7001 (shown as a main computer). In addition, it includes a plurality of storage devices 7003md as an auxiliary storage 7003 (shown as an auxiliary storage). The host 7001 and the auxiliary storage 7003 are connected via an auxiliary storage area network 7004 (shown as a SAN: Storage Area Network) and an auxiliary storage control circuit 7002 (shown as an auxiliary storage controller).

[0352] The host computer 7001 is equivalent to a computer that accesses data stored in the auxiliary storage 7003. The hosts 7001 may be connected to each other via a network.

[0353] In the auxiliary memory 7003, the access speed of data is shortened by using a flash memory, that is, the time required for data storage and output is shortened, but this time is much longer than the time required for DRAM which can be used as a cache memory in the auxiliary memory. In the auxiliary storage system, in order to solve the problem of the long access speed of the auxiliary memory 7003, a cache memory is generally set in the auxiliary memory to shorten the time required for data storage and output.

[0354] The cache memory described above is used in the auxiliary storage control circuit 7002 and the auxiliary memory 7003. Data exchanged between the host 7001 and the auxiliary memory 7003 is stored in the cache memory in the auxiliary storage control circuit 7002 and the auxiliary memory 7003 and then output to the host 7001 or the auxiliary memory 7003.

[0355] When an OS transistor is used as a transistor for storing data in the cache memory to hold a potential corresponding to the data, the refresh frequency can be reduced to reduce power consumption. In addition, miniaturization can be achieved by stacking memory cell arrays.

[0356] Note that by using a semiconductor device of one embodiment of the present invention for any one or more selected from electronic components, electronic devices, large computers, space equipment, and data centers, it is expected that the effect of reducing power consumption can be expected. Therefore, it is currently believed that as the energy demand for high performance or high integration of semiconductor devices increases, the emission of greenhouse gases represented by carbon dioxide (CO2) can also be reduced by using a semiconductor device of one embodiment of the present invention. In addition, a semiconductor device of one embodiment of the present invention has low power consumption, so it is also effective as a measure against global warming.

[0357] The configuration, structure, method, and the like described in this embodiment mode can be used in combination with the configuration, structure, method, and the like described in other embodiments mode and the like as appropriate. [Example 1]

[0358] A semiconductor device including a CPU equivalent to the computing device 100 described in Embodiment 1 and an accelerator equivalent to the computing device 200 was prototyped using a stacking technology including an element layer (also referred to as an OS layer) of a transistor (IGZO-FET) using a crystalline In-Ga-Zn-Oxide semiconductor for a semiconductor layer. The prototyped semiconductor device includes a power supply circuit, a CPU memory for holding CPU data, and the like as other components. The CPU memory is equivalent to the memory device 300 described in Embodiment 1.

[0359] The prototype semiconductor device was manufactured by laminating two layers of an OS layer, which is an element layer of an IGZO-FET, manufactured by a 200 nm process, on a Si CMOS circuit manufactured by a 130 nm process.

[0360] Fig.23 Schematic diagram showing the chip appearance of a semiconductor device 10X produced in a trial manner. Fig.23 In the embodiment, an OS layer is partially provided on the element layer 20 provided with the SiCMOS circuit. Fig.23 The CPU shown in the figure is provided with an OS flip-flop OSFF in which data holding circuits (hereinafter referred to as backup memories) FD1 and FD2 are stacked on a scan flip-flop SFF included in an element layer 20 . Fig.23 The accelerator ACC shown in the figure is provided with a plurality of blocks, including a product-sum operation processing element (hereinafter also referred to as an operation element PE) provided in the element layer 20 and ACC memories MB1 and MB2 stacked on the operation element PE. In addition, the element layer 20 is provided with a CPU memory MEM and a power supply circuit PC stacked on the OS layer.

[0361] Fig.24 Schematic diagram for explaining the bank switching of the OS trigger (OSFF) and the bank switching of the operation element PE. The bank switching of the OS trigger (OSFF) is performed by switching the data read from the backup memories FD1 and FD2 provided on the scan trigger SFF. The bank switching of the operation element PE is performed by switching the data read from the ACC memories MB1 and MB2 provided on the operation element PE. Fig.24 In the present invention, backup memories FD1, FD2 and ACC memories MB1, MB2 are arranged in OS layers OS1, OS2, and scan flip-flops SFF and operation elements PE are arranged in element layer Si including Si CMOS circuits.

[0362] Bank switching can be performed by switching between two states, context 0 and context 1. Context 0 reads data from backup memory FD1 and ACC memory MB1 of OS layer OS1 to scan flip-flop SFF and computing element PE. Context 1 reads data from backup memory FD2 and ACC memory MB2 of OS layer OS2 to scan flip-flop SFF and computing element PE.

[0363] Fig.25The system structure of the trial-produced semiconductor device 10X is shown. The trial-produced semiconductor device 10X is equipped with an ARMCortex-M0 CPU (core), 8kByte CPU memory (MEM), accelerator (ACC), power supply circuit (PC), power management circuit (PMU), general purpose IO (GPIO), external memory IF (External Memory Interface, ExMIF), bus bridge (BB), watchdog (WD), serial communication interface (SPI, UART). Each circuit is electrically connected through an AHB bus (AHB lite), an APB bus (APB), etc.

[0364] The accelerator (ACC) is an AI accelerator that stores the weight data of the artificial neural network (NN) in a memory (ACC memory) on the computing element PE. Fig.26 ). Considering the trade-off between the reduced drive area and improved latency caused by fewer / more memory block divisions in the computing element PE, it was decided to arrange the blocks of the 4kB two-layer memory shared by 16 computing elements PE (PEs) into 8 blocks. In the computing element PE, different weight data (NN1, NN2) is maintained in two NOSRAMs by stacking the OS layer, thereby being able to switch between two states (context 0, context 1).

[0365] The accelerator (ACC) corresponds to the binary neural network (BNN) for low-power operation. The accelerator (ACC) has a built-in controller, which has a memory / AI mode switching function and is assembled with a serializer-deserializer (SerDes) in addition to a structure that changes the number of parallel operation elements PE driven according to the neural network. In the operation element PE, weight data (W[7:0]) and input data (A[7:0]) are input to the XNOR. The weight data is read out from the ACC memory MB1 and MB2 through the drive circuit (R / W DRV). The counter (Popcount) is used to count the data of the XNOR and add it to the data of the accumulator (register Reg.). 8 multiplication and addition operations (MAC) are performed in parallel with 1 clock, and the results are temporarily stored in the accumulator (register Reg.), thereby obtaining the data (ACC[10:0]) that has undergone multiplication and addition operations. After repeating the same process according to the number of inputs (neurons), threshold processing (bias data T[10:0]) is performed, thereby completing the operation of one layer of the network. The bias data is read out from the ACC memories MB1 and MB2 through the drive circuit (R / W DRV). The maximum number of parallel drives of the operation element PE is 128. In a fully connected network including three hidden layers, derivation can be performed with 194 clocks.

[0366] The OS layer including the ACC memory to be accessed can be selected using a layer selection driver LSD made of only OS transistors ( Fig. 27 ). In order to suppress the decrease in the threshold of the word line (RWL, WWL) voltage caused by the switching of the n-channel transistor (nMOS), the layer selection driver LSD adopts a structure including a bootstrap circuit. Since the layer selection driver LSD and the memory cells of the ACC memories MB1 and MB2 can be set in the OS layer at the same time, there is no area cost even if the number of stacked layers increases. In addition, there is no need to change the address size of the driver circuit (R / W DRV) made of Si-CMOS, and its area and power do not increase.

[0367] The CPU has a structure of a normally-off CPU capable of power gating. The CPU core of the CPU is Cortex-M0 (registered trademark) manufactured by ARM. A backup memory is configured just above the scan trigger SFF, and each OS layer is stacked in a manner with zero area overhead. By utilizing the characteristics of a monolithic stack, a fine-grained and irregular configuration is possible. In the backup memory, different data can be maintained in two backup memories by stacking OS layers, thereby enabling switching between two states (context 0, context 1).

[0368] In the OS flip-flop (OSFF), a 3T1C / unit memory is placed just above the scan flip-flop SFF, and each OS layer is stacked in such a way that the area overhead is zero ( Fig.28 The scan trigger SFF includes a trigger (FF). By utilizing the characteristics of the monolithic stack, a fine-grained and irregular configuration can be performed. Data backup and recovery can be performed between the memory of 3T1C / unit and the scan trigger SFF.

[0369] Fig.29 Yes Description Fig. 27 The accelerator (ACC) and Fig.28 The OS trigger (OSFF) shown in the figure is a timing diagram of the operation when switching between context 0 and context 1. Fig.29 This is a timing diagram for explaining the operation of a signal (PG_EN) used when power gating (PG) of a power management circuit (PMU) is utilized.

[0370] In the OS trigger (OSFF), the signal BK[0] (BK[1]) is supplied to the memory of the OS layer of the first layer (second layer) corresponding to context 0 (context 1) to retain data, and then the data is written back to the scan trigger SFF using the signal RE[1] (RE[0]) corresponding to context 1 (context 0). Tasks and results are backed up using the signal BK[1] (BK[0]), thereby achieving context switching. After data retention, it is transferred to sleep mode, thereby enabling PG. 4045 scan triggers SFF are backed up / restored at a time at 160ns / 180ns, and the energy is confirmed to be 510fJ / bit / 111fJ / bit respectively through chip evaluation.

[0371] The ACC memories MB1 and MB2 included in the accelerator ACC can realize context switching by simply switching the layer selection signal. When the read word line (RWL) is activated using the CMOS driver in the state of selecting any OS layer, the storage cells of the ACC memories MB1 and MB2 in the row of the corresponding OS layer can be accessed. Since the storage cells of the ACC memories MB1 and MB2 retain data during PG, no special work is required.

[0372] The signal waveform of the semiconductor device 10X produced by trial production is confirmed. Fig.30 As shown, the waveforms of switching between OS1 and OS2 and switching between signals BK[0], BK[1] and signals RE[0], RE[1] due to context switching can be confirmed.

[0373] Fig.31This is a diagram illustrating the operation state when the operation element PE is driven in parallel in the accelerator (ACC). As operations, product-sum operations (MAC), threshold processing (TH), and output (OUT) are performed in each layer (PL1 to PL4). HCLK is 10MHz, and PECLK (access clock) is 400kHz. In a fully connected network including 784 input layers (PL1) and three hidden layers (PL2 to PL4: 128 layers), derivation can be performed with 194 clocks.

[0374] Fig.32 A graph showing the results of chip evaluation, in which the left vertical axis represents the operation efficiency, the right vertical axis represents the classification accuracy, and the horizontal axis represents the access clock frequency. Fig.32 As shown, the conditions for high classification accuracy and high access clock frequency of the accelerator ACC are 4.44TOPS / W (PECLK (access clock frequency) is 400kHz, and the system clock frequency is 10MHz). The memory readout used for derivation is the critical path. The derivation accuracy decreases at the maximum frequency (400kHz), but it is possible to improve performance through memory optimization.

[0375] Fig.33A is a graph comparing the energy of a derivation (using the MNIST database) using only CPU memory and cores with a derivation using an accelerator ACC. Fig.33A This is a graph with energy as the vertical axis. The energy derived using only the CPU memory and core is 1681.97 μJ, while the energy derived using the accelerator ACC is reduced to 0.19 μJ. In addition, Fig.33B The vertical axis represents the execution time. The derived execution time can also be shortened from 3.55s to 485μs ( Fig.33B As a result, it was confirmed that derivation can be performed based on the frame rate of the video data (for example, 60fps, 16ms).

[0376] Fig.34 This is a schematic diagram comparing the effect of low power consumption when executing context switching and power gating (PG) on the chip of the present embodiment including two OS layers (OS / OS / Si (OS memory) structure), a chip including one OS layer and an OS / Si (OS memory) structure, and a chip without an OS layer. Fig.34 The vertical axis represents power and the horizontal axis represents time. An OS / Si chip is a chip that has a layer of OS memory stacked on a CMOS circuit. An Si (SRAM) chip is a chip that uses SRAM as an accelerator without using OS. Since SRAM is a volatile memory and cannot be PG, a structure that reduces standby power by clock gating (CG) is used for comparison.

[0377] The power is estimated by taking the intermittent operation of PG (CG) (standby period) as an example, in which two neural networks (NN1, NN2) are switched to perform deduction (using the MNIST database) (active period) and then perform PG (CG) (standby period).

[0378] Chips with OS / Si structures and chips with Si (SRAM) structures as accelerators (using SRAM generator estimation) can only store data equivalent to one neural network in memory. Therefore, the weight data W needs to be rewritten for each derivation. Specifically, in the Si (SRAM) structure and the OS / Si (OS memory) structure, the weight data W of the neural network NN1 is maintained (stored W NN1) and derivation (derivation NN1), and then the weight data W of the neural network NN2 is maintained (stored W NN2) and derivation (derivation NN2), and the above work is repeated.

[0379] On the other hand, the stacked OS / OS / Si structure can achieve rapid context switching and achieve low power consumption by ensuring the time of PG. Specifically, in the OS / OS / Si (OS memory) structure, the weight data W of the neural networks NN1 and NN2 can be switched for deduction, thereby enabling continuous deduction (deriving NN1) and deduction (deriving NN2).

[0380] Fig.35 is with Fig.34 Related schematic diagrams comparing the operation of accelerators of the OS / OS / Si structure, OS / Si structure and Si (SRAM) structure when performing context switching.

[0381] like Fig.35 As shown, in the Si (SRAM) structure and the OS / Si structure, the weight data W of the neural network NN1 is maintained in the SRAM or OS Mem. (W is stored in NN1), deduction is performed in the computing elements PEs (deriving NN1), and then the weight data W of the neural network NN2 is maintained in the SRAM or OS memory (W is stored in NN2) and deduction is performed (deriving NN2), and the above steps are repeated.

[0382] On the other hand, in the stacked OS / OS / Si structure, the weight data W of the neural networks NN1 and NN2 are maintained in the two-layer OS memory (storage W), and the data in the OS memory can be switched to perform derivation (deriving NN1, derivation NN2). Thus, derivation (deriving NN1) and derivation (deriving NN2) can be performed continuously.

[0383] Fig.36AThe vertical axis represents power, which shows the power measurement results of the chip with OS / OS / Si structure including two OS layers when using the accelerator ACC for derivation, when writing to the ACC memory, and when PG. In addition, Fig.36A Shows the ratio of core, PMU, ACC and other powers. In addition, Fig.36B The vertical axis represents percentage, which shows the ratio of the core, PMU, ACC and other powers during derivation using the accelerator ACC, during ACC memory writing and during PG in a chip with an OS / OS / Si structure including two OS layers.

[0384] Depend on Fig.36A , Fig.36B The results show that the power of the derivation using the accelerator ACC, the power of the ACC memory write, and the power of the PG are 386.5μW, 637.4μW, and 0.89μW respectively. When the derivation assumes a frame rate of 60fps, the average power of this chip is 25.15μW, which can reduce the power by 79% compared with the Si (SRAM) structure.

[0385] Fig.37A The figure shows the relationship between the frequency (intermittent operation cycle: horizontal axis) and power consumption (vertical axis) of the accelerators of the OS / OS / Si structure, OS / Si structure, and Si (SRAM) structure when they work by switching the two-layer neural network (2NN). As can be seen from the figure, when working by switching the two-layer neural network, the power consumption of the OS / OS / Si structure can be reduced.

[0386] Fig.37B The relationship between the frequency (intermittent working cycle: horizontal axis) and the power consumption (vertical axis) of the accelerators of the OS / OS / OS / OS / Si structure, OS / OS / Si structure, OS / Si structure, and Si (SRAM) structure when operating by switching a four-layer neural network (4NN). When operating by switching a four-layer neural network, the effect of reducing power consumption of the OS / OS / Si structure is small. By adopting a structure in which the number of OS layers is set according to the number of layers of the neural network, the effect of reducing power consumption can be increased.

[0387] Fig.37C This is a comparison chart of the power consumption (power consumption @16ms: vertical axis) of a two-layer neural network (2NN) and a four-layer neural network (4NN) when the accelerators of the OS / OS / OS / OS / Si structure, OS / OS / Si structure, OS / Si structure, and Si (SRAM) structure are switched at 16ms. Fig.37C It can be seen that by adopting a structure in which the number of OS layers is set according to the number of layers of the neural network, the effect of reducing power consumption can be increased.

[0388] Fig.38A This is a graph showing the relationship between the structure of the OS layer (number of OS layers (OS / OS / Si: OS memory)) corresponding to the number of neural networks (1, 2, 4, 8 networks) and the block size of the accelerator (ACC block size). Similarly, Fig.38B This is a graph showing the relationship between the structure of the OS layer corresponding to the number of neural networks (1, 2, 4, 8 networks) and the standby power at PG. Fig.38C This is a graph showing the relationship between the structure of the OS layer corresponding to the number of neural networks (1, 2, 4, 8 networks) and the power consumption (active power) during driving. FIG. 38A to FIG. 38C The block size, standby power, and power consumption of the accelerator when the number of neural networks in the Si (SRAM) structure without an OS layer (address size expansion rate (Si: SRAM))) is increased are also shown.

[0389] like FIG. 38A to FIG. 38C As shown, in the structure of the accelerator including the OS layer corresponding to the number of neural networks (1, 2, 4, 8 networks), even if the structure of the OS layer corresponding to the number of neural networks is increased, the block size does not change. The standby power and power consumption are the same. In the Si (SRAM) structure, as the number of neural networks increases, the block size, power consumption and standby power increase. When the number of neural networks is small, the Si (SRAM) structure has an advantage in power consumption.

[0390] As described above, by utilizing the memory included in the OS layer to switch libraries, there is no need to extend the execution time of PG by rewriting the ACC memory due to context switching. Even when the memory is set in the OS / OS / Si structure including two OS layers, there are advantages in power and area, which can prove the effectiveness of the present system.

[0391] Fig.39 This is a top-down photo of the tube core. Fig.40 This is a cross-sectional photo. Fig.40In the figure, S / D Electrode, Top Gate, and Back Gate are shown as source electrode / drain electrode, gate electrode, and back gate electrode. The semiconductor device described in this embodiment is manufactured by the following process: two layers of IGZO-FET element layers manufactured by 200nm process are stacked on Si CMOS circuit manufactured by 130nm process. It is possible to realize a structure in which the OS layer is used as backup memory, ACC memory, and CPU memory, and each layer of memory (OS memory) is equivalent to a library. In a system proposed according to this structure, by linking the library switching of the ACC memory with the library switching of the backup memory to switch the derivation of different neural networks with low latency and low power, the standby time of power gating can be extended.

[0392] <Notes on the Descriptions in This Manual, etc.> Hereinafter, comments will be added to the description of the above-mentioned embodiment and each configuration in the embodiment.

[0393] The structure described in each embodiment can be appropriately combined with the structure described in other embodiments to constitute one mode of the present invention. In addition, when a plurality of structural examples are described in one embodiment, these structural examples can be appropriately combined.

[0394] In addition, the content (or part thereof) described in a certain embodiment may be applied, combined or replaced with other content (or part thereof) described in that embodiment and / or content (or part thereof) described in one or more other embodiments.

[0395] The contents described in the embodiments refer to the contents described using various drawings in each embodiment or the contents described using articles described in the specification.

[0396] In addition, more figures may be formed by combining a drawing (or part thereof) shown in a certain embodiment with other parts of the drawing, other drawings (or parts thereof) shown in the embodiment, and / or drawings (or parts thereof) shown in one or more other embodiments.

[0397] In this specification, etc., constituent elements are classified according to function and are represented as independent blocks in a block diagram. However, it is difficult to classify constituent elements according to function in actual circuits, etc., and sometimes one circuit involves multiple functions or multiple circuits involve one function. Therefore, the division of blocks in a block diagram is not limited to the constituent elements described in the specification, but can be appropriately different according to the situation.

[0398] In the drawings, the size, thickness of a layer or area is sometimes exaggerated for the sake of clarity. Therefore, the present invention is not limited to the dimensions in the drawings. The drawings are for the sake of clarity and are not limited to the shapes or values ​​shown in the drawings. For example, it may include uneven signals, voltages or currents caused by noise or timing deviations.

[0399] In this specification, etc., when describing the connection relationship of a transistor, the expressions "one of the source and the drain" (first electrode or first terminal) and "the other of the source and the drain" (second electrode or second terminal) are used. This is because the source and the drain of a transistor are interchangeable depending on the structure or operating conditions of the transistor. Note that the source and the drain of a transistor may be appropriately referred to as a source (drain) terminal or a source (drain) electrode, etc., depending on the situation.

[0400] In addition, in this specification, "electrode" or "wiring" does not limit the function of a component. For example, an "electrode" is sometimes used as a part of a "wiring", and vice versa. Furthermore, "electrode" and "wiring" also include a case where a plurality of "electrodes" or "wiring" are formed as one.

[0401] In addition, in this specification, etc., voltage and potential can be appropriately exchanged. Voltage refers to the potential difference from the reference potential. For example, when the reference potential is the ground voltage (ground voltage), voltage can be exchanged for potential. The ground potential does not necessarily mean 0V. Note that potential is relative, and the potential supplied to wiring, etc. sometimes changes according to the reference potential.

[0402] In this specification, the words "film" and "layer" may be interchanged depending on the situation or state. For example, "conductive layer" may be interchanged with "conductive film". Also, "insulating film" may be interchanged with "insulating layer".

[0403] In this specification, etc., a switch refers to an element having a function of controlling whether current flows by changing to a conductive state (on state) or a non-conductive state (off state). Alternatively, a switch refers to an element having a function of selecting and switching a current path.

[0404] In this specification, etc., for example, the channel length refers to the distance between the source and the drain in the area where the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in an on state) and the gate overlap or in the area where the channel is formed in a top view of the transistor.

[0405] In this specification, etc., for example, the channel width refers to the length of the region where the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in an on state) and the gate electrode overlap, or the portion where the source and drain electrodes face each other in the region where the channel is formed.

[0406] In this specification, etc., a node may be referred to as a terminal, wiring, electrode, conductive layer, conductor, impurity region, etc. depending on the circuit structure or device structure, etc. In addition, a terminal, wiring, etc. may also be referred to as a node.

[0407] In this specification, etc., "A and B are connected" means that A and B are electrically connected. Here, "A and B are electrically connected" means a connection that can transmit an electric signal between A and B when an object (element such as a switch, transistor element or diode, or a circuit including the element and wiring, etc.) exists between A and B. Note that the case where A and B are electrically connected includes the case where A and B are directly connected. Here, direct connection between A and B means a connection that can transmit an electric signal between A and B through wiring (or electrodes) etc. without passing through the above-mentioned object. In other words, direct connection means a connection that can be regarded as the same circuit diagram when expressed using an equivalent circuit. [Explanation of symbols]

[0408] 10: semiconductor device, 20: element layer, 21: transistor, 22: semiconductor layer, 30: element layer, 31: transistor, 32: semiconductor layer, 100: operation device, 110: register, 120: scan trigger, 121: selector, 122: trigger, 130: data holding circuit, 132: transistor, 133: transistor, 134: transistor, 135: capacitor, 200: operation device, 210: storage circuit, 211: operation circuit, 220: layer selection circuit, 221: write word line driver, 230: layer selection circuit, 231: read word line driver, 241: read circuit, 300: memory device, 310: storage layer.

Claims

1. A semiconductor device comprising: A first arithmetic device including a register; as well as a second computing device including a storage circuit, a layer selection circuit and a computing circuit, The first computing device and the second computing device are arranged in an element layer formed by stacking a plurality of second element layers on a first element layer. The first element layer is provided with a first transistor including silicon in a semiconductor layer having a channel formation region, The second element layer includes a second transistor including an oxide semiconductor in a semiconductor layer having a channel formation region. The register includes a trigger and a data holding circuit. The trigger and the operation circuit are arranged in the first element layer. The data holding circuit is provided in each of a plurality of the second element layers on the first element layer including the flip-flop, Furthermore, the storage circuit and the layer selection circuit are provided in each of the plurality of second element layers on the first element layer including the arithmetic circuit.

2. The semiconductor device according to claim 1, wherein an input terminal of the trigger is electrically connected to each of the output terminals of the data holding circuit, and an output terminal of the trigger is electrically connected to each of the input terminals of the data holding circuit, The data holding circuit has a function of holding data corresponding to a task executed by the first computing device by rendering the second transistor non-conductive.

3. The semiconductor device according to claim 1, The storage circuit includes a storage unit electrically connected to a write word line and a read word line. Furthermore, the layer selection circuit has a function of outputting a signal supplied to the write word line and the read word line.

4. The semiconductor device according to claim 1, wherein the storage circuits arranged in different second element layers each include weight data used in arithmetic processing based on a neural network, And the weight data input to the operation circuit is switched by the layer selection circuit.

5. The semiconductor device according to claim 1, The data holding circuit has a region overlapping with the flip-flop when viewed from a planar perspective.

6. The semiconductor device according to claim 1, The storage circuit has a region overlapping with the operation circuit when viewed from a planar perspective.

7. The semiconductor device according to claim 1, The oxide semiconductor includes In, Ga, and Zn.

8. The semiconductor device according to claim 1, The operation circuit has the function of performing product and sum operations.

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