Thermally stable graphene-containing laminates

Abstract

The present invention provides a graphene-containing laminate, the graphene-containing laminate comprising, in order: a substrate; a graphene layer structure; a first metal oxide layer formed of a first metal oxide, wherein the first metal oxide is a transition metal oxide; and a second metal oxide layer formed of a second metal oxide; wherein the thickness of the first metal oxide layer is 0.1 nm to 5 nm; and wherein the work function of the first metal oxide layer is 5 eV or more.

Description

[0001] The present invention relates to a graphene-containing laminate and a method for producing a graphene-containing laminate, as well as an electronic device comprising the laminate, in particular a Hall sensor. The graphene-containing laminate has an improved thermal stability relative to those known in the prior art, thus providing the use of the device at elevated temperatures and for extended periods of time, whereby the properties of the device remain sufficiently unchanged for reliable operation. More particularly, the graphene-containing laminate comprises a graphene layer structure having a first metal oxide layer formed of a transition metal oxide, followed by a second metal oxide layer, on the graphene layer structure.

[0002] Graphene is a leading two-dimensional material that is used in a wide range of products due to its excellent properties. The electronic properties of graphene are particularly remarkable and are used to produce electronic devices (especially microelectronic devices) that exhibit properties that are several orders of magnitude better than their non-graphene counterparts. Most notable are the uses of graphene in electronic devices and their component parts, including transistors, LEDs, photovoltaic cells, Hall effect sensors, diodes, electro-optic modulators (EOMs), etc.

[0003] Thus, various electronic devices incorporating graphene layer structures (monolayer or multilayer graphene) are known in the prior art to provide improvements in such devices relative to earlier devices and electronic products. These improvements include structural improvements through the use of thinner and lighter materials (which can result in flexible electronics), and performance improvements, such as increased electrical and thermal conductivity to allow for more efficient operation.

[0004] It is known to provide graphene layer structures with a range of different charge carrier concentrations, and low values ​​are useful for certain applications. By varying the growth conditions, the charge carrier concentration can be optimized. The inventors have found that the most effective method for producing high-quality graphene, in particular directly on a substrate providing a non-metallic surface suitable for subsequent use in an electronic device, is disclosed in WO 2017 / 029470 (the contents of which are incorporated herein by reference in their entirety).

[0005] One way to further reduce the charge carrier concentration is doping, which is known from WO 2017 / 029470. This method involves intentionally introducing dopants to reversely dope the graphene material and reduce the charge carrier concentration (e.g. n-doping a p-type graphene layer). The method of WO 2017 / 029470 involves directly doping graphene during production, for example by using CH3Br as a precursor. However, the presence of dopant atoms may lead to a reduction in carrier mobility due to scattering effects.

[0006] Another method for reducing the surface carrier concentration is disclosed in WO 2021 / 008938, which relates to a method for producing a polymer-coated graphene layer structure. The publication discloses forming graphene on a substrate by CVD (preferably using a method as disclosed in WO 2017 / 029470), the graphene having a first charge carrier concentration, and coating the graphene layer structure with a polymer composition to form an impermeable coating, the coated graphene having a surface charge carrier concentration that can be less than 10 12 cm -2 Such a low charge carrier concentration is achieved by using dopants in the coating to counteract the intrinsic doping of the graphene formed directly on the substrate by CVD.

[0007] GB 2601104 discloses forming an air and / or moisture barrier coating on graphene, the coating being formed from a composition comprising a precursor for an inorganic oxide, fluoride or sulfide barrier coating, the composition further comprising a dopant for doping the graphene. The charge carrier concentration of the coated graphene may be less than that of the uncoated graphene, less than 5×10 12 cm -2 , preferably less than 10 12 cm -2 .

[0008] Appl. Phys. Lett. 2010, 96, 213104 "Surface transfer holedoping of epitaxial graphene using MoO3 thin film", and US2013 / 048952 A1 with many authors as inventors, discloses hole doping of graphene by deposition of a MoO3 layer to provide about 1.0×10 13 cm -2 The hole density.

[0009] Scientific Reports, 2014, 4, 5380 "Metal Oxide Induced Charge Transfer Doping and Band Alignment of Graphene Electrodes for Efficient Organic Light Emitting Diodes" similarly involves a MoO3 layer on graphene and its incorporation into OLEDs. The purpose of MoO3 doping graphene is to improve sheet resistance, which is generally provided by increasing charge carriers such as holes. After storage in air, an increase in sheet resistance of about 10% was observed.

[0010] C.2019,142,468 "Gateless and reversible carrier density tunability inepitaxial graphene devices functionalized with chromium tricarbonyl" relates to devices with tunable charge carrier density, whereby the carrier density increases due to heat and returns to its low value within about 24 hours after the device is exposed to air.

[0011] Despite these advances in the prior art, a problem that remains with graphene-based electronic devices is that the properties of graphene are known to drift over time due to use. While the aforementioned advances have served to provide the desired electronic properties, most specifically charge carrier concentration, and to protect the graphene from atmospheric contamination, the inventors have found that the deposited materials used to act as a barrier themselves lead to doping of the graphene layer structure. As a result, the electronic properties of graphene are still subject to drift, and the inventors have sought to address this problem. Drift in charge carrier concentration is a significant problem in at least two key respects: (i) when the device is used at elevated temperatures (i.e., above ambient temperature, e.g., in excess of 50°C), whereby changes in charge carrier concentration are accelerated, and (ii) reliance on low charge carrier concentrations close to the Dirac point (e.g., less than 5×10 12 cm -2 , especially around 10 11 or 10 10 When approaching the Dirac point, small changes in charge carrier concentration are associated with much larger relative changes when compared to graphene, which has a much larger charge carrier concentration.

[0012] GB 2602119 relates to graphene Hall sensors and methods of manufacturing the same, and discloses patterning a dielectric on graphene by physical vapor deposition, and preferably also includes forming an airtight coating. UK Patent Application No. 2203362.5 similarly relates to graphene Hall sensors and methods of manufacturing the same, and discloses forming a dielectric on graphene by ALD and forming a second dielectric thereon, wherein the production uses photolithography. The contents of both documents are incorporated herein by reference in their entirety.

[0013] While these two references provide graphene Hall sensors of good quality, they can suffer from drift, especially at elevated temperatures, such that graphene is not thermally stable and the devices are not suitable for long-term use at temperatures exceeding 50 °C without inevitable drawbacks in performance or the need for more frequent calibration.

[0014] It is known that there are problems with depositing dielectric layers on the surface of pristine graphene (especially graphene grown directly on a substrate, which has not been transferred and therefore has significantly fewer defects) by ALD. Adv.Mater.Interfaces 2017, 4, 1700232 "Atomic Layer Deposition for Graphene Device Integration" and Appl.Sci.2020, 10 (7), 2440 "Atomic Layer Deposition of High-k Insulators on Epitaxial Graphene: A Review" provide an in-depth overview of growing dielectric layers on graphene by ALD. Dielectric layers are key components of electronic devices, and ALD is the preferred deposition method in various cases because it can provide films of uniform thickness. This review focuses on ALD on pristine graphene and on graphene that has been "surface-prepared" by, for example, using an organic polymer or self-assembled monolayer, a metal or metal oxide seed layer, or surface functionalization.

[0015] In order to solve the problem of such “non-in-situ” seeding, C.2019, 5(3), 53 “Recent Advances in Seeded and Seed-Layer-Free Atomic Layer Deposition of High-K Dielectrics on Graphene for Electronics” reviews more recent advances in ALD of high-k dielectrics on graphene using an “in-situ” seed layer.

[0016] ACS Nano 2010, 4, 5, 2667 “Epitaxial Graphene Materials Integration: Effects of Dielectric Overlayers on Structural and Electronic Properties” provides a study of depositing Al2O3, HfO2, TiO2, and Ta2O5 on epitaxial graphene by using seeds formed by metal deposition and oxidation before depositing the oxide by ALD.

[0017] The present invention seeks to provide improved graphene-containing laminates and related electronic devices incorporating the same which overcome or significantly reduce the various problems associated with the prior art or at least provide a commercially useful alternative.

[0018] According to a first aspect, the present invention provides a graphene-containing laminate comprising, in order:

[0019] substrate;

[0020] Graphene layer structure;

[0021] a first metal oxide layer formed of a first metal oxide, wherein the first metal oxide is a transition metal oxide; and

[0022] a second metal oxide layer formed of a second metal oxide;

[0023] wherein the thickness of the first metal oxide layer is 0.1 nm to 5 nm; and

[0024] The work function of the first metal oxide layer is 5 eV or greater.

[0025] According to a second aspect, the present invention also provides a method for forming a graphene-containing laminate, the method comprising:

[0026] providing a graphene layer structure on a substrate;

[0027] forming a first metal oxide layer on the graphene layer structure, wherein the first metal oxide layer is formed of a transition metal oxide and has a work function of 5 eV or more; and forming a second metal oxide layer on the first metal oxide layer, wherein the second metal oxide layer is formed of a second metal oxide;

[0028] The thickness of the first metal oxide layer is 0.1 nm to 5 nm.

[0029] The present disclosure will now be further described. In the following paragraphs, different aspects / embodiments of the present disclosure are defined in more detail. Unless clearly indicated to the contrary, each aspect / embodiment so defined can be combined with any other one or more aspects / embodiments. Specifically, any feature indicated as preferred or advantageous can be combined with any other one or more features indicated as preferred or advantageous. This is intended to be able to combine the features disclosed about the method with those disclosed about the graphene-containing laminate, and vice versa. Therefore, a graphene-containing laminate can be obtained by the method, and the method is also a method suitable for manufacturing the graphene-containing laminate described herein.

[0030] The present invention relates to graphene-containing laminates and methods of forming graphene-containing laminates. As described in more detail herein, the graphene-containing laminate includes a substrate having a graphene layer structure and a first metal oxide layer and a second metal oxide layer on the substrate. As such, there are no intermediate layers between any given layer referred to as being "on" another layer.

[0031] Graphene is a well-known two-dimensional material and refers to an allotrope of carbon, containing a monolayer of carbon atoms in a hexagonal lattice. As used herein, graphene refers to one or more layers of graphene. Therefore, the present invention relates to the formation of monolayer graphene and multilayer graphene. As used herein, graphene refers to a graphene layer structure, preferably having 1 to 10 monolayers of graphene. In many subsequent applications of graphene-containing laminates, one monolayer of graphene is particularly preferred (especially for Hall sensors). Therefore, the graphene layer structure is preferably a graphene monolayer. However, for certain applications where 2 or 3 layers of graphene may be preferred, multilayer graphene may be preferred.

[0032] The graphene layer structure is disposed on a substrate, preferably on a non-metallic surface of the substrate. Preferably, the surface is an electrically insulating surface (e.g., the substrate can be a silicon substrate with a silicon dioxide surface). The substrate can also be a CMOS wafer, which can be silicon-based and have associated circuits embedded in the substrate. The substrate can also include one or more layers (e.g., a region or channel of an embedded waveguide material (e.g., silicon nitride) suitable for EOM). In another example, the substrate can include a non-metallic layer and a conductive layer (e.g., a silicon on insulator (SOI) substrate, such as a silicon substrate with a silicon oxide layer) providing a non-metallic growth surface. The conductive layer can be used as a contact portion of an electronic device.

[0033] Preferably, the non-metal surface on which the graphene layer structure is arranged is silicon (Si), silicon carbide (SiC), silicon nitride (Si3N4), silicon dioxide (SiO2), sapphire (Al2O3), aluminum gallium oxide (AGO), hafnium dioxide (HfO2), zirconium dioxide (ZrO2), yttria-stabilized hafnium dioxide (YSH), yttria-stabilized zirconium oxide (YSZ), magnesium aluminate (MgAl2O4), yttrium orthoaluminate (YAlO3), titanate Strontium (SrTiO3), cerium oxide (Ce2O3), scandium oxide (Sc2O3), erbium oxide (Er2O3), magnesium difluoride (MgF2), calcium difluoride (CaF2), strontium difluoride (SrF2), barium difluoride (BaF2), scandium trifluoride (ScF3), germanium (Ge), hexagonal boron nitride (h-BN), cubic boron nitride (c-BN) and / or III / V semiconductors such as aluminum nitride (AlN) and gallium nitride (GaN). Preferably, the substrate comprises silicon, silicon nitride, silicon dioxide, sapphire, aluminum nitride, YSZ, germanium and / or calcium difluoride. Preferably, the non-metallic surface is sapphire, yttria-stabilized zirconium oxide or calcium difluoride, preferably wherein the sapphire is c-plane or r-plane sapphire (i.e., the surface provides a crystallographic c-plane or r-plane orientation). R-plane sapphire is preferred. In some embodiments, the substrate may be composed of one such material.

[0034] The thickness of the substrate is not limited and can be any conventional thickness typical of the electronic device substrate. Typically, the thickness of such a substrate is 300 microns to 2 mm thick. In some preferred embodiments, the thickness of the substrate can be reduced by thinning to obtain a thin graphene-containing laminate, and finally a thin electronic device (for example, as described in British Patent Application No. 2102218.1). Preferably, such thinning is carried out on a silicon substrate with a thin insulating layer on which a graphene layer structure is provided. Thinning can be carried out by etching and / or grinding (preferably etching after preliminary grinding) with an etchant. The substrate thickness after thinning can be 200 microns or less, preferably 100 microns or less. Such a step can also be referred to as "wafer back grinding" and advantageously provides a thin temperature-stabilized electronic device. It is not desirable to be bound by theory, and it is believed that thinner devices are more susceptible to temperature fluctuations, and therefore, a more thermally stable graphene layer structure is particularly advantageous for improving device life.

[0035] The graphene-containing laminate further comprises a first metal oxide layer formed of a first metal oxide, wherein the first metal oxide is a transition metal oxide, and a second metal oxide layer formed of a second metal oxide on the first metal oxide layer. The second metal oxide layer is a dielectric layer, which is preferably formed by ALD as described herein. Therefore, it should be understood that the second metal oxide is different from the first metal oxide and does not need to have a high work function, and therefore may have a work function of less than 6 eV, less than 5.5 eV, or even less than 5 eV. Preferably, the second metal oxide is selected from: Al2O3, ZnO, TiO2, ZrO2, HfO2, MgAl2O4, YSZ and mixtures thereof, preferably aluminum oxide (Al2O3) or hafnium dioxide (HfO2), which are particularly suitable for ALD.

[0036] The thickness of the first metal oxide layer is 0.1nm to 5nm. The inventor has found that this thickness can be used to control the doping degree of the graphene layer structure to reach the desired charge carrier concentration, so that a larger thickness leads to more p-doping. The desired nominal thickness can be achieved by using a quartz crystal microbalance (Quartz Crystal Microbalance, QCM) during formation, which provides an in-situ measurement of the amount of deposited material for technicians when implementing the method. Therefore, the thickness of the layer is the average thickness of the layer. At a thickness of 2nm or less, the layer usually forms a layer that can be referred to as a "seed" or "island", without forming a uniform layer. Then, those skilled in the art can easily determine the thickness using conventional techniques such as atomic force microscopy (AFM) as well. In general, a complete layer will be formed with a larger thickness (e.g., greater than 2nm), so that it is preferred that the maximum thickness of any part of the first metal oxide layer is not more than 5nm, or not more than 3nm.

[0037] A thickness of at least 0.5 nm, for example 0.5 nm to 3 nm, or 0.5 nm to 2 nm, has been found to be particularly suitable for providing the desired doping level and temperature stability. Preferably, the first metal oxide layer covers 50% or more and / or 90% or less of the area of ​​the graphene layer structure, leaving the remaining 50% or less and / or 10% or more of the area of ​​the graphene layer structure exposed during the formation of the second metal oxide layer. Preferably, the second metal oxide layer has a thickness of 5 nm or more and / or 250 nm or less, preferably 10 nm or more and / or 100 nm or less, and in some embodiments, less than 20 nm, or preferably 30 nm to 80 nm. Such a thickness provides a suitable conformal layer across the graphene layer structure and the first metal oxide.

[0038] The inventors have found that the layer added to the graphene surface can continue to affect its charge carrier concentration. Without wishing to be bound by theory, the inherent and inevitable defects and deficiencies in the layer formed by physical and / or chemical deposition methods initially lead to graphene doping and to both graphene doping over time through continued use. At higher temperatures, this can be significantly accelerated. However, as a suitably thin transition metal oxide layer of a seed layer, particularly a seed layer with a sufficiently high work function, a graphene-containing laminate with a thermally stable charge carrier concentration is provided in combination with a second metal oxide layer. This result is particularly unexpected because the "second metal oxide" alone provides minimal additional temperature stability.

[0039] Therefore, the work function of the first metal oxide layer is 5 eV or greater. Preferably, the work function of the first metal oxide layer is 5.5 eV or greater, preferably 6 eV or greater, more preferably 6.5 eV or greater. The work function of known and available metal oxides is generally not greater than 8 eV, or even 7.5 eV. For example, suitable transition metal oxides can be selected from: molybdenum oxide (e.g., MoO3, MoO2), chromium oxide (e.g., CrO3, Cr2O3), vanadium oxide (V2O5), tungsten oxide (WO3), nickel oxide (NiO), cobalt oxide (Co3O4), copper oxide (CuO), silver oxide (AgO), titanium oxide (TiO2), tantalum oxide (Ta2O5) and mixtures thereof; preferably molybdenum oxide (e.g., MoO3), chromium oxide (e.g., CrO3), vanadium oxide, tungsten oxide, nickel oxide and mixtures thereof; preferably molybdenum oxide, chromium oxide and mixtures thereof. Preferred metal oxides can be simply formed directly as oxides on the graphene layer structure, for example, by PVD.

[0040] Preferably, as a result of the combination of materials and manufacturing methods described herein, the graphene layer structure has a thickness of less than 5×1012 cm -2 , preferably less than 2×10 12 cm -2 , more preferably less than 10 12 cm -2 The charge carrier concentration is measured at ambient conditions (e.g., 25° C.) after fabrication. The graphene-containing laminate may be incorporated to fabricate a device, and thus the charge carrier concentration refers to the charge carrier concentration of the final fabricated laminate or device. In some embodiments, particularly for low temperature applications as described herein, the charge carrier density is preferably greater than 1×10 12 cm -2 , or greater than 3×10 12 cm -2 , and / or less than 8×10 12 cm -2 , for example, 4×10 12 cm -2 Up to 6×10 12 cm -2 .

[0043] Preferably, the graphene layer structure has a thermally stable charge carrier concentration and / or resistivity at temperatures above 50°C. That is, preferably, the charge carrier concentration and / or resistivity changes by less than 0.05% / day when measured at 125°C. It is also preferred that the charge carrier concentration and / or resistivity changes by less than 0.01% / day when measured at 25°C. Such measurements can be performed in ambient air with about 21% 02 by volume and / or a relative humidity of 85% or more, which is typical for automotive test standards. The measurement of the resistivity change is generally much simpler and indicates a change in the charge carrier concentration.

[0044] Preferably, the graphene layer structure has a thickness greater than 800 cm when measured at room temperature (e.g. 25° C.) using standard techniques due to its novel structure and manufacturing method. 2 / Vs, preferably greater than 1000cm 2 / Vs. It is desirable to have high mobility because it improves device performance. The presence of dopants usually inhibits electron mobility, so by avoiding the use of dopants, electron mobility can be improved. However, the inventors have found that doping graphene with a first metal oxide layer formed by a transition metal oxide with a work function greater than 5eV does not have a negative impact on mobility.

[0045] Another aspect of the present invention provides an electronic device, preferably a sensor, which includes a graphene-containing laminate as described herein. Examples of sensors that can benefit from being formed by such a graphene-containing laminate include Hall sensors, temperature sensors, and magnetoresistive sensors (as described in GB 2602119, British Patent Application No. 2106821.8, and British Patent Application No. 2115100.6, respectively, the contents of which are incorporated herein by reference as a whole) and current sensors. The electronic device includes one or more contacts in contact with the graphene layer structure. The contact is a standard component in the manufacture of an electronic device, which is well known to those skilled in the art and can be deposited during the manufacture of a graphene-containing laminate and / or after the manufacture of the laminate. The contact provides a connection point with an electronic circuit (for example, via a metal wire combined with the contact or by using a "flip chip" solder bump for soldering). Therefore, when installed in an electronic circuit and current is provided to the device, the electronic device is a functional device. As will be appreciated, large-area graphene-containing laminates (i.e., wafers having a diameter greater than or equal to 5 cm (2 inches), for example) can be processed to produce arrays of electronic devices on a common underlying substrate. These can then be cut into individual devices such that the electronic devices comprise portions of the larger graphene-containing laminate.

[0046] Typically, the contacts are metal contacts, such as those formed from chromium, titanium, aluminum, nickel, tungsten and / or gold. Typically, a plurality of contacts are provided that contact the graphene layer structure of the graphene-containing laminate. These may have edges and / or surfaces that contact the graphene layer structure. Such contacts may be deposited by PVD techniques such as electron beam evaporation.

[0047] The architecture provided by the layered structure of graphene, dielectric metal oxide and substrate is particularly suitable for incorporation into sensors, and most preferably Hall sensors, although with appropriate further processing it may also be used in other devices, such as transistors, capacitors, diodes (including LEDs and solar cells and resonant tunneling diodes), and photonic devices such as electro-optic modulators. As a result, the device is suitable for use at temperatures in excess of 50°C, preferably in excess of 100°C, whereby the graphene has a thermally stable charge carrier concentration as described herein.

[0048] According to another aspect, there is provided the use of the electronic device described herein at temperatures exceeding 50° C., preferably exceeding 100° C., and can be used at temperatures up to about 200° C. Thus, such a device can be used in high temperature applications, such as the automotive industry, where temperature stability at temperatures of about 125° C. is required, and the aerospace industry, where temperature stability at temperatures of about 180° C. is required.

[0049] In addition, the inventors have found that the final device can be used at low temperatures, such as below 120K. In particular, the present disclosure relates to the operation of the device at low temperatures not greater than: 20K, 10K, 5K, 4K, 3K, 2K, 1.5K or 1K. The device may also be suitable for use at millikelvin temperatures (i.e., less than 1K). In some embodiments, such as for Hall sensors, the device may exhibit a substantially linear temperature dependence over a wide magnetic field range, such as from -1T to +1T, from -7T to +7T, preferably from -14T to +14T. In some embodiments, when measured at -1T to +1T, the Hall sensor may exhibit a nonlinear error of the linear fit of 1% or less, preferably 0.1% or less.

[0050] In some embodiments, the device is capable of operating at a temperature of at least 1000°C, such as about 1350°C. A particularly preferred device for use at such extreme temperatures is a temperature sensor in which the resistance of the graphene layer structure is used to determine the temperature. The inventors have found that tungsten is a suitable metal contact for such a device, for example as a source contact and a drain contact. Typically, much higher temperatures (e.g., due to its very high melting point) are required during tungsten deposition in order to provide effective electrical contact between the metal and the graphene. As a result, it is preferred to deposit the tungsten metal contact in an air and moisture atmosphere, such as in a vacuum or inert atmosphere. Such a device includes a capping layer as described herein to completely encapsulate the graphene layer structure. For such a device to withstand such high temperatures, it is believed that the graphene layer structure must be completely encapsulated with an air and moisture barrier, otherwise the graphene may oxidize and decompose to release carbon monoxide, which may even occur under a nominal vacuum or inert atmosphere due to unavoidable trace amounts of oxygen and / or moisture.

[0051] The inventors have also found that electronic devices formed from and including the graphene-containing laminates of the present invention are particularly stable under applied stress and / or strain forces. In particular, the inventors have found that devices such as Hall sensors including such graphene-containing laminates exhibit substantially no deviation in baseline measurements (within observable background noise), even when forces sufficient to damage the underlying substrate / wafer are applied.

[0052] The stresses and strains that a device may experience at the chip level during the integration and packaging steps may cause changes in the performance of the device and its characteristics. Such packaging steps are conventional and well known, and include steps such as wafer dicing, die attachment, wire bonding (e.g., using ultrasonic power), and welding (providing thermal stress). Such changes may invalidate measurements made at the wafer level (or early in manufacturing) that can be used to screen working devices for electronic device production and provide data for the final data sheet. This may mean that measurements must be repeated, increasing complexity and cost. Permanent strains caused by thermal cycling within the device or printed circuit board assembly during operation will also affect strain at the chip level. Therefore, by reducing the impact of strain on device performance, this can help accuracy and / or reduce the complexity of any recalibration required for compensation and / or supporting electronic devices, and can eliminate this need entirely.

[0053] Thus, the graphene-containing laminates and resulting devices are particularly suitable for packaging that is critical to commercial electronic devices. The improved stability under stress and strain is also believed to be beneficial for packaged electronic devices such as packaged Hall sensors, as the devices are particularly suitable for use in automotive applications and / or at high temperatures as described herein, as the devices are more robust and resistant to the forces that they may be subjected to while in use and throughout their life cycle.

[0054] The first metal oxide layer can be deposited using conventional means in the art, such as PVD techniques, such as sputtering or evaporation (such as thermal evaporation). The first metal oxide layer is usually not formed by metal deposition and oxidation, because it is unreliable to completely oxidize the metal to provide a sufficiently high work function of 5eV or more for the metal oxide without causing undesirable oxidation and thus damaging the graphene layer structure below. In addition, such a method may introduce impurities that may otherwise act as a dopant, ultimately affecting stability at elevated temperatures. Similarly, the first metal oxide layer is usually not formed by a method using a metal oxide precursor (such as, in particular, a metal organic compound). That is, by techniques such as PVD, the first metal oxide layer can be directly formed as a metal oxide on the surface of the graphene layer structure.

[0055] The second metal oxide layer can be formed by sputtering, thermal evaporation, electron beam evaporation or ALD. Preferably, the second metal oxide layer is formed by atomic layer deposition (ALD). ALD is particularly preferred because the inventors were surprised to find that it further improves temperature stability. ALD is a technology known in the art. It includes at least two precursors reacting in a sequential, self-limiting manner. Due to the layer-by-layer growth mechanism, repeated cycles of individual precursors allow the growth of layers in a conformal manner (i.e., uniform thickness over the entire surface). Aluminum oxide is a particularly preferred coating material and can be formed by sequential exposure to trimethylaluminum (TMA) and an oxygen source, preferably one or more of water (H2O), O2 and ozone (O3).

[0056] Suitable precursors for providing the desired inorganic elements (eg, aluminum atoms or hafnium atoms for aluminum oxide and hafnium dioxide) are well known, commercially available, and are not particularly limited.

[0057] Preferably, metal alkyl, metal alkoxide or metal halide is used as the metal precursor by ALD (i.e., the metal alkyl is (R) n M, metal alkoxide is (RO) n M, and the metal halide is (X) n ALD is a process for forming a second metal oxide layer by using a metal halide such as a metal chloride (e.g., AlCl3 and HfCl4). Alternatively, a metal amide, a metal alkoxide, or an organometallic precursor may be used. Hafnium precursors include, for example, tetrakis(dimethylamino)hafnium(IV), tetrakis(diethylamino)hafnium(IV), hafnium(IV) tert-butoxide, and dimethylbis(cyclopentadienyl)hafnium(IV). Preferably, the barrier layer is aluminum oxide, and preferably, the aluminum precursor for ALD is a trialkylaluminum or a trialkoxyaluminum, such as trimethylaluminum, tris(dimethylamino)aluminum, tris(2,2,6,6-tetramethyl-3,5-heptanedione)aluminum, or tris(acetylacetonate)aluminum.

[0058] In some embodiments, ALD is performed at a relatively low deposition temperature of 80° C. or less, whereas it is quite typical in the art that ALD of metal oxides is performed at temperatures of 150° C. or more. For example, ALD can be performed at a temperature of 60° C. or less. In some preferred embodiments, ALD is performed at higher temperatures, such as up to 400° C., such as up to 300° C., such as from 100° C. to 200° C. Such temperatures may be preferred when using HO as a precursor to form the second metal oxide layer.

[0059] Preferably, the second metal oxide layer is formed by ALD using ozone as an oxygen precursor. Ozone is an oxygen precursor particularly suitable for low temperature ALD. Preferably, ozone is provided as a mixture with oxygen, preferably at a concentration (i.e., the concentration of the oxygen precursor) of 5 wt % to 30 wt %, more preferably 10 wt % to 20 wt %.

[0060] ALD, particularly when using ozone, can be used to functionalize any exposed portion of a graphene layer structure having a seed layer thereon (this typically occurs where the thickness is 2 nm or less). Ozone is also used to p-dope the graphene layer structure, although the inventors have found that ozone p-doping is not stable upon heating in the absence of a transition metal oxide. For example, an aluminum oxide layer deposited by ALD using ozone as a precursor onto bare graphene does not provide a thermally stable graphene-containing laminate.

[0061] As will be appreciated, the second metal oxide layer may be formed from two or more sublayers of metal oxide. For example, in some particularly preferred embodiments, the layer is formed from two sublayers of metal oxide, each sublayer being formed by ALD. In some preferred embodiments, the second metal oxide layer comprises two sublayers of metal oxide, each sublayer being formed from the same material, such as aluminum oxide. Each sublayer may be formed under different deposition conditions. Preferably, the lower sublayer, deposited before the upper sublayer and directly deposited on the first metal oxide layer, is formed by ALD at a lower temperature than the upper sublayer. Preferably, the lower sublayer is deposited at a temperature as described above for the second metal oxide layer and / or is deposited using ozone. The lower sublayer preferably has a thickness of 30 nm or less, preferably 20 nm or less.

[0062] The upper sublayer may be deposited at a temperature of 100°C or higher, preferably 120°C or higher. The upper sublayer may be formed using the same deposition conditions as the ALD of the capping layer. Preferably, the upper sublayer is formed using H2O as an oxygen precursor. Deposition by ALD at a higher temperature and / or using water as a precursor typically produces a dielectric layer having a higher density, which, without wishing to be bound by theory, is believed to provide a density sufficient to block moisture from entering the first sublayer. Therefore, even if the same material is used, the sublayer may be easily detected in the resulting product using conventional techniques in the art (e.g., cross-sectional scanning tunneling microscopy). The use of such a sublayer in the second metal oxide layer is particularly preferred for forming a graphene-containing laminate for forming a Hall sensor therefrom, because the appropriate doping of the lower sublayer from ozone deposition provides enhanced sensitivity while the upper sublayer provides a combined benefit of an enhanced barrier layer, thereby providing a highly sensitive (for sensing applications) and temperature-stable device in an atmosphere containing oxygen and moisture.

[0063] Without wishing to be bound by theory, it is believed that the use of at least two sub-layers for the first dielectric material layer may provide a more robust device. In particular, the inventors have found that bubbles may form, which may damage the "one-dimensional" connection between the graphene and the ohmic contact. These bubbles are believed to be caused by trapped gases remaining during the deposition process. This is a particular problem for devices used at non-ambient temperatures, whereby temperature cycles may induce the release of trapped gases. In particular, it has been observed that the use of ozone during ALD can cause such problems (although this may be a preferred embodiment in order to affect the charge carrier density, and the problem can be solved by using additional layers as described herein). Then, the method of producing the precursor may preferably include a degassing step to remove such gases during production. This may simply be caused by the deposition of another layer (e.g. an upper layer), which deposition occurs primarily before the photolithography step and the deposition of the ohmic contact (and the second dielectric material layer).

[0064] Preferably, the method further comprises forming a capping layer on the second metal oxide layer, wherein the capping layer is formed of a third metal oxide and / or metal nitride. The capping layer generally encapsulates the other layers and is used to protect the graphene layer structure from air and / or moisture contamination from the atmosphere, especially when the laminate is included in an electronic device. Therefore, a portion of the capping layer may also be provided on the peripheral portion of the edge of the substrate directly adjacent to the graphene layer structure. The third metal oxide is preferably selected from the group described for the second metal oxide, i.e., a group consisting of: Al2O3, ZnO, TiO2, ZrO2, HfO2, MgAl2O4, YSZ and mixtures thereof. Preferred metal nitrides that can be used for the capping layer include silicon nitride and aluminum nitride. For the second metal oxide layer, the capping layer is preferably formed by ALD. More preferably, H2O is used as an oxygen precursor for the capping layer and / or ALD is performed at a temperature of 100°C or higher (e.g., about 150°C). Low temperature ALD growth and / or ozone-based ALD growth of the second metal oxide layer is particularly suitable for growth and doping, but the inventors have found that it may be less dense than layers grown at higher temperatures and / or with H2O. Therefore, the cover layer can have a higher density than the second metal oxide layer and provide protection for the graphene layer structure in the final device from contamination from ambient air and moisture. Therefore, the cover layer is particularly preferred, although it will be understood that the benefits of thermal stability provided by the first metal oxide layer and the second metal oxide layer can be utilized, for example, when the product is packaged or otherwise maintained in an environment that is substantially free of air and / or moisture (e.g., under a vacuum or inert atmosphere).

[0065] Although the second metal oxide layer and the capping layer can be formed from the same metal oxide and / or formed under the same conditions, in some embodiments, the second metal oxide layer and the capping layer are formed from different materials and / or deposited under different conditions such that the formed layers are significantly different.

[0066] Preferably, the capping layer is formed at a temperature of 100°C or higher. The inventors have found that during manufacturing, especially when carried out at such elevated temperatures, there is an initial variation in charge carrier concentration during the different processing steps. Therefore, the method may include an annealing step, typically carried out under an inert atmosphere such as nitrogen, heated to 100°C or higher.

[0067] The covering layer can be simply understood as the third metal oxide layer, which will be used to encapsulate other layers of the laminate / device through the covering layer, and thus encapsulate the graphene layer structure and the first metal oxide layer and the second metal oxide layer. In particular, the method for manufacturing an electronic device including a laminate may include depositing additional steps of a contact portion in contact with the graphene layer structure. The graphene / first metal oxide / second metal oxide stack can be etched by a photolithography step or any other suitable etching step, so that the edge of the graphene layer structure is exposed. Typically, such a step is used to shape the stack as needed, and thus shape the graphene layer structure. Preferably, the thickness of the covering layer is 50nm or more. There is no specific upper limit, but the thickness of the covering layer is generally no more than 500nm, preferably less than 250nm.

[0068] Preferably, the graphene layer structure is formed directly on the substrate by CVD. Formation can be considered to be synonymous with synthesis, deposition, production and growth. CVD generally refers to a series of chemical vapor deposition techniques, each of which involves vacuum deposition to produce thin film materials such as two-dimensional crystalline materials such as graphene. Volatile precursors (those in gas phase or suspended in a gas) decompose to release the substances (carbon in the case of graphene) required to form the desired material. CVD as described herein is intended to refer to thermal CVD, so that the formation of graphene by the decomposition of a carbon-containing precursor is the result of thermal decomposition of the carbon-containing precursor.

[0069] Therefore, the physical transfer process is avoided by growing graphene directly on substrate by CVD.The physical transfer of graphene (usually from copper substrate physical transfer) introduces many defects, which has a negative impact on the physical properties and electronic properties of graphene.Therefore, those skilled in the art can easily determine whether the graphene layer structure and the laminate containing graphene by extension are the graphene layer structure and the laminate containing graphene of the graphene layer structure of CVD growth directly grown on the specific material using the conventional techniques in the art (such as atomic force microscope (AFM) and energy dispersion X-ray (EDX) spectrum).The graphene layer structure does not have copper pollution and does not have transfer polymer residues due to the absence of these materials in the process obtaining graphene substrate.In addition, such processing is usually not suitable for large-scale manufacturing (such as large-scale manufacturing on the CMOS substrate of a manufacturing plant).Inadvertent doping, particularly the inadvertent doping from catalytic metal substrate and etching solution, also can cause the production of graphene not as commercial production required as fully consistent between samples. However, through routine optimization on the part of those skilled in the art, the advantages of thermal stability at relatively low charge carrier concentrations can still be achieved for graphene provided by other means, but the process is laborious and therefore unsuitable for large-scale manufacturing. In other methods, graphene is grown by decomposition of the surface of a silicon carbide substrate. Although such methods avoid transfer, the substrate is generally more expensive than other substrates, and the resulting graphene may retain a certain degree of covalent bonding to the substrate, which is not desirable.

[0070] As will be appreciated, CVD grown graphene is formed on a surface of a substrate which may be referred to as the growth surface of the growth substrate. Preferably, the method involves forming graphene by thermal CVD such that decomposition is a result of heating a carbon-containing precursor. Preferably, the temperature of the growth surface during CVD is from 700°C to 1350°C, preferably from 800°C to 1250°C, more preferably from 1000°C to 1250°C. The inventors have found that such temperatures are particularly effective for providing graphene growth by CVD directly on the materials described herein.

[0071] Preferably, the CVD reaction chamber used in the method disclosed herein is a cold wall reaction chamber, wherein the heater connected to the substrate is the only heat source of the reaction chamber. In a particularly preferred embodiment, the CVD reaction chamber includes a close-coupled nozzle with a plurality of precursor inlet points or an array of precursor inlet points. Such a CVD device including a close-coupled nozzle may be known for MOCVD processes. Therefore, the method may alternatively be said to be carried out using an MOCVD reactor including a close-coupled nozzle. In either case, the nozzle is preferably configured to provide a minimum spacing of less than 100 mm, more preferably less than 25 mm, and even more preferably less than 10 mm between the surface of the substrate and the plurality of precursor inlet points. As will be understood, constant spacing means that the minimum spacing between the surface of the substrate and each precursor inlet point is substantially the same. Minimum spacing refers to the minimum spacing between the precursor inlet point and the substrate surface (i.e., the surface of the metal oxide layer). Therefore, such an embodiment relates to a "vertical" arrangement, wherein the plane including the precursor inlet point is substantially parallel to the plane of the substrate surface (i.e., the growth surface).

[0072] The precursor entry points into the reaction chamber are preferably cooled. The inlet or showerhead (when used) is preferably actively cooled by an external coolant (e.g. water) to maintain a relatively cool temperature at the precursor entry points so that the temperature of the precursor is less than 100°C, preferably less than 50°C as the precursor passes through the plurality of precursor entry points and into the reaction chamber. For the avoidance of doubt, the addition of precursor at a temperature above ambient does not constitute heating of the chamber, as this would dissipate temperature in the chamber and is part of the reason for establishing a temperature gradient in the chamber.

[0073] Preferably, a combination of sufficiently small spacing between the substrate surface and the plurality of precursor entry points and cooling of the precursor entry points, together with heating the substrate to the decomposition range of the precursor, produces a sufficiently steep thermal gradient extending from the substrate surface to the precursor entry points to allow graphene to form on the substrate surface. As disclosed in WO 2017 / 029470, very steep thermal gradients can be used to promote the formation of high quality and uniform graphene directly on a non-metallic substrate, preferably across the entire surface of the substrate. The diameter of the substrate can be at least 5 cm (2 inches), at least 15 cm (6 inches), or at least 30 cm (12 inches). Apparatus particularly suitable for the methods described herein includes Close Coupled Reactor and TurboDisk Reactor.

[0074] Therefore, in a particularly preferred embodiment, in which the method of the present invention relates to a method for forming a graphene layer structure on a growth surface by CVD using a method as disclosed in WO 2017 / 029470, the method comprises:

[0075] providing a growth substrate on a heated susceptor in a closely coupled reaction chamber having a plurality of cooled inlets arranged such that, in use, the inlets are distributed across the growth substrate and have a constant spacing relative to the substrate;

[0076] Cooling the inlet to below 100°C (i.e., to ensure that the precursor is cool when it enters the reaction chamber);

[0077] introducing a carbon-containing precursor in a gas phase and / or suspended in a gas through an inlet and into a closely coupled reaction chamber; and

[0078] heating the susceptor to achieve a growth surface temperature at least 50° C. above the decomposition temperature of the precursor to provide a sufficiently steep thermal gradient between the substrate surface and the inlet to allow graphene to form from carbon released from the decomposed precursor;

[0079] The constant spacing is less than 100 mm, preferably less than 25 mm, even more preferably less than 10 mm.

[0080] The most common carbon-containing precursor in the field of graphene growth is methane (CH4). Particularly preferred organic compounds for use as carbon-containing precursors are hydrocarbons, and methods of forming graphene therefrom by CVD are described in UK Patent Application No. 2103041.6, the contents of which are incorporated herein in their entirety.

[0081] Graphene formed directly on a substrate by such methods generally has a desired level of intrinsic n-doping, which is very suitable for being offset by the doping from the transition metal oxide layer with a high work function (the doping of which is related to the thickness of the layer). The "grown" doping level of the graphene can be fine-tuned by conventional changes in the growth process, for example by the choice of substrate, precursors and the choice of growth / decomposition temperature. However, the graphene layer structure can be provided on a non-metallic surface of a substrate from, for example, a copper foil by known transfer techniques, but this is less suitable for large-scale manufacturing due to the possible variability of the electronic properties of the graphene layer structure as provided on the substrate.

[0082] In view of the foregoing description, a preferred embodiment is an electronic device, in particular a sensor (e.g., a Hall sensor), comprising a graphene-containing laminate and one or more contacts (for a Hall sensor, typically four or more) in contact with the graphene layer structure of the graphene-containing laminate, the graphene-containing laminate comprising, in order:

[0083] a substrate (preferably sapphire, but according to other embodiments described herein may alternatively be a substrate formed of a silicon support having a non-metallic growth surface as described herein);

[0084] A graphene layer structure (preferably a graphene monolayer);

[0085] a first metal oxide layer formed of molybdenum oxide (i.e., first metal oxide) having a thickness of 0.5 nm to 3 nm (preferably 2 nm to 3 nm);

[0086] a second metal oxide layer (preferably having a thickness of 30 nm to 80 nm) formed of a second metal oxide;

[0087] A covering layer, which is on the second metal oxide layer and on the surrounding portion of the edge of the substrate directly adjacent to the graphene layer structure and encapsulates all of one or more contacts (although it may be etched to expose a portion of the contact to allow electrical connection (e.g., by wire bonding)), the covering layer is formed of a third metal oxide (preferably with a thickness of 50nm or greater).

[0088] The second metal oxide layer and the third metal oxide layer may both be formed of the same or different metal oxides (e.g., they may both be formed of aluminum oxide or hafnium oxide). In some embodiments, the second metal oxide layer may be formed of two or more sublayers of metal oxides, or may be formed of a single layer.

[0089] Therefore, a preferred method of forming a sensor, particularly the above-described sensor, is a method comprising:

[0090] providing a graphene layer structure on a substrate by CVD growth directly on the substrate;

[0091] forming a molybdenum oxide layer having a thickness of 0.5 nm to 3 nm on the graphene layer structure by PVD; and

[0092] forming a second metal oxide layer on the molybdenum oxide layer, wherein the second metal oxide layer is formed of the second metal oxide by ALD using H2O as an oxygen precursor at a temperature of 100°C or higher;

[0093] Patterning a stack formed of the graphene layer structure, the molybdenum oxide, and the second metal oxide (e.g., patterning into a cross shape suitable for a Hall sensor);

[0094] forming one or more contacts each in direct contact with an edge of the graphene layer structure (and on an adjacent portion of the substrate surface exposed by the patterning);

[0095] A capping layer is formed on the second metal oxide layer, all of the one or more contacts, and the surrounding exposed portion of the remaining exposed edge of the substrate directly adjacent to the graphene layer structure by ALD using H2O as an oxygen precursor at a temperature of 100°C or higher, wherein the capping layer is formed of a third metal oxide and / or metal nitride. Preferably, the method further comprises etching the capping layer to expose a portion of each of the one or more contacts.

[0096] The sensor may preferably be formed as part of an array of sensors on a common substrate.The method preferably further comprises packaging the electronic device by steps such as wafer dicing, die attach, wire bonding and molding to form a packaged sensor.

[0097] Attached photos

[0098] The invention will now be further described with reference to the following non-limiting drawings, in which:

[0099] Figure 1 A method of forming a graphene-containing laminate according to the present invention is shown.

[0100] Figure 2 A cross section of an electronic device including a graphene-containing laminate is shown.

[0101] Figure 3 A cross section of another electronic device including a graphene-containing laminate is shown.

[0102] Figure 4 is a graph of average drift rates of electronic devices according to the present invention at 20°C and 130°C and of comparative devices at 130°C.

[0103] Figure 5 is a graph showing the thermal stability of a plurality of graphene-containing laminates after several days at 130°C.

[0104] Figure 6 is a graph of device resistance versus time for two graphene Hall sensor devices according to the present invention.

[0105] Figure 7 is a graph of the Hall sensitivity of a Hall sensor device according to the invention versus temperature at three temperature rises.

[0106] Figure 8 is a SEM image of a Hall sensor according to one embodiment of the present invention.

[0107] Fig. 9 is a SEM image of a Hall sensor according to another embodiment of the present invention.

[0108] Fig.10is a SEM image of a Hall sensor according to another embodiment of the present invention.

[0109] Fig.11 is a graph of Hall voltage (V) versus time (seconds) measured for the Hall sensor when a force of 600 gf was intermittently applied.

[0110] Fig.12 is a plot of background Hall voltage (V) versus time (seconds) measured for the Hall sensor when no force is applied.

[0111] Fig.13 is a graph of the Hall voltage (V) measured for the Hall sensor versus time when a force of 8,500 gf is applied (top), and a related graph of the force (gf) applied at the same time (bottom).

[0112] Fig.14 Two graphs of simultaneously measured Hall voltages are provided, wherein the bottom graph is a graph of the Hall voltage (mV) measured for a Hall sensor versus time (seconds) when increasing forces (gf) are intermittently applied, and the top graph is a comparison graph of the background Hall voltage (μV) measured for an adjacent Hall sensor when no force is applied.

[0113] Figure 1 An exemplary method according to the invention is shown in cross section. First a sapphire substrate 105 having a graphene monolayer 110 thereon is provided. The graphene monolayer is preferably formed directly on the surface of the sapphire substrate 105 surface by thermal CVD in a previous step.

[0114] The method then involves depositing 205 a first metal oxide layer 115 formed of molybdenum oxide, specifically MoO3. The first metal oxide layer 115 has an average thickness of 0.1 nm to 5 nm (e.g., about 1 nm or about 2 nm), and the layer covers more than 50% of the surface area of ​​the graphene monolayer 110. A portion of the graphene monolayer remains exposed, and a second metal oxide 120 layer is deposited 210 thereon and on the first metal oxide layer 115 itself. The second metal oxide layer 120 is an aluminum oxide layer formed by ALD 210 using trimethylaluminum and ozone as precursors at a temperature below 60° C., preferably about 40° C. The cycle of trimethylaluminum and ozone is repeated until a thickness of about 15 nm is reached, thereby forming a graphene-containing laminate having a thermally stable charge carrier concentration.

[0115] In another preferred embodiment, the second metal oxide layer 120 is an aluminum oxide layer formed by ALD 210 using trimethylaluminum and H2O as precursors at a temperature above 100° C., such as about 150° C. Using this method, thicker ALD layers are preferred, and the thickness of the second metal oxide layer 120 can be greater than 50 nm, such as about 65 nm.

[0116] Figure 2 is a cross section of an exemplary Hall sensor 100 including a laminate containing graphene. Figure 1 As shown, the graphene-containing laminate is formed by a substrate 105, a graphene monolayer 110, a first metal oxide layer 115 and a second metal oxide layer 120. For the Hall sensor 100, the substrate 105 may preferably be an r-plane sapphire, thereby forming a graphene monolayer 110 on the r-plane growth surface of the substrate 105. In such an embodiment, the average thickness of the first metal oxide 115 may be about 1nm. In another preferred embodiment, the substrate 105 is a c-plane sapphire (and the first metal oxide 115 may be thicker, for example, 1nm to 5nm, for example, 2nm to 3nm). The graphene monolayer 110 and the first metal oxide layer 115 and the second metal oxide layer 120 have been etched and formed into a cross shape suitable for a Hall sensor. Such a shape is well known to those skilled in the art and is not particularly limited. At the far end of the graphene monolayer 110 etched by the graphene-containing laminate, metal contacts 125a and 125b, each of which contacts the edge of the graphene monolayer 110, are provided. The Hall sensor 100 also includes a capping layer 130 formed of, for example, aluminum oxide, which may also be formed by ALD using H2O as an oxygen precursor at a temperature of about 150°C until a thickness greater than 50 nm is reached. The capping layer 130 completely encapsulates the stack of the graphene monolayer 110, the first metal oxide layer 115, and the second metal oxide layer 120, including any edges of the graphene monolayer 110 that remain exposed due to etching (at Figure 2 125a and 125b). When the capping layer 130 is formed by ALD, the capping layer 130 may also encapsulate the metal contacts. Metal lines may be connected directly through the capping layer 130 to the contacts for connection to the electronic circuit, or the capping layer 130 may be etched to expose the contacts 125a and 125b. Alternatively, the patterned capping layer 130 may be deposited by PVD techniques, leaving a portion of the metal contacts 125a and 125b exposed for connecting the Hall sensor 100 to the electronic circuit. The charge carrier concentration of the final device 100 may be about 5×10 11 cm -2 to about 10 12 cm -2 .

[0117] Figure 3 is basically equivalent to Figure 2 A cross section of an exemplary preferred Hall sensor 300 of the Hall sensor 100 is shown. The Hall sensor 300 includes a graphene-containing laminate formed by a substrate 305, a graphene monolayer 310, a first metal oxide layer 315 (MoO3), and a second metal oxide layer. The difference is that the second metal oxide layer of the Hall sensor 300 is formed, for example, by ALD from two sublayers 320a, 320b each formed of aluminum oxide. The lower sublayer 320a is about 15nm thick and is formed by ALD using ozone at a temperature below 60°C. The upper sublayer 320b is about 65nm thick and is formed by ALD using H2O as a precursor at a temperature of about 150°C.

[0118] For the Hall sensor 100, the graphene monolayer 310 and the first metal oxide layer 315 and the second metal oxide layer 320a, 320b have been etched and formed into a cross shape suitable for the Hall sensor. At the far end of the graphene monolayer 310 where the graphene-containing laminate has been etched, metal contacts 325a and 325b are provided, each of which contacts the edge of the graphene monolayer 310. The Hall sensor 300 also includes a capping layer 330 formed of, for example, aluminum oxide, which can also be formed by ALD, but is formed at a temperature of about 150°C using H2O as an oxygen precursor until a thickness of more than 50 nm is reached.

[0119] Figure 3 The cross section of the device in is also representative of other electronic devices, such as temperature sensors. In one embodiment of such a device suitable for use at extremely high temperatures (eg, greater than 1000° C.), the metal contacts 125a and 125b are formed of tungsten.

[0120] Figure 4 is a graph of an average resistance drift rate in % / day of a Hall sensor device according to the present invention, the Hall sensor device including a MoO 3 doped seed layer and second and third metal oxide layers formed of Al 2 O 3 . Figure 4 The example data in show that the resistance of the graphene layer structure has minimal drift (typically less than 0.1% / day, with error bars showing standard deviation within a batch of devices) at both 20°C and 130°C. On the other hand, the reference Hall sensor device without the MoO3 layer shows a much larger drift of about 0.65% / day at 130°C.

[0121] Figure 5is a graph showing the thermal stability of various graphene-containing laminates after several days at 130° C. in an inert nitrogen atmosphere. The comparative graphene-containing laminates include a substrate, graphene, and a “second metal oxide layer” formed of Al 2 O 3 directly on the graphene (i.e., without a first transition metal oxide with a high work function; drawn with triangles). In the absence of such a layer, the measured carrier concentration is not thermally stable and increases rapidly to more than 5×10 12 cm -2 (in absolute terms) and continues to increase.

[0122] The first inventive graphene-containing laminate comprises a substrate, graphene, a first MoO3 layer and a second Al2O3 layer (drawn with circles). The second inventive graphene-containing laminate is based on the first inventive laminate and further comprises a third covering Al2O3 layer (drawn with diamonds). The inventive graphene-containing laminate comprising a MoO3-doped seed layer provides improved thermal stability for the graphene layer structure. After more than 4 or 5 days at 130°C, the carrier concentration remains below 2×10 12 cm -2 , and usually less than 10 12 cm -2 .

[0123] The inventive examples not including a capping layer showed an initial high carrier concentration that quickly stabilized to less than 2×10 12 cm -2 Although the sample may show initial changes when heated directly after fabrication, the sample typically stabilizes to the desired value within 1 day (e.g., within about 8 hours). With respect to the stability parameters discussed herein, these parameters are measured from the starting point 12 hours after fabrication of the final electronic component (e.g., Hall sensor) to ensure that this initial stabilization has been completed.

[0124] Figure 6 is a graph of the charge carrier concentration of graphene versus time (in days) for two Hall sensor devices according to the present invention. Device 1 was manufactured according to method 3, and device 2 was manufactured according to method 4. For both devices, the laminate was exposed to the atmosphere and chemicals before depositing the cover layer (i.e. after the photolithography process of the second metal oxide layer). After about 9 days, device 1 showed a change in the device resistance of about 10%, while device 2 showed a negligible change after the same period of time. Figure 6 It is shown that the second metal oxide layer formed from two sub-layers improves the stability of the final device.

[0125] Figure 7is a plot of Hall sensitivity versus temperature for three temperature ramps for a Hall sensor device fabricated according to Method 4. The data shows that the Hall sensitivity varies linearly over multiple temperature ramps up to about 180°C. The device was mounted on a hot plate and the Hall characteristics of the device were measured using the Van der Pauw method. The stage was heated and allowed to stabilize, and then multiple Hall measurements were taken and averaged. This process was repeated at different temperatures. Ramp 1 had a maximum temperature of 75°C, Ramp 2 had a maximum temperature of 130°C, and Ramp 3 had a maximum temperature of 180°C.

[0126] Figures 8 to 10 are SEM images of different embodiments of Hall sensor devices according to the present invention including a graphene-containing laminate as described herein. Each of these Hall sensors consists of a sapphire substrate shaped as a cross and a monolayer of graphene. Each sensor also includes a first metal oxide layer formed of MoO3 with a nominal thickness of about 1 nm on and across the monolayer of graphene. Each device includes a different second metal oxide layer, but has an equivalent aluminum oxide cover layer.

[0127] exist Figure 8 In the device, the second metal oxide layer formed on the first metal oxide layer is formed of aluminum oxide by ALD. Figure 8 The device includes Figure 8 The same ALD aluminum oxide layer (e.g., with the lower sublayer) but Fig. 9 The second metal oxide layer of the device is further formed by ALD from an additional aluminum oxide layer under different conditions (eg, as an upper sublayer formed by ALD using water as a precursor). Fig.10 Devices and Fig. 9 The device is identical to that of , except that the lower aluminum oxide sublayer is formed by evaporation.

[0128] As can be seen from the SEM images, the inventors have found that in some embodiments, blistering of graphene may occur. It was found that blistering became more pronounced during use of the device at elevated temperatures or low temperatures and associated temperature cycles to ambient temperatures. These bubbles are believed to be generated by trapped gases remaining during the deposition process. Blistering is not desirable due to the increased risk of damaging the contact between the graphene and the contact portion. Fig. 9 Adding a sub-layer to the second metal oxide layer is shown to reduce the incidence of such bubbles. Furthermore, by forming a lower sub-layer of the second metal oxide by evaporation, blistering is further reduced. Example

[0129] Method 1

[0130] According to the method of WO 2017 / 029470, a graphene monolayer was grown directly on the surface of a sapphire substrate. The graphene on sapphire was then used to make a Hall sensor device according to the method disclosed in GB 2602119, except that a MoO3 layer was first deposited across the graphene monolayer via thermal evaporation at ambient temperature until a nominal thickness of 1 nm as measured by QCM was reached.

[0131] A second metal oxide layer formed of Al2O3 was formed on the MoO3 layer as a Hall cross shape via electron beam evaporation through a shadow mask. Oxygen plasma etching removed the graphene that was not protected by the cross. Metal contacts were deposited via evaporation through a shadow mask (10nm Ti, via electron beam, and 200nm Au, via heat). The Al2O3 capping layer was deposited by ALD at 150°C until a thickness of about 65nm was reached. The devices were then singulated and wire bonded into LCC packages.

[0132] The packages were placed in a test socket in a controlled chamber heated to 130°C under ambient air atmosphere and the device resistance was monitored during the test time. The results are shown in Figure 4 The reference device has no MoO3 layer and is fabricated directly according to GB 2602119, and the resistance drift is measured by periodic Hall measurements at ambient temperature before and after heating.

[0133] Method 2

[0134] According to the method of WO 2017 / 029470, a graphene monolayer was grown directly on the surface of a sapphire substrate. A MoO3 layer was deposited across the graphene monolayer via thermal evaporation at ambient temperature until a nominal thickness of 1 nm as measured by QCM was reached.

[0135] An Al2O3 layer was deposited onto the MoO3 coated graphene monolayer by ALD using ozone as the oxygen precursor at a temperature of about 40° C. The cycle of oxygen and aluminum precursor was repeated until a thickness of about 15 nm was reached.

[0136] Optionally, a capping layer formed of Al 2 O 3 is deposited by ALD at a temperature of 150° C. until a thickness of about 65 nm is reached.

[0137] Samples of 1 cm2 were cut from the wafer (i.e., with or without a cover layer) for testing. The carrier concentration was measured initially (day 0) and then the samples were placed on a hot plate at approximately 130°C under nitrogen. The samples were periodically removed from the hot plate and the carrier concentration was measured. The results are shown in Figure 5 middle.

[0138] In a comparative example, a graphene monolayer was likewise grown directly on the surface of a sapphire substrate according to the method of WO 2017 / 029470. An Al2O3 layer was deposited onto the graphene monolayer by ALD using ozone as an oxygen precursor at a temperature of about 40°C. The cycle of oxygen and aluminum precursors was repeated again until a thickness of about 15 nm was reached. Comparative results are also shown in Figure 5 middle.

[0139] Method 3

[0140] According to the method of WO 2017 / 029470, a graphene monolayer was grown directly on the surface of a sapphire substrate. A MoO3 layer was deposited across the graphene monolayer via thermal evaporation at ambient temperature until a nominal thickness of 1 nm as measured by QCM was reached.

[0141] A 15 nm Al2O3 layer was deposited onto the MoO3 coated graphene monolayer by ALD using ozone as an oxygen precursor at a temperature of about 40°C. The Al2O3 layer and the underlying graphene were then patterned into a Hall sensor cross using conventional photolithography and etching techniques. Contacts were then deposited to contact the edges of the graphene. A capping layer formed of Al2O3 was deposited by ALD at a temperature of 150°C until a thickness of about 65 nm was reached.

[0142] The device and Figure 6 The same as device 1 in.

[0143] Method 4

[0144] According to the method of WO 2017 / 029470, a graphene monolayer was grown directly on the surface of a sapphire substrate. A MoO3 layer was deposited across the graphene monolayer via thermal evaporation at ambient temperature until a nominal thickness of 1 nm as measured by QCM was reached.

[0145] A 15 nm Al2O3 (sub)layer was deposited onto the MoO3 coated graphene monolayer by ALD at a temperature of about 40°C using ozone as an oxygen precursor, followed directly by the formation of an additional 65 nm Al2O3 (sub)layer, but at a temperature of about 150°C using H2O as a precursor. The Al2O3 layer and the underlying graphene were then patterned into a Hall sensor cross using conventional photolithography and etching techniques. Contacts were then deposited to contact the edges of the graphene. A capping layer formed of Al2O3 was deposited by ALD at a temperature of 150°C until a thickness of about 65 nm was reached.

[0146] The device and Figure 6 The same as device 2 in.

[0147] Stress testing

[0148] A Hall sensor of the present invention fabricated according to Method 3 above was used as the main Hall sensor for stress testing (except that the Hall sensor was formed with a 65 nm Al 2 O 3 layer on a MoO 3 coated graphene monolayer instead of a 15 nm layer).

[0149] The tests performed were based on a typical four-point bending stress test. The tests were performed on a sapphire wafer of approximately 3×3.5 cm by two anvils each having two rollers, with the rollers of the lower anvil spaced 2 cm apart. The tests were performed in a temperature-controlled environment at 22°C.

[0150] The Hall sensor leads were bonded to a flexible PCB that was secured to the wafer with adhesive. The leads were then soldered to the PCB and connected to a set of screw terminals on a perforated strip board that had attached contact pins for connecting test leads. The contact pins were connected to a Keithley 2450 power supply and a MiST test box using hook probes and alligator clip test leads, respectively.

[0151] The magnetic field is applied by a strong permanent magnet directly below the primary Hall sensor to be tested. A secondary unstressed (control) Hall sensor is positioned between the permanent magnet and the primary Hall sensor, approximately 1 cm below the wafer, and between the lower rollers of the anvil. The permanent magnet generates a Hall voltage of approximately 300 μV in the primary Hall sensor, as Fig.13 (top image) shown.

[0152] During the application of force (i.e. stress / strain or load) to the wafer, rotating current measurements were made on the MiST, and non-rotating current measurements were made with the Keithley. The data shown in the figure is based only on the MiST data. In all tests, the load rate was 8,000gf / sec. For the former measurement, the rotation rate was 1kHz, the dwell time was 150μs, the drive current was 200μA, and the gain was 100. The Keithley 2450 provided a non-rotating stable drive current of 200μA to the other on-wafer sensor, while also measuring the Hall voltage.

[0153] Repeated measurements were performed under a force nominally equal to a 600g weight (600gf) to stress the wafer while measuring the Hall voltage of both the primary and secondary sensors. The results are shown in Fig.11 and 12 (one for each of the primary and secondary sensors, recorded simultaneously). Both plots of the Hall voltage versus time show only background noise, indicating that no changes in the Hall voltage could be observed due to the forces and stresses applied during the test.

[0154] The test was repeated and conducted at a force nominally equal to 8.5 kg (8,500 gf). The results are shown in Fig.13 Figure 1 shows a schematic diagram of a wafer fracture pattern in which a change of about 20 μV (top graph) in the measured Hall voltage of the primary sensor can be observed under an applied force (bottom graph). The force / load distribution shown in the bottom graph clearly illustrates the discontinuity corresponding to the wafer fracture point.

[0155] The test was repeated by intermittently applying increasing forces, starting at 1800 gf and increasing in increments of 200 gf up to a force of 4,200 gf, and then starting at 4,500 gf and increasing in increments of 500 gf up to a force of 8,500 gf. The results are shown in Fig.14 (recordings were taken simultaneously for both the primary and secondary sensors). The data show that a similar change in Hall voltage of about 30 μV can be observed in the primary sensor at each application of force, with this change increasing slightly as the applied force increases. The reference signal of the secondary sensor (top graph) also changes significantly, indicating that the change in the signal may not be due to just the applied stress.

[0156] Crucially, the data showed that the applied stresses did not induce a baseline shift, and the long-term sensitivity of the wafer sensing element did not appear to be affected by the test (even after the wafer was cracked) and the sensor returned to normal operation. The change of about 20μV is believed to be related to the change in the angle of the sensor relative to the angle of the applied magnetic field during wafer bending. Similarly, a drift of about 7μV was observed in the reference sensor, but because the distance between the magnet and the secondary reference sensor was greatly reduced, no drift was observed in the primary sensor.

[0157] As used herein, unless the context clearly indicates otherwise, the singular form includes plural referents. The use of the term "comprising" is intended to be interpreted as including such features but not excluding other features, and is also intended to include options for features that are necessarily limited to those described. In other words, unless the context clearly indicates otherwise, the term also includes the limitations of "essentially consisting of..." (intended to mean that specific additional components may be present as long as they do not have a substantial effect on the basic characteristics of the features) and "consisting of..." (intended to mean that no other features may be included, so that if the components are expressed as percentages in their proportions, these components add up to 100%, while taking into account any unavoidable impurities).

[0158] It will be understood that, although the terms "first", "second", etc. can be used in this article to describe different elements, layers and / or parts, the elements, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, layer or part from another or additional element, layer or part. It will be understood that the term "on..." is intended to mean "directly on...", so that there is no intermediate layer between when a material is said to be "on" another material. For ease of description, spatially relative terms such as "under...", "under...", "under...", "lower", "above...", "above...", "above", etc. can be used herein to describe the relationship between an element or feature and another element or feature. It will be understood that the spatially relative terms are intended to cover the different orientations of the device in use or operation except for the orientation depicted in the drawings. For example, if the device described herein is turned over, the elements described as "under" or "below" other elements or features will be oriented to "above" or "above" other elements or features. Therefore, the example term "under..." can cover both above and below orientations. The device may be otherwise oriented and the spatially relative descriptors used herein interpreted accordingly.

[0159] The foregoing detailed description has been provided by way of illustration and example, and is not intended to limit the scope of the appended claims. Many variations in the presently preferred embodiments shown herein will be apparent to those of ordinary skill in the art and are still within the scope of the appended claims and their equivalents.

Claims

1. A graphene-containing laminate, comprising in order: substrate; Graphene layer structure; a first metal oxide layer formed of a first metal oxide, wherein the first metal oxide is a transition metal oxide; and a second metal oxide layer formed of a second metal oxide; wherein the thickness of the first metal oxide layer is 0.1 nm to 5 nm; and The work function of the first metal oxide layer is 5 eV or greater. 2 . The graphene-containing laminate according to claim 1 , wherein the work function of the first metal oxide layer is 5.5 eV or more, preferably 6 eV or more, and more preferably 6.5 eV or more.

3. The graphene-containing laminate according to claim 1 or claim 2, wherein the transition metal oxide is selected from the group consisting of molybdenum oxide, chromium oxide, vanadium oxide, tungsten oxide, nickel oxide and mixtures thereof, preferably molybdenum oxide, chromium oxide and mixtures thereof.

4. The graphene-containing laminate according to any preceding claim, further comprising a capping layer on the second metal oxide layer, wherein the capping layer is formed of a third metal oxide and / or metal nitride. 5 . The graphene-containing laminate according to claim 1 , wherein the first metal oxide layer has a thickness of 0.5 nm or more and / or 3 nm or less. 6 . The graphene-containing laminate according to claim 1 , wherein the first metal oxide layer covers 50% or more and / or 90% or less of the area of ​​the graphene layer structure.

7. The graphene-containing laminate according to any preceding claim, wherein the second metal oxide layer has a thickness of 5 nm or more and / or 250 nm or less, preferably 10 nm or more and / or 150 nm or less.

8. A method according to any preceding claim, wherein the second metal oxide is selected from the group consisting of: aluminium oxide, hafnium oxide and mixtures thereof.

9. A graphene-containing laminate according to any preceding claim, wherein the substrate comprises sapphire, YSZ or CaF2, preferably, wherein the sapphire is c-plane sapphire or r-plane sapphire.

10. The graphene-containing laminate according to any of the preceding claims, wherein the charge carrier concentration of the graphene layer structure is less than 5×10 12 cm -2 , preferably less than 2×10 12 cm -2 .

11. The graphene-containing laminate according to any of the preceding claims, wherein the graphene layer structure has a thermally stable electrical resistance at a temperature exceeding 50°C.

12. The graphene-containing laminate according to claim 11, wherein the resistance of the graphene layer structure changes by less than 0.05% / day when measured at 125°C, and preferably, wherein the resistance changes by less than 0.01% / day when measured at 25°C.

13. An electronic device, preferably a sensor, comprising a graphene-containing laminate according to any preceding claim, and one or more contacts in contact with the graphene layer structure.

14. An electronic device according to claim 13, wherein the device is intended for use at temperatures exceeding 50°C, preferably exceeding 100°C.

15. The electronic device according to claim 13 or claim 14, wherein the electronic device is a Hall sensor.

16. Use of an electronic device according to any one of claims 13 to 15 at a temperature exceeding 50°C.

17. A method of forming a graphene-containing laminate, the method comprising: providing a graphene layer structure on a substrate; forming a first metal oxide layer on the graphene layer structure, wherein the first metal oxide layer is formed of a transition metal oxide and has a work function of 5 eV or more; as well as forming a second metal oxide layer on the first metal oxide layer, wherein the second metal oxide layer is formed of a second metal oxide; Wherein, the thickness of the first metal oxide layer is 0.1 nm to 5 nm. The method according to claim 17 , wherein the first metal oxide is formed by PVD.

19. The method according to claim 17 or claim 18, wherein the second metal oxide layer is formed by atomic layer deposition (ALD), preferably at a temperature of 80°C or less, more preferably at a temperature of 60°C or less.

20. The method according to any one of claims 17 to 19, wherein the second metal oxide layer is formed by ALD using ozone as an oxygen precursor.

21. The method according to any one of claims 17 to 20, further comprising forming a capping layer on the second metal oxide layer, wherein the capping layer is formed of a third metal oxide and / or metal nitride, preferably wherein the capping layer has a thickness of 50 nm or greater, preferably wherein the capping layer is formed by ALD.

22. The method of claim 21, wherein the third metal oxide is selected from the group consisting of aluminum oxide, hafnium oxide, and mixtures thereof.

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