Verification method and device for arbitration mechanism of multi-channel I2C controller and storage medium
By setting up a main receiver and a main transmitter in the I2C communication system, and allowing multiple transmitters to send data at the same time for bus arbitration, the conflict problem when multiple hosts send data at the same time is solved, and the verification efficiency of the arbitration function is improved.
Patent Information
- Application Number
- CN202411706989.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-26
- Publication Date
- 2025-02-21
AI Technical Summary
In the existing I2C communication system, multiple hosts are prone to conflicts when sending data at the same time, resulting in a complex and inefficient bus arbitration verification environment.
By setting any I2C controller as the main receiver and other controllers as the main transmitter, the first transmitter is controlled to send data first, and the remaining transmitters send different data at the same time for bus arbitration, verifying that there will be no data on the data bus. Lost.
Simplifies the verification environment, improves the verification efficiency of multiple I2C controller arbitration functions, and improves the user experience.
Smart Images
Figure CN119493361A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of information processing, and in particular to a verification method, device and storage medium for a multi-channel I2C controller arbitration mechanism. Background Art
[0002] I2C (Inter-Integrated Circuit) technology is a widely used serial communication protocol. It was developed by Philips (now NXP Semiconductors) in the early 1980s and has become a standard that is widely used in various electronic devices and systems. The I2C arbitration mechanism ensures that there will be no conflicts during the communication process of IoT devices, thereby ensuring the accuracy and real-time nature of the data.
[0003] During the research process of conceiving and forming this application, the applicant discovered at least the following problems: in a multi-host I2C communication system, there may be two or more hosts on the bus sending data to the device at the same time. Since these hosts all use the two physical lines SDA and SCL, a conflict occurs. To resolve this conflict, bus arbitration must be performed, and the host determines whether it can have control of the bus. However, the verification environment of the bus arbitration method in the current I2C communication system is cumbersome and complex, often takes a lot of time, and is inefficient. Summary of the invention
[0004] In order to alleviate the above problems, the present application provides a verification method for a multi-channel I2C controller arbitration mechanism, wherein the data lines of the multi-channel I2C controllers are connected to each other on a data bus, and the clock lines of the multi-channel I2C are connected to each other on a clock bus; the verification method comprises: Set any I2C controller as a master receiver and each of the other I2C controllers as a master transmitter; Control any one of the main transmitters to be the first transmitter to first send data to the main receiver, and set the transmission data of each of the remaining main transmitters to be different data; Each remaining master transmitter is enabled to simultaneously send data to the master receiver for bus arbitration to verify that no data loss occurs on the data bus.
[0005] Optionally, the step of setting any one I2C controller as a master receiver and setting each of the other I2C controllers as a master transmitter includes: Set the device address configuration of the master receiver to the target address of the master transmitter.
[0006] Optionally, the step of controlling any one of the main transmitters to be the first transmitter to first send data to the main receiver, and setting the transmission data of each of the remaining main transmitters to different data includes: The operation interval of each master transmitter sending data is controlled to be zero to avoid delayed response.
[0007] Optionally, the step of causing each remaining master transmitter to simultaneously send data to the master receiver for bus arbitration to verify that no data loss occurs on the data bus includes: The bus idle detection time of each of the remaining master transmitters is set to the same value, so that each of the remaining master transmitters simultaneously sends data to the master receiver for bus arbitration.
[0008] Optionally, the step of setting the bus idle detection time of each of the remaining master transmitters to the same value so that each of the remaining master transmitters simultaneously sends data to the master receiver for bus arbitration includes: Each of the remaining master transmitters simultaneously enters bus idle timing after the first transmitter completes sending data, and simultaneously sends data to the data bus after timing for the same length of time to perform bus arbitration.
[0009] Optionally, the step of setting the detection bus idle time of each of the remaining master transmitters to the same value comprises: The bus idle detection time of each of the remaining master transmitters is set to a maximum value.
[0010] Optionally, the step of causing each remaining master transmitter to simultaneously send data to the master receiver for bus arbitration to verify that no data loss occurs on the data bus includes: The master receiver is changed to another I2C controller in turn, and the data bus is re-verified without data loss.
[0011] Optionally, the step of causing each remaining master transmitter to simultaneously send data to the master receiver for bus arbitration to verify that no data loss occurs on the data bus includes: The first transmitter that first sends data to the main receiver is replaced in turn with any other main transmitter to re-verify that no data loss occurs on the data bus.
[0012] The present application also provides a verification device for a multi-channel I2C controller arbitration mechanism, the verification device comprising a processor and a memory; The memory stores a computer program, and when the computer program is executed by the processor, the steps of the verification method of the multi-channel I2C controller arbitration mechanism as described above are implemented.
[0013] The present application also provides a storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the verification method of the multi-channel I2C controller arbitration mechanism as described above are implemented.
[0014] The present application provides a verification method, a verification device and a storage medium for a multi-channel I2C controller arbitration mechanism, which are based on the fact that multiple I2C controllers work on the same bus; any I2C controller is set as a master receiver, and each of the other I2C controllers is set as a master transmitter; any master transmitter is controlled to be the first transmitter to first send data to the master receiver, and the transmission data of each of the remaining master transmitters is set to different data; each of the remaining master transmitters simultaneously sends data to the master receiver for bus arbitration to verify that no data loss occurs on the data bus; the verification environment is simpler, and the arbitration functions of multiple I2C controllers can be quickly verified, thereby improving verification efficiency and user experience. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] The drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application. In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments are briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor.
[0016] Figure 1 This is a flow chart of a verification method for a multi-channel I2C controller arbitration mechanism according to an embodiment of the present application.
[0017] Figure 2 This is a bus connection diagram of multiple I2C controllers according to an embodiment of the present application.
[0018] The realization of the purpose, functional features and advantages of this application will be further described in conjunction with the embodiments and with reference to the accompanying drawings. The above-mentioned drawings have shown clear embodiments of this application, which will be described in more detail later. These drawings and textual descriptions are not intended to limit the scope of the concept of this application in any way, but to illustrate the concept of this application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION
[0019] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.
[0020] It should be noted that, in this article, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined by their explanation in the specific embodiment or further combined with the context of the specific embodiment.
[0021] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.
[0022] First embodiment The present application provides a verification method for an arbitration mechanism of a multi-channel I2C controller, wherein data lines of the multi-channel I2C controllers are interconnected on a data bus, and clock lines of the multi-channel I2C controllers are interconnected on a clock bus.
[0023] I2C (Inter-Integrated Circuit) technology is a widely used serial communication protocol, which is mainly used for short-distance data transmission between integrated circuits (ICs).
[0024] Figure 1 This is a flow chart of a verification method for a multi-channel I2C controller arbitration mechanism according to an embodiment of the present application.
[0025] like Figure 1 As shown, in one embodiment, the verification method includes: S10: Set any one of the I2C controllers as a master receiver, and set each of the other I2C controllers as a master transmitter.
[0026] IoT devices usually contain a large number of sensors and actuators, and these devices need to exchange data frequently. The I2C bus has been widely used in the field of IoT due to its simplicity and efficiency. I2C is a serial communication bus that uses two signal lines, the serial data line SDA and the serial clock line SCL, to communicate. At any time, there is only a simple master-slave relationship. According to the direction of data transmission, the host can be the master transmitter or the master receiver. In a multi-host I2C communication system, multiple hosts on the bus can send control and byte transmission data to other devices.
[0027] S20: Control any one of the master transmitters to be the first transmitter to first send data to the master receiver, and set the transmission data of each of the remaining master transmitters to be different data.
[0028] Exemplarily, each remaining master transmitter may wait when the first transmitter sends data, wait for the first transmitter to complete sending and enter the bus idle state and time out, and then send different data to the data bus at the same time.
[0029] S30: each of the remaining master transmitters simultaneously sends data to the master receiver for bus arbitration to verify that no data loss occurs on the data bus.
[0030] During the operation of the I2C bus, there may be two or more hosts sending data to the device at the same time. Since these hosts all use the two physical lines SDA and SCL, this will cause a conflict. To resolve this conflict, bus arbitration is required so that each host can determine whether it can have control of the bus.
[0031] In the process of bus arbitration, it is divided into synchronization of SCL line and arbitration of SDA line, both of which are expressed as line "AND". For SCL line, when multiple hosts want to control the bus clock, as long as there is a host that wants to control the bus to be low at the current moment, SCL will be low level, that is, 0&1 = 0. Only when all hosts want to control the bus to be high level, SCL will be high, that is, 1&1 = 1. For SDA line, it has the same logic as SCL. At the same time, after the host sends 1 bit of data, it will compare the data on the bus with the data it wants to send. If the data on the bus is the same as the data it wants to send, it will continue to send. If it detects that the data on the bus is different from the data it sends, it will exit the bus competition. This ensures that the data on the bus will not be lost.
[0032] The present application provides a verification method, a verification device and a storage medium for a multi-channel I2C controller arbitration mechanism. The embodiments are based on the fact that multiple I2C controllers work on the same bus; any I2C controller is set as a master receiver, and each of the other I2C controllers is set as a master transmitter; any master transmitter is controlled to be the first transmitter to first send data to the master receiver, and the transmission data of each of the remaining master transmitters is set to different data; each of the remaining master transmitters simultaneously sends data to the master receiver for bus arbitration to verify that no data loss occurs on the data bus; the verification environment is simpler, and the arbitration functions of multiple I2C controllers can be quickly verified, thereby improving verification efficiency and user experience.
[0033] Optionally, the step of setting any one I2C controller as a master receiver and setting each of the other I2C controllers as a master transmitter includes: Set the device address configuration of the master receiver to the target address of the master transmitter.
[0034] Exemplarily, the slave controller may be a master receiver, and the host controller may be a master transmitter. The device address of the I2C slave controller may be set, and the address may be configured as the target address for the host controller to send data.
[0035] Optionally, the step of controlling any one of the main transmitters to be the first transmitter to first send data to the main receiver, and setting the transmission data of each of the remaining main transmitters to different data includes: The operation interval of each master transmitter sending data is controlled to be zero to avoid delayed response.
[0036] Exemplarily, the operations of sending data can be controlled to be close and without any delayed response operations in between, so that when the first transmitter is controlled to send data, other main transmitters receive the request to send data at this time, but detect that there is a host on the bus sending data, and thus enter a waiting state.
[0037] Optionally, the step of causing each remaining master transmitter to simultaneously send data to the master receiver for bus arbitration to verify that no data loss occurs on the data bus includes: The bus idle detection time of each of the remaining master transmitters is set to the same value, so that each of the remaining master transmitters simultaneously sends data to the master receiver for bus arbitration.
[0038] Exemplarily, setting the detection bus idle time to the same value can enable other master transmitters to simultaneously enter the data transmission state after waiting for the same length of time after the first transmitter completes sending data.
[0039] Optionally, the step of setting the bus idle detection time of each of the remaining master transmitters to the same value so that each of the remaining master transmitters simultaneously sends data to the master receiver for bus arbitration includes: Each of the remaining master transmitters simultaneously enters bus idle timing after the first transmitter completes sending data, and simultaneously sends data to the data bus after timing for the same length of time to perform bus arbitration.
[0040] Exemplarily, after the first transmitter completes sending data, other master transmitters may simultaneously enter the data sending state after waiting for the same length of time, thereby entering the bus arbitration state.
[0041] Optionally, the step of setting the detection bus idle time of each of the remaining master transmitters to the same value comprises: The bus idle detection time of each of the remaining master transmitters is set to a maximum value.
[0042] The I2C host controller is set to detect the bus idle time as the maximum value, so that each master transmitter can obtain sufficient detection and response time, so that the bus system has sufficient stability during the verification process.
[0043] Optionally, the step of setting the detection bus idle time of each of the remaining master transmitters to the same value comprises: The bus idle detection time of each of the remaining master transmitters is set to a minimum value.
[0044] Setting the I2C host controller to detect the bus idle time to the minimum value can obtain the minimum system response time and improve the system verification efficiency.
[0045] Optionally, the step of causing each remaining master transmitter to simultaneously send data to the master receiver for bus arbitration to verify that no data loss occurs on the data bus includes: The master receiver is changed to another I2C controller in turn, and the data bus is re-verified without data loss.
[0046] Exemplarily, the main receiver is replaced and re-verified, so that arbitration verification can be performed on the original main receiver to ensure that the arbitration function of the system is normal.
[0047] Optionally, the step of causing each remaining master transmitter to simultaneously send data to the master receiver for bus arbitration to verify that no data loss occurs on the data bus includes: The first transmitter that first sends data to the main receiver is replaced in turn with any other main transmitter to re-verify that no data loss occurs on the data bus.
[0048] Exemplarily, exemplary, the first transmitter is replaced and re-verified, so that the arbitration verification can be performed on the original first transmitter to ensure that the arbitration function of the system is normal.
[0049] Second embodiment The present application also provides a verification device for a multi-channel I2C controller arbitration mechanism, the verification device comprising a processor and a memory; The memory stores a computer program, and when the computer program is executed by the processor, the steps of the verification method of the multi-channel I2C controller arbitration mechanism as described above are implemented.
[0050] Figure 2 This is a bus connection diagram of multiple I2C controllers according to an embodiment of the present application.
[0051] like Figure 2 In one embodiment, the verification device of the multi-channel I2C controller arbitration mechanism includes at least four I2C controllers. During arbitration verification, a verification environment is first prepared. The required verification environment is that four or more I2C controllers are integrated in a SOC, and the SDA and SCL lines of these I2C controllers are connected accordingly.
[0052] Assume that there are four I2C controllers to be verified: the first controller A, the second controller B, the third controller C, and the fourth controller D. Configure the first controller A, the second controller B, and the third controller C as the host mode, and configure the fourth controller D as the slave mode. (For more than four controllers, only one needs to be selected as the slave mode, and the rest are configured as the host mode).
[0053] Set the I2C host controller to detect the bus idle time to the maximum value, set the device address of the I2C slave controller, and configure the address as the target address of the host.
[0054] After all controls are initialized, the first controller A, the second controller B, and the third controller C are configured to send data to the fourth controller D respectively, and the data sent by the second controller B and the third controller C need to be configured differently (the software controls the data sending operations to be close and there should be no delayed response operations in between, so that when the first controller A is controlled to send data, the second controller B and the third controller C receive the request to send data at this time, but detect that there is a host sending data on the bus. The second controller B and the third controller C will enter the bus idle timing after the first controller A completes the sending. At this time, the two controllers are timing at the same time, and the next data will be sent at the same time, that is, arbitration will occur).
[0055] By following the above sequence, the arbitration function verification of the second controller B and the third controller C controlled by I2C can be completed. Next, the roles can be changed to verify other controllers in a loop. For example, the third controller C can be selected as a slave, and the first controller A, the second controller B, and the fourth controller D can be configured as the host mode. The second controller B sends data first, and the first controller A and the fourth controller D send data immediately afterwards, and the arbitration function verification of the first controller A and the fourth controller D can be completed.
[0056] Third embodiment The present application also provides a storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the verification method of the multi-channel I2C controller arbitration mechanism as described above are implemented.
[0057] The present application provides a verification method, a verification device and a storage medium for a multi-channel I2C controller arbitration mechanism, which are based on the fact that multiple I2C controllers work on the same bus; any I2C controller is set as a master receiver, and each of the other I2C controllers is set as a master transmitter; any master transmitter is controlled to be the first transmitter to first send data to the master receiver, and the transmission data of each of the remaining master transmitters is set to different data; each of the remaining master transmitters simultaneously sends data to the master receiver for bus arbitration to verify that no data loss occurs on the data bus; the verification environment is simpler, and the arbitration functions of multiple I2C controllers can be quickly verified, thereby improving verification efficiency and user experience.
[0058] It should be noted that in the present application, step codes such as S10, S20, etc. are used for the purpose of expressing the corresponding content more clearly and concisely, and do not constitute a substantial limitation on the sequence. When implementing the step, those skilled in the art may execute S20 first and then S10, etc., but these should all be within the scope of protection of the present application.
[0059] In the embodiments of the system and storage medium provided in the present application, all technical features of any of the above-mentioned method embodiments may be included, and the expanded and explained contents of the specification are basically the same as those of the above-mentioned method embodiments, and will not be repeated here.
[0060] The embodiment of the present application further provides a computer program product, which includes a computer program code. When the computer program code runs on a computer, the computer executes the methods in the above various possible implementation modes.
[0061] An embodiment of the present application also provides a chip, including a memory and a processor, the memory is used to store a computer program, and the processor is used to call and run the computer program from the memory, so that a device equipped with the chip executes the methods in various possible implementation modes as described above.
[0062] It is understood that the above scenarios are only examples and do not constitute a limitation on the application scenarios of the technical solutions provided in the embodiments of the present application. The technical solutions of the present application can also be applied to other scenarios. For example, it is known to those skilled in the art that with the evolution of the system architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.
[0063] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.
[0064] The steps in the method of the embodiment of the present application can be adjusted in order, combined and deleted according to actual needs.
[0065] The units in the device of the embodiment of the present application can be merged, divided and deleted according to actual needs.
[0066] In the present application, the same or similar terminology concepts, technical solutions and / or application scenario descriptions are generally described in detail only the first time they appear. When they appear again later, they are generally not repeated for the sake of brevity. When understanding the technical solutions and other contents of the present application, for the same or similar terminology concepts, technical solutions and / or application scenario descriptions that are not described in detail later, reference can be made to the previous related detailed descriptions.
[0067] In the present application, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.
[0068] The various technical features of the technical solution of the present application can be arbitrarily combined. In order to make the description concise, not all possible combinations of the various technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of the present application.
[0069] The above are only preferred embodiments of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.
Claims
1. A verification method for a multi-channel I2C controller arbitration mechanism, characterized in that: The data lines of the multiple I2C controllers are connected to each other on a data bus, and the clock lines of the multiple I2C controllers are connected to each other on a clock bus; the verification method comprises: Set any I2C controller as a master receiver and each of the other I2C controllers as a master transmitter; Control any one of the main transmitters to be the first transmitter to first send data to the main receiver, and set the transmission data of each of the remaining main transmitters to be different data; Each remaining master transmitter is enabled to simultaneously send data to the master receiver for bus arbitration to verify that no data loss occurs on the data bus.
2. A verification method for a multi-channel I2C controller arbitration mechanism according to claim 1, characterized in that: The step of setting any I2C controller as a master receiver and setting each of the other I2C controllers as a master transmitter comprises: Set the device address configuration of the master receiver to the target address of the master transmitter.
3. A verification method for a multi-channel I2C controller arbitration mechanism according to claim 2, characterized in that: The step of controlling any one of the main transmitters to be the first transmitter to first send data to the main receiver, and setting the transmission data of each of the remaining main transmitters to different data comprises: The operation interval of each master transmitter sending data is controlled to be zero to avoid delayed response.
4. A verification method for a multi-channel I2C controller arbitration mechanism according to claim 3, characterized in that: The step of causing each remaining master transmitter to simultaneously send data to the master receiver for bus arbitration to verify that no data loss occurs on the data bus includes: The bus idle detection time of each of the remaining master transmitters is set to the same value, so that each of the remaining master transmitters simultaneously sends data to the master receiver for bus arbitration.
5. A verification method for a multi-channel I2C controller arbitration mechanism according to claim 4, characterized in that: The step of setting the detection bus idle time of each of the remaining master transmitters to the same value so that each of the remaining master transmitters simultaneously sends data to the master receiver for bus arbitration comprises: Each of the remaining master transmitters simultaneously enters bus idle timing after the first transmitter completes sending data, and simultaneously sends data to the data bus after timing for the same length of time to perform bus arbitration.
6. A verification method for a multi-channel I2C controller arbitration mechanism according to claim 5, characterized in that: The step of setting the detection bus idle time of each of the remaining master transmitters to the same value comprises: The bus idle detection time of each of the remaining master transmitters is set to a maximum value.
7. A verification method for a multi-channel I2C controller arbitration mechanism according to any one of claims 1 to 6, characterized in that: The step of causing each remaining master transmitter to simultaneously send data to the master receiver for bus arbitration to verify that no data loss occurs on the data bus includes: The master receiver is changed to another I2C controller in turn, and the data bus is re-verified without data loss.
8. A verification method for a multi-channel I2C controller arbitration mechanism according to any one of claims 1 to 6, characterized in that: The step of causing each remaining master transmitter to simultaneously send data to the master receiver for bus arbitration to verify that no data loss occurs on the data bus includes: The first transmitter that first sends data to the main receiver is replaced in turn with any other main transmitter to re-verify that no data loss occurs on the data bus.
9. A verification device for a multi-channel I2C controller arbitration mechanism, characterized in that: The verification device includes a processor and a memory; The memory stores a computer program, and when the computer program is executed by the processor, the steps of the verification method of the multi-channel I2C controller arbitration mechanism according to any one of claims 1 to 8 are implemented.
10. A storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by the processor, the steps of the verification method of the multi-channel I2C controller arbitration mechanism according to any one of claims 1 to 8 are implemented.