Processing method and device of serial peripheral interface equipment

Abstract

The invention provides a processing method and device for serial peripheral interface equipment. The processing method of the serial peripheral interface device comprises the steps that a PCIE device driver and an SPI device driver are arranged on a driver layer, the PCIE device driver comprises an SPI controller driver, the SPI controller driver comprises a sequence used for storing information of multiple SPI devices supported by the SPI controller driver, and the sequence is configured to allow the information of the SPI devices to be connected to be added; the SPI device driver obtains information of a connected target SPI device, and determines whether the sequence has information of the SPI device matched with the information of the target SPI device or not; and in response to the information of the SPI device matched with the information of the target SPI device in the sequence, generating a device node corresponding to the target SPI device in an application layer. The processing method provided by the embodiment of the invention is good in expansibility and high in universality, and is beneficial to improving the program burning efficiency.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a method and apparatus for processing a serial peripheral interface device. Background Art

[0002] Field programmable gate array (FPGA) works as a peripheral component interconnect express (PCIE) device connected to the host, which can complete high-speed and reliable data transmission. Since FPGA is based on static random access memory, the program will be lost when the power is off. After power is on, the program needs to be reloaded from the external storage medium to achieve normal operation. The medium for storing the program is generally a serial peripheral interface (SPI) flash memory. There are two main methods for burning FPGA programs in existing SPI Flash: using the official burning tool on the computer side, burning the program through the joint test action group (JTAG) interface, and developing a dedicated program burning system.

[0003] Using the official burning software and connecting the JTAG interface for burning requires opening the chassis on site, which is inconvenient and inefficient. Dedicated program burning systems are generally developed for a single SPI Flash, integrating the application environment, PCIE driver, SPI controller driver, and SPI device driver on the host computer. If the SPI Flash needs to be replaced for various reasons, the host computer and driver will need to be changed, increasing the time cost and maintenance cost of software development. Summary of the invention

[0004] The present application provides a method and apparatus for processing a serial peripheral interface device. The following introduces various aspects involved in the present application.

[0005] In a first aspect, the present application provides a method for processing a serial peripheral interface device, comprising: setting a quick peripheral interconnect standard PCIE device driver and a serial peripheral interface SPI device driver at a driver layer, the PCIE device driver including an SPI controller driver, the SPI controller driver including a sequence for storing information of multiple SPI devices supported by it, and the sequence being configured to allow the addition of information of the SPI device to be connected; the SPI device driver obtains information of a connected target SPI device, and determines whether the sequence contains information of the SPI device that matches the information of the target SPI device based on the information of the target SPI device; in response to the sequence containing information of the SPI device that matches the information of the target SPI device, generating a device node corresponding to the target SPI device at an application layer.

[0006] In a second aspect, the present application provides a processing device for a serial peripheral interface device, comprising: a setting module, used to set a quick peripheral interconnect standard PCIE device driver and a serial peripheral interface SPI device driver at a driver layer, the PCIE device driver includes an SPI controller driver, the SPI controller driver includes a sequence for storing information of multiple SPI devices supported by it, the sequence is configured to allow the addition of information of the SPI device to be connected, the SPI device driver obtains information of a connected target SPI device, and determines whether the sequence contains the SPI device that matches the information of the target SPI device based on the information of the target SPI device; a generation module, used to generate a device node corresponding to the target SPI device at an application layer in response to the SPI device that matches the information of the target SPI device in the sequence.

[0007] In a third aspect, the present application provides a processing device for a serial peripheral interface device, comprising: a memory for storing code; and a processor connected to the memory for executing the code stored in the memory so that the processing device executes the method described in the first aspect.

[0008] In a fourth aspect, the present application provides a non-volatile computer-readable storage medium, which stores a computer program, and when the computer program is executed by a processor, it can implement the method described in the first aspect.

[0009] In a fifth aspect, the present application provides a computer program product, which, when executed on an electronic device, enables the electronic device to implement the method described in the first aspect.

[0010] In the embodiment of the present application, a PCIE device driver and a SPI device driver are set in the driver layer of the Linux framework system, and the PCIE device driver includes an SPI controller driver, and the SPI controller driver includes a sequence for storing information of multiple SPI devices supported by it. The SPI device driver matches the SPI device supported by the SPI controller driver in the sequence according to the information of the target SPI device obtained, and generates a device node corresponding to the target SPI device in the application layer. In the embodiment of the present application, when it is necessary to use other types of SPI devices (such as Flash) in addition, the required SPI device variables can be added to the sequence driven by the SPI controller. In this way, the SPI device can be accessed at the application layer, and the operation is simple, and there is no need to modify the application layer code for the second time, and the scalability is good and the versatility is strong. In the embodiment of the present application, the SPI Flash burns the FPGA program without disassembling the chassis, which is convenient to operate and helps to improve the efficiency of the burning program. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in describing the embodiments of the present application.

[0012] Figure 1 It is a flowchart of a processing method for a serial peripheral interface device provided in an embodiment of the present application.

[0013] Figure 2 It is a schematic diagram of the system framework of the Linux system provided in the embodiment of the present application.

[0014] Figure 3 yes Figure 1 A flowchart of a possible implementation of the method.

[0015] Figure 4 yes Figure 3 A flowchart of a possible implementation method of step S3090 is shown.

[0016] Figure 5 It is a schematic diagram of the composition of a processing device of a serial peripheral interface device provided in an embodiment of the present application.

[0017] Figure 6 It is a schematic diagram of the composition of another processing device of a serial peripheral interface device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0018] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The same or similar reference numerals are used in the drawings to represent the same or similar modules. It should be understood that the drawings are only schematic, and the protection scope of the present application is not limited thereto.

[0019] First, the application scenarios and related professional terms involved in the embodiments of the present application are introduced.

[0020] Peripheral Component Interconnect Express (PCIE) is a high-speed serial computer expansion bus used to connect peripherals such as graphics cards, hard drives, and network cards. It is also used between chips. PCIE is a bus standard for connecting computer motherboards and external devices. PCIE devices refer to devices connected to the motherboard through the PCIE bus.

[0021] Field Programmable Gate Array (FPGA) is a product that is further developed based on programmable devices such as programmable array logic and general array logic. FPGA uses basic hardware such as random access memory (RAM), logic units, multipliers, etc., and combines hardware description language programming to realize chip-specific functions.

[0022] The Serial Peripheral Interface (SPI) is a high-speed, full-duplex, synchronous communication bus that uses a master-slave communication mode to achieve data exchange between devices. The SPI bus allows the processor to communicate and exchange data with various peripheral devices in a serial manner. Peripheral devices include flash memory, analog / digital converters, network controllers, etc. The SPI bus uses a master-slave communication mode. Whether the master device sends or receives data, or the slave device sends or receives data, the master device needs to provide a clock to initiate data transmission. The operating system of the system on chip (SOC) is usually a Linux system, and the Linux system's controller driver for SPI only provides the implementation and use of the master device mode.

[0023] In application scenarios that require high bandwidth and low latency, FPGA works as a PCIE device connected to the host to complete high-speed and reliable data transmission. Since FPGA is implemented based on static random access memory (SRAM), the program will be lost when the power is off. After power is on, the program needs to be reloaded from the external storage medium to achieve normal operation. The medium for storing programs is generally SPIFlash. That is, the FPGA program is burned through SPI Flash. Program burning is to write the data of the program execution file to the specified location of the program memory, so as to achieve normal operation of the program. Flash memory is a non-volatile memory that can realize read and write data operations, such as storing programs.

[0024] There are two main methods for burning FPGA programs in SPI Flash:

[0025] Method 1: Use the official burning tool on the computer (PC) to burn the program through the Joint Test Group Interface (JTAG). Most advanced devices support the JTAG protocol, such as digital signal processors (DSPs), FPGA devices, etc. The standard JTAG interface has 4 lines: TMS, TCK, TDI, and TDO, which are mode selection, clock, data input, and data output lines respectively.

[0026] Method 2: Develop a program burning system. The system provides a host computer, on which the application environment, PCIE driver, SPI controller driver and SPI device driver are integrated, and the SPI burning logic program is realized. The driver is a program in the computer that drives the hardware to work, enabling data transmission and control between the operating system and the hardware.

[0027] In method 1, the burning program needs to use a dedicated program downloader on the PC side and download through the JTAG interface (serial port), which makes the burning program slow. In addition, after the product is delivered to the customer, each time the program is burned, it is necessary to open the chassis on site for close operation, use the official burning software and connect the JTAG interface for burning, which is inconvenient and has low operating efficiency.

[0028] Dedicated program burning systems are generally developed for a single SPI Flash, which is more convenient than the program burning method of method 1 and does not require opening the chassis. However, the program burning host computer developed based on the PCIE bus and a specific SPI Flash chip is highly specialized and less versatile. If the SPI Flash needs to be replaced for various reasons, such as the SPI Flash being discontinued or replaced with a more cost-effective SPI Flash, the host computer and driver will need to be changed, and it is difficult to change the program burning system, which increases the time cost and maintenance cost of software development.

[0029] It should be noted that the above-mentioned problem that the PCIE device has poor convenience and poor versatility in burning FPGA programs based on SPI Flash is only an example. The embodiments of the present application can be applied to any type of scenario where the communication driver between the PCIE device and the SPI device has poor convenience and poor versatility.

[0030] Therefore, it is necessary to design a technical solution for burning FPGA programs in SPI Flash that is easy to use and has good versatility.

[0031] Based on this, the embodiment of the present application proposes a processing method for a serial peripheral interface device. The processing method for a serial peripheral interface device in the embodiment of the present application is applied to a Linux operating system. Figure 1 The processing method of the serial peripheral interface device of the embodiment of the present application is described in detail. Figure 1 As shown, the processing method of the serial peripheral interface device in the embodiment of the present application may mainly include steps S110 to S130, and these steps are described in detail below.

[0032] It should be pointed out that the size of the serial numbers of the steps in the embodiments of the present application does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0033] In step S110, a Peripheral Component Interconnect Express (PCIE) device driver and a Serial Peripheral Interface (SPI) device driver are set in the driver layer. The PCIE device driver includes an SPI controller driver, and the SPI controller driver includes a sequence for storing information of multiple SPI devices supported by it. The sequence is configured to allow the addition of information of the SPI device to be connected supported by the SPI controller driver.

[0034] The SPI controller driver defines the basic logic of SPI timing. The SPI controller driver is used when the SPI device driver accesses the SPI Flash. The SPI working timing mode is determined by the matching relationship between the clock polarity (CPOL) and the clock phase (CPHA). CPOL indicates the state of the initial level of the clock signal (idle state). CPOL is 0, which means that the initial state of the clock signal is low level, and 1 means that the initial level of the clock signal is high level. CPHA is 0, which means that the data is sampled at the first clock change edge, and CPHA is 1, which means that the data is sampled at the second clock change edge. There are 4 working timing modes according to different combinations of CPOL and CPHA.

[0035] The plurality of SPI devices are devices supported by the SPI controller driver, and the SPI device may be, for example, a flash memory. The flash memory is used for data storage, backup, and parameter curing, and the flash memory is mainly divided into two types: NOR type and NAND type.

[0036] Sequences can be arrays, queues, lists, etc. An array is a sequence of ordered elements, which is allocated continuously in memory and has simple access to data.

[0037] In some implementations, the array for storing information of multiple SPI devices is configured to allow the addition of information of SPI devices to be connected that are supported by the SPI controller driver. In this way, attribute information of new SPI devices can be added at any time, such as adding information of more cost-effective SPI Flash chips, thereby providing scalability.

[0038] In the SPI controller driver, the hardware information spi_hardware_info array can be defined to store information of multiple SPI devices.

[0039] The array for storing information of multiple SPI devices may be a two-dimensional array, for example, each row represents a SPI device, and each column represents a different attribute parameter.

[0040] In some implementations, the sequence stores values ​​of multiple parameters for characterizing information of the SPI device, and the information of the SPI device can be stored in the sequence in the form of parameters (variables). The multiple parameters characterizing the information of the SPI device include at least some or all of the following parameters: name, identifier, storage size, chip select number, bus number, and transmission mode. For example, each group of parameters (variables) in the spi_hardware_info array contains parameters such as the name (name), identifier (ID), storage size, chip select number, bus number, and transmission mode of a specific model of a SPI device.

[0041] In step S120, the SPI device driver obtains information of the connected target SPI device, and determines whether there is information of an SPI device matching the information of the target SPI device in the sequence according to the information of the target SPI device.

[0042] The target SPI device may be an SPI device to be accessed. The SPI device driver may obtain model information of the connected target SPI device, such as a name and an ID. According to the name and ID information of the target SPI device, the query sequence may be used to query whether there is information of an SPI device that matches the information of the target SPI device. In other words, the query sequence may be used to query whether the information of any SPI device matches the information of the target SPI device. In some embodiments, the SPI device driver may query the sequence using its own query function.

[0043] In other embodiments, in order to enable the SPI device driver to quickly match the SPI device, the SPI controller driver also includes a scanning function. The step S120 of determining whether the sequence contains information of an SPI device that matches the information of the target SPI device based on the information of the target SPI device may include: the SPI device driver calls the scanning function; the scanning function queries the sequence based on the information of the target SPI device to determine whether the sequence contains information of an SPI device that matches the information of the target SPI device.

[0044] For example, a scan function is created in the SPI controller driver for the SPI device driver to call. The SPI device driver matches the model name and identifier of the target SPI device through the scan function to confirm whether the target SPI device is in the support list of the SPI controller driver. If it is in the support list of the SPI controller driver, all parameter information of the SPI device is obtained.

[0045] In some implementations, the sequence may be an array, and the above-mentioned scanning function queries the sequence according to the information of the target SPI device to determine whether the sequence has information of an SPI device that matches the information of the target SPI device, which may include: the scanning function determines the total number of queries according to the number of multiple SPI devices in the array; according to the total number of queries, queries the name parameter in the array to determine whether the name of the first SPI device is the same as the name of the target SPI device, and the first SPI device is any device among the multiple SPI devices; in response to the name of the first SPI device being the same as the name of the target SPI device, queries the identifier parameter in the array to determine whether the identifier of the first SPI device is the same as the identifier of the target SPI device. That is, the information of a parameter in the array is matched with the information of the corresponding parameter of the target SPI device in a polling manner.

[0046] In step S130 , in response to the SPI device information in the sequence matching the information of the target SPI device, a device node corresponding to the target SPI device is generated at the application layer.

[0047] In some implementations, based on the memory technology device (MTD) subsystem of the Linux system, the target SPI device is registered as an MTD device in the SPI device driver, and a target MTD device node ( / dev / mtdblock1 device node) corresponding to the target SPI device is generated in the application layer for access by the application layer.

[0048] In some implementations, the application layer accesses data from the target SPI device based on the dd command and the target MTD device node. dd is a command on Unix and Unix-like systems, and its main function is to convert and copy files. For example, at the application layer, the existing dd command is used to read and write data from the SPI Flash chip.

[0049] In some implementations, the application layer can verify the data of the target SPI device based on the md5sum command. The md5sum algorithm is a commonly used hash algorithm used to calculate the message digest algorithm 5 (MD5) hash value of the data. MD5 is a widely used cryptographic hash function that can calculate information of any length bit by bit and map it to a fixed-length hash value (message digest), usually 128 bits.

[0050] In the embodiment of the present application, a PCIE device driver and a SPI device driver are set in the driver layer of the Linux framework system, and the PCIE device driver includes an SPI controller driver, and the SPI controller driver includes a sequence for storing information of multiple SPI devices supported by it. The SPI device driver matches the SPI device supported by the SPI controller driver in the sequence according to the information of the target SPI device obtained, and generates a device node corresponding to the target SPI device in the application layer. In the embodiment of the present application, when it is necessary to use other types of SPI devices (such as Flash) in addition, the required SPI device variables can be added to the sequence driven by the SPI controller. In this way, the SPI device can be accessed at the application layer, and the operation is simple, and there is no need to modify the application layer code for the second time, and the scalability is good and the versatility is strong. In the embodiment of the present application, the SPI Flash burns the FPGA program without disassembling the chassis, which is convenient to operate and helps to improve the efficiency of the burning program.

[0051] The method of the embodiment of the present application is further explained below in combination with some possible implementation methods of the present application.

[0052] Figure 2 It is an application Figure 1 A schematic diagram of the system framework of the Linux system of the method. Figure 2 As shown, the Linux system framework 200 may include a driver layer, an application layer, and a hardware layer ( Figure 2 not shown).

[0053] At the driver layer, a PCIE device driver 210 and a SPI device driver 230 are set. The PCIE device driver includes a SPI controller driver 220. The SPI controller driver 220 includes a scan function 221 and a spi_hardware_info array 222 for storing information of multiple SPI devices. The SPI device driver 230 uses the SPI controller driver 220 when accessing the SPI device hardware.

[0054] At the application layer, there are Linux console 260 and MTD subsystem 250. MTD subsystem 250 can generate / dev / mtdblock1 device node, and the application of Linux console 260 can access SPI device through the device node. In Linux console 260, dd command can directly read and write disk device. For example, at the application layer, dd command is used to read and write data of SPI Flash chip. The application layer can verify the burning file based on md5sum command.

[0055] visible, Figure 2 The embodiment is based on the existing Linux driver framework, and adds a spi_hardware_info array 222 and a scan function 221 to the SPI controller driver 220, so that the SPI device driver 230 can be compatible with a variety of different SPI devices and match the newly added SPI device, so as to perform read and write access to it.

[0056] Figure 3 yes Figure 1 A flowchart of a possible implementation of the method. Figure 3 In the method, FPGA is a PCIE device of the Linux host, and the target SPI device is a SPI Flash chip. Figure 3 As shown, the processing method of the embodiment of the present application may mainly include steps S3010 to S3110, and these steps are described in detail below.

[0057] In step S3010, start.

[0058] In step S3020, the base address register (BAR) and space resources of the PCIE are initialized.

[0059] FPGA is a PCIE device of the Linux host, so register a PCIE device driver for FPGA. In the PCIE device driver, initialize the PCIE base address register and request the I / O resource space of the PCIE device.

[0060] In step S3030, the I / O port of the PCIE is mapped to obtain a virtual base address of the I / O port.

[0061] Map the I / O port of PCIE to obtain the virtual address space, which is convenient for subsequent access to the Flash register of the PCIE device plug-in.

[0062] In step S3040, apply for the SPI controller.

[0063] The SPI controller driver controls the read and write timing of the SPI Flash through the SPI bus. The SPI working timing mode is determined by the matching relationship between the clock polarity (CPOL) and the clock phase (CPHA).

[0064] In step S3050, set the spi_controller structure member variables and functions.

[0065] The SPI controller uses the spi_controller structure. spi_controller represents the SPI controller driver (host driver), which contains variables and data transmission functions such as SPI polarity, byte low-order first, default chip select signal, bus number, and number of supported chip select signals.

[0066] In step S3060, set the spi_bitbang structure member variables and functions.

[0067] The SPI controller is usually responsible for transmitting data through the spi_bitbang structure. In the specific description of the SPI controller, the address of the spi_controller structure is assigned to the spi_bitbang variable master. In this way, through the function pointed to by the spi_bitbang.txrx_bufs function pointer, the rx_buf pointer of the spi_transfer structure is used as the buffer for Flash read data, and the tx_buf pointer is used as the buffer for Flash write data, so as to realize data sending and receiving through SPI.

[0068] In step S3070, the SPI controller registers the new SPI device.

[0069] In the SPI controller driver, the spi_controller structure is initialized according to the variables of the spi_hardware_info array, thereby binding the SPI device and the SPI controller. The values ​​of the spi_hardware_info array variables (parameters) are assigned to the SPI device spi_device structure, and the spi_add_device function is used to register a new SPI device.

[0070] The following uses the SPI Flash chips w25q128 and w25q64 as examples to illustrate the parameters of the spi_hardware_info array.

[0071]

[0072] From the spi_flash_info instance of the spi_hardware_info array variable, we can see that name defines the name of the SPI device w25q128, w25q64; chip_id combines the manufacturer ID and device ID of the SPI device; chip_sel sets the chip select number of the SPI device; bus_num sets the bus number where the SPI device is located; mode can select the SPI transmission mode; platform_data is used to initialize the relevant functions of the SPI device, etc. When replacing the SPI Flash chip, it is convenient to add an instance like w25q128 or w25q64 in the spi_hardware_info array, and it will eventually be registered as a SPI device.

[0073] The same SPI device driver can drive multiple SPI devices. The information of these SPI devices is defined in the spi_hardware_info array of the SPI controller driver in the form of variables, which can be used by the SPI device driver and the MTD subsystem. For different SPI devices, the chip model name, ID, storage size, chip select, bus number and other parameter information are different. These parameter information can distinguish different SPI devices and help increase the versatility of SPI device drivers.

[0074] In step S3080, the SPI device driver calls the scan matching function.

[0075] The SPI device driver will call the scan function in the SPI controller driver to match the corresponding SPI device.

[0076] In step S3090, it is determined whether a SPI device is matched. The specific operation process can be referred to below Figure 4 If a SPI device is matched, the process proceeds to step S3100; if no SPI device is matched, the process proceeds to step S3110.

[0077] In step S3100, the SPI Flash device is registered as an MTD device.

[0078] Based on the MTD subsystem, the SPI Flash device is registered as an MTD device. With the help of the existing MTD subsystem, the / dev / mtdblock1 device node is provided to the application layer.

[0079] In this way, at the application layer, it is convenient to use the dd command to access the / dev / mtdblock1 device node to perform read and write operations on the SPIFlash. For example, to write the firmware content fpga.bin to the SPI Flash (the corresponding MTD device node is / dev / mtdblock1), the command used is:

[0080] "dd if=in_fpga.bin of= / dev / mtdblock1 bs=1count=2192012status=progress"

[0081] For example, to read the burned firmware content to out_fpga.bin, use the command:

[0082] "dd of=out_fpga.bin if= / dev / mtdblock1 bs=1count=2192012status=progress"

[0083] The fpga.bin file is usually used to store the configuration bitstream of the FPGA.

[0084] You can use the md5sum algorithm to generate the hash value of the xxx.bin file before and after burning to ensure the integrity of the burned file. The verification command is: md5sum xxx.bin.

[0085] Through the spi_hardware_info array variable and scan matching function driven by the Flash controller, the SPI device driver can obtain the information of the SPI Flash chip model, match the SPI device, and then register it as an MTD device, thereby using the existing MTD subsystem framework of Linux to provide the / dev / mtdblock1 device node to the application layer. There is no need to develop software separately, and the existing dd command of the system is used, which reduces the development cycle.

[0086] In step S3110, end.

[0087] End the overall process of SPI device driver configuration.

[0088] In the embodiment of the present application, a PCIE device driver and a SPI device driver are set in the driver layer of the Linux framework system, and the PCIE device driver includes an SPI controller driver, and the SPI controller driver includes an array for storing information of multiple SPI devices supported by it. The SPI device driver matches the SPI device supported by the SPI controller driver in the array according to the information of the target SPI device obtained, and generates a device node corresponding to the target SPI device in the application layer. In the embodiment of the present application, when it is necessary to use other types of SPI devices (such as Flash) in addition, the required SPI device variables can be added to the array driven by the SPI controller. In this way, the SPI device can be accessed at the application layer, the operation is simple, and there is no secondary modification of the application layer code, which has strong applicability and good scalability. In the embodiment of the present application, the SPI Flash burns the FPGA program without disassembling the chassis, which is convenient to operate and helps to improve the efficiency of the burning program.

[0089] Figure 4 yes Figure 3 A flowchart of a possible implementation of step S3090 is shown. Figure 4 As shown, specifically, the method for matching the target SPI device in step S3090 may mainly include steps S3091 to S3099, which are described in detail below.

[0090] In step S3091, start.

[0091] In step S3092, the SPI device driver inputs the name parameter of the SPI Flash chip.

[0092] In step S3093, the number of variables in the spi_hardware_info array is calculated to determine the total number of polls, that is, the total number of queries.

[0093] In the scan function, the parameter name of the variable in the spi_hardware_info array will be polled and searched, and the number of polling times shall not be greater than the total number of queries.

[0094] In step S3094, poll and compare whether the value of the name parameter is equal to the value of name in the spi_hardware_info array variable.

[0095] If the match fails, it means that the target SPI device does not exist, and the SPI device driver will be exited and the process will proceed to step S3099. If the match succeeds, the process will proceed to step S3095.

[0096] In step S3095, the ID and manufacturer ID of the SPI Flash device are read.

[0097] In step S3096, the value of the two-byte identifier (ID) parameter is constructed.

[0098] Call the read ID register function to obtain the device ID and manufacturer ID of the SPI device, which constitute the two-byte ID information of the SPI Flash.

[0099] In step S3097, compare whether the ID parameter of the SPI Flash is equal to the ID in the spi_hardware_info array variable.

[0100] Poll to match the ID in the spi_hardware_info array to ensure the consistency of the matching SPI device, which helps to enhance credibility. If the match fails, it means that the target SPI device does not exist, and the SPI device driver will be exited and enter step S3099. If the match is successful, it will enter step S3098.

[0101] In step S3098, the parameter value of the spi_hardware_info array is returned.

[0102] Thus, the SPI device driver obtains the spi_hardware_info array variable of the matched SPI device, that is, obtains the values ​​of all parameters of the specific target SPI Flash device, and obtains the information of the target SPI Flash device.

[0103] At step S3099, end.

[0104] The entire process of determining whether the target SPI device is matched is completed.

[0105] Combination of the above Figure 1-Figure 4 The method embodiment of the present application is described in detail. Figures 5 and 6 The device embodiment of the present application is described in detail. It should be understood that the description of the device embodiment corresponds to the description of the method embodiment, so the parts not described in detail can refer to the previous method embodiment.

[0106] An embodiment of the present application also provides a processing device for a serial peripheral interface device. Figure 5 Schematic diagram of the composition of the processing device of the serial peripheral interface device provided in the embodiment of the present application. Figure 5 As shown, the processing device 500 of the serial peripheral interface device includes: a setting module 510 and a generating module 520.

[0107] The setting module 510 is used to set the PCIE device driver and the SPI device driver in the driver layer. The PCIE device driver includes the SPI controller driver, and the SPI controller driver includes a sequence for storing information of multiple SPI devices supported by it, and the sequence is configured to allow the addition of information of a new SPI device to be connected. The SPI device driver obtains the information of the connected target SPI device, and determines whether the sequence has the information of the SPI device that matches the information of the target SPI device according to the information of the target SPI device.

[0108] The generating module 520 is used to generate a device node corresponding to the target SPI device at the application layer in response to the information of the SPI device in the sequence that matches the information of the target SPI device.

[0109] Understandably, Figure 2 The Linux system architecture is Figure 5 A possible implementation manner of a processing device of a serial peripheral interface device.

[0110] Optionally, the sequence stores values ​​of multiple parameters for characterizing information of the SPI device, and the multiple parameters include at least some or all of the following parameters: name, identifier, storage size, chip select number, bus number, and transmission mode.

[0111] Optionally, the SPI controller driver further includes a scanning function. The SPI device driver calls the scanning function; the scanning function queries the sequence according to the information of the target SPI device to determine whether the sequence contains information of an SPI device that matches the information of the target SPI device.

[0112] Optionally, the sequence is an array, and the scanning function determines the total number of queries according to the number of multiple SPI devices in the array; according to the total number of queries, queries the name parameter in the array to determine whether the name of the first SPI device is the same as the name of the target SPI device, and the first SPI device is any device among the multiple SPI devices; in response to the name of the first SPI device being the same as the name of the target SPI device, queries the identifier parameter in the array to determine whether the identifier of the first SPI device is the same as the identifier of the target SPI device.

[0113] Optionally, the generating module 520 is used to generate a target MTD device node corresponding to the target SPI device at the application layer based on the memory technology device MTD subsystem.

[0114] Optionally, the application layer accesses data from the target SPI device based on the dd command and the target MTD device node, and / or the application layer verifies data from the target SPI device based on the md5sum command.

[0115] Optionally, the target SPI device is a SPI flash memory.

[0116] Figure 6 Schematic diagram of component units / partial component units of another processing device of a serial peripheral interface device provided in an embodiment of the present application. Figure 6 As shown, the processing device 600 of the serial peripheral interface device may include: a memory 610 and at least one processor 620 .

[0117] The memory 610 is used to store codes or computer programs.

[0118] The processor 620 is connected to the memory 610 and is used to execute the code or computer program stored in the memory 610 to control the processing device 600 of the serial peripheral interface device to execute any of the processing methods described above.

[0119] Exemplarily, the computer program may be divided into one or more modules / units, one or more modules / units are stored in the memory 610 and executed by the processor 620 to complete the present application.

[0120] Those skilled in the art will understand that Figure 6 The processing device 600 of the serial peripheral interface device is merely an example and does not constitute a limitation on the processing device of the serial peripheral interface device. The processing device 600 may include more or less components than shown in the figure, or some components may be combined, or different components may be included.

[0121] The processor 620 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor, or the processor may be any conventional processor, etc.

[0122] The processing device 600 of the serial peripheral interface device provided in this embodiment can execute the above method embodiment, and its implementation principle and technical effect are similar, which will not be repeated here.

[0123] An embodiment of the present application further provides a non-volatile computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments can be implemented.

[0124] An embodiment of the present application provides a computer program product. When the computer program product runs on an electronic device, the electronic device can implement the steps in the above-mentioned method embodiments when executing the computer program product.

[0125] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above method embodiments, which can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a computer-readable storage medium. When the computer program is executed by the processor, the steps of the above method embodiments can be implemented. Among them, the computer program includes computer program code, which can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may at least include: any entity or device that can carry the computer program code to the camera / electronic device, recording medium, computer memory, read-only memory (ROM), random access memory (RAM), read-only compact disc (CD-ROM), magnetic tape, floppy disk and optical data storage device. The computer-readable storage medium mentioned in the present application can be a non-volatile storage medium, in other words, it can be a non-transient storage medium.

[0126] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0127] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0128] In the embodiments provided in the present application, it should be understood that the disclosed devices / equipment and methods can be implemented in other ways. For example, the device / equipment embodiments described above are only schematic, for example, the division of modules or units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0129] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0130] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0131] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0132] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0133] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A processing method for a serial peripheral interface device, characterized in that: include: A PCIE device driver and a SPI device driver are provided at the driver layer, wherein the PCIE device driver includes an SPI controller driver, and the SPI controller driver includes a sequence for storing information of a plurality of SPI devices supported by the SPI device driver, wherein the sequence is configured to allow the information of the SPI device to be connected to be added; The SPI device driver obtains information of a connected target SPI device, and determines, based on the information of the target SPI device, whether the sequence contains information of the SPI device that matches the information of the target SPI device; In response to the sequence having information of the SPI device matching the information of the target SPI device, a device node corresponding to the target SPI device is generated at the application layer.

2. The processing method according to claim 1, characterized in that: The sequence stores values ​​of multiple parameters for characterizing information of the SPI device, and the multiple parameters include at least part or all of the following parameters: name, identifier, storage size, chip select number, bus number, and transmission mode.

3. The processing method according to claim 1, characterized in that: The SPI controller driver further includes a scanning function, which determines, based on the information of the target SPI device, whether the sequence contains information of the SPI device that matches the information of the target SPI device, including: The SPI device driver calls the scanning function; The scanning function queries the sequence according to the information of the target SPI device to determine whether the sequence contains information of the SPI device that matches the information of the target SPI device.

4. The processing method according to claim 3, characterized in that: The sequence is an array, and the scanning function queries the sequence according to the information of the target SPI device to determine whether the sequence contains information of the SPI device that matches the information of the target SPI device, including: The scanning function determines a total number of queries based on the number of the plurality of SPI devices in the array; According to the total number of queries, query the name parameter in the array to determine whether the name of the first SPI device is the same as the name of the target SPI device, the first SPI device being any one of the multiple SPI devices; In response to the name of the first SPI device being the same as the name of the target SPI device, an identifier parameter in the array is queried to determine whether an identifier of the first SPI device is the same as an identifier of the target SPI device.

5. The processing method according to claim 1, characterized in that: The generating of a device node corresponding to the target SPI device at the application layer includes: Based on the memory technology device MTD subsystem of the Linux system, a target MTD device node corresponding to the target SPI device is generated at the application layer.

6. The processing method according to claim 5, characterized in that: The method further comprises: The application layer performs data access to the target SPI device based on the dd command and the target MTD device node, and / or, The application layer verifies the data of the target SPI device based on the md5sum command.

7. The processing method according to any one of claims 1 to 6, characterized in that: The target SPI device is a SPI flash memory.

8. A processing device for a serial peripheral interface device, characterized in that: include: A setting module is used to set a quick peripheral interconnection standard PCIE device driver and a serial peripheral interface SPI device driver in a driver layer, wherein the PCIE device driver includes an SPI controller driver, and the SPI controller driver includes a sequence for storing information of multiple SPI devices supported by it, and the sequence is configured to allow the addition of information of the SPI device to be connected, and the SPI device driver obtains information of a target SPI device to be connected, and determines whether there is an SPI device in the sequence that matches the information of the target SPI device according to the information of the target SPI device; A generating module is used for generating a device node corresponding to the target SPI device at an application layer in response to the SPI device in the sequence having information matching the target SPI device.

9. A processing device for a serial peripheral interface device, characterized in that: include: A memory for storing codes; A processor is connected to the memory and is used to execute the code stored in the memory so that the processing device executes the processing method as described in any one of claims 1 to 7.

10. A non-volatile computer-readable storage medium, characterized in that: A computer program is stored thereon, and when the computer program is executed, the computer program is used to implement the processing method according to any one of claims 1 to 7.

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