Phase change memory and operation method

Abstract

The invention discloses a phase change memory and an operation method, the phase change memory comprises a word line, a bit line and a memory module, the memory module is connected with the word line and the bit line to which a reverse voltage difference is applied in a setting operation, the threshold voltage of the memory module can be reduced, and the performance of the memory module is improved. Therefore, under the condition that the threshold voltage of the memory module after the reset operation is kept unchanged, the difference between the threshold voltage of the memory module after the reset operation and the threshold voltage of the memory module after the setting operation is increased, and the read window margin is further improved.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a phase change memory and an operating method thereof. Background Art

[0002] The read window margin (RWM) and cycle performance of phase change memory (PCM) are two key technical indicators. Among them, the read window margin refers to the ability of the phase change memory to stably distinguish different states (such as "0" and "1") during the read operation.

[0003] However, as the number of cycle operations of the phase change memory increases, the read window margin will deteriorate, which hinders the further application of the phase change memory. Summary of the invention

[0004] The present application provides a phase change memory and an operation method to alleviate the technical problem of deterioration of read window margin.

[0005] In a first aspect, the present application provides a phase change memory, which includes a word line, a bit line and a storage module. The storage module connects the word line and the bit line to which a reverse voltage difference is applied during a set operation to reduce a threshold voltage of a set state of the storage module.

[0006] Optionally, in a set operation of the memory module, the memory module is connected to a word line to which a negative voltage is applied and a bit line to which a positive voltage is applied.

[0007] Optionally, in a set operation of the memory module, the positive voltage of the bit line continues for a period of time and then decreases at a preset negative slope.

[0008] Optionally, the memory module is connected to a word line and a bit line to which a forward voltage difference is applied during a reset operation, so as to increase a reset state threshold voltage of the memory module.

[0009] Optionally, in a reset operation of the memory module, the memory module is connected to a word line to which a positive voltage is applied and a bit line to which a negative voltage is applied.

[0010] Optionally, the negative voltage is less than or equal to -3V and greater than or equal to -5V; the positive voltage is greater than or equal to 3V and less than or equal to 6V.

[0011] Optionally, the storage module includes a gate tube and a storage unit connected in series, the storage unit is connected to the word line, and the gate tube is connected to the bit line; the threshold voltage of the storage module is the sum of the threshold voltage of the gate tube and the threshold voltage of the storage unit.

[0012] Optionally, the memory cell includes tellurium, germanium and antimony elements; in a set operation, the tellurium element migrates to the bit line, and the germanium and antimony elements migrate to the word line; in a reset operation of the memory module, the tellurium element migrates to the word line, and the germanium and antimony elements migrate to the bit line.

[0013] In a second aspect, the present application provides an operating method, which is applied to the above-mentioned phase change memory, and the operating method includes applying a reverse voltage difference between the word line and the bit line connected to the storage module selected for the set operation if a set operation is performed on the storage module; and applying a forward voltage difference between the word line and the bit line connected to the storage module selected for the reset operation if a reset operation is performed on the storage module.

[0014] Optionally, if a setting operation is performed on the storage module, a reverse voltage difference is applied between a word line and a bit line connected to the storage module selected for the setting operation, including: applying a negative voltage to the word line and applying a positive voltage to the bit line.

[0015] Optionally, if a reset operation is performed on the memory module, a positive voltage difference is applied between a word line and a bit line connected to the memory module selected for the reset operation, including: applying a positive voltage to the word line and applying a negative voltage to the bit line.

[0016] The phase change memory and operation method provided by the present application can reduce the threshold voltage of the storage module by connecting the word line and the bit line to which a reverse voltage difference is applied during the set operation of the storage module, thereby increasing the difference between the threshold voltage of the storage module after the reset operation and the threshold voltage of the storage module after the set operation while keeping the threshold voltage of the storage module after the reset operation unchanged, thereby improving the read window margin.

[0017] Furthermore, compared to the longer application cycle required to improve the read window margin by developing new materials, the above-mentioned application of a reverse voltage difference to the word line and the bit line during the set operation can improve the read window margin in a shorter application cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0019] Figure 1 Schematic diagram of normal distribution of threshold voltage in related technology.

[0020] Figure 2 It is a schematic diagram of the change between the number of cycles and the bit error rate (Raw Bit Error Rate, RBER) in the related art.

[0021] Figure 3 A schematic diagram of the structure of a phase change memory provided in an embodiment of the present application.

[0022] Figure 4 This is a schematic diagram of the operating voltage for set and reset.

[0023] Figure 5 Schematic diagram of the change of threshold voltage after set operation under positive and reverse voltages.

[0024] Figure 6 Schematic diagram of the change in threshold voltage after reset operation under positive and reverse voltages. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0026] In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicating the number of technical features indicated. Therefore, the features specified as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0027] Figure 1 Schematic diagram of normal distribution of threshold voltage in related technology. Figure 1 In the figure, the horizontal axis represents the threshold voltage (Vt) of each storage module in the phase change memory, the vertical axis represents the number (Num) of the threshold voltage (Vt) of each storage module in the phase change memory, and each curve represents the normal distribution of the threshold voltage (Vt) of the phase change memory after different numbers of cycle operations.

[0028] from Figure 1 It can be seen that as the number of cycle operations increases, the Set tail deteriorates. Tail is the area where the normal distribution of Set vt is greater than positive 3.5σ. Here, σ refers to the standard deviation. Set refers to the set operation, which is to change the data in the storage module from 0 to 1.

[0029] Figure 2 Schematic diagram of the change between the number of cycles and the number of error bits in the related art. Figure 2 In the figure, the horizontal axis represents the number of cycles, i.e., the number of cyclic operations, and the vertical axis represents the bit error rate (RBER).

[0030] from Figure 2 It can be seen that with the increase of cycle number, RBER gradually increases.

[0031] from Figure 1 and Figure 2 It can be seen that after multiple cycles, the elements in the phase change memory are enriched under the action of the electric field, resulting in poor set tail and smaller RWM. The poor cycling performance of PCM hinders the further application of phase change memory.

[0032] This embodiment provides a phase change memory 100. Figures 3 to 6 ,like Figure 3 As shown, the phase change memory 100 includes a word line WL, a bit line BL and a memory module 10, and the memory module 10 is connected to the word line WL and the bit line BL.

[0033] In some embodiments, the memory module 10 includes a gate transistor OTS and a memory cell PCM1 connected in series, the memory cell PCM1 is connected to a word line WL, and the gate transistor OTS is connected to a bit line BL.

[0034] In some embodiments, such as Figure 4 As shown, the memory module 10 connects the word line WL and the bit line BL to which a reverse voltage difference is applied in a set operation (SET) to reduce the threshold voltage of the set state of the memory module 10 .

[0035] It can be understood that the phase change memory 100 provided in the present application can reduce the threshold voltage of the storage module 10 by connecting the word line WL and the bit line BL to which a reverse voltage difference is applied during the set operation of the storage module 10, thereby increasing the difference between the threshold voltage of the storage module 10 after the reset operation and the threshold voltage of the storage module 10 after the set operation while keeping the threshold voltage of the storage module 10 after the reset operation unchanged, thereby improving the read window margin.

[0036] Furthermore, compared to the longer application cycle required to improve the read window margin by developing new materials, the read window margin can be improved in a shorter application cycle by applying a reverse voltage difference to the word line WL and the bit line BL during the set operation.

[0037] It should be noted that the threshold voltage of the memory module 10 is the sum of the threshold voltage of the gate transistor OTS and the threshold voltage of the memory cell PCM1. The word line WL and the bit line BL applied with a reverse voltage difference means that the difference between the word line voltage (VWL) and the bit line voltage (VBL) is a negative voltage.

[0038] In some of the embodiments, in a set operation of the memory module 10 , the memory module 10 is connected to a word line WL to which a negative voltage is applied and a bit line BL to which a positive voltage is applied.

[0039] It should be noted that compared with the set operation and the reset operation, in which a positive voltage is applied to the word line WL and a negative voltage is applied to the bit line BL, this embodiment overcomes the technical prejudice in this field and can not only realize the normal set operation but also reduce the threshold voltage of the storage module 10, thereby improving the read window margin.

[0040] In some embodiments, such as Figure 4 As shown, in the set operation of the memory module 10, the positive voltage VBL of the bit line BL lasts for a period of time and then decreases according to a preset negative slope.

[0041] It should be noted that this is conducive to further obtaining a better positioning effect.

[0042] In some embodiments, such as Figure 4 As shown, the memory module 10 connects the word line WL and the bit line BL to which a positive voltage difference is applied in the reset operation (RESET) to increase the threshold voltage of the memory module 10 in the reset state.

[0043] It should be noted that the word line WL and the bit line BL to which a positive voltage difference is applied means that the difference between the word line voltage (VWL) and the bit line voltage (VBL) is a positive voltage. This increases the threshold voltage of the memory module 10, thereby further increasing the difference between the threshold voltage of the memory module 10 after the reset operation and the threshold voltage of the memory module 10 after the set operation, thereby improving the read window margin. The reset operation refers to changing the data in the memory module 10 from 1 to 0.

[0044] Alternatively, if Figure 4 As shown, in the reset operation of the memory module 10, the memory module 10 is connected to the word line WL to which a positive voltage is applied and the bit line BL to which a negative voltage is applied. It should be noted that this is conducive to further increasing the threshold voltage of the memory module 10. The absolute value of the word line voltage can be greater than the absolute value of the bit line voltage.

[0045] For example, the negative voltage is less than or equal to -3 V and greater than or equal to -5 V, and the positive voltage is greater than or equal to 3 V and less than or equal to 6 V. Such a range of positive and negative voltages allows the word line voltage and the bit line voltage to be interchanged in the set operation and the reset operation, thereby reducing the use of hardware circuits, reducing costs and area.

[0046] See also Figure 5 and Figure 6 ,exist Figure 5 and Figure 6In the figure, the vertical axis represents the threshold voltage (Vt) of the storage module 10, SET(P) represents that a forward voltage difference or a forward voltage is applied between the word line WL and the bit line BL, SET(N) represents that a reverse voltage difference or a reverse voltage is applied between the word line WL and the bit line BL, RESET(P) represents that a forward voltage difference or a forward voltage is applied between the word line WL and the bit line BL, and RESET(N) represents that a reverse voltage difference or a reverse voltage is applied between the word line WL and the bit line BL.

[0047] from Figure 5 It can be seen that after the set operation, the threshold voltage Vt of the storage module 10 is reduced by SET(N) in which a reverse voltage difference or reverse voltage is applied between the word line WL and the bit line BL, compared with SET(P) in which a forward voltage difference or forward voltage is applied between the word line WL and the bit line BL.

[0048] from Figure 6 It can be seen that after the reset operation, the threshold voltage Vt of the storage module 10 increases when a forward voltage difference or a forward voltage is applied between the word line WL and the bit line BL by RESET (P) compared to RESET (N) when a reverse voltage difference or a reverse voltage is applied between the word line WL and the bit line BL.

[0049] Since the read window margin (RWM) is positively correlated with the difference ΔVt between the threshold voltages, that is, the larger ΔVt is, the larger RWM is. ΔVt is equal to the difference between Reset Vt and Set Vt, Reset Vt represents the threshold voltage of the memory module 10 after the reset operation, and Set Vt represents the threshold voltage of the memory module 10 after the set operation.

[0050] Set Vt is smaller under reverse voltage than under forward voltage, and Reset Vt is larger under forward voltage than under reverse voltage. This can increase ΔVt and thus increase RWM.

[0051] In some embodiments, the memory cell PCM1 includes tellurium, germanium and antimony elements; in a set operation, the tellurium element migrates to the bit line BL, and the germanium and antimony elements migrate to the word line WL; in a reset operation of the memory module 10, the tellurium element migrates to the word line WL, and the germanium and antimony elements migrate to the bit line BL.

[0052] It should be noted that in the phase change memory 100 (PCM), germanium (Ge) and antimony (Sb) carry positive charges, and tellurium (Te) carries negative charges. Under a forward voltage, Ge and Sb drift toward the negative electrode, and Te drifts toward the positive electrode. Both positive Set and Reset operations will intensify this process. After multiple Set and Reset operations, the elements are enriched at the positive and negative electrodes, respectively, causing the material to fail.

[0053] Here, the positive electrode refers to the word line WL or the bit line BL to which a positive voltage is applied, and the negative electrode refers to the word line WL or the bit line BL to which a negative voltage is applied.

[0054] A forward voltage is applied to the selected memory module 10 through the word line WL and the bit line BL to reset, and a reverse voltage is applied to the selected memory module 10 through the word line WL and the bit line BL to set. Under the reverse voltage, the Set will restore the Ge and Sb drifting to the negative electrode to their previous positions. Similarly, the drift of Te to the positive electrode will also be weakened. The same elements will no longer form clusters, thereby enhancing the cycle performance of the PCM.

[0055] In some of the embodiments, the present application provides an operating method, which is applied to the above-mentioned phase change memory 100, and the operating method includes applying a reverse voltage difference between the word line WL and the bit line BL connected to the storage module 10 selected for the set operation if a set operation is performed on the storage module 10; and applying a forward voltage difference between the word line WL and the bit line BL connected to the storage module 10 selected for the reset operation if a reset operation is performed on the storage module 10.

[0056] It can be understood that since the operating method provided in the present application is applied to the above-mentioned phase change memory 100, the threshold voltage of the storage module 10 can also be reduced by connecting the word line WL and the bit line BL to which a reverse voltage difference is applied during the set operation through the storage module 10, so that the difference between the threshold voltage of the storage module 10 after the reset operation and the threshold voltage of the storage module 10 after the set operation can be increased while keeping the threshold voltage of the storage module 10 after the reset operation unchanged, thereby improving the read window margin.

[0057] Furthermore, compared to the longer application cycle required to improve the read window margin by developing new materials, the read window margin can be improved in a shorter application cycle by applying a reverse voltage difference to the word line WL and the bit line BL during the set operation.

[0058] Furthermore, the set operation and the reset operation use opposite voltage directions, which helps to reduce element diffusion and improve the cycle performance of the phase change memory 100 .

[0059] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0060] The phase change memory and operation method provided in the embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solution and core idea of ​​the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A phase change memory, characterized in that: The phase change memory comprises: word lines and bit lines; A storage module is provided, wherein the storage module connects the word line and the bit line to which a reverse voltage difference is applied in a set operation, so as to reduce a threshold voltage of a set state of the storage module.

2. The phase change memory according to claim 1, characterized in that: In a set operation of the memory module, the memory module is connected to the word line to which a negative voltage is applied and the bit line to which a positive voltage is applied.

3. The phase change memory according to claim 2, characterized in that: In the setting operation of the memory module, the positive voltage of the bit line continues for a period of time and then decreases according to a preset negative slope.

4. The phase change memory according to claim 1, characterized in that: The memory module connects the word line and the bit line to which a forward voltage difference is applied in a reset operation, so as to increase a threshold voltage of a reset state of the memory module.

5. The phase change memory according to claim 4, characterized in that: In a reset operation of the memory module, the memory module is connected to the word line to which a positive voltage is applied and the bit line to which a negative voltage is applied.

6. The phase change memory according to claim 2 or 5, characterized in that: The negative voltage is less than or equal to -3V and greater than or equal to -5V; the positive voltage is greater than or equal to 3V and less than or equal to 6V.

7. The phase change memory according to any one of claims 1 to 5, characterized in that: The storage module comprises a gate tube and a storage unit connected in series, the storage unit is connected to the word line, and the gate tube is connected to the bit line; The threshold voltage of the storage module is the sum of the threshold voltage of the gate transistor and the threshold voltage of the storage unit.

8. The phase change memory according to claim 7, characterized in that: The storage unit includes tellurium, germanium and antimony; In the set operation, the tellurium element migrates to the bit line, and the germanium element and the antimony element migrate to the word line; In a reset operation of the memory module, the tellurium element migrates to the word line, and the germanium element and the antimony element migrate to the bit line.

9. An operating method, characterized in that: The operating method is applied to the phase change memory according to any one of claims 1 to 8, and the operating method comprises: If a setting operation of the storage module is performed, a reverse voltage difference is applied between the word line and the bit line connected to the storage module selected for the setting operation; If the memory module is reset, a forward voltage difference is applied between the word line and the bit line connected to the memory module selected for the reset operation.

10. The operating method according to claim 9, characterized in that: If the setting operation of the storage module is performed, applying a reverse voltage difference between the word line and the bit line connected to the storage module selected for the setting operation comprises: applying a negative voltage to the word line and a positive voltage to the bit line; If the memory module is reset, a forward voltage difference is applied between the word line and the bit line connected to the memory module selected for the reset operation, including: A positive voltage is applied to the word line, and a negative voltage is applied to the bit line.

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