Semiconductor structure and manufacturing method thereof
By adjusting the concentration of B in the interlayer dielectric layer to provide free B, the problem of void defects easily occur at the fragile points at the bottom of the contact hole is solved, and the effect of improving product reliability and yield is achieved.
Patent Information
- Application Number
- CN202311033955.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-16
- Publication Date
- 2025-02-21
AI Technical Summary
In the prior art, hollow defects are easily generated at the fragile points at the bottom of the contact hole, resulting in a decrease in product reliability and yield.
By adjusting the concentration of B in the interlayer dielectric layer, free B diffuses to the fragile point of the adhesion barrier layer and reacts with WF6 to form a W nucleation layer when the adhesion barrier layer is incomplete or the film layer is of poor quality. , reduce the contact area between WF6 and the adhesive layer, and avoid hollow defects.
It effectively improves the hollow defect problem in the contact hole and improves the reliability and yield of the product.
Smart Images
Figure CN119495634A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of semiconductors and relates to a semiconductor structure and a manufacturing method thereof. Background Art
[0002] The contact hole (CT) process consists of two parts. One part is the deposition of the adhesive barrier layer (Glue Layer). The adhesive barrier layer is usually divided into two layers, such as Ti (titanium) layer and TiN (titanium nitride) layer, or Ta (tantalum) layer and TaN (tantalum nitride) layer. The Ti layer or Ta layer plays a role of cleaning and adhesion, and the TiN layer or TaN layer plays a role of blocking, preventing WF6 (tungsten hexafluoride) from directly contacting the Ti layer or Ta layer to react and produce defects. The other part is to deposit a W plug in the contact hole (the main gas is SiH4 (silane) and WF6 to react to produce W). The adhesive barrier layer is due to the fluctuation of the process capability of the PVD (physical vapor deposition) machine and the special high aspect ratio structure of the contact hole. The bottom of the contact hole and the sidewall near the bottom of the contact hole are due to the process fluctuation of the adhesive barrier layer, resulting in problems with the quality / coverage and specifications of the deposited adhesive barrier layer, which is easy to encounter void defects during the contact hole filling W process, affecting reliability and yield.
[0003] The main practice in the industry is to use a method similar to atomic deposition, where SiH4 is first introduced, and after SiH4 is evenly spread on the surface of the contact hole, WF6 is introduced to react and generate thin W, and the cycle is repeated five or six times to form a 5nm thick nucleus. This method has the following disadvantages: (1) The nucleation efficiency is low, which affects production capacity; (2) Because the reaction between SiH4 and WF6 requires TiN or TaN to catalyze, it is easy for void defects to be generated in the parts of the contact hole where the TiN layer or TaN layer is not well covered due to the reaction between WF6 and the Ti or Ta layer.
[0004] Therefore, how to improve the process to improve the hole defect problem in the contact hole has become an important technical problem that needs to be solved urgently by those skilled in the art.
[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention
[0006] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a semiconductor structure and a method for manufacturing the same, so as to solve the problem in the prior art that void defects are easily generated at the weak point at the bottom of the contact hole, resulting in reduced product reliability and yield.
[0007] To achieve the above-mentioned object and other related objects, the present invention provides a method for manufacturing a semiconductor structure, comprising the following steps:
[0008] Providing a substrate, the substrate comprising an interlayer dielectric layer and a contact hole located in the interlayer dielectric layer;
[0009] forming an adhesion barrier layer on the inner wall of the contact hole, wherein the adhesion barrier layer comprises an adhesion layer / barrier layer stacked in sequence;
[0010] forming a W plug in the contact hole, wherein the W plug is spaced from the inner wall of the contact hole by the adhesion barrier layer, and the source gas used to form the W plug includes tungsten hexafluoride;
[0011] Before forming the W plug, the B concentration in the preset area of the interlayer dielectric layer is adjusted to a preset concentration, the preset concentration is greater than 2.3wt%, and the preset area starts from the side wall of the contact hole and extends horizontally outward by a preset length.
[0012] Optionally, the preset concentration ranges from 3wt% to 5wt%.
[0013] Optionally, before forming the W plug, the method of adjusting the B concentration of a preset area of the interlayer dielectric layer to a preset concentration includes: growing a dielectric layer with a B concentration of the preset concentration as the interlayer dielectric layer, and the preset area is the entire area of the interlayer dielectric layer.
[0014] Optionally, the interlayer dielectric layer includes a borophosphosilicate glass layer, and a method for forming the borophosphosilicate glass layer includes a normal pressure chemical vapor deposition method; and the adhesion layer / barrier layer includes a Ti / TiN layer or a Ta / TaN layer.
[0015] Optionally, the method for adjusting the B concentration in a preset area of the interlayer dielectric layer to a preset concentration before forming the W plug includes: growing a dielectric layer with a B concentration lower than the preset concentration as the interlayer dielectric layer, and after forming the contact hole and the adhesion barrier layer, using an ion implantation method to implant B ions into a local area of the interlayer dielectric layer, wherein the local area starts from the side wall of the contact hole and extends horizontally outward by 5nm-15nm.
[0016] Optionally, while B ions are implanted in a local region of the interlayer dielectric layer, B ions are also implanted in the adhesion barrier layer.
[0017] Optionally, the energy range of the ion implantation is 4KeV-8KeV, and the dose range of the ion implantation is 3×10 14 atoms / cm 2 -8×10 14 atoms / cm2 .
[0018] Optionally, the interlayer dielectric layer includes a borophosphosilicate glass layer, and the adhesion layer / barrier layer includes a Ti / TiN layer or a Ta / TaN layer.
[0019] Optionally, the substrate further includes an isolation layer located on a top surface of the interlayer dielectric layer, and the isolation layer has an opening at a location where the contact hole is located.
[0020] The present invention also provides a semiconductor structure, comprising:
[0021] A substrate, comprising an interlayer dielectric layer and a contact hole located in the interlayer dielectric layer;
[0022] An adhesion barrier layer, located on the inner wall of the contact hole, the adhesion barrier layer comprising an adhesion layer / barrier layer stacked in sequence;
[0023] A W plug is located in the contact hole, and the W plug is spaced from the inner wall of the contact hole by the adhesion barrier layer;
[0024] The B concentration in the preset region of the interlayer dielectric layer is greater than 2.3 wt %, and the preset region starts from the side wall of the contact hole and extends horizontally outward by a preset length.
[0025] As described above, the method for manufacturing the semiconductor structure of the present invention provides free B by adjusting the concentration of B in the interlayer dielectric layer. When the adhesion barrier layer is not fully covered or the film quality is poor, the free B diffuses to the weak point of the adhesion barrier layer and reacts with WF6 to generate a W-shaped nucleation layer, thereby reducing the contact area between WF6 and the adhesion layer in the adhesion barrier layer, avoiding void defects caused by incomplete coverage of the barrier layer in the adhesion barrier layer during the W deposition process, thereby improving the void defect problem and effectively improving the reliability and yield of the product. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figure 1 A schematic diagram showing a void defect generated at a weak point on the sidewall of a contact hole near the bottom.
[0027] Figure 2 Shown is a schematic diagram of an example structure of a semiconductor structure manufactured using the semiconductor structure manufacturing method of the present invention.
[0028] Figure 3 A schematic diagram showing an exemplary structure of a substrate provided by the method for manufacturing a semiconductor structure of the present invention is shown.
[0029] Figure 4 It is a schematic diagram showing a structure obtained after forming an adhesion barrier layer on the inner wall of a contact hole by using the method for manufacturing a semiconductor structure of the present invention.
[0030] Figure 5 It is a schematic diagram showing a structure obtained after a W plug is formed in a contact hole using the method for manufacturing a semiconductor structure of the present invention.
[0031] Figure 6 It is a schematic diagram showing ion implantation before forming a W plug in the method for manufacturing a semiconductor structure of the present invention.
[0032] Figure 7 Shown is a schematic diagram of an exemplary structure of the semiconductor structure of the present invention.
[0033] Component number description
[0034] 101 Vulnerabilities
[0035] 102 Void Defect
[0036] 201 Interlayer dielectric layer
[0037] 202 contact hole
[0038] 203 substrate layer
[0039] 204 Isolation Layer
[0040] 205 Adhesion layer
[0041] 206 Barrier layer
[0042] 207 Vulnerability
[0043] 208 W plug DETAILED DESCRIPTION
[0044] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0045] See also Figures 1 to 7 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0046] See also Figure 1, which is a schematic diagram showing a void defect 102 at a weak point 101 on the side wall of a contact hole near the bottom, wherein due to the high aspect ratio of the contact hole and the fluctuation in the process capability of depositing TiN or TaN on the bottom side wall, insufficient TiN or TaN coverage and poor growth quality are likely to occur, resulting in the weak point 101, causing the exposed Ti or Ta to directly contact with WF6 to produce gaseous TiF x or TaF x Overflowing outward, taking Ti as an example, the relevant reaction equation is: 2WF6+3Ti→2W+3TiF4, wherein this reaction occurs when SiH4 and WF6 react in large quantities to generate W, and the reaction between Ti and WF6 is relatively violent, thereby causing an explosion gap, resulting in W being unable to form a film normally at the fragile point 101, thereby forming the void defect 102.
[0047] See also Figure 2 , which is a schematic diagram of an exemplary structure of a semiconductor structure manufactured by the method for manufacturing a semiconductor structure of the present invention, wherein the adhesion barrier layer takes a Ti / TiN stack as an example. When the adhesion barrier layer has the problem of insufficient TiN coverage / poor growth quality, a good W filling effect can still be achieved. This is because the overall or local B concentration of the interlayer dielectric layer increases, and the free B diffuses to the weak point of the Ti / TiN adhesion barrier layer and reacts with WF6 to generate a W nucleation layer and BH3. The relevant reaction equation is: 2B+WF6=W+2BF3, wherein this reaction occurs before SiH4 and WF6 react in large quantities to generate W, and the gas generated by the reaction of free B and WF6 is well extracted, which can improve the performance of W deposition in the contact hole and reduce the probability of void defects.
[0048] Specifically, the method for manufacturing a semiconductor structure of the present invention comprises the following steps:
[0049] S1: providing a substrate, wherein the substrate comprises an interlayer dielectric layer and a contact hole located in the interlayer dielectric layer;
[0050] S2: forming an adhesion barrier layer on the inner wall of the contact hole, wherein the adhesion barrier layer comprises an adhesion layer / barrier layer stacked in sequence;
[0051] S3: forming a W plug in the contact hole, wherein the W plug is spaced from the inner wall of the contact hole by the adhesion barrier layer, and the source gas used to form the W plug includes tungsten hexafluoride;
[0052] Before forming the W plug, the B concentration in the preset area of the interlayer dielectric layer is adjusted to a preset concentration, the preset concentration is greater than 2.3wt%, and the preset area starts from the side wall of the contact hole and extends horizontally outward by a preset length.
[0053] Each step of the method for manufacturing the semiconductor structure of the present invention will be described in detail below with reference to the accompanying drawings.
[0054] First see Figure 3 , perform the step S1: provide a substrate, the substrate comprising an interlayer dielectric layer 201 and a contact hole 202 located in the interlayer dielectric layer 201.
[0055] As an example, the substrate further includes a substrate layer 203 , and the interlayer dielectric layer 201 is located on the substrate layer 203 .
[0056] As an example, the substrate layer 203 may be made of silicon, germanium, silicon germanium, silicon carbide, III-V compounds or other suitable semiconductor substrates, and the substrate layer 203 may be prefabricated with required semiconductor elements, such as MOS transistors, Schottky transistors, etc.
[0057] As an example, the interlayer dielectric layer 201 is a borophosphosilicate glass (BPSG) layer, wherein the interlayer dielectric layer 201 contains B to facilitate planarization and reduce the temperature required for reflow.
[0058] As an example, the contact hole 202 is formed in the interlayer dielectric layer 201 by semiconductor processes such as photolithography and etching, and the aspect ratio of the contact hole 202 can be adjusted according to actual needs.
[0059] As an example, the substrate further includes an isolation layer 204 located on the top surface of the interlayer dielectric layer 201, and the isolation layer 204 has an opening at the location of the contact hole 202. The isolation layer 204 is mainly used to isolate the interlayer dielectric layer 201 from the upper metal layer (subsequently formed on the isolation layer 204), prevent the ions (such as B ions and P ions) precipitated from the interlayer dielectric layer 201 from diffusing and affecting the upper metal layer, and can also repair the damage to the surface of the interlayer dielectric layer 201 caused by chemical mechanical polishing (CMP) during the planarization process.
[0060] As an example, the isolation layer 204 may be TEOS (tetraethoxysilane, also known as tetraethyl silicate) or other suitable materials.
[0061] Please see again Figure 4 , performing the step S2: forming an adhesion barrier layer on the inner wall of the contact hole 202, the adhesion barrier layer comprising an adhesion layer 205 and a barrier layer 206 stacked in sequence.
[0062] As an example, the adhesion layer / barrier layer includes a Ti / TiN layer or a Ta / TaN layer.
[0063] Specifically, under ideal conditions, the adhesion layer 205 can completely cover the bottom wall and side walls of the contact hole 202, and the barrier layer 206 can completely cover the surface of the adhesion layer 205. However, when the aspect ratio of the contact hole 202 is high and the process capability of depositing the barrier layer fluctuates, problems such as insufficient barrier layer coverage and poor growth quality are likely to occur, especially at the lower position of the side wall of the contact hole 202. Figure 4 A weak point 207 which is not covered by the barrier layer is shown as an example.
[0064] Please see again Figure 5 , performing the step S3: forming a W plug 208 in the contact hole 202 , wherein the W plug 208 is spaced from the inner wall of the contact hole 202 by the adhesion barrier layer.
[0065] As an example, the W plug 208 is formed by chemical vapor deposition (CVD), and the source gases used are mainly tungsten hexafluoride (WF6) and silane (SiH4).
[0066] Specifically, in order to avoid the occurrence of void defects in the W plug 208 due to the existence of the fragile point 207, in the present invention, before forming the W plug 208, the B concentration in the preset area of the interlayer dielectric layer 201 is adjusted to a preset concentration, and the preset concentration is greater than 2.3wt%. The preset area starts from the side wall of the contact hole 202 and extends horizontally outward by a preset length, thereby ensuring that there is enough B near the side wall of the contact hole 202, and utilizing the critical surface reaction of free B and WF6 at the fragile point 207 to generate W layer nucleation, thereby reducing the contact area between WF6 and the adhesion layer 205, and avoiding void defects caused by incomplete coverage of the barrier layer 206.
[0067] In some embodiments, the predetermined region is the entire region of the interlayer dielectric layer 201. In this case, a dielectric layer having a B concentration of the predetermined concentration may be directly grown on the substrate layer 203 as the interlayer dielectric layer 201.
[0068] As an example, the preset concentration range is preferably 3wt%-5wt%, wherein if the B concentration in the interlayer dielectric layer 201 is too low, it is insufficient to react at the fragile point to generate good quality W, and if the B concentration in the interlayer dielectric layer 201 is too high, it will affect the temperature required for the planarization reflow process.
[0069] The following is an example of the relevant parameters for preparing a BPSG layer with a B concentration of 3.1wt% as the interlayer dielectric layer 201 using atmospheric pressure chemical vapor deposition (AP-CVD), wherein the reaction equation is: O3+TEOS+B(OC2H5)3+PO(OC2H5)3→BPSG(3.1%)+by-products, the O3 flow rate is 8000sccm, the TEOS flow rate is 1050sccm, the TEPO flow rate is 50sccm, the TEB flow rate is 260sccm, the reaction temperature is 480°, and the gas pressure is 200.0torr.
[0070] In some other embodiments, the preset region is a local region of the interlayer dielectric layer 201. The method for adjusting the B concentration of the preset region of the interlayer dielectric layer 201 to a preset concentration before forming the W plug includes: first growing a dielectric layer with a B concentration lower than the preset concentration as the interlayer dielectric layer 201, and after forming the contact hole 202 and the adhesion barrier layer, implanting B ions into a local region of the interlayer dielectric layer 201 by an ion implantation method, wherein the local region starts from the side wall of the contact hole 202 and extends horizontally outward by 5nm-15nm.
[0071] As an example, see Figure 6 , which is a schematic diagram showing ion implantation before forming the W plug.
[0072] As an example, the original B concentration of the interlayer dielectric layer 201 is 2.3wt%. The purpose of ion implantation is to adjust the dielectric layer near the side wall of the contact hole 202 to a higher concentration (greater than 2.3wt%, preferably 3wt%-5wt%) to provide enough free B.
[0073] As an example, while B ions are implanted in a local region of the interlayer dielectric layer, B ions are also implanted in the adhesion barrier layer, that is, the adhesion layer 205 and the barrier layer 206 .
[0074] As an example, the energy range of the ion implantation is 4KeV-8KeV, and the dose range of the ion implantation is 3×10 14 atoms / cm 2 -8×10 14 atoms / cm 2 .
[0075] As an example, the B ions are implanted obliquely, for example, at an angle of 45° (relative to the plane where the interlayer dielectric layer 201 is located), which is beneficial for the ion implantation into the sidewall of the contact hole 202 .
[0076] As an example, the ion implantation process is divided into multiple times, for example, 4 times, that is, all ion amounts are implanted in four times. Before the next ion implantation, the wafer is rotated by a certain angle, so that the B ions can be implanted more uniformly in the contact holes.
[0077] The method for manufacturing the semiconductor structure of the present invention provides free B by adjusting the concentration of B in the interlayer dielectric layer. When the adhesion barrier layer is not fully covered or the film quality is poor, the free B diffuses to the weak points of the adhesion barrier layer and reacts with WF6 to generate a W-shaped nucleation layer, thereby reducing the contact area between WF6 and the adhesion layer, avoiding void defects caused by incomplete coverage of the barrier layer during the W deposition process, thereby improving the void defect problem and effectively improving the reliability and yield of the product.
[0078] The present invention also provides a semiconductor structure, see Figure 7 , which is a schematic diagram of an exemplary structure of the semiconductor structure, includes a substrate, an adhesion barrier layer and a W plug 208, wherein the substrate includes an interlayer dielectric layer 201 and a contact hole 202 located in the interlayer dielectric layer 201, the adhesion barrier layer is located on the inner wall of the contact hole 202, the adhesion barrier layer includes an adhesion layer 205 and a barrier layer 206 stacked in sequence, the W plug 208 is located in the contact hole 202, and the W plug 208 is spaced from the inner wall of the contact hole 202 by the adhesion barrier layer, wherein the B concentration of a preset area of the interlayer dielectric layer 201 is greater than 2.3wt%, and the preset area starts from the side wall of the contact hole 202 and extends horizontally outward by a preset length. In this embodiment, the substrate also includes a substrate layer 203 located below the interlayer dielectric layer 201 and an isolation layer 204 located above the interlayer dielectric layer 201, and the isolation layer 204 has an opening at the location of the contact hole 202.
[0079] It should be pointed out that, depending on the specific aspect ratio of the contact hole 202 and the fluctuation of the process capability of depositing TiN, the barrier layer 206 may completely cover the surface of the adhesion layer 205, or there may be problems of insufficient barrier layer coverage and poor growth quality. However, regardless of whether the barrier layer 206 completely covers the surface of the adhesion layer 205, in the semiconductor structure of the present invention, the W plug 208 has no void defects or the void defects are significantly improved. The reason is that the overall area or local area of the interlayer dielectric layer 201 has a higher B concentration, which can improve the performance of contact hole W deposition and reduce the probability of void defects.
[0080] In summary, the method for manufacturing the semiconductor structure of the present invention provides free B by adjusting the concentration of B in the interlayer dielectric layer. When the adhesion barrier layer is not fully covered or the film quality is poor, the free B diffuses to the weak point of the adhesion barrier layer and reacts with WF6 to form a W-shaped nucleation layer, thereby reducing the contact area between WF6 and the adhesion layer in the adhesion barrier layer, avoiding void defects caused by incomplete barrier coverage in the adhesion barrier layer during the W deposition process, thereby improving the void defect problem and effectively improving the reliability and yield of the product. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.
[0081] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A method for manufacturing a semiconductor structure, characterized in that: The following steps are involved: Providing a substrate, the substrate comprising an interlayer dielectric layer and a contact hole located in the interlayer dielectric layer; forming an adhesion barrier layer on the inner wall of the contact hole, wherein the adhesion barrier layer comprises an adhesion layer / barrier layer stacked in sequence; forming a W plug in the contact hole, wherein the W plug is spaced from the inner wall of the contact hole by the adhesion barrier layer, and the source gas used to form the W plug includes tungsten hexafluoride; Before forming the W plug, the B concentration in the preset area of the interlayer dielectric layer is adjusted to a preset concentration, the preset concentration is greater than 2.3wt%, and the preset area starts from the side wall of the contact hole and extends horizontally outward by a preset length.
2. The method for manufacturing a semiconductor structure according to claim 1, wherein: The preset concentration ranges from 3wt% to 5wt%.
3. The method for manufacturing a semiconductor structure according to any one of claims 1 to 2, characterized in that: The method of adjusting the B concentration of a preset area of the interlayer dielectric layer to a preset concentration before forming the W plug includes: growing a dielectric layer with a B concentration of the preset concentration as the interlayer dielectric layer, and the preset area is the entire area of the interlayer dielectric layer.
4. The method for manufacturing a semiconductor structure according to claim 3, characterized in that: The interlayer dielectric layer includes a borophosphosilicate glass layer, and the method for forming the borophosphosilicate glass layer includes a normal pressure chemical vapor deposition method; the adhesion layer / barrier layer includes a Ti / TiN layer or a Ta / TaN layer.
5. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The method for adjusting the B concentration of a preset area of the interlayer dielectric layer to a preset concentration before forming the W plug comprises: growing a dielectric layer with a B concentration lower than the preset concentration as the interlayer dielectric layer, and after forming the contact hole and the adhesion barrier layer, using an ion implantation method to implant B ions into a local area of the interlayer dielectric layer, wherein the local area starts from the side wall of the contact hole and extends horizontally outward by 5nm-15nm.
6. The method for manufacturing a semiconductor structure according to claim 5, characterized in that: While B ions are implanted in the local region of the interlayer dielectric layer, B ions are also implanted in the adhesion barrier layer.
7. The method for manufacturing a semiconductor structure according to claim 5, characterized in that: The energy range of the ion implantation is 4KeV-8KeV, and the dose range of the ion implantation is 3×10 14 atoms / cm 2 -8×10 14 atoms / cm 2 .
8. The method for manufacturing a semiconductor structure according to any one of claims 5 to 7, characterized in that: The interlayer dielectric layer includes a borophosphosilicate glass layer, and the adhesion layer / barrier layer includes a Ti / TiN layer or a Ta / TaN layer.
9. The method for manufacturing a semiconductor structure according to claim 1, wherein: The substrate further comprises an isolation layer located on the top surface of the interlayer dielectric layer, and the isolation layer has an opening at the location of the contact hole.
10. A semiconductor structure, characterized in that: include: A substrate, comprising an interlayer dielectric layer and a contact hole located in the interlayer dielectric layer; an adhesion barrier layer, located on the inner wall of the contact hole, the adhesion barrier layer comprising an adhesion layer / barrier layer stacked in sequence; a W plug, located in the contact hole, the W plug and the inner wall of the contact hole being spaced apart by the adhesion barrier layer; The B concentration in the preset region of the interlayer dielectric layer is greater than 2.3 wt %, and the preset region starts from the side wall of the contact hole and extends horizontally outward by a preset length.