Electronic package and fabrication method thereof
By using an offset suppression layer with a thermal expansion coefficient matching the package colloid in the semiconductor package, the problem of semiconductor chip offset caused by mismatch in the thermal expansion coefficient is solved, and the yield of the package is improved.
Patent Information
- Application Number
- CN202311055037.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-08-15
- Filing Date
- 2023-08-21
- Publication Date
- 2025-02-21
AI Technical Summary
During the molding or curing of high-temperature packaging colloids, the semiconductor chip is offset and yield loss due to the mismatch of the thermal expansion coefficient of the glass substrate and the packaging colloids.
A shift suppression layer with an offset suppression layer relative to the first surface and the second surface, whose thermal expansion coefficient is equal to or close to the packaging colloid is formed on the carrier, covering the first electronic component and the second electronic component to suppress its deviation. shift.
By using the offset suppression layer, the offset of the packaging colloid to the semiconductor chip is effectively suppressed or prevented, and the yield of the package is improved, and the deviation problem caused by the difference in thermal expansion coefficient is avoided.
Smart Images
Figure CN119495646A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a packaging structure, in particular to an electronic packaging component with a deviation suppression layer and a manufacturing method thereof. Background Art
[0002] When a semiconductor chip on a glass substrate is subjected to a high-temperature molding or curing process of a packaging colloid, since the coefficient of thermal expansion (CTE) of the glass substrate is much smaller than that of the packaging colloid, for example, the CTEs of the glass substrate and the packaging colloid are 0.3 ppm / K and 7 ppm / K respectively, the glass substrate will expand outward when the packaging colloid is heated and will contract inward when the packaging colloid is cooled, causing the semiconductor chip to shift outward by an expansion amount as the glass substrate expands outward and shift inward by an inward amount as the glass substrate contracts inward.
[0003] Furthermore, since the thermal expansion coefficient of the glass substrate (e.g., 0.3ppm / K) and the thermal expansion coefficient of the packaging colloid (e.g., 7ppm / K) are not at the same level, the outward expansion and inward contraction of the semiconductor chip on the glass substrate are not the same or the difference is too large, causing the semiconductor chip to shift (e.g., unable to return to the initial position), thereby causing a loss in the yield of the semiconductor package.
[0004] Figures 1A to 1C It is a cross-sectional schematic diagram of a method for manufacturing a conventional semiconductor package 1 .
[0005] like Figure 1A As shown, two semiconductor chips 12 are first disposed on a glass substrate 10 having a first length L1 through an adhesive layer 11, respectively. Each semiconductor chip 12 may have an active surface 12a, an inactive surface 12b and a side surface 12c. A plurality of electrode pads 12d may be formed on the active surface 12a of the semiconductor chip 12, and the initial position of the semiconductor chip 12 (such as the side surface 12c) is the first position P1.
[0006] like Figure 1B As shown, when the semiconductor chip 12 on the glass substrate 10 is subjected to a high-temperature molding or curing process of the encapsulation 13, the glass substrate 10 will expand outward from the first length L1 (see FIG. 1 ) along the outward expansion direction A1 when the encapsulation 13 is heated. Figure 1A ) expands outward to a second length L2, and the semiconductor chip 12 shifts from the first position P1 (initial position) to the second position P2 as the glass substrate 10 expands outward, and the first position P1 and the second position P2 of the semiconductor chip 12 differ by an outward expansion amount B1 (such as a first offset distance).
[0007] like Figure 1CAs shown, the glass substrate 10 will shrink from the second length L2 (see FIG. Figure 1B ) shrinks inward to a third length L3, and the semiconductor chip 12 shifts from the second position P2 to the third position P3 as the glass substrate 10 shrinks inward, and the second position P2 and the third position P3 of the semiconductor chip 12 differ by a shrinkage amount B2 (such as a second offset distance).
[0008] In other words, in the conventional semiconductor package 1, the thermal expansion coefficient of the glass substrate 10 (e.g., 0.3 ppm / K) is much smaller than the thermal expansion coefficient of the encapsulation colloid 13 (e.g., 7 ppm / K) and they are not of the same grade, so that the outward expansion amount B1 and the inward contraction amount B2 of the semiconductor chip 12 on the glass substrate 10 are not equal or the difference is too large, causing the semiconductor chip 12 to shift (e.g., unable to return to the initial position or the first position P1), thereby causing a yield loss of the semiconductor package 1.
[0009] Therefore, how to overcome the above-mentioned problems of the prior art has become a difficult problem that needs to be overcome urgently in the industry. Summary of the invention
[0010] In view of the various deficiencies of the above-mentioned prior art, the present invention provides an electronic package, comprising: a carrier; an offset suppression layer having a first surface and a second surface opposite to each other, and the second surface is disposed on the carrier; a first electronic component and a second electronic component, which are respectively disposed on the first surface of the offset suppression layer; and a packaging colloid, which is formed on the first surface of the offset suppression layer to respectively cover the first electronic component and the second electronic component, wherein the offset suppression layer is used to suppress the offset of the first electronic component and the second electronic component.
[0011] The present invention also provides a method for manufacturing an electronic package, comprising: arranging an offset suppression layer having a first surface and a second surface opposite to each other on a carrier with the second surface thereof; arranging a first electronic component and a second electronic component on the first surface of the offset suppression layer respectively; and forming a packaging colloid on the first surface of the offset suppression layer to respectively cover the first electronic component and the second electronic component, wherein the offset suppression layer is used to suppress the offset of the first electronic component and the second electronic component.
[0012] In the aforementioned electronic package and the manufacturing method thereof, the electronic package may also include a first adhesive layer and a second adhesive layer, so as to respectively bond the first electronic component and the second electronic component to the first surface of the offset suppression layer through the first adhesive layer and the second adhesive layer.
[0013] In the aforementioned electronic package and its manufacturing method, the offset suppression layer can be made of polyimide material, so that the offset suppression layer made of polyimide material is formed or coated on the carrier. At the same time, the thermal expansion coefficient of the offset suppression layer and the thermal expansion coefficient of the packaging colloid can be equal or close to each other and belong to the same level.
[0014] In the aforementioned electronic package and its manufacturing method, the thickness of the offset suppression layer can be between 40 microns and 70 microns, or the ratio of the thickness of the offset suppression layer to the thickness of the packaging colloid can be 1.75:1, or the thickness of the first electronic component and the thickness of the second electronic component can be less than 60 microns.
[0015] In the aforementioned electronic package and the manufacturing method thereof, the first surface of the offset suppression layer may be a rough surface, and the rough surface of the offset suppression layer is bonded to the packaging colloid used to cover the first electronic component and the second electronic component.
[0016] In the aforementioned electronic package and its manufacturing method, the first surface of the offset suppression layer may be formed with a plurality of protrusions and a plurality of recesses, and the plurality of protrusions and a plurality of recesses of the first surface of the offset suppression layer are combined with the packaging colloid for covering the first electronic component and the second electronic component.
[0017] In the aforementioned electronic package and its manufacturing method, the first surface of the offset suppression layer may be formed with a first recess and a second recess, and the first electronic component and the second electronic component are respectively coupled to the first recess and the second recess of the first surface of the offset suppression layer.
[0018] As can be seen from the above, in the electronic package and the manufacturing method thereof of the present invention, an offset suppression layer is mainly formed on a carrier, so that a first electronic component and a second electronic component are respectively arranged on the offset suppression layer, and then a packaging colloid is formed on the offset suppression layer to respectively cover the first electronic component and the second electronic component, so that the offset suppression layer can effectively suppress or prevent the possible offset of the packaging colloid to the first electronic component and the second electronic component, thereby avoiding the yield loss of the semiconductor package.
[0019] At the same time, the present invention utilizes the equal or similar thermal expansion coefficients of the offset suppression layer and the packaging colloid, so that the first electronic component and the second electronic component on the offset suppression layer have equal or similar outward expansion amounts when the packaging colloid is heated and inward shrinkage amounts when the packaging colloid is cooled, so as to achieve the offset suppression effect of the first electronic component and the second electronic component on the offset suppression layer during the molding or curing process of the packaging colloid, thereby avoiding the offset of the first electronic component and the second electronic component due to the excessive difference in thermal expansion coefficients of different materials or not belonging to the same level.
[0020] Furthermore, the thickness of the offset suppression layer of the present invention may be between 40 and 70 microns (μm), or the ratio of the thickness of the offset suppression layer to the thickness of the packaging colloid may be approximately 1.75:1, or the thickness of the first electronic component and the thickness of the second electronic component may be less than 60 μm, so that the offset suppression layer can provide the best offset suppression effect for the first electronic component and the second electronic component. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] Figures 1A to 1C The cross-sectional view is a schematic diagram of a conventional method for manufacturing a semiconductor package.
[0022] FIG. 2A to FIG. 2C It is a cross-sectional schematic diagram of the method for manufacturing the electronic package of the present invention.
[0023] Figure 3A and Figure 3B They are cross-sectional schematic diagrams of different embodiments of the electronic package of the present invention.
[0024] Main component symbols
[0025] 1 Semiconductor Package
[0026] 10 Glass Substrate
[0027] 11 Adhesive layer
[0028] 12 Semiconductor Chip
[0029] 12a, 24a, 25a Action surface
[0030] 12b, 24b, 25b Non-active surface
[0031] 12c,24c,25c side
[0032] 12d,24d,25d electrode pads
[0033] 13,26 Encapsulation colloid
[0034] 2 Electronic packaging
[0035] 20 Bearing
[0036] 20a First side
[0037] 20b Second side
[0038] 21. Deviation suppression layer
[0039] 21a First surface
[0040] 21b Second surface
[0041] 21c convex part
[0042] 21d concavity
[0043] 21e first recess
[0044] 21f Second recess
[0045] 22 First adhesive layer
[0046] 23 Second adhesive layer
[0047] 24 First Electronic Components
[0048] 25 Second electronic component
[0049] 26a Surface
[0050] A1 Expansion direction
[0051] A2 Indent direction
[0052] B1 Expansion
[0053] B2 Indent
[0054] H1,H2,H3,H4 Thickness
[0055] P1 First position
[0056] P2 Second position
[0057] P3 Third position
[0058] L1 First Length
[0059] L2 Second length
[0060] L3 The third length. DETAILED DESCRIPTION
[0061] The following describes the implementation of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.
[0062] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions under which the present invention can be implemented, so they have no substantial technical significance. Any structural modification, change in proportional relationship, or adjustment in size should still fall within the scope of the technical contents disclosed by the present invention without affecting the effects and purposes that can be achieved by the present invention. At the same time, the terms such as "upper", "lower", "one", "first", and "second" quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of the present invention without substantially changing the technical contents.
[0063] FIG. 2A to FIG. 2C The cross-sectional view of the manufacturing method of the electronic package 2 of the present invention is shown in FIG. Meanwhile, the term "at least one" in the present invention means more than one (such as one, two, three or more than four), and "more than one" means more than two (such as two, three, four or more than ten).
[0064] like Figure 2A As shown, a carrier 20 having a first side 20a (such as the upper side) and a second side 20b (such as the lower side) is provided, and a displacement suppression layer 21 having a first surface 21a (such as the upper surface) and a second surface 21b (such as the lower surface) is formed on the first side 20a of the carrier 20 with the second surface 21b, and at least one first electronic component 24 and at least one second electronic component 25 are respectively arranged at different positions on the first surface 21a of the displacement suppression layer 21. For example, the first electronic component 24 and the second electronic component 25 are respectively bonded to different positions on the first surface 21a of the displacement suppression layer 21 through a first adhesive layer 22 and a second adhesive layer 23.
[0065] In one embodiment, the carrier 20 may be a glass substrate, a semiconductor substrate, a silicon substrate, etc., and the carrier 20 may also be other carrier units for carrying the first electronic component 24 and the second electronic component 25, such as a wafer, a silicon interposer, or other plates, but is not limited thereto.
[0066] In one embodiment, the first electronic component 24 or the second electronic component 25 may be an active component, a passive component or a combination thereof. For example, the active component is a semiconductor chip, and the passive component is a resistor, a capacitor or an inductor.
[0067] In one embodiment, the first electronic component 24 may be a semiconductor chip and has an opposite active surface 24a and an inactive surface 24b, and also has a side surface 24c respectively connecting the active surface 24a and the inactive surface 24b, and the active surface 24a of the first electronic component 24 may have a plurality of electrode pads 24d. Meanwhile, the second electronic component 25 may be another semiconductor chip and has an opposite active surface 25a and an inactive surface 25b, and also has a side surface 25c respectively connecting the active surface 25a and the inactive surface 25b, and the active surface 25a of the second electronic component 25 may have a plurality of electrode pads 25d.
[0068] like Figure 2B As shown, the first electronic component 24 and the second electronic component 25 on the offset suppression layer 21 are subjected to a molding and curing process of the encapsulant 26, and the encapsulant 26 is formed on the first surface 21a of the offset suppression layer 21 to respectively cover the first electronic component 24 and the second electronic component 25.
[0069] In one embodiment, the encapsulation colloid 26 is formed on the first surface 21a of the offset suppression layer 21, so as to respectively cover the first adhesive layer 22 (such as the side), the second adhesive layer 23 (such as the side), the first electronic component 24 (such as the side 24c) and the second electronic component 25 (such as the side 25c) through the encapsulation colloid 26.
[0070] In one embodiment, the encapsulant 26 may be further formed on the active surface 24 a of the first electronic component 24 and the active surface 25 a of the second electronic component 25 to cover the plurality of electrode pads 24 d and the plurality of electrode pads 25 d.
[0071] In one embodiment, the offset suppression layer 21 may be made of a polyimide (PI) material, so that the offset suppression layer 21 made of the polyimide (PI) material is formed or coated on the first side 20a of the carrier 20, and the thermal expansion coefficient of the offset suppression layer 21 (e.g., 4 ppm / K) may be equal to or close to the thermal expansion coefficient of the packaging colloid 26 (e.g., 7 ppm / K), so that the thermal expansion coefficient of the offset suppression layer 21 and the thermal expansion coefficient of the packaging colloid 26 are of the same level.
[0072] In one embodiment, the thermal expansion coefficient of the offset suppression layer 21 (e.g., 4 ppm / K) and the thermal expansion coefficient of the encapsulant 26 (e.g., 7 ppm / K) are equal or similar, so that the "extension amount" of the first electronic component 24 and the second electronic component 25 on the offset suppression layer 21 when the encapsulant 26 is heated and the "contraction amount" when the encapsulant 26 is cooled are equal or similar. Thus, the present invention can achieve the offset suppression effect of the first electronic component 24 and the second electronic component 25 on the offset suppression layer 21 during the molding or curing process of the encapsulant 26, thereby avoiding the offset of the first electronic component 24 and the second electronic component 25 due to the large difference in thermal expansion coefficients of different materials or not belonging to the same level.
[0073] like Figure 2C As shown, in one embodiment, a portion of the encapsulant 26 can be further removed by thinning methods such as grinding, etching or photolithography, so that a surface 26a (such as the upper surface) of the encapsulant 26 exposes multiple electrode pads 24d on the active surface 24a of the first electronic component 24 and multiple electrode pads 25d on the active surface 25a of the second electronic component 25.
[0074] In one embodiment, the surface 26a (such as the upper surface) of the encapsulant 26 can be coplanar with the active surface 24a of the first electronic component 24 and / or the active surface 25a of the second electronic component 25, so that the surface 26a of the encapsulant 26 is flush with the active surface 24a of the first electronic component 24 and / or the active surface 25a of the second electronic component 25, but the present invention is not limited thereto.
[0075] In one embodiment, the thickness H1 of the offset suppression layer 21 may be between 40 μm and 70 μm, so that the offset suppression layer 21 can provide the best offset suppression effect for the first electronic component 24 and the second electronic component 25 .
[0076] In one embodiment, the thickness H1 of the offset suppression layer 21 and the thickness H4 of the encapsulant 26 can be selected according to different requirements of the thickness H2 of the first electronic component 24 and the thickness H3 of the second electronic component 25. For example, the ratio of the thickness H1 of the offset suppression layer 21 to the thickness H4 of the encapsulant 26 can be about 1.75:1, that is, the thickness H1 of the offset suppression layer 21 is about 1.75 times the thickness H4 of the encapsulant 26, so that the offset suppression layer 21 can provide the best offset suppression effect for the first electronic component 24 and the second electronic component 25.
[0077] In one embodiment, the thickness H2 of the first electronic component 24 and the thickness H3 of the second electronic component 25 may be less than 60 μm, so that the offset suppression layer 21 can provide the best offset suppression effect for the first electronic component 24 and the second electronic component 25 .
[0078] Figure 3A and Figure 3B They are cross-sectional schematic diagrams of different embodiments of the electronic package 2 of the present invention.
[0079] like Figure 3A As shown, the first surface 21a (such as the upper surface) of the offset suppression layer 21 of the present embodiment can be a rough surface (such as a non-flat surface or a non-smooth surface), and the rough surface of the offset suppression layer 21 can be bonded to the first adhesive layer 22 and the second adhesive layer 23, respectively, and can also be bonded to the encapsulation 26 used to cover the first electronic component 24 and the second electronic component 25. Accordingly, the present invention can improve the bonding strength of the offset suppression layer 21 with the first adhesive layer 22, the second adhesive layer 23 and the encapsulation 26 respectively through the rough surface of the offset suppression layer 21, and can also make the first electronic component 24 and the second electronic component 25 on the rough surface of the offset suppression layer 21 less susceptible to the molding or curing process of the encapsulation 26 and thus causing offset.
[0080] For example, the first surface 21a (such as the upper surface) of the offset suppression layer 21 may be formed with a plurality of protrusions 21c (such as protrusions) and a plurality of recesses 21d (such as recesses). The plurality of protrusions 21c and the plurality of recesses 21d of the first surface 21a of the offset suppression layer 21 may be combined with the first adhesive layer 22 and the second adhesive layer 23, and may also be combined with the packaging colloid 26 used to cover the first electronic component 24 and the second electronic component 25.
[0081] like Figure 3B As shown, at least one first recess 21e and at least one second recess 21f may be formed at the first surface 21a (such as the upper surface) of the displacement suppression layer 21 of the present embodiment to respectively accommodate at least one first electronic component 24 and at least one second electronic component 25, and the first electronic component 24 and the second electronic component 25 may be respectively bonded to the first recess 21e and the second recess 21f of the first surface 21a of the displacement suppression layer 21 through the first adhesive layer 22 and the second adhesive layer 23. Accordingly, the present invention can effectively fix (restrict) the first electronic component 24 on the first adhesive layer 22 and the second electronic component 25 on the second adhesive layer 23 at the first recess 21e and the second recess 21f of the first surface 21a of the displacement suppression layer 21, and can also make the first electronic component 24 and the second electronic component 25 at the first recess 21e and the second recess 21f of the first surface 21a of the displacement suppression layer 21 less susceptible to the molding or curing process of the encapsulant 26 and thus cause displacement.
[0082] For example, the first adhesive layer 22 and the inactive surface 24b of the first electronic component 24 may be respectively located in the first recess 21e of the offset suppression layer 21, and a portion of the side surface 24c of the first electronic component 24 may directly contact the side wall of the first recess 21e of the offset suppression layer 21. At the same time, the second adhesive layer 23 and the inactive surface 25b of the second electronic component 25 may be respectively located in the second recess 21f of the offset suppression layer 21, and a portion of the side surface 25c of the second electronic component 25 may directly contact the side wall of the second recess 21f of the offset suppression layer 21.
[0083] The present invention also provides an electronic package 2, comprising: a carrier 20; a deviation suppression layer 21, which is formed on the carrier 20, and the deviation suppression layer 21 has a first surface 21a and a second surface 21b opposite to each other; a first electronic component 24 and a second electronic component 25, which are respectively arranged on the first surface 21a of the deviation suppression layer 21; and a packaging colloid 26, which is formed on the first surface 21a of the deviation suppression layer 21 to respectively cover the first electronic component 24 and the second electronic component 25, wherein the deviation suppression layer 21 is used to suppress the deviation of the first electronic component 24 and the second electronic component 25.
[0084] In one embodiment, the electronic package 2 may also include a first adhesive layer 22 and a second adhesive layer 23 , wherein the first electronic component 24 and the second electronic component 25 are bonded to the first surface 21 a of the offset suppression layer 21 via the first adhesive layer 22 and the second adhesive layer 23 , respectively.
[0085] In one embodiment, the offset suppression layer 21 may be made of a polyimide (PI) material, so that the offset suppression layer 21 made of the polyimide (PI) material is formed or coated on the first side 20 a of the carrier 20 .
[0086] In one embodiment, the thermal expansion coefficient of the offset suppression layer 21 and the thermal expansion coefficient of the encapsulant 26 are equal to or close to each other and belong to the same level.
[0087] In one embodiment, the thickness H1 of the offset suppression layer 21 is between 40 micrometers and 70 micrometers.
[0088] In one embodiment, the ratio of the thickness H1 of the offset suppression layer 21 to the thickness H4 of the encapsulant 26 is approximately 1.75:1, that is, the thickness H1 of the offset suppression layer 21 is approximately 1.75 times the thickness H4 of the encapsulant 26 .
[0089] In one embodiment, the thickness H2 of the first electronic component 24 and the thickness H3 of the second electronic component 25 are both less than 60 micrometers.
[0090] In one embodiment, the first surface 21 a of the offset suppression layer 21 is a rough surface, and the rough surface of the offset suppression layer 21 is bonded to the encapsulant 26 for encapsulating the first electronic component 24 and the second electronic component 25 .
[0091] In one embodiment, the first surface 21a of the offset suppression layer 21 is formed with a plurality of protrusions 21c and a plurality of recesses 21d, and the plurality of protrusions 21c and a plurality of recesses 21d of the first surface 21a of the offset suppression layer 21 are combined with the packaging resin 26 for covering the first electronic component 24 and the second electronic component 25.
[0092] In one embodiment, the first surface 21a of the offset suppression layer 21 is formed with a first recess 21e and a second recess 21f, and the first electronic component 24 and the second electronic component 25 are respectively coupled to the first recess 21e and the second recess 21f of the first surface 21a of the offset suppression layer 21.
[0093] In summary, the electronic package and method thereof of the present invention have at least the following features, advantages or technical effects.
[0094] 1. When the present invention performs a molding or curing process of the packaging colloid on the first electronic component and the second electronic component, the packaging colloid can be formed on the offset suppression layer to respectively cover the first electronic component and the second electronic component, so that the offset suppression layer can effectively suppress or prevent the possible offset of the packaging colloid on the first electronic component and the second electronic component, thereby avoiding the yield loss of the semiconductor package.
[0095] Second, the present invention utilizes the equal or similar thermal expansion coefficients of the offset suppression layer and the encapsulation colloid, so that the first electronic component and the second electronic component on the offset suppression layer expand outward when the encapsulation colloid is heated and shrink inward when the encapsulation colloid is cooled to be equal or similar, so as to achieve the offset suppression effect of the first electronic component and the second electronic component on the offset suppression layer during the molding or curing process of the encapsulation colloid, thereby avoiding the offset of the first electronic component and the second electronic component due to the large difference in thermal expansion coefficients of different materials or not belonging to the same level.
[0096] 3. The thickness of the offset suppression layer of the present invention may be between 40 and 70 microns (μm), or the ratio of the thickness of the offset suppression layer to the thickness of the encapsulation colloid may be approximately 1.75:1, or the thickness of the first electronic component and the thickness of the second electronic component may be less than 60 μm, so that the offset suppression layer can provide the best offset suppression effect for the first electronic component and the second electronic component.
[0097] Fourth, the first surface of the offset suppression layer of the present invention can be a rough surface (such as a non-flat surface or a non-smooth surface), so that the bonding strength between the offset suppression layer and the packaging colloid can be improved through this rough surface, and the first electronic component and the second electronic component on the rough surface of the offset suppression layer can be less susceptible to the molding or curing process of the packaging colloid and cause offset.
[0098] 5. The first surface of the offset suppression layer of the present invention can be formed with a plurality of protrusions and a plurality of recesses, so as to enhance the bonding strength between the offset suppression layer and the packaging colloid through the plurality of protrusions and a plurality of recesses, and also make the first electronic components and the second electronic components on the plurality of protrusions and a plurality of recesses of the offset suppression layer less susceptible to displacement caused by the molding or curing process of the packaging colloid.
[0099] 6. The first surface of the offset suppression layer of the present invention can be formed with a first recess and a second recess to respectively accommodate the first electronic component and the second electronic component, so as to facilitate fixing (confining) the first electronic component and the second electronic component at the first recess and the second recess on the first surface of the offset suppression layer, so that the first electronic component and the second electronic component are not easily affected by the molding or curing process of the packaging colloid and cause offset.
[0100] The above embodiments are used to illustrate the principles and effects of the present invention, but are not used to limit the present invention. Any person skilled in the art may modify the above embodiments without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the claims.
Claims
1. An electronic package, comprising: a bearing member; A deviation suppression layer has a first surface and a second surface opposite to each other, and the second surface is disposed on the carrier; A first electronic element and a second electronic element are respectively disposed on the first surface of the offset suppression layer; as well as A packaging colloid is formed on the first surface of the displacement suppression layer to respectively cover the first electronic component and the second electronic component, wherein the displacement suppression layer is used to suppress the displacement of the first electronic component and the second electronic component. 2 . The electronic package as claimed in claim 1 , further comprising a first adhesive layer and a second adhesive layer, so that the first electronic component and the second electronic component are bonded to the first surface of the offset suppression layer through the first adhesive layer and the second adhesive layer respectively.
3. The electronic package of claim 1, wherein: The offset suppression layer is made of polyimide material.
4. The electronic package of claim 1, wherein: The thermal expansion coefficient of the offset suppression layer is equal to or close to the thermal expansion coefficient of the packaging colloid and belongs to the same level.
5. The electronic package of claim 1, wherein: The thickness of the offset suppression layer is between 40 micrometers and 70 micrometers.
6. The electronic package of claim 1, wherein: The ratio of the thickness of the offset suppression layer to the thickness of the encapsulant is 1.75:
1.
7. The electronic package of claim 1, wherein: The thickness of the first electronic component and the thickness of the second electronic component are both less than 60 micrometers.
8. The electronic package of claim 1, wherein: The first surface of the offset suppression layer is a rough surface, and the rough surface of the offset suppression layer is combined with the packaging colloid used for covering the first electronic component and the second electronic component.
9. The electronic package of claim 1, wherein: A plurality of convex portions and a plurality of concave portions are formed on the first surface of the offset suppression layer, and the plurality of convex portions and the plurality of concave portions of the first surface of the offset suppression layer are combined with the packaging colloid for covering the first electronic component and the second electronic component.
10. The electronic package of claim 1, wherein: A first concave portion and a second concave portion are formed on the first surface of the offset suppression layer, and the first electronic component and the second electronic component are respectively combined with the first concave portion and the second concave portion of the first surface of the offset suppression layer.
11. A method for manufacturing an electronic package, comprising: A displacement suppression layer having a first surface and a second surface opposite to each other is disposed on a carrier with the second surface; Disposing a first electronic component and a second electronic component on the first surface of the offset suppression layer respectively; as well as A packaging colloid is formed on the first surface of the displacement suppression layer to respectively cover the first electronic component and the second electronic component, wherein the displacement suppression layer is used to suppress the displacement of the first electronic component and the second electronic component.
12. The method for manufacturing an electronic package according to claim 11, wherein: The manufacturing method also includes bonding the first electronic component and the second electronic component to the first surface of the offset suppression layer through a first adhesive layer and a second adhesive layer respectively.
13. The method for manufacturing an electronic package according to claim 11, wherein: The offset suppression layer is made of polyimide material.
14. The method for manufacturing an electronic package according to claim 11, wherein: The thermal expansion coefficient of the offset suppression layer is equal to or close to the thermal expansion coefficient of the packaging colloid and belongs to the same level.
15. The method for manufacturing an electronic package according to claim 11, wherein: The thickness of the offset suppression layer is between 40 micrometers and 70 micrometers.
16. The method for manufacturing an electronic package according to claim 11, wherein: The ratio of the thickness of the offset suppression layer to the thickness of the encapsulant is 1.75:
1.
17. The method for manufacturing an electronic package according to claim 11, wherein: The thickness of the first electronic component and the thickness of the second electronic component are both less than 60 micrometers.
18. The method for manufacturing an electronic package according to claim 11, wherein: The first surface of the offset suppression layer is a rough surface, and the rough surface of the offset suppression layer is combined with the packaging colloid used for covering the first electronic component and the second electronic component.
19. The method for manufacturing an electronic package according to claim 11, wherein: A plurality of convex portions and a plurality of concave portions are formed on the first surface of the offset suppression layer, and the plurality of convex portions and the plurality of concave portions of the first surface of the offset suppression layer are combined with the packaging colloid for covering the first electronic component and the second electronic component.
20. The method for manufacturing an electronic package according to claim 11, wherein: A first concave portion and a second concave portion are formed on the first surface of the offset suppression layer, and the first electronic component and the second electronic component are respectively combined with the first concave portion and the second concave portion of the first surface of the offset suppression layer.