Semiconductor package

Abstract

A semiconductor package includes: a first semiconductor die; a first underfill layer on an upper surface of the first semiconductor die; a second underfill layer on the first underfill layer; providing a second semiconductor die over the second underfill layer; and a mold layer on a side surface of the second semiconductor die, a side surface of the second underfill layer, and an upper surface of the first semiconductor die. The first semiconductor die includes a first substrate, a first redistribution pattern on the first substrate, a first redistribution dielectric layer provided on the first redistribution pattern, and a first dam on the first redistribution dielectric layer and along an edge of the first substrate, the first underfill layer contacting a side surface of the first dam.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0108994 filed on August 21, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a semiconductor package, and more particularly, to a semiconductor package including a dam and a multi-layer underfill layer. Background Art

[0004] Integrated circuit chips are typically provided with semiconductor packages to be appropriately applied to circuit boards of electronic products or otherwise combined in electronic systems. In a typical semiconductor package, an integrated circuit chip (or semiconductor chip) may be mounted on a printed circuit board (PCB) and may be electrically connected to the PCB by bonding interconnects or bumps. With the development of the electronics industry, various studies have been conducted to improve the reliability and durability of semiconductor packages. Summary of the invention

[0005] One or more example embodiments provide a semiconductor package having improved reliability.

[0006] The problems to be solved by one or more example embodiments are not limited to the problems mentioned above, and those skilled in the art will appreciate that one or more example embodiments may solve other problems not mentioned. In addition, one or more example embodiments may not solve any of the problems mentioned.

[0007] According to one aspect of an example embodiment, a semiconductor package includes: a first semiconductor die; a first bottom fill layer on an upper surface of the first semiconductor die; a second bottom fill layer on the first bottom fill layer; a second semiconductor die on the second bottom fill layer; and a mold layer provided on a side surface of the second semiconductor die, a side surface of the second bottom fill layer, and an upper surface of the first semiconductor die, wherein the first semiconductor die includes: a first substrate; a first redistribution pattern on the first substrate; a first redistribution dielectric layer on the first redistribution pattern; and a first dam on the first redistribution dielectric layer and along an edge of the first substrate, the first bottom fill layer contacting a side surface of the first dam.

[0008] According to another aspect of the example embodiments, a semiconductor package includes: a first semiconductor die; a first bottom fill layer on an upper surface of the first semiconductor die; a second bottom fill layer on the first bottom fill layer; a second semiconductor die on the second bottom fill layer; an internal connection member in the second bottom fill layer and connecting the first semiconductor die and the second semiconductor die; and a mold layer on a side surface of the second semiconductor die, a side surface of the second bottom fill layer, and an upper surface of the first semiconductor die, wherein the first semiconductor die includes: a first substrate; a first redistribution pattern on the first substrate; a first redistribution dielectric layer on the first redistribution pattern; A first dam on the dielectric layer and along an edge of the first substrate; a second redistribution pattern, including a via portion penetrating the first redistribution dielectric layer and contacting the first redistribution pattern and a pad portion on the first redistribution dielectric layer; and a conductive pattern on the second redistribution pattern, wherein the first bottom fill layer contacts a side surface of the first dam, wherein the first semiconductor die has a first width in a width direction, wherein the first bottom fill layer has a second width in the width direction that is smaller than the first width, wherein the second bottom fill layer has a third width in the width direction that is smaller than the second width, and wherein the second semiconductor die has a fourth width in the width direction that is smaller than the third width.

[0009] According to one aspect of an example embodiment, a semiconductor package includes: a first semiconductor die; a first bottom fill layer on an upper surface of the first semiconductor die; a second bottom fill layer on the first bottom fill layer; a second semiconductor die on the second bottom fill layer; and a mold layer on a side surface of the second semiconductor die, a side surface of the second bottom fill layer, and an upper surface of the first semiconductor die, wherein an upper surface of the first bottom fill layer has a first surface roughness, an upper surface of the second bottom fill layer has a second surface roughness, and the second surface roughness is not as rough as the first surface roughness. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects and features will become more apparent from the following description of example embodiments with reference to the accompanying drawings, in which:

[0011] Figure 1 is a plan view of a semiconductor package according to one or more example embodiments;

[0012] Figure 2 According to one or more example embodiments, Figure 1 A cross-sectional view taken along line AA';

[0013] Figure 3A and Figure 3B According to one or more example embodiments Figure 2 an enlarged view of a portion “P1”;

[0014] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G and Figure 4H The following are sequentially shown for manufacturing according to one or more example embodiments. Figure 2 A view of a semiconductor packaging process;

[0015] Figure 5 According to one or more example embodiments Figure 4C An enlarged view of the portion “P2” in FIG.

[0016] Fig. 6A , Figure 6B and Figure 6C The following are sequentially shown for manufacturing according to one or more example embodiments. Figure 2 A view of a semiconductor packaging process;

[0017] Fig. 7A , Figure 7B and Figure 7C According to one or more example embodiments Figure 2 The enlarged view corresponding to the portion “P1”;

[0018] Fig. 8A , Figure 8B , Figure 8C and Fig.8D It is shown in sequence that the manufacturing Fig. 7A A view of a semiconductor packaging process;

[0019] Fig. 9A and Fig. 9B According to one or more example embodiments Figure 2 The enlarged view corresponding to the portion “P1”;

[0020] Fig. 10A , Fig. 10B , Fig. 10C and Fig. 10D It is shown in sequence that the manufacturing Fig. 9A A view of a semiconductor packaging process;

[0021] Fig.11 is a cross-sectional view of a semiconductor package according to one or more example embodiments;

[0022] Fig.12 is a cross-sectional view of a semiconductor package according to one or more example embodiments;

[0023] Fig.13is a cross-sectional view of a semiconductor package according to one or more example embodiments;

[0024] Fig.14 is a cross-sectional view of a semiconductor package according to one or more example embodiments;

[0025] Fig.15 is a cross-sectional view of a semiconductor package according to one or more example embodiments; and

[0026] Fig.16 is a cross-sectional view of a semiconductor package according to one or more example embodiments. DETAILED DESCRIPTION

[0027] Hereinafter, example embodiments will be described in detail with reference to the accompanying drawings. Herein, terms indicating order such as first, second, etc. may be used to distinguish components performing the same / similar functions, and their numbers may change depending on the order in which they are mentioned.

[0028] Figure 1 is a plan view of a semiconductor package according to one or more example embodiments. Figure 2 According to one or more example embodiments, Figure 1 A cross-sectional view taken along line AA'. Figure 3A and Figure 3B According to one or more example embodiments Figure 2 An enlarged view of portion “P1”.

[0029] Reference Figure 1 , Figure 2 , Figure 3A and Figure 3B , a semiconductor package 1000 according to one or more example embodiments includes a first semiconductor die CH1, a first underfill layer UF1, a second underfill layer UF2, a second semiconductor die CH2, and a first mold layer MD1 covering them, which are stacked in sequence. For example, the first mold layer MD1 may include an insulating resin, such as an epoxy molding compound (EMC). The first mold layer MD1 may further include a filler, and the filler may be dispersed in the insulating resin. Here, the "semiconductor die" may also be referred to as a "semiconductor chip". The first semiconductor die CH1 and the second semiconductor die CH2 may each independently be a memory die, a logic circuit die, or a buffer die.

[0030] The first semiconductor die CH1 includes a first substrate 10. The first substrate 10 may be a silicon single crystal substrate or a silicon on insulator (SOI) substrate. The first substrate 10 may include a front surface 10b and a rear surface 10a facing or opposite to each other. The first interlayer insulating layer 3 may be disposed on the front surface 10b of the first substrate 10. The first interlayer insulating layer 3 may have a single-layer or multi-layer structure of at least one of silicon oxide, silicon nitride, silicon oxynitride, and a porous insulator.

[0031] The first transistor and the multi-layer first interconnection line 5 may be arranged in the first interlayer insulating layer 3. The first conductive pad 9 may be arranged below the first interlayer insulating layer 3. The first conductive bumps 11 may be bonded to the first conductive pads 9, respectively. The first interconnection line 5, the first conductive pad 9 and the first conductive bump 11 may each include at least one metal selected from aluminum, tungsten, copper, titanium and tantalum. The first solder layer 13 may be bonded below the first conductive bump 11. The first solder layer 13 may also be referred to as an "external connection terminal". For example, the first solder layer 13 may be formed of SnAg. The lower surface of the first interlayer insulating layer 3 may be covered by a first passivation layer 7. The first passivation layer 7 may have a single-layer or multi-layer structure of at least one of SiN, SiCN and polyimide.

[0032] The rear surface 10a of the first substrate 10 may be covered by a first back insulating layer 15. The first back insulating layer 15 may be formed of, for example, silicon oxide. The first through via TV1 may penetrate the first back insulating layer 15, the first substrate 10, and a portion of the first interlayer insulating layer 3. The first through via TV1 may include a metal such as copper or tungsten. The first through via insulating layer TL1 may be interposed between the first through via TV1 and the first substrate 10. The first through via insulating layer TL1 may be formed of silicon oxide. An air gap may be provided in the first through via insulating layer TL1.

[0033] The first redistribution dielectric layer IL1 and the second redistribution dielectric layer IL2 are sequentially stacked on the first back insulating layer 15. The first redistribution dielectric layer IL1 and the second redistribution dielectric layer IL2 may include a photoimageable dielectric (PID) resin. The first redistribution pattern RP1 is disposed between the first redistribution dielectric layer IL1 and the second redistribution dielectric layer IL2. The second redistribution pattern RP2 is disposed on the second redistribution dielectric layer IL2. The first redistribution pattern RP1 and the second redistribution pattern RP2 may each include a metal such as copper. According to one or more example embodiments, the lower surfaces of the first redistribution pattern RP1 and the second redistribution pattern RP2 may be coated with a diffusion barrier layer ( Fig.14The diffusion barrier layer may include at least one of titanium, titanium nitride, tantalum, tantalum nitride, and tungsten nitride. Each of the first redistribution pattern RP1 and the second redistribution pattern RP2 may have a via portion VP, a line portion LP, and a pad portion PP. The via portion VP may have a width that becomes narrower as the via portion VP goes downward.

[0034] The via portion VP of the first redistribution pattern RP1 may penetrate the first redistribution dielectric layer IL1 and may contact the first through via TV1. The line portion LP and the pad portion PP of the first redistribution pattern RP1 are disposed between the first and second redistribution dielectric layers IL1 and IL2.

[0035] The via portion VP of the second redistribution pattern RP2 may penetrate the second redistribution dielectric layer IL2 and may contact the pad portion PP of the first redistribution pattern RP1. The line portion LP and the pad portion PP of the second redistribution pattern RP2 are disposed on the second redistribution dielectric layer IL2. The second conductive pad CP is disposed on the pad portion PP of the second redistribution pattern RP2. The second conductive pad CP may include at least one metal selected from gold and nickel. The second conductive pad CP may also be referred to as a "wetting layer".

[0036] The first semiconductor die CH1 according to one or more example embodiments further includes a first dam DM1 disposed on an edge of the second redistribution dielectric layer IL2. The first dam DM1 may be formed of a single layer or a multilayer structure of at least one of a conductive material and an insulating material. According to one or more example embodiments, the first dam DM1 may be formed with the same PID as the second redistribution dielectric layer IL2. An interface may or may not exist between the first dam DM1 and the second redistribution dielectric layer IL2. Figure 1 As shown, the first dam DM1 may be disposed in a closed curve shape along an edge of the first semiconductor die CH1 when viewed in a plan view.

[0037] The second semiconductor die CH2 may include a second substrate 100. The second substrate 100 may be a silicon single crystal substrate or a silicon on insulator (SOI) substrate. The second substrate 100 may include a front surface 100b and a rear surface 100a facing or opposite to each other. A second interlayer insulating layer 103a and a third interlayer insulating layer 103b may be sequentially disposed on the bottom surface of the front surface 100b of the second substrate 100. The second interlayer insulating layer 103a and the third interlayer insulating layer 103b may each have a single-layer or multi-layer structure of at least one of silicon oxide, silicon nitride, silicon oxynitride, and a porous insulator.

[0038] The first transistor and the multi-layer second interconnection line 105 may be disposed in the second interlayer insulating layer 103a. The third conductive pad 109 may be disposed below the second interlayer insulating layer 103a. The lower surface of the third interlayer insulating layer 103b may be covered by the second passivation layer 107. The second passivation layer 107 may cover the side surface and a portion of the bottom surface of the third conductive pad 109. The second conductive bumps 111 may penetrate the second passivation layer 107 and may be bonded to the third conductive pads 109, respectively. The second conductive bumps 111 of the second semiconductor die CH2 may be bonded to the second conductive pads CP of the first semiconductor die CH1 through the second solder layer 113. The second solder layer 113 may also be referred to as an "internal connection member".

[0039] The second interconnection line 105, the third conductive pad 109 and the second conductive bump 111 may each include at least one metal selected from aluminum, tungsten, copper, titanium and tantalum. For example, the second solder layer 113 may be formed of SnAg. The second passivation layer 107 may have a single layer or multilayer structure of at least one of SiN, SiCN and polyimide.

[0040] The first underfill layer UF1 may be disposed on the second redistribution dielectric layer IL2 and in the first dam DM1. The first underfill layer UF1 may cover the upper surface of the second redistribution dielectric layer IL2, the side surface of the first dam DM1, and the side surfaces of the second redistribution pattern RP2 and the second conductive pad CP. The first underfill layer UF1 may contact the side surface of the first dam DM1. The upper surface UF1_US of the first underfill layer UF1 may be coplanar with the upper surface DM1_US of the first dam DM1.

[0041] The second bottom filling layer UF2 may be interposed between the first bottom filling layer UF1 and the second semiconductor die CH2, and may cover the side surfaces of the second conductive bump 111 and the second solder layer 113. A fillet portion UF2_F as a part of the second bottom filling layer UF2 may protrude beyond the side surface of the second semiconductor die CH2. The side surface of the fillet portion UF2_F of the second bottom filling layer UF2 may be rounded, and the upper end of the fillet portion UF2_F may be higher than the lower surface of the second semiconductor die CH2. When Figure 1 When viewed in a plan view of , the width of the rounded portion UF2_F of the second underfill layer UF2 may be widest at the center of the side surface of the second semiconductor die CH2 and may become narrower toward the edge of the second semiconductor die CH2.

[0042] The first bottom filling layer UF1 and the second bottom filling layer UF2 may include a non-conductive film (NCF). The first bottom filling layer UF1 and the second bottom filling layer UF2 may each be referred to as a "non-conductive layer". The first bottom filling layer UF1 and the second bottom filling layer UF2 may each independently include a thermosetting resin or a photocurable resin. In addition, the first bottom filling layer UF1 and the second bottom filling layer UF2 may each independently further include an organic filler or an inorganic filler. The organic filler may include, for example, a polymer material. The inorganic filler may include, for example, silicon oxide (SiO 2 ).

[0043] For example, refer to Figure 3B , the resin forming the first bottom filling layer UF1 may be different from the resin forming the second bottom filling layer UF2. At least one of the first fillers PC1 dispersed in the first bottom filling layer UF1 may have a size (average size or diameter), shape and / or material different from the size (average size or diameter), shape and / or material of at least one of the second fillers PC2 dispersed in the second bottom filling layer UF2. Some of the first fillers PC1 may protrude beyond the upper surface UF1_US of the first bottom filling layer UF1. Some of the first fillers PC1 may exist at the interface between the first bottom filling layer UF1 and the second bottom filling layer UF2. That is, some of the first fillers PC1 may be in contact with the first bottom filling layer UF1 and the second bottom filling layer UF2 at the same time. The upper surface UF1_US of the first bottom filling layer UF1 may have a first surface roughness. The upper surface UF2_US of the second bottom filling layer UF2 may have a second surface roughness less than the first surface roughness. As a result, the surface area of ​​the upper surface UF1_US of the first underfill layer UF1 may be increased, thereby improving adhesion between the first underfill layer UF1 and the second underfill layer UF2.

[0044] Reference Figure 1 , the first semiconductor die CH1 may have a first width WT1 in the first direction X. The first underfill layer UF1 may have a second width WT2 in the first direction X that is smaller than the first width WT1. The second underfill layer UF2 may have a third width WT3 in the first direction X that is smaller than the second width WT2. The second semiconductor die CH2 may have a fourth width WT4 in the first direction X that is smaller than the third width WT3.

[0045] In the semiconductor package 1000 according to one or more example embodiments, the upper surface of the second redistribution dielectric layer IL2 may be bent by the first redistribution pattern RP1. The height of the upper surface of the second redistribution dielectric layer IL2 disposed on the first redistribution pattern RP1 may be relatively higher than the height of the upper surface of the second redistribution dielectric layer IL2 disposed on the edge of the back side of the first semiconductor die CH1. Due to this height difference, the distance between the second semiconductor die CH2 and the first semiconductor die CH1 at the edge of the second semiconductor die CH2 may be relatively large.

[0046] When the bottom filling layer inserted between the second semiconductor die CH2 and the first semiconductor die CH1 is formed by a single layer, the possibility that the space below the edge of the second semiconductor die CH2 is not filled by the bottom filling layer may be increased. This can be referred to as an unfilled problem. This unfilled problem may cause cracking or peeling of the mold layer and deteriorate the reliability of the semiconductor package. When the thickness of the bottom filling layer having a single-layer structure is increased in order to prevent the unfilled problem, the width of the rounded corner portion of the bottom filling layer will also become wider, so there is a risk that the rounded corner portion of the bottom filling layer is exposed at the side surface of the mold layer, which may cause the reliability of the semiconductor package to deteriorate. In addition, when the thickness of the bottom filling layer increases, the possibility of a non-wet defect in which the second solder layer 113 does not contact the second conductive pad CP may be increased. This reduces the reliability of the semiconductor package.

[0047] However, in one or more example embodiments, the bottom fill layer has a double-layer structure of a first bottom fill layer UF1 and a second bottom fill layer UF2. The space between the first semiconductor die CH1 and the second semiconductor die CH2 may be narrowed by the first bottom fill layer UF1. As a result, the thickness of the second bottom fill layer UF2 may be relatively reduced, and the width of the rounded corner portion UF2_F of the second bottom fill layer UF2 may also be narrowed. Therefore, the second bottom fill layer UF2 may not be exposed at the side surface of the first mold layer MD1, and the possibility of non-wetting defects may be reduced. In addition, due to the first dam DM1, the first bottom fill layer UF1 is not exposed to the side of the first mold layer MD1. As a result, the reliability of the semiconductor package 1000 may be improved.

[0048] Here, the underfill layer has a double-layer structure of a first underfill layer UF1 and a second underfill layer UF2 , but the underfill layer may have a multi-layer structure of three or more layers.

[0049] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G and Figure 4H The following are sequentially shown for manufacturing according to one or more example embodiments. Figure 2 A view of the process of semiconductor packaging. Figure 5 yes Figure 4C An enlarged view of portion “P2” in FIG.

[0050] Reference Figure 4A , a wafer CH1_W for first semiconductor dies (hereinafter, referred to as a first semiconductor die wafer CH1_W) is prepared. The first semiconductor die wafer CH1_W may have a device region DR and a separation region SR between the device regions DR. In each device region DR, the first semiconductor die wafer CH1_W may have a reference Figure 2 The internal structure described in one or more example embodiments of the present invention. A first through via TV1 and a first via insulating layer TL1 may be formed in the first semiconductor die wafer CH1_W. On the front surface 10b of the first substrate 10 of the first semiconductor die wafer CH1_W, a first interlayer insulating layer 3, a first interconnect line 5, a first passivation layer 7, a first conductive pad 9, a first conductive bump 11, and a first solder layer 13 may be formed. The first semiconductor die wafer CH1_W may be bonded to the carrier substrate CRS through an adhesive layer ADL. The rear surface 10a of the first substrate 10 of the first semiconductor die wafer CH1_W may be ground to expose the first through via TV1 and the first via insulating layer TL1 and to form a first back side insulating layer 15.

[0051] A first redistribution dielectric layer IL1 may be formed on the first back insulating layer 15. The first redistribution dielectric layer IL1 may be formed of a photoimageable dielectric (PID) resin. An exposure and development process may be performed to form a first via hole exposing the first through via TV1 in the first redistribution dielectric layer IL1. A first mask pattern defining a planar shape of a first redistribution pattern RP1 may be formed on the first redistribution dielectric layer IL1, and a plating process may be performed to form the first redistribution pattern RP1. Then, the first mask pattern may be removed. Some of the first redistribution pattern RP1 may fill the first via hole.

[0052] A second redistribution dielectric layer IL2 may be formed on the first redistribution dielectric layer IL1 and the first redistribution pattern RP1. The second redistribution dielectric layer IL2 may be formed of a photoimageable dielectric (PID) resin. The upper surface of the second redistribution dielectric layer IL2 may be formed to be bent through the first redistribution pattern RP1. An exposure and development process may be performed to form a second via hole exposing the first redistribution pattern RP1 in the second redistribution dielectric layer IL2. A second mask pattern defining a planar shape of the second redistribution pattern RP2 may be formed on the second redistribution dielectric layer IL2, and a plating process may be performed to form the second redistribution pattern RP2 and a second conductive pad CP. Then, the second mask pattern may be removed. Some of the second redistribution pattern RP2 may fill the second via hole.

[0053] Reference Figure 4B , a first dam DM1 may be formed on the second redistribution dielectric layer IL2. The first dam DM1 may be formed of a photoimageable dielectric (PID) resin. The first dam DM1 may be formed by coating a photosensitive insulating resin and then performing an exposure and development process. The first dam DM1 may be formed to overlap the separation region SR and expose the device region DR. When viewed in a plan view, Figure 4B The first dam DM1 may be formed to have a mesh shape.

[0054] Reference Figure 4C and Figure 5 , a first underfill layer UF1 may be formed on the first semiconductor die wafer CH1_W. The first underfill layer UF1 may be formed by laminating a non-conductive film (NCF) in a heated state. The first underfill layer UF1 may be formed to cover the first dam DM1, the second redistribution dielectric layer IL2, the second redistribution pattern RP2, and the second conductive pad CP. In one or more example embodiments, the first underfill layer UF1 may be formed to have a flat upper surface.

[0055] Reference Figure 4D and Figure 4E , a first etching process PLS1 may be performed to remove an upper portion of the first underfill layer UF1, thereby exposing the upper surfaces of the first dam DM1 and the second conductive pad CP. The first etching process PLS1 may be performed using, for example, oxygen (O 2 ) or CF 4 Due to the first etching process PLS1, the upper surface UF1_US of the first bottom filling layer UF1 may have a relatively large surface roughness, such as Figure 3B In addition, some first fillers PC1 dispersed in the first underfill layer UF1 may be exposed by the first etching process PLS1.

[0056] Reference Figure 4F , prepare the second semiconductor die CH2. Each second semiconductor die CH2 may have the same Figure 2 The same structure as described in one or more example embodiments. Each second semiconductor die CH2 may include a second substrate 100, a second interlayer insulating layer 103a, a second interconnect line 105, a third interlayer insulating layer 103b, a second passivation layer 107, a third conductive pad 109, a second conductive bump 111, and a second solder layer 113. A second bottom fill layer UF2 may be formed below the second semiconductor die CH2. The second bottom fill layer UF2 may be formed by laminating a non-conductive film (NCF) in a heated state. According to one or more example embodiments, the edge of the second bottom fill layer UF2 may have a right-angle cross-section. The second bottom fill layer UF2 may be formed to cover the second passivation layer 107, the second conductive bump 111, and the second solder layer 113. The second semiconductor die CH2 on which the second bottom fill layer UF2 may be formed is disposed on the device region DR of the first semiconductor die wafer CH1_W to correspond to the device region DR, respectively.

[0057] Reference Figure 4G , a thermal compression process may be performed so that the second solder layer 113 of the second semiconductor die CH2 penetrates the second bottom fill layer UF2 and is bonded to the second conductive pad CP. According to one or more example embodiments, the flux included in the NCF as the second bottom fill layer UF2 may remove the oxide layer on the surface of the second solder layer 113 and / or the second conductive pad CP. In the thermal compression process, the NCF as the second bottom fill layer UF2 may also be compressed in a partially melted state and may protrude to have a rounded portion ( Figure 3A UF2_F in ).

[0058] In the method of manufacturing a semiconductor package according to one or more example embodiments, the space between the first semiconductor die CH1 and the second semiconductor die CH2 may be narrowed by the first bottom fill layer UF1. As a result, the thickness of the second bottom fill layer UF2 may be relatively reduced, and the width of the rounded corner portion UF2_F of the second bottom fill layer UF2 may also be narrowed. Therefore, the second bottom fill layer UF2 may not be exposed to the side of the first mold layer MD1, and the possibility of non-wetting defects may be reduced. In addition, due to the first dam DM1, the first bottom fill layer UF1 is not exposed to the side of the first mold layer MD1. As a result, the reliability of the semiconductor package 1000 may be improved.

[0059] Reference Figure 4H, a first mold layer MD1 may be formed on the first semiconductor die wafer CH1_W using a mold. Subsequently, the adhesive layer ADL and the carrier substrate CRS are removed from the first semiconductor die wafer CH1_W. Then, a singulation process may be performed to cut the separation region SR. Thus, the Figure 2 A semiconductor package 1000 is provided.

[0060] Fig. 6A , Figure 6B and Figure 6C The following are sequentially shown for manufacturing according to one or more example embodiments. Figure 2 A view of the process of semiconductor packaging.

[0061] Reference Fig. 6A and Figure 6B ,exist Figure 4F In the embodiment, when NCF is laminated on the second semiconductor die CH2 as the second underfill layer UF2, a second etching process PLS2 may be performed on the second underfill layer UF2. The second etching process PLS2 may be performed using, for example, oxygen (O 2 ) or CF 4 Plasma etching process. Figure 6B As shown, a portion of the second underfill layer UF2 may be removed by the second etching process PLS2, and a surface of the second solder layer 113 may be exposed.

[0062] Reference Figure 6C , on which can be formed Figure 6B The second semiconductor die CH2 of the second underfill layer UF2 is disposed on the device region DR of the first semiconductor die wafer CH1_W to correspond to the device region DR respectively. Subsequently, when a thermal compression process is performed, the second solder layer 113 of the second semiconductor die CH2 may be bonded to the second conductive pad CP of the first semiconductor die wafer CH1_W. Then, the first mold layer MD1 may be formed, and a singulation process may be performed to cut the separation region SR. Thus, the Figure 2 A semiconductor package 1000 is provided.

[0063] Fig. 7A , Figure 7B and Figure 7C According to one or more example embodiments Figure 2 The enlarged view corresponding to the portion “P1”.

[0064] Reference Fig. 7AIn the semiconductor package according to one or more example embodiments, the upper surface DM1_US of the first dam DM1 may have a first height HT1 from the rear surface 10a of the first substrate 10 of the first semiconductor die CH1. The upper surface CP_US of the second conductive pad CP may have a second height HT2 from the rear surface 10a of the first substrate 10 of the first semiconductor die CH1. The second height HT2 may be less than the first height HT1. The upper surface of the first bottom fill layer UF1 may have a concave-convex structure. The first bottom fill layer UF1 may cover the lower side wall of the first dam DM1 and may expose the upper side wall DM1_UW of the first dam DM1. The side surface CP_W of the second conductive pad CP may be covered by the first bottom fill layer UF1. The rounded portion UF2_F of the second bottom fill layer UF2 may be spaced apart from the upper side wall DM1_UW of the first dam DM1. According to one or more example embodiments, other structures may be the same as those of reference 1. Figure 2 The structures described are the same / similar.

[0065] Reference Figure 7B In the semiconductor package according to one or more example embodiments, the rounded corner portion UF2_F of the second underfill layer UF2 may cover the upper end UF1_UE of the first underfill layer UF1 and may be spaced apart from the first dam DM1. According to one or more example embodiments, other structures may be similar to those of reference 1. Fig. 7A The structures described are the same / similar.

[0066] Reference Figure 7C In the semiconductor package according to one or more example embodiments, the rounded corner portion UF2_F of the second underfill layer UF2 may partially cover the upper surface DM1_US of the first dam DM1 and may be spaced apart from the edge of the first mold layer MD1. According to one or more example embodiments, other structures may be similar to those of the reference Fig. 7A The structures described are the same / similar.

[0067] Fig. 8A , Figure 8B , Figure 8C and Fig.8D It is shown in sequence that the manufacturing Fig. 7A A view of the process of semiconductor packaging.

[0068] Reference Figure 4B and Fig. 8A ,exist Figure 4A In a state where the first dam DM1 is formed on the second redistribution dielectric layer IL2, the first dam DM1 may be formed to be higher than the second conductive pad CP (HT1>HT2).

[0069] Reference Figure 4C and Figure 8B, a first underfill layer UF1 can be formed on the first semiconductor die wafer CH1_W. The first underfill layer UF1 can be formed by laminating a non-conductive film (NCF) in a heated state. The first underfill layer UF1 can be formed to cover the first dam DM1, the second redistribution dielectric layer IL2, the second redistribution pattern RP2, and the second conductive pad CP. In one or more example embodiments, the first underfill layer UF1 can be formed to have an irregular (concave-convex structure) contour through the first dam DM1 and the second redistribution pattern RP2. Since the first dam DM1 can be formed higher than the second conductive pad CP, a thickness difference of the first underfill layer UF1 may occur. Specifically, according to one or more example embodiments, the first underfill layer UF1 can be formed to have a first thickness TH1 on the first dam DM1 and a second thickness TH2 on the second conductive pad CP, and the second thickness TH2 can be thicker than the first thickness TH1.

[0070] Referring to Figure 4D and Figure 8C , a first etching process PLS1 can be performed to remove the upper portion of the first underfill layer UF1 and expose the upper surface DM1_US of the first dam DM1. However, since HT1 > HT2 and TH1 < TH2, the upper surface CP_US and the side surface CP_W of the second conductive pad CP can be covered by the first underfill layer UF1.

[0071] Referring to Fig.8D , the first etching process PLS1 is continuously performed on the first underfill layer UF1 to expose the upper surface CP_US of the second conductive pad CP. Therefore, a portion of the first underfill layer UF1 covering the upper sidewall DM1_UW of the first dam DM1 can be removed to expose the upper sidewall DM1_UW of the first dam DM1. According to one or more example embodiments, other manufacturing processes can be the same / similar to the manufacturing processes described above.

[0072] Fig. 9A and Fig. 9B is an enlarged view corresponding to the portion "P1" of Figure 2 according to one or more example embodiments.

[0073] Referring to Fig. 9AIn the semiconductor package according to one or more example embodiments, the upper surface DM1_US of the first dam DM1 may have a first height HT1 from the rear surface 10a of the first substrate 10 of the first semiconductor die CH1. The upper surface CP_US of the second conductive pad CP may have a second height HT2 from the rear surface 10a of the first substrate 10 of the first semiconductor die CH1. The second height HT2 may be greater than the first height HT1. The upper surface of the first bottom fill layer UF1 may have a concave-convex structure. The first bottom fill layer UF1 may cover the entire side wall DM1_W of the first dam DM1. The first bottom fill layer UF1 may expose the upper surface DM1_US of the first dam DM1. The first bottom fill layer UF1 may cover the lower side wall of the second conductive pad CP and expose the upper side wall CP_UW of the second conductive pad CP. The rounded portion UF2_F of the second bottom fill layer UF2 may be spaced apart from the first dam DM1. According to one or more example embodiments, other structures may be the same as those described with reference to FIG. Figure 2 The structures described are the same / similar.

[0074] Reference Fig. 9B In the semiconductor package according to one or more example embodiments, the first underfill layer UF1 may cover the upper surface DM1_US of the first dam DM1. According to one or more example embodiments, other structures may be similar to those of reference 1. Fig. 9A The structures described are the same / similar.

[0075] Fig. 10A , Fig. 10B , Fig. 10C and Fig. 10D It is shown in sequence that the manufacturing Fig. 9A A view of the process of semiconductor packaging.

[0076] Reference Figure 4B and Fig. 10A ,exist Figure 4A In a state where the first dam DM1 may be formed on the second redistribution dielectric layer IL2. According to one or more example embodiments, the first dam DM1 may be formed lower than the second conductive pad CP (HT1). <HT2)。

[0077] Reference Figure 4C and Fig. 10B, a first underfill layer UF1 can be formed on the first semiconductor die wafer CH1_W. The first underfill layer UF1 can be formed by laminating a non-conductive film (NCF) in a heated state. The first underfill layer UF1 can be formed to cover the first dam DM1, the second redistribution dielectric layer IL2, the second redistribution pattern RP2, and the second conductive pad CP. In one or more example embodiments, the first underfill layer UF1 can be formed to have an irregular (concave-convex structure) profile through the first dam DM1 and the second redistribution pattern RP2. Since the first dam DM1 can be formed lower than the second conductive pad CP, a thickness difference of the first underfill layer UF1 may occur. Specifically, according to one or more example embodiments, the first underfill layer UF1 can be formed to have a first thickness TH1 on the first dam DM1 and a second thickness TH2 on the second conductive pad CP, and the second thickness TH2 can be thinner than the first thickness TH1.

[0078] Referring to Figure 4D and Fig. 10C , a first etching process PLS1 can be performed to remove the upper portion of the first underfill layer UF1 and expose the upper surface CP_US of the second conductive pad CP. However, since HT1 < HT2 and TH1 > TH2, the upper surface DM1_US and the side surface DM1_W of the first dam DM1 can be covered by the first underfill layer UF1.

[0079] Referring to Fig. 10D , the first etching process PLS1 can be continuously performed on the first underfill layer UF1 to expose the upper surface DM1_US of the first dam DM1. As a result, a portion of the first underfill layer UF1 covering the upper sidewall CP_UW of the second conductive pad CP can be removed to expose the upper sidewall CP_UW of the second conductive pad CP. According to one or more example embodiments, other manufacturing processes can be the same / similar to the manufacturing processes described above.

[0080] Fig.11 is a cross-sectional view of a semiconductor package according to one or more example embodiments.

[0081] Referring to Fig.11 , according to one or more example embodiments, a semiconductor package 1001 includes a first semiconductor die CH1, a first underfill layer UF1, a second underfill layer UF2, a second semiconductor die CH2, a third underfill layer UF3, and a third semiconductor die CH3 stacked in sequence, and a first mold layer MD1 covering them. According to one or more example embodiments, the first semiconductor die CH1, the first underfill layer UF1, and the second underfill layer UF2 can have the same as that referring to Figure 2 , Figure 3A and Figure 3BThe second semiconductor die CH2 may be the same as or similar to the structure described above. Figure 2 The first mold layer MD1 may be similar to the second semiconductor die CH2, but may further include a second through via TV2 and a second via insulating layer TL2. The third semiconductor die CH3 may be similar to the second semiconductor die CH2, but may not include the second through via TV2 and the second via insulating layer TL2. The third bottom fill layer UF3 may fill the space between the second semiconductor die CH2 and the third semiconductor die CH3. The third bottom fill layer UF3 may extend to cover the side surface of the second semiconductor die CH2 and contact the side surface of the second semiconductor die CH2 and the upper end of the second bottom fill layer UF2. The upper surface of the first mold layer MD1 may be coplanar with the upper surface of the third semiconductor die CH3.

[0082] Fig.12 is a cross-sectional view of a semiconductor package according to one or more example embodiments.

[0083] Reference Fig.12 , the semiconductor package 1002 according to one or more example embodiments includes a first semiconductor die CH1, a first underfill layer UF1, a second underfill layer UF2, a second semiconductor die CH2, a third underfill layer UF3, a fourth underfill layer UF4, and a third semiconductor die CH3 stacked in sequence, and a first mold layer MD1 covering them. According to one or more example embodiments, the first semiconductor die CH1, the first underfill layer UF1, and the second underfill layer UF2 may have the same Figure 2 , Figure 3A and Figure 3B The structures described are the same / similar structures.

[0084] The second semiconductor die CH2 may be connected to Figure 2The second semiconductor die CH2 is similar to the second semiconductor die CH2, but may further include a second through-via TV2 and a second through-via insulating layer TL2. The second back side insulating layer 115 may be disposed on the rear surface 100a of the second substrate of the second semiconductor die CH2. The third redistribution dielectric layer IL3 may be disposed on the second back side insulating layer 115. The third redistribution pattern RP3 may be disposed on the third redistribution dielectric layer IL3. The via portion VP of the third redistribution pattern RP3 may penetrate the third redistribution dielectric layer IL3 and may contact the second through-via TV2. The fourth redistribution dielectric layer IL4 may be disposed on the third redistribution dielectric layer IL3. The upper surface of the fourth redistribution dielectric layer IL4 may have a concave-convex structure. The fourth redistribution pattern RP4 may be disposed on the fourth redistribution dielectric layer IL4. The via portion VP of the fourth redistribution pattern RP4 may penetrate the fourth redistribution dielectric layer IL4 and may contact the third redistribution pattern RP3. The second conductive pad CP may be disposed on the fourth redistribution pattern RP4. The second dam DM2 may be disposed on the fourth redistribution dielectric layer IL4. The third underfill layer UF3 may be in contact with the upper surface of the fourth redistribution dielectric layer IL4 and the side surface of the second dam DM2. The fourth underfill layer UF4 may be disposed on the third underfill layer UF3. The fourth underfill layer UF4 may be spaced apart from the second dam DM2. According to one or more example embodiments, other structures may be the same / similar to the structures described above.

[0085] Fig.13 is a cross-sectional view of a semiconductor package according to one or more example embodiments.

[0086] Reference Fig.13 , a semiconductor package 1003 according to one or more example embodiments includes a first semiconductor die CH1, a second semiconductor die CH2, a third semiconductor die CH3, and a fourth semiconductor die CH4 stacked in sequence and a first mold layer MD1 covering them. The second semiconductor die CH2, the third semiconductor die CH3, and the fourth semiconductor die CH4 may be memory chips that perform the same function. According to one or more example embodiments, the first semiconductor die CH1 may be connected to a first semiconductor die CH4. Figure 2The first semiconductor die CH1 may be the same / similar to the first semiconductor die CH1. The first semiconductor die CH1 may be a buffer die. The first dam DM1 may be disposed on an edge of a rear surface of the first semiconductor die CH1. The first underfill layer UF1 and the second underfill layer UF2 may be interposed between the first semiconductor die CH1 and the second semiconductor die CH2. The second semiconductor die CH2, the third semiconductor die CH3, and the fourth semiconductor die CH4 may be the same memory die. The second semiconductor die CH2, the third semiconductor die CH3, and the fourth semiconductor die CH4 may be DRAM chips. The third underfill layer UF3 may be interposed between the second semiconductor die CH2 and the third semiconductor die CH3. The fourth underfill layer UF4 may be interposed between the third semiconductor die CH3 and the fourth semiconductor die CH4. The semiconductor package 1003 may be a high bandwidth memory (HBM) chip. According to one or more example embodiments, other structures may be the same / similar to the structures described above.

[0087] Fig.14 is a cross-sectional view of a semiconductor package according to one or more example embodiments.

[0088] Reference Fig.14 , a semiconductor package 1004 according to one or more example embodiments includes a first sub-semiconductor package PK1 and a second sub-semiconductor package PK2 stacked thereon. The first sub-semiconductor package PK1 includes a first redistribution substrate RD1, a first underfill layer UF1, a second underfill layer UF2, a first semiconductor die CH1, a first mold layer MD1, and a mold via MV.

[0089] The first redistribution substrate RD1 may include a first redistribution dielectric layer IL1, a second redistribution dielectric layer IL2, a third redistribution dielectric layer IL3, and a fourth redistribution dielectric layer IL4 stacked in sequence. The first redistribution dielectric layer IL1, the second redistribution dielectric layer IL2, the third redistribution dielectric layer IL3, and the fourth redistribution dielectric layer IL4 may each include a PID resin. An under bump UBM may be inserted in the first redistribution dielectric layer IL1. The external connection terminals OB may each be bonded to the under bump UBM. The under bump UBM may include a conductive material. The first redistribution substrate RD1 may include a first redistribution pattern RP1, a second redistribution pattern RP2, and a third redistribution pattern RP3. The lower surfaces of the first redistribution pattern RP1, the second redistribution pattern RP2, and the third redistribution pattern RP3 may be covered by a diffusion barrier layer BM. The second conductive pad CP may be disposed on the third redistribution pattern RP3. The diffusion barrier layer BM may include at least one of titanium, titanium nitride, tantalum, and tantalum nitride. The first dam DM1 may be disposed on the fourth redistribution dielectric layer IL4. The first dam DM1 may be formed of a PID resin. The first dam DM1 may be disposed between the second conductive pads CP.

[0090] The mold path MV may be disposed on the third redistribution pattern RP3 disposed at the edge in the third redistribution pattern RP3. The mold path MV may penetrate the first mold layer MD1. Among the third redistribution patterns RP3, the third redistribution pattern RP3 disposed at the center thereof may be bonded to the first semiconductor die CH1. The second redistribution substrate RD2 may be disposed on the first mold layer MD1. The second redistribution substrate RD2 may include a fifth redistribution dielectric layer IL5, a sixth redistribution dielectric layer IL6, and a seventh redistribution dielectric layer IL7 stacked in sequence. The second redistribution substrate RD2 may include a fourth redistribution pattern RP4, a fifth redistribution pattern RP5, and a sixth redistribution pattern RP6. The second dam DM2 may be disposed on the edge of the second redistribution substrate RD2. The fifth redistribution dielectric layer IL5, the sixth redistribution dielectric layer IL6, the seventh redistribution dielectric layer IL7, and the second dam DM2 may be formed of a PID resin.

[0091] The third bottom fill layer UF3 and the fourth bottom fill layer UF4 may be disposed on the second redistribution substrate RD2. According to one or more example embodiments, the third bottom fill layer UF3 may be the same / similar to the first bottom fill layer UF1. According to one or more example embodiments, the fourth bottom fill layer UF4 may be the same / similar to the second bottom fill layer UF2. The second sub-semiconductor package PK2 may be disposed on the fourth bottom fill layer UF4.

[0092] The second sub-semiconductor package PK2 may include a package substrate SB, a second semiconductor die CH2 mounted on the package substrate SB, and a second mold layer MD2 covering them. The second semiconductor die CH2 may be electrically connected to the package substrate SB by, for example, a wire 360. The second semiconductor die CH2 is shown as a single semiconductor die or semiconductor chip, but may be a semiconductor package including multiple semiconductor dies of the same or different types. The second semiconductor die CH2 may be one selected from the following: an image sensor chip, such as a complementary metal oxide semiconductor (CMOS) imaging sensor (CIS); a memory device chip, such as a flash memory chip, a dynamic random access memory (DRAM) chip, a static random access memory (SRAM) chip, an electrically erasable programmable read-only memory (EEPROM) chip, a phase change memory (PRAM) chip, a magnetic RAM (MRAM) chip, a resistive RAM (ReRAM) chip, a high bandwidth memory (HBM) chip, and a hybrid memory cube (HMC) chip; a microelectromechanical system (MEMS) device chip; or an application specific integrated circuit (ASIC) chip.

[0093] The second mold layer MD2 may include the same material as the first mold layer MD1. The wire 360 ​​may include copper or gold. The package substrate SB may be, for example, a double-sided or multi-layer printed circuit board. The package substrate SB may include an upper substrate pad 380 disposed on its upper surface and a lower substrate pad 382 disposed on its lower surface. Internal interconnects may be disposed within the package substrate SB to connect the upper substrate pad 380 and the lower substrate pad 382. The upper substrate pad 380 and the lower substrate pad 382 may include at least one of gold, copper, aluminum, and nickel. According to one or more example embodiments, other configurations may be the same / similar to the configurations described above.

[0094] Fig.15 is a cross-sectional view of a semiconductor package according to one or more example embodiments.

[0095] Reference Fig.15 , the first sub-semiconductor package PK1 included in the semiconductor package 1005 according to one or more example embodiments includes a first redistribution substrate RD1, a connection substrate 900 and a first semiconductor die CH1 mounted on the first redistribution substrate RD1, a first mold layer MD1 covering them, and a second redistribution substrate RD2 on the first mold layer MD1.

[0096] The connection substrate 900 may include a cavity region CV at its center. The first semiconductor die CH1 may be disposed in the cavity region CV. The connection substrate 900 may include a plurality of base layers 910 and a conductive structure 920. The base layer 910 may include an insulating material. For example, the base layer 910 may include a carbon-based material, ceramic, or polymer. The conductive structure 920 may include a connection pad 921, a first connection path 922, a connection interconnect line 923, and a second connection path 924.

[0097] The first underfill layer UF1 and the second underfill layer UF2 may be interposed between the connection substrate 900 and the first redistribution substrate RD1. A space between an inner wall of the cavity region CV of the connection substrate 900 and the first semiconductor die CH1 may be filled with a first mold layer MD1.

[0098] The auxiliary via 213 may penetrate the first mold layer MD1 to connect the second connection via 924 of the connection substrate 900 and the fourth redistribution pattern RP4 of the second redistribution substrate RD2. According to one or more example embodiments, other configurations may be the same / similar to those described above.

[0099] Fig.16 is a cross-sectional view of a semiconductor package according to one or more example embodiments.

[0100] Reference Fig.16 , a semiconductor package 1006 according to one or more example embodiments includes an intermediate substrate IPS disposed on a packaging substrate PPS, a first semiconductor die CH1 and a second semiconductor die CH2 mounted side by side on the intermediate substrate IPS, and a heat dissipation member HS covering them. The first semiconductor die CH1 and the second semiconductor die CH2 may also be referred to as "semiconductor devices" or "semiconductor chips". The first semiconductor die CH1 may be a central processing unit (CPU) chip or an application-specific integrated circuit (ASIC) chip. The second semiconductor die CH2 may be, for example, an HBM chip. The packaging substrate PPS and the intermediate substrate IPS may each be a printed circuit board.

[0101] The first dam DM1 may be disposed on the packaging substrate PPS. The packaging substrate PPS may include a first upper conductive pattern CP2 and a first lower conductive pattern CP1 and a first internal interconnect IC1 connecting them. The external connection terminal OB may be bonded to the first lower conductive pattern CP1. The intermediary substrate IPS may be bonded to the first upper conductive pattern CP2 of the packaging substrate PPS through the internal connection terminal IB. The first underfill layer UF1 and the second underfill layer UF2 may be interposed between the intermediary substrate IPS and the packaging substrate PPS.

[0102] The second dam DM2 may be disposed on the interposer substrate IPS. The interposer substrate IPS may include a second upper conductive pattern CP4, a second lower conductive pattern CP3, and a second internal interconnect IC2. The first semiconductor die CH1 may include a first chip conductive pad CP5. The second semiconductor die CH2 may include a second chip conductive pad CP6. The third bottom fill layer UF3 and the fourth bottom fill layer UF4 may be interposed between the first semiconductor die CH1 and the interposer substrate IPS. According to one or more example embodiments, the third bottom fill layer UF3 may be the same / similar to the first bottom fill layer UF1. According to one or more example embodiments, the fourth bottom fill layer UF4 may be the same / similar to the second bottom fill layer UF2.

[0103] The fifth bottom fill layer UF5 and the sixth bottom fill layer UF6 may be interposed between the second semiconductor die CH2 and the intermediate substrate IPS. According to one or more example embodiments, the fifth bottom fill layer UF5 may be the same / similar to the first bottom fill layer UF1. According to one or more example embodiments, the sixth bottom fill layer UF6 may be the same / similar to the second bottom fill layer UF2. The fourth bottom fill layer UF4 and the sixth bottom fill layer UF6 may be spaced apart from the second dam DM2. The thermal interface material layer TIM may be interposed between the heat dissipation member HS and the first and second semiconductor dies CH1 and CH2. According to one or more example embodiments, other structures may be the same / similar to the structures described above.

[0104] In a semiconductor package according to one or more example embodiments, a multi-layer underfill layer is interposed between a first semiconductor die on which a backside redistribution pattern may be formed and a second semiconductor die disposed on the first semiconductor die. In addition, a dam is disposed on an edge of the first semiconductor die so that the underfill layer is not exposed to a side of the mold layer. Therefore, the reliability of the semiconductor package can be improved.

[0105] Although one or more example embodiments are specifically shown and described above, it will be understood by those skilled in the art that many modifications and changes in form and detail may be made without departing from the spirit and scope of the appended claims. Therefore, one or more example embodiments shown and described above should be considered in all respects as illustrative and not restrictive. In addition, one or more example embodiments may be combined with each other.

Claims

1. A semiconductor package, comprising: a first semiconductor die; a first underfill layer on an upper surface of the first semiconductor die; a second bottom filling layer, on the first bottom filling layer; a second semiconductor die on the second underfill layer; as well as a mold layer on a side surface of the second semiconductor die, a side surface of the second bottom filling layer, and the upper surface of the first semiconductor die, Wherein, the first semiconductor die comprises: a first substrate; a first redistribution pattern on the first substrate; a first redistribution dielectric layer on the first redistribution pattern; and a first dam on an edge of the first substrate and the first redistribution dielectric layer, and The first bottom filling layer contacts a side surface of the first dam.

2. The semiconductor package according to claim 1, wherein The second underfill layer is spaced apart from the side surface of the first dam.

3. The semiconductor package according to claim 1, wherein: The upper surface of the first bottom filling layer has a first surface roughness, and The upper surface of the second bottom filling layer has a second surface roughness that is smaller than the first surface roughness.

4. The semiconductor package according to claim 1, wherein: The first bottom filling layer includes a first filler dispersed in the first bottom filling layer, Wherein, the second bottom filling layer includes a second filler, and Wherein, at least one of the second fillers includes a material different from that of at least one of the first fillers, or has a size different from that of at least one of the first fillers.

5. The semiconductor package according to claim 4, wherein: At least one of the first fillers is disposed at an interface between the first underfill layer and the second underfill layer.

6. The semiconductor package according to claim 1, wherein The first semiconductor die has a first width in a width direction, The first bottom filling layer has a second width in the width direction that is smaller than the first width. wherein the second bottom filling layer has a third width in the width direction that is smaller than the second width, and The second semiconductor die has a fourth width in the width direction that is smaller than the third width.

7. The semiconductor package of claim 1 , further comprising an internal connection member in the second underfill layer and connecting the first semiconductor die to the second semiconductor die, in, The first semiconductor die further comprises: The second redistribution pattern comprises: a via portion penetrating the first redistribution dielectric layer and contacting the first redistribution pattern; and a pad portion on the first redistribution dielectric layer; and a conductive pattern on the second redistribution pattern, wherein the upper surface of the first dam has a first height from the upper surface of the first substrate in a height direction, wherein the upper surface of the conductive pattern has a second height from the upper surface of the first substrate in the height direction, wherein the second height is lower than the first height, and The upper side wall of the first dam is not covered by the first bottom filling layer.

8. The semiconductor package of claim 1 , further comprising an internal connection member in the second underfill layer and connecting the first semiconductor die to the second semiconductor die, in, The first semiconductor die further comprises: The second redistribution pattern comprises: a via portion penetrating the first redistribution dielectric layer and contacting the first redistribution pattern; and a pad portion on the first redistribution dielectric layer; and a conductive pattern on the second redistribution pattern, wherein the upper surface of the first dam has a first height from the upper surface of the first substrate in a height direction, wherein the upper surface of the conductive pattern has a second height from the upper surface of the first substrate in the height direction, wherein the first height is lower than the second height, and Wherein, the upper side wall of the conductive pattern is not covered by the first bottom filling layer.

9. The semiconductor package according to claim 8, wherein: The first underfill layer extends to cover the upper surface of the first dam.

10. The semiconductor package according to claim 1, further comprising: a third semiconductor die on the second semiconductor die and covered by the mold layer; as well as a third bottom filling layer between the second semiconductor die and the third semiconductor die, The third bottom filling layer extends to contact the side surface of the second semiconductor die and the upper end of the second bottom filling layer.

11. The semiconductor package according to claim 1, further comprising: a third bottom fill layer on the second semiconductor die; a fourth bottom filling layer, on the third bottom filling layer; as well as a third semiconductor die, on the fourth bottom fill layer, wherein the second semiconductor die comprises a second dam provided at an edge of an upper surface of the second semiconductor die, wherein the third bottom filling layer contacts the side surface of the second dam, and Wherein, the fourth bottom filling layer is spaced apart from the side surface of the second dam.

12. The semiconductor package according to claim 1, wherein The first dam and the first redistribution dielectric layer include the same material.

13. A semiconductor package, comprising: a first semiconductor die; a first underfill layer on an upper surface of the first semiconductor die; a second bottom filling layer, on the first bottom filling layer; a second semiconductor die on the second underfill layer; an internal connection member in the second underfill layer and connecting the first semiconductor die and the second semiconductor die; as well as a mold layer on a side surface of the second semiconductor die, a side surface of the second bottom filling layer, and the upper surface of the first semiconductor die, Wherein, the first semiconductor die comprises: a first substrate; a first redistribution pattern on the first substrate; a first redistribution dielectric layer on the first redistribution pattern; a first dam provided on the first redistribution dielectric layer and along an edge of the first substrate; a second redistribution pattern including a via portion and a pad portion, the via portion penetrating the first redistribution dielectric layer and contacting the first redistribution pattern, the pad portion being on the first redistribution dielectric layer; and a conductive pattern on the second redistribution pattern, wherein the first bottom filling layer contacts a side surface of the first dam, The first semiconductor die has a first width in a width direction, The first bottom filling layer has a second width in the width direction that is smaller than the first width. wherein the second bottom filling layer has a third width in the width direction that is smaller than the second width, and The second semiconductor die has a fourth width in the width direction that is smaller than the third width.

14. The semiconductor package according to claim 13, wherein: The upper surface of the first dam has a first height from the upper surface of the first substrate in a height direction. wherein the upper surface of the conductive pattern has a second height from the upper surface of the first substrate in the height direction, wherein the second height is lower than the first height, and The upper side wall of the first dam is not covered by the first bottom filling layer.

15. The semiconductor package according to claim 13, wherein: The upper surface of the first dam has a first height from the upper surface of the first substrate in a height direction. wherein the upper surface of the conductive pattern has a second height from the upper surface of the first substrate in the height direction, wherein the first height is lower than the second height, and Wherein, the upper side wall of the conductive pattern is not covered by the first bottom filling layer.

16. The semiconductor package according to claim 15, wherein: The first underfill layer extends to cover the upper surface of the first dam.

17. The semiconductor package according to claim 13, further comprising: a third bottom fill layer on the second semiconductor die; a fourth bottom filling layer, on the third bottom filling layer; as well as a third semiconductor die, on the fourth bottom fill layer, wherein the second semiconductor die comprises a second dam, the second dam being at an edge of an upper surface of the second semiconductor die, wherein the third bottom filling layer contacts the side surface of the second dam, and Wherein, the fourth bottom filling layer is spaced apart from the side surface of the second dam.

18. A semiconductor package, comprising: a first semiconductor die; a first underfill layer on an upper surface of the first semiconductor die; a second bottom filling layer, on the first bottom filling layer; a second semiconductor die on the second underfill layer; as well as a mold layer on a side surface of the second semiconductor die, a side surface of the second bottom filling layer, and the upper surface of the first semiconductor die, The upper surface of the first bottom filling layer has a first surface roughness, and The upper surface of the second bottom filling layer has a second surface roughness that is smaller than the first surface roughness.

19. The semiconductor package according to claim 18, wherein: The first bottom filling layer includes a first filler dispersed in the first bottom filling layer, Wherein, the second bottom filling layer includes a second filler, and Wherein, at least one of the second fillers includes a material different from that of at least one of the first fillers, or has a size different from that of at least one of the first fillers.

20. The semiconductor package according to claim 19, wherein At least one of the first fillers is disposed at an interface between the first underfill layer and the second underfill layer.

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