Semiconductor device

Abstract

A semiconductor device includes: an upper conductive line extending in a first horizontal direction over a substrate; a channel layer facing the upper conductive line in a second horizontal direction perpendicular to the first horizontal direction; a gate dielectric film between the channel layer and the upper conductive line; a conductive contact pattern including a lower surface in contact with the upper surface of the channel layer and sidewalls including a first sidewall facing the upper conductive line in the second horizontal direction; and an insulating spacer including a first portion between the upper conductive line and the conductive contact pattern in the second horizontal direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0106422 filed on August 14, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] Apparatus and devices consistent with the present disclosure relate to a semiconductor device, and more particularly, to a semiconductor device including a channel layer including an oxide semiconductor. Background Art

[0004] Due to the advancement of electronic technology, semiconductor devices have been rapidly reduced in size, and thus, a transistor including a channel layer including an oxide semiconductor material has been proposed to reduce leakage current through a channel region. Summary of the invention

[0005] On the one hand, a semiconductor device having a structure with improved reliability is provided, which has improved reliability by ensuring electrical connection between a channel layer and a conductive contact pattern contacting the channel layer in a transistor including a channel layer containing an oxide semiconductor material and by preventing a short circuit between other conductive components adjacent to the channel layer and the conductive contact pattern.

[0006] According to an aspect of one or more embodiments, there is provided a semiconductor device, including: an upper conductive line extending along a first horizontal direction above a substrate; a channel layer facing the upper conductive line in a second horizontal direction perpendicular to the first horizontal direction; a gate dielectric film located between the channel layer and the upper conductive line; a conductive contact pattern including a lower surface and a side wall, the lower surface contacting an upper surface of the channel layer, the side wall including a first side wall facing the upper conductive line in the second horizontal direction; and an insulating spacer including a first portion located between the upper conductive line and the conductive contact pattern in the second horizontal direction.

[0007] According to another aspect of one or more embodiments, there is provided a semiconductor device, comprising: a plurality of lower conductive lines, the plurality of lower conductive lines being arranged in parallel with each other over a substrate; a mold insulating pattern, which is arranged on the plurality of lower conductive lines and defines a transistor region extending in a first horizontal direction; a plurality of channel layers, the plurality of channel layers being arranged in a row along the first horizontal direction in the transistor region, each of the plurality of channel layers including a vertical channel portion facing a sidewall of the mold insulating pattern; a plurality of upper conductive lines, the plurality of upper conductive lines being arranged respectively over the plurality of channel layers, each of the plurality of upper conductive lines having a sidewall facing the vertical channel portion of a corresponding channel layer in the plurality of channel layers; and a plurality of gate dielectric films, the plurality of gate dielectric films respectively Located between multiple channel layers and multiple upper conductive lines; multiple conductive contact patterns, the multiple conductive contact patterns are connected to the vertical channel parts of the corresponding channel layers in the multiple channel layers; and multiple insulating spacers, the multiple insulating spacers are respectively on the multiple gate dielectric films, wherein each of the multiple conductive contact patterns includes a lower surface and a first side wall, the lower surface contacts the upper surface of the vertical channel part, the first side wall faces the corresponding upper conductive line in the multiple upper conductive lines in a second horizontal direction perpendicular to the first horizontal direction, and each of the multiple insulating spacers includes a first part located between the corresponding upper conductive line in the multiple upper conductive lines and the corresponding conductive contact pattern in the multiple conductive contact patterns in the second horizontal direction.

[0008] According to another aspect of one or more embodiments, a semiconductor device is provided, including: a peripheral circuit region, which is arranged on a substrate and includes a plurality of peripheral circuits; a lower conductive line, which is arranged on the peripheral circuit region and connected to the plurality of peripheral circuits; a molded insulating pattern, which is arranged on the lower conductive line and has a sidewall defining a transistor region; a channel layer, which is arranged in the transistor region and includes an oxide semiconductor layer, the channel layer having a lower surface and a vertical channel portion, the lower surface being in contact with an upper surface of the lower conductive line, the vertical channel portion facing the sidewall of the molded insulating pattern; a gate dielectric film, which covers the channel layer in the transistor region; an upper conductive line, which is arranged on the gate dielectric film in the transistor region and has a sidewall facing the vertical channel portion, the upper conductive line extending in a first horizontal direction; a conductive contact pattern, which includes a lower surface and a first sidewall, the lower surface being in contact with an upper surface of the channel layer, the first sidewall facing the upper conductive line in a second horizontal direction perpendicular to the first horizontal direction; and an insulating spacer, which includes a first portion located between the upper conductive line and the conductive contact pattern in the second horizontal direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Various embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1is a plan layout diagram showing some components of a semiconductor device according to some embodiments;

[0011] Figure 2 is along Figure 1 The line A-A' intercepts Figure 1 A cross-sectional view of a semiconductor device;

[0012] Figure 3 is along Figure 1 The line B-B' intercepts Figure 1 A cross-sectional view of a semiconductor device;

[0013] Figure 4 yes Figure 2 An enlarged cross-sectional view of a region EX1;

[0014] Figure 5 is a cross-sectional view of a semiconductor device according to some embodiments;

[0015] Figure 6 yes Figure 5 An enlarged cross-sectional view of a region EX2;

[0016] Figure 7 is a cross-sectional view of a semiconductor device according to some embodiments;

[0017] Figure 8 is a cross-sectional view of a semiconductor device according to some embodiments;

[0018] Fig. 9 yes Figure 8 An enlarged cross-sectional view of region EX3;

[0019] Fig.10 is a cross-sectional view of a semiconductor device according to some embodiments;

[0020] FIG. 11A to FIG. 19B are diagrams respectively illustrating a process sequence of a method for manufacturing a semiconductor device according to some embodiments, and specifically, Fig.11A , Fig. 12A and Fig.15A are plan layout diagrams each showing some components of a semiconductor device according to a process sequence for describing a method of manufacturing a semiconductor device, Fig. 11B , Fig. 12B , Fig.13 , Fig.14 , Fig. 15B , Fig.16A , Fig.17A , Fig.18A and Fig.19A are each showing a semiconductor device according to a process sequence and along Figure 1 A cross-sectional view of a portion corresponding to a cross-sectional view taken along line AA', and Fig. 16B , Fig. 17B , Fig.18B and Fig.19B They are Fig.16A , Fig.17A , Fig.18A and Fig.19A An enlarged cross-sectional view of a region EX1;

[0021] FIG. 20A to FIG. 24B are diagrams respectively illustrating a process sequence of a method for manufacturing a semiconductor device according to some embodiments, and specifically, Fig. 20A , Fig.21A , Fig.22A , Fig.23A and Fig.24A are each showing a semiconductor device according to a process sequence and along Figure 1 A cross-sectional view of a portion corresponding to a cross-sectional view taken along line AA', and Fig. 20B , Fig.21B , Fig. 22B , Fig. 23B and Fig. 24B They are Fig. 20A , Fig.21A , Fig.22A , Fig.23A and Fig.24A An enlarged cross-sectional view of a region EX2; and

[0022] Fig.25A is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to some embodiments, and Fig.25B yes Fig.25A An enlarged cross-sectional view of area EX3. DETAILED DESCRIPTION

[0023] Hereinafter, various embodiments will be described in detail with reference to the accompanying drawings. Throughout the specification, the same components are represented by the same reference numerals, and repeated descriptions thereof are omitted for brevity. In addition, in the accompanying drawings, some components may be enlarged relative to other components to make the illustration clearer, and therefore, the accompanying drawings should not be considered to be drawn to scale.

[0024] Figure 1 is a plan layout diagram showing some components of the semiconductor device 100 according to some embodiments. Figure 2 is along Figure 1 The line A-A' intercepts Figure 1 A cross-sectional view of a semiconductor device 100 is shown in FIG. Figure 3 is along Figure 1 The line B-B' intercepts Figure 1 A cross-sectional view of the semiconductor device 100, and Figure 4 yes Figure 2 An enlarged cross-sectional view of region EX1.

[0025] Reference Figures 1 to 4 , the semiconductor device 100 may include a substrate 102, a peripheral circuit structure PCA disposed on the substrate 102 and including a plurality of peripheral circuits, and a plurality of bit lines BL and a plurality of shielding structures SL disposed on the peripheral circuit structure PCA.

[0026] In some embodiments, the substrate 102 may include silicon, for example, single crystal silicon, polycrystalline silicon, or amorphous silicon. In some embodiments, the substrate 102 may include at least one selected from Ge, SiGe, SiC, GaAs, InAs, and InP. In some embodiments, the substrate 102 may include a conductive region, for example, a well doped with impurities or a structure doped with impurities.

[0027] Each of the plurality of bit lines BL may be connected to at least one peripheral circuit among the plurality of peripheral circuits of the peripheral circuit structure PCA. Each of the plurality of shielding structures SL may be floating. The plurality of bit lines BL and the plurality of shielding structures SL may be insulated from each other by the interlayer dielectric 106F. The plurality of shielding structures SL may be covered by the interlayer dielectric 106G, and the plurality of bit lines BL may pass through the interlayer dielectrics 106F and 106G in a vertical direction (e.g., Z direction). The plurality of bit lines BL may each be connected to the peripheral circuit of the peripheral circuit structure PCA through some of the plurality of conductive plugs P1, P2, and P3 and the plurality of wiring layers M1 and M2 included in the peripheral circuit structure PCA.

[0028] The peripheral circuit structure PCA may include a plurality of core circuits 104. The plurality of core circuits 104 may each include a first conductive pattern C1 and a second conductive pattern C2, which are sequentially arranged on the substrate 102 in the order described. The first conductive pattern C1 and the second conductive pattern C2 may constitute various circuit devices arranged on the peripheral circuit structure PCA for controlling the functions of the semiconductor device. In some embodiments, the peripheral circuit structure PCA may also include various active elements (such as transistors, etc.) and various passive elements (such as capacitors, resistors, inductors, etc.).

[0029] In some embodiments, the plurality of peripheral circuits of the peripheral circuit structure PCA may include, but are not limited to, a sub-word line driver (SWD) block, a sense amplifier (S / A) block, and / or control logic. The plurality of peripheral circuits of the peripheral circuit structure PCA may include NMOS transistors and PMOS transistors. The plurality of peripheral circuits may be electrically connected to conductive lines (e.g., a plurality of bit lines BL arranged on the peripheral circuit structure PCA) through a plurality of conductive plugs P1, P2, and P3 and a plurality of wiring layers M1 and M2.

[0030] In the peripheral circuit structure PCA, components that need to be insulated from each other among the plurality of core circuits 104, the plurality of conductive plugs P1, P2, and P3, and the plurality of wiring layers M1 and M2 can maintain a required insulation distance between each other through a plurality of interlayer dielectrics 106A, 106B, 106C, 106D, and 106E. Each of the plurality of interlayer dielectrics 106A, 106B, 106C, 106D, 106E, 106F, and 106G may include, but is not limited to, an oxide film, a nitride film, or a combination thereof.

[0031] In some embodiments, the peripheral circuit structure PCA located on the substrate 102 may be omitted. In this case, the peripheral circuit structure PCA may be arranged on the substrate 102 and on the substrate 102. Figure 2 and Figure 3 In some embodiments, the peripheral circuit structure PCA may be arranged in another region separate from the region shown in FIG. Figure 1 ) in an area where the cell array area is laterally separated.

[0032] A plurality of bit lines BL and a plurality of shielding structures SL may be arranged above the substrate 102 to be spaced apart from each other in a first horizontal direction (e.g., X direction) and to extend longitudinally in a second horizontal direction (e.g., Y direction) perpendicular to the first horizontal direction (X direction). A plurality of bit lines BL and a plurality of shielding structures SL may extend parallel to each other in the second horizontal direction (Y direction). In some embodiments, each of the plurality of bit lines BL may include, but is not limited to, Ti, TiN, Ta, TaN, Mo, Ru, W, WN, Co, Ni, TiSi, TiSiN, WSi, WSiN, TaSi, TaSiN, RuTiN, CoSi, NiSi, polysilicon, or a combination thereof. In this document, the bit line BL may be referred to as a lower conductive line. In some embodiments, each of the plurality of shielding structures SL may include, but is not limited to, W, Al, Cu, or a combination thereof. In some embodiments, each of the plurality of shielding structures SL may include, but is not limited to, W, Al, Cu, or a combination thereof. In some embodiments, each of the plurality of shielding structures SL may include a conductive film and an air gap or void in the conductive film, and the conductive film includes W, Al, Cu, or a combination thereof.

[0033] The mold insulating pattern 110 may be disposed on or over the plurality of bit lines BL and the plurality of shielding structures SL. The mold insulating pattern 110 may have a shape defining a transistor region TRR (see Figure 1) sidewall 110s. Each of the mold insulating pattern 110 and the transistor region TRR defined by the sidewall 110s of the mold insulating pattern 110 may extend longitudinally in the first horizontal direction (X direction). The mold insulating pattern 110 may include a lower mold pattern 110A, a first mold insulating pattern 110B, and a second mold insulating pattern 110C, and the lower mold pattern 110A, the first mold insulating pattern 110B, and the second mold insulating pattern 110C are sequentially stacked on the plurality of bit lines BL and the interlayer dielectric 106G in the vertical direction (Z direction) in the order described. Each of the lower mold pattern 110A, the first mold insulating pattern 110B, and the second mold insulating pattern 110C may include a silicon oxide film, a silicon nitride film, or a combination thereof. For example, in some embodiments, the lower mold pattern 110A and the second mold insulating pattern 110C may each include a silicon nitride film, and the first mold insulating pattern 110B may include a silicon oxide film. However, the embodiments are not limited thereto, and in some embodiments, each of the lower mold pattern 110A, the first mold insulating pattern 110B, and the second mold insulating pattern 110C may include the same material.

[0034] like Figure 1 and Figure 2 As shown, in the transistor region TRR, a plurality of channel layers 120 may be arranged in a row in a first horizontal direction (X direction). Each of the plurality of channel layers 120 may include a vertical channel portion VC facing the sidewall of the mold insulating pattern 110 and a horizontal channel portion HC in contact with the upper surface of the bit line BL. In each of the plurality of channel layers 120, the vertical channel portion VC may be in contact with the sidewall of the mold insulating pattern 110 and may extend longitudinally from the horizontal channel portion HC in a vertical direction (Z direction).

[0035] In the transistor region TRR, a plurality of transistors each including a plurality of channel layers 120 may be arranged. The plurality of transistors may include two transistors facing each other in a second horizontal direction (Y direction) perpendicular to the first horizontal direction (X direction), and the two transistors may share one channel layer 120 among the plurality of channel layers 120. Each of the plurality of channel layers 120 may contact an upper surface of one bit line BL among the plurality of bit lines BL.

[0036] In some embodiments, the channel layer 120 may include an oxide semiconductor layer including InGaZnO (IGZO), Sn-IGZO, InWO (IWO), InZnO (IZO), ZnSnO (ZTO), ZnO, yttrium-doped zinc oxide (YZO), InGaSiO (IGSO), InO, SnO, TiO, ZnON, MgZnO, ZrInZnO, HfInZnO, SnInZnO, SiInZnO, GaZnSnO, ZrZnSnO, or a combination thereof. In some embodiments, the channel layer 120 may include Si, Ge, SiGe, a III-V compound semiconductor, or a combination thereof. The II-IV compound semiconductor may include, but is not limited to, GaAs or InSb. For example, the channel layer 120 may include IGZO.

[0037] like Figure 1 and Figure 2 As shown, a gate dielectric film 130 covering the channel layer 120 and a plurality of word lines WL covering the gate dielectric film 130 may be arranged in the transistor region TRR. The plurality of word lines WL may be arranged parallel to each other in the second horizontal direction (Y direction) and extend longitudinally in the first horizontal direction (X direction). In this article, the word line WL may be referred to as an upper conductive line. In the transistor region TRR, a word line WL may contact a gate dielectric film 130. Each of the plurality of channel layers 120 may face the word line WL in the second horizontal direction (Y direction) with a gate dielectric film 130 therebetween.

[0038] like Figure 1 As shown, each of the multiple word lines WL may include a portion WLP1 and a portion WLP2, wherein the portion WLP1 faces the channel layer 120 in the second horizontal direction (Y direction) with a gate dielectric film 130 therebetween, and the portion WLP2 faces the molded insulating pattern 110 in the second horizontal direction (Y direction) with a gate dielectric film 130 therebetween.

[0039] like Figure 2 As shown, the bit line BL may be spaced apart from the word line WL in a vertical direction (Z direction) with the channel layer 120 and the gate dielectric film 130 therebetween. The bit line BL may have an upper surface contacting the channel layer 120.

[0040] One channel layer 120 may face the surface of each of the two word lines WL. A gate dielectric film 130 may be disposed between the channel layer 120 and the word line WL. The gate dielectric film 130 may include a vertical portion and a horizontal portion, the vertical portion being located between the word line WL and the vertical channel portion VC of the channel layer 120, and the horizontal portion being located between the word line WL and the horizontal channel portion HC of the channel layer 120.

[0041] In some embodiments, the gate dielectric film 130 may include a high-K film having a dielectric constant higher than that of a silicon oxide film. In some embodiments, the gate dielectric film 130 may include at least one material selected from hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), lead zirconate titanate (PZT), strontium bismuth tantalate (STB), bismuth iron oxide (BFO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO). Each of the plurality of word lines WL may include Ti, TiN, Ta, TaN, Mo, Ru, W, WN, TiSiN, WSiN, polysilicon, or a combination thereof.

[0042] In the transistor region TRR, the lower insulating liner 142 and the upper insulating partition wall 144 may be arranged on or above the channel layer 120 between two word lines WL that are adjacent to each other and spaced apart from each other in the second horizontal direction (Y direction). The lower insulating liner 142 and the upper insulating partition wall 144 may include insulating films containing materials different from each other, respectively. For example, in some embodiments, the lower insulating liner 142 may include a silicon nitride film, and the upper insulating partition wall 144 may include a silicon oxide film, but the embodiment is not limited thereto.

[0043] A plurality of conductive contact patterns 150 may be respectively arranged on the plurality of channel layers 120. Each of the plurality of conductive contact patterns 150 may be connected to one of the plurality of channel layers 120. Each of the plurality of conductive contact patterns 150 may include a lower surface 150B contacting an upper surface of a vertical channel portion VC of the channel layer 120, a first sidewall 150S1 facing the word line WL in the second horizontal direction (Y direction), and a second sidewall 150S2 facing the mold insulating pattern 110 in the second horizontal direction (Y direction). The first sidewall 150S1 and the second sidewall 150S2 of the conductive contact pattern 150 may be located on opposite sides to each other in the second horizontal direction (Y direction).

[0044] Each of the plurality of conductive contact patterns 150 may include a metal-containing film. In some embodiments, each of the plurality of conductive contact patterns 150 may include Ti, TiN, Ta, TaN, Mo, Ru, W, WN, TiSiN, WSiN, Ni, Ru, or a combination thereof. For example, each of the plurality of conductive contact patterns 150 may have a stacked structure of a conductive barrier film including TiN and a conductive film including W.

[0045] The insulating spacer 148 may be located between the word line WL and the conductive contact pattern 150 in the second horizontal direction (Y direction). The insulating spacer 148 may be disposed on the gate dielectric film 130. The insulating spacer 148 may include a first portion ISp1 located between the word line WL and the conductive contact pattern 150 and a second portion ISp2 located between the gate dielectric film 130 and the conductive contact pattern 150. The insulating spacer 148 may surround the sidewall of the conductive contact pattern 150 such that the insulating spacer 148 contacts each of the first sidewall 150S1 and the second sidewall 150S2 of the conductive contact pattern 150 in the second horizontal direction (Y direction). In some embodiments, when the conductive contact pattern 150 is in the plane ( Figures 1 to 4 When viewed in the XY plane in FIG. 1 ), the insulating spacer 148 may have a ring shape surrounding the conductive contact pattern 150. In some embodiments, the conductive contact pattern 150 may be spaced apart from the mold insulating pattern 110 in the second horizontal direction (Y direction) with the insulating spacer 148 therebetween.

[0046] In some embodiments, the insulating spacer 148 may include silicon oxide, silicon nitride, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, or a combination thereof. As used herein, each of the terms "SiCN", "SiBN", "SiON", "SiOCN", "SiBCN", and "SiOC" refers to a material including the elements included in the corresponding term, rather than a chemical formula representing a stoichiometric relationship.

[0047] like Figure 1 As shown, a plurality of channel layers 120, and thus a plurality of conductive contact patterns 150, may be regularly arranged at regular intervals in a first horizontal direction (X direction) and a second horizontal direction (Y direction). Figure 1An example is shown in which a plurality of channel layers 120, and therefore a plurality of conductive contact patterns 150, are arranged in a matrix structure in a plane (e.g., an XY plane) above the substrate 102, but the embodiment is not limited thereto. For example, a plurality of channel layers 120, and therefore a plurality of conductive contact patterns 150, may be arranged in a honeycomb structure in a plane (e.g., an XY plane) above the substrate 102. A plurality of conductive landing pads LP may be arranged on a plurality of channel layers 120, respectively, and therefore, on a plurality of conductive contact patterns 150, respectively. Each of the plurality of conductive landing pads LP may be connected to a corresponding conductive contact pattern 150 in the plurality of conductive contact patterns 150. The plurality of conductive landing pads LP may be insulated from each other by an isolation insulating film 160. In some embodiments, each of the plurality of conductive landing pads LP may include a metal-containing film. In some embodiments, each of the plurality of conductive landing pads LP may include Ti, TiN, Ta, TaN, Mo, Ru, W, WN, TiSiN, WSiN, Ni, Ru, or a combination thereof.

[0048] The semiconductor device 100 may further include a plurality of capacitor structures CAP respectively arranged on the plurality of conductive landing pads LP. The etch stop film 162 and the interlayer dielectric 170 may be sequentially stacked on the plurality of conductive landing pads LP and the isolation insulating film 160 in the order described. Each of the plurality of capacitor structures CAP may pass through the interlayer dielectric 170 and the etch stop film 162 in the vertical direction (Z direction), and thus be connected to a corresponding conductive landing pad LP among the plurality of conductive landing pads LP. The etch stop film 162 may include a silicon nitride film, and the interlayer dielectric 170 may include a silicon oxide film.

[0049] Figure 5 and Figure 6 is a diagram illustrating a semiconductor device 200 according to some embodiments, and specifically, Figure 5 is the semiconductor device 200 and along Figure 1 A cross-sectional view of a portion corresponding to a cross-sectional view taken along line AA', and Figure 6 yes Figure 5 An enlarged cross-sectional view of region EX2. Figure 5 and Figure 6 In, with Figures 1 to 4 The same reference numerals in the drawings respectively denote the same components, and repeated descriptions thereof are omitted here for the sake of brevity.

[0050] Reference Figure 5 and Figure 6 , the semiconductor device 200 has the same Figures 1 to 4 The semiconductor device 100 is described as having substantially the same configuration. However, the semiconductor device 200 includes a plurality of conductive contact patterns 250 and a plurality of insulating spacers 248 .

[0051] A plurality of conductive contact patterns 250 may be respectively arranged on the plurality of channel layers 120. Each of the plurality of conductive contact patterns 250 may be connected to a corresponding channel layer 120 among the plurality of channel layers 120. Each of the plurality of conductive contact patterns 250 may include a first lower surface B1 contacting an upper surface of a vertical channel portion VC of the channel layer 120, a second lower surface B2 contacting an upper surface of a first mold insulating pattern 110B of the mold insulating pattern 110, and a surface 250C contacting a sidewall of the vertical channel portion VC of the channel layer 120.

[0052] Each of the plurality of conductive contact patterns 250 may include a first sidewall 250S1 facing the word line WL in the second horizontal direction (Y direction) and a second sidewall 250S2 facing the mold insulation pattern 110 in the second horizontal direction (Y direction). The first sidewall 250S1 and the second sidewall 250S2 of the conductive contact pattern 250 may be located on opposite sides to each other in the second horizontal direction (Y direction). The constituent material of each of the plurality of conductive contact patterns 250 is substantially the same as the constituent material of each of the plurality of conductive contact patterns 150 described above.

[0053] The semiconductor device 200 may include a plurality of insulating spacers 248. Each of the plurality of insulating spacers 248 may be disposed between a corresponding conductive contact pattern 250 among a plurality of conductive contact patterns 250 and a word line WL adjacent to the corresponding conductive contact pattern 250. Each of the plurality of insulating spacers 248 may not include a portion between the corresponding conductive contact pattern 250 and the mold insulating pattern 110. In other words, the insulating spacer 248 may omit a portion between the second sidewall 250S2 of the corresponding conductive contact pattern 250 and the mold insulating pattern 110, so that the insulating spacer 248 is not disposed between the second sidewall 250S2 of the corresponding conductive contact pattern 250 and the mold insulating pattern 110.

[0054] A plurality of insulating spacers 248 may be arranged one by one between the word line WL and the corresponding conductive contact pattern 250 in the second horizontal direction (Y direction). Each of the plurality of insulating spacers 248 may be arranged on the corresponding gate dielectric film 130. Each of the plurality of insulating spacers 248 may include a first portion ISp1 located between the word line WL and the conductive contact pattern 250 and a second portion ISp2 located between the gate dielectric film 130 and the conductive contact pattern 250. Therefore, each of the plurality of insulating spacers 248 may surround only some of the sidewalls of the corresponding conductive contact pattern 250, so that each of the plurality of insulating spacers 248 is in contact with the first sidewall 250S1 of the conductive contact pattern 250, but not in contact with the second sidewall 250S2 of the conductive contact pattern 250. The second sidewall 250S2 of the conductive contact pattern 250 may be in contact with the mold insulating pattern 110.

[0055] Each of the plurality of conductive contact patterns 250 may be in contact with the upper surface and sidewall of the corresponding channel layer 120 in the plurality of channel layers 120. Each of the plurality of conductive contact patterns 250 may have a lower surface with a step. More specifically, each of the plurality of conductive contact patterns 250 may have a first lower surface B1 in contact with the upper surface of the vertical channel portion VC of the corresponding channel layer 120 and a second lower surface B2 in contact with the mold insulation pattern 110. A first vertical distance from the upper surface of the bit line BL overlapping the conductive contact pattern 250 in the vertical direction (Z direction) to the first lower surface B1 of the conductive contact pattern 250 may be different from a second vertical distance from the upper surface of the bit line BL to the second lower surface B2 of the conductive contact pattern 250. The second vertical distance may be less than the first vertical distance. As used herein, the term "vertical distance (or vertical length)" refers to a distance (or length) in the vertical direction (Z direction).

[0056] The first lower surface B1 of the conductive contact pattern 250 may be in contact with the upper surface of the vertical channel portion VC of the corresponding channel layer 120, and the second lower surface B2 of the conductive contact pattern 250 may be in contact with the upper surface of the first mold insulation pattern 110B of the mold insulation pattern 110. The second sidewall 250S2 of the conductive contact pattern 250 may be in contact with the second mold insulation pattern 110C of the mold insulation pattern 110. The conductive contact pattern 250 may have a surface extending between the first lower surface B1 and the second lower surface B2 of the conductive contact pattern 250 and in contact with the sidewall of the corresponding channel layer 120.

[0057] Each of the plurality of conductive contact patterns 250 may include a first portion, the first portion being in contact with a corresponding insulating spacer 248 of the plurality of insulating spacers 248 and having a first lower surface B1 and a first sidewall 250S1, and a second portion being in contact with the mold insulating pattern 110 and having a second lower surface B2 and a second sidewall 250S2, and a vertical length of the first portion of each of the plurality of conductive contact patterns 250 may be smaller than a vertical length of the second portion of each of the plurality of conductive contact patterns 250. The vertical length of each of the plurality of insulating spacers 248 may be smaller than a vertical length of the second portion of each of the plurality of conductive contact patterns 250.

[0058] The second sidewall 250S2 of the conductive contact pattern 250 may contact the second mold insulating pattern 110C of the mold insulating pattern 110. The constituent material of the insulating spacer 248 may be the same as that of the reference Figure 2 and Figure 4 The materials of construction of the insulating spacers 148 described are substantially the same.

[0059] Figure 7 is a cross-sectional view illustrating a semiconductor device 200A according to some embodiments. Figure 7 The semiconductor device 200A is shown in FIG. Figure 5 The enlarged cross-sectional structure of the portion corresponding to the region EX2. Figure 7 In, with Figures 1 to 6 The same reference numerals in the drawings respectively denote the same components, and repeated descriptions thereof are omitted here for the sake of brevity.

[0060] Reference Figure 7 , the semiconductor device 200A has the same Figure 5 and Figure 6 The semiconductor device 200 described above has substantially the same configuration. However, the semiconductor device 200A includes a conductive contact pattern 250A.

[0061] The conductive contact pattern 250A has the same Figure 5 and Figure 6 The conductive contact pattern 250A may have substantially the same configuration as described above, however, the conductive contact pattern 250A may have a first lower surface B1 in contact with an upper surface of the vertical channel portion VC of the channel layer 120 and a second lower surface B2A in contact with the mold insulating pattern 110. The second lower surface B2A of the conductive contact pattern 250A may be the lowest surface of the conductive contact pattern 250A closest to the substrate 102. A vertical level LV21 of the second lower surface B2A of the conductive contact pattern 250A may be closer to the substrate 102 than a vertical level LV22 of an interface between the first mold insulating pattern 110B and the second mold insulating pattern 110C (see Figure 5 ).

[0062] The first lower surface B1 of the conductive contact pattern 250A may contact the upper surface of the vertical channel portion VC of the channel layer 120, and the second lower surface B2A of the conductive contact pattern 250A may contact the first mold insulation pattern 110B of the mold insulation pattern 110. The second sidewall 2AS2 of the conductive contact pattern 250A may contact each of the first mold insulation pattern 110B and the second mold insulation pattern 110C of the mold insulation pattern 110. The conductive contact pattern 250A may have a surface 250CA extending between the first lower surface B1 and the second lower surface B2A of the conductive contact pattern 250A and contacting the sidewall of the channel layer 120.

[0063] The conductive contact pattern 250A may include a first portion and a second portion, the first portion being in contact with the insulating spacer 248 and having a first lower surface B1 and a first sidewall 250S1, the second portion being in contact with the mold insulating pattern 110 and having a second lower surface B2A and a second sidewall 2AS2, and the vertical length of the first portion of the conductive contact pattern 250A may be smaller than the vertical length of the second portion of the conductive contact pattern 250A. The vertical length of the insulating spacer 248 may be smaller than the vertical length of the second portion of the conductive contact pattern 250A.

[0064] Figure 8 and Fig. 9 are diagrams each illustrating a semiconductor device 300 according to some embodiments, and specifically, Figure 8 is the semiconductor device 300 and along Figure 1 A cross-sectional view of a portion corresponding to a cross-sectional view taken along line AA', and Fig. 9 yes Figure 8 An enlarged cross-sectional view of region EX3. Figure 8 and Fig. 9 In, with Figures 1 to 7 The same reference numerals in the drawings respectively denote the same components, and repeated descriptions thereof are omitted here for the sake of brevity.

[0065] Reference Figure 8 and Fig. 9 , the semiconductor device 300 has the same Figures 1 to 4 The semiconductor device 100 is described as having substantially the same configuration. However, the semiconductor device 300 includes a plurality of conductive contact patterns 350 and a plurality of insulating spacers 248 .

[0066] A plurality of conductive contact patterns 350 may be respectively arranged on the plurality of channel layers 120. Each of the plurality of conductive contact patterns 350 may be connected to a corresponding channel layer 120 among the plurality of channel layers 120. Each of the plurality of conductive contact patterns 350 may include a lower surface 350B in contact with an upper surface of a vertical channel portion VC of the channel layer 120 and a surface 350C in contact with a sidewall of the vertical channel portion VC of the channel layer 120.

[0067] Each of the plurality of conductive contact patterns 350 may include a first sidewall 350S1 facing the word line WL in the second horizontal direction (Y direction) and a second sidewall 350S2 facing the mold insulating pattern 110 in the second horizontal direction (Y direction). The first sidewall 350S1 and the second sidewall 350S2 of the conductive contact pattern 350 may be located on opposite sides to each other in the second horizontal direction (Y direction). The first sidewall 350S1 of the conductive contact pattern 350 may contact the insulating spacer 248. The second sidewall 350S2 of the conductive contact pattern 350 may contact the mold insulating pattern 110. The second sidewall 350S2 of the conductive contact pattern 350 may include a curved surface convex toward the mold insulating pattern 110. The constituent material of each of the plurality of conductive contact patterns 350 may be substantially the same as the constituent material of each of the plurality of conductive contact patterns 150 described above.

[0068] Each of the plurality of insulating spacers 248 may include a first portion ISp1 located between the word line WL and the conductive contact pattern 350 and a second portion ISp2 located between the gate dielectric film 130 and the conductive contact pattern 350. Each of the plurality of insulating spacers 248 may surround only some of the sidewalls of the corresponding conductive contact pattern 350, such that each of the plurality of insulating spacers 248 is in contact with a first sidewall 350S1 of the conductive contact pattern 350 but is not in contact with a second sidewall 350S2 of the conductive contact pattern 350.

[0069] Each of the plurality of conductive contact patterns 350 may be in contact with an upper surface and a sidewall of a corresponding channel layer 120 among the plurality of channel layers 120. Each of the plurality of conductive contact patterns 350 may include a lower surface 350B in contact with an upper surface of a vertical channel portion VC of the channel layer 120. A lowest point of a second sidewall 350S2 of the conductive contact pattern 350 may be closer to the substrate 102 than a lower surface 350B of the conductive contact pattern 350 in contact with an upper surface of the vertical channel portion VC. The second sidewall 350S2 of the conductive contact pattern 350 may be in contact with a second mold insulating pattern 110C of the mold insulating pattern 110. The conductive contact pattern 350 may have a surface extending between a lower surface 350B of the conductive contact pattern 350 and a lowest point of the second sidewall 350S2 of the conductive contact pattern 350 and in contact with a sidewall of the channel layer 120.

[0070] Each of the plurality of conductive contact patterns 350 may include a first portion that contacts a corresponding insulating spacer 248 of the plurality of insulating spacers 248 and has a lower surface 350B, and a second portion that contacts the mold insulating pattern 110 and has a second sidewall 350S2 including a curved surface, and a vertical length of the first portion of each of the plurality of conductive contact patterns 350 may be smaller than a vertical length of the second portion of each of the plurality of conductive contact patterns 350. The vertical length of each of the plurality of insulating spacers 248 may be smaller than a vertical length of the second portion of each of the plurality of conductive contact patterns 350.

[0071] Fig.10 is a cross-sectional view illustrating a semiconductor device 300A according to some embodiments. Fig.10 The semiconductor device 300A is shown in FIG. Figure 8 The enlarged cross-sectional structure of the portion corresponding to the region EX3. Fig.10 In, with Figures 1 to 9 The same reference numerals in the drawings respectively denote the same components, and repeated descriptions thereof are omitted here for the sake of brevity.

[0072] Reference Fig.10 , the semiconductor device 300A has the same Figure 8 and Fig. 9 The semiconductor device 300A is described as having substantially the same configuration. However, the semiconductor device 300A includes a conductive contact pattern 350A.

[0073] The conductive contact pattern 350A has the same Figure 8 and Fig. 9The conductive contact pattern 350A may have a substantially similar configuration to that described above. However, the conductive contact pattern 350A may have a lower surface 350B, a first side wall 350S1, and a second side wall 350S2, the lower surface 350B being in contact with the upper surface of the vertical channel portion VC of the channel layer 120, the first side wall 350S1 being in contact with the insulating spacer 248, and the second side wall 350S2 being in contact with the mold insulating pattern 110. The first side wall 350S1 and the second side wall 350S2 of the conductive contact pattern 350A may be located on opposite sides to each other in the second horizontal direction (Y direction). The second side wall 350S2 of the conductive contact pattern 350A may be in contact with the mold insulating pattern 110. The second side wall 350S2 of the conductive contact pattern 350A may include a curved surface convex toward the mold insulating pattern 110. The constituent material of each of the plurality of conductive contact patterns 350A is substantially the same as the constituent material of each of the plurality of conductive contact patterns 150 described above.

[0074] Each of the plurality of insulating spacers 248 may include a first portion ISp1 located between the word line WL and the corresponding conductive contact pattern 350A and a second portion ISp2 located between the gate dielectric film 130 and the corresponding conductive contact pattern 350A. Each of the plurality of insulating spacers 248 may surround only some of the sidewalls of the conductive contact pattern 350A, such that each of the plurality of insulating spacers 248 is in contact with a first sidewall 350S1 of the conductive contact pattern 350A but is not in contact with a second sidewall 350S2 of the conductive contact pattern 350A.

[0075] Each of the plurality of conductive contact patterns 350A may contact an upper surface and a sidewall of a corresponding channel layer 120 among the plurality of channel layers 120. Each of the plurality of conductive contact patterns 350A may have a lower surface 350B in contact with an upper surface of a vertical channel portion VC of the channel layer 120 and a surface 350CA in contact with a sidewall of the vertical channel portion VC of the channel layer 120.

[0076] The lowest point of the second sidewall 350S2 of the conductive contact pattern 350A may be closer to the substrate 102 than the lower surface 350B of the conductive contact pattern 350A in contact with the upper surface of the vertical channel portion VC. The second sidewall 350S2 of the conductive contact pattern 350A may be in contact with the first mold insulation pattern 110B and the second mold insulation pattern 110C of the mold insulation pattern 110. The surface 350CA of the conductive contact pattern 350A may be in contact with the sidewall of the vertical channel portion VC of the channel layer 120 between the lower surface 350B of the conductive contact pattern 350A and the lowest point of the second sidewall 350S2.

[0077] Each of the plurality of conductive contact patterns 350A may include a first portion having a first sidewall 350S1 and a lower surface 350B, and a second portion contacting the mold insulating pattern 110 and having a second sidewall 350S2 having a curved surface, and a vertical length of the first portion of each of the plurality of conductive contact patterns 350A may be smaller than a vertical length of the second portion of each of the plurality of conductive contact patterns 350A. A vertical length of each of the plurality of insulating spacers 248 may be smaller than a vertical length of the second portion of each of the plurality of conductive contact patterns 350A.

[0078] A vertical level LV31 of the lowest point of the second sidewall 350S2 of the conductive contact pattern 350A may be closer to the substrate 102 than a vertical level LV32 of an interface between the first mold insulation pattern 110B and the second mold insulation pattern 110C (see FIG. 1 ). Figure 8 ). The second sidewall 350S2 of the conductive contact pattern 350A may contact each of the first mold insulation pattern 110B and the second mold insulation pattern 110C of the mold insulation pattern 110. The conductive contact pattern 350A may have a surface 350CA extending between a lower surface 350B of the conductive contact pattern 350A and a lowest point of the second sidewall 350S2 and contacting a sidewall of the channel layer 120.

[0079] The conductive contact pattern 350A may include a first portion and a second portion, the first portion being in contact with the insulating spacer 248 and having a lower surface 350B and a first side wall 350S1, the second portion being in contact with the molded insulating pattern 110 and having a second side wall 350S2, and the vertical length of the first portion of the conductive contact pattern 350A may be smaller than the vertical length of the second portion of the conductive contact pattern 350A.

[0080] Reference Figures 1 to 10 Each of the described semiconductor devices 100, 200, 200A, 300, and 300A includes an insulating spacer 148 or 248 between a word line WL and a corresponding conductive contact pattern 150, 250, 250A, 350, or 350A. Therefore, according to the various embodiments described above, electrical connection between the channel layer 120 and the conductive contact pattern 150, 250, 250A, 350, or 350A can be ensured, and short circuits between other conductive components adjacent to the channel layer 120, such as short circuits between the word line WL and the conductive contact pattern 150, 250, 250A, 350, or 350A, can be prevented. As shown in FIG. Figures 5 to 10As described above, according to the various embodiments described above, each of the semiconductor devices 200, 200A, 300, and 300A may have a structure in which the conductive contact pattern 250, 250A, 350, or 350A contacts the upper surface and the sidewall of the channel layer 120. Therefore, according to the various embodiments described above, an increased contact area between the channel layer 120 and the conductive contact pattern 250, 250A, 350, or 350A may be ensured, thereby improving the reliability of each of the semiconductor devices 200, 200A, 300, and 300A.

[0081] Next, a method of manufacturing a semiconductor device according to some embodiments is described by taking a specific example.

[0082] FIG. 11A to FIG. 19B are diagrams respectively illustrating the process sequence of a method for manufacturing a semiconductor device according to some embodiments. More specifically, Fig.11A , Fig. 12A and Fig.15A are plan layout diagrams each showing some components of a semiconductor device according to a process sequence for describing a method of manufacturing the semiconductor device. Fig. 11B , Fig. 12B , Fig.13 , Fig.14 , Fig. 15B , Fig.16A , Fig.17A , Fig.18A and Fig.19A are each showing a semiconductor device according to a process sequence and along Figure 1 The cross-sectional view of the portion corresponding to the cross-sectional view taken along the line AA', and specifically, Fig. 11B yes Fig.11A The semiconductor device is along Fig.11A A cross-sectional view taken along line AA' of Fig. 12B yes Fig. 12A The semiconductor device is along Fig. 12A A cross-sectional view taken along line AA' of Fig. 15B yes Fig.15A The semiconductor device is along Fig.15A A cross-sectional view taken along line AA'. Fig. 16B , Fig. 17B , Fig.18B and Fig.19B They are Fig.16A , Fig.17A , Fig.18A and Fig.19A An enlarged cross-sectional view of the region EX1. FIG. 11A to FIG. 19B Describes the manufacturing Figures 1 to 4 The method of the semiconductor device 100 is shown in FIG. FIG. 11A to FIG. 19B In, with Figures 1 to 4The same reference numerals in the drawings respectively denote the same components, and repeated descriptions thereof are omitted here for the sake of brevity.

[0083] Reference Fig.11A and Fig. 11B , a plurality of peripheral circuits may be formed on the substrate 102, thereby forming a peripheral circuit structure PCA on the substrate 102, the plurality of peripheral circuits including a plurality of core circuits 104, a plurality of conductive plugs P1, P2 and P3, and a plurality of wiring layers M1 and M2. Next, an interlayer dielectric 106F may be formed on the peripheral circuit structure PCA (see Figure 3 ) and a plurality of shielding structures SL each passing through the interlayer dielectric 106F, then an interlayer dielectric 106G is formed to cover the interlayer dielectric 106F and the plurality of shielding structures SL, and thereafter, a plurality of bit lines BL may be formed passing through the interlayer dielectrics 106F and 106G (see Figure 3 ).

[0084] Next, a lower mold pattern 110A, a first mold insulating pattern 110B, and a second mold insulating pattern 110C may be formed in this order on the plurality of bit lines BL, thereby forming the mold insulating pattern 110 .

[0085] Reference Fig. 12A and Fig. 12B , a plurality of openings 110H may be formed in the mold insulating pattern 110. Some regions of each of the plurality of bit lines BL may be exposed through the plurality of openings 110H. Each of the plurality of openings 110H formed in the mold insulating pattern 110 may provide a transistor region TRR (see Figure 1 ).

[0086] Reference Fig.13 , the initial channel layer 120L may be formed to conformally cover the surfaces exposed in the plurality of openings 110H formed in the mold insulating pattern 110. In some embodiments, the initial channel layer 120L may include an oxide semiconductor layer. The oxide semiconductor layer may include IGZO, Sn-IGZO, IWO, IZO, ZTO, ZnO, YZO, IGSO, InO, SnO, TiO, ZnON, MgZnO, ZrInZnO, HfInZnO, SnInZnO, SiInZnO, GaZnSnO, ZrZnSnO, or a combination thereof. For example, in an embodiment, the initial channel layer 120L may include IGZO. In some embodiments, the initial channel layer 120L may include Si, Ge, SiGe, a II IV group compound semiconductor, or a combination thereof. The II IV group compound semiconductor may include, but is not limited to, GaAs or InSb.

[0087] In some embodiments, the preliminary channel layer 120L may be formed by at least one of a chemical vapor deposition (CVD) process, a low pressure CVD process, a plasma enhanced CVD process, a metal organic CVD (MOCVD) process, and an atomic layer deposition (ALD) process. In some embodiments, the preliminary channel layer 120L may have a thickness of, but is not limited to, about 1 nm to about 50 nm.

[0088] Reference Fig.14 ,exist Fig.13 In the resultant product, a sacrificial pattern SM1 may be formed to cover the preliminary channel layer 120L, and then the preliminary channel layer 120L is etched by using the sacrificial pattern SM1 as an etch mask, thereby dividing the preliminary channel layer 120L into a plurality of channel layers 120 .

[0089] Reference Fig.15A and Fig. 15B , can be obtained by Fig.14 The sacrificial pattern SM1 is removed from the resulting product to expose the upper surface of each of the plurality of channel layers 120 , and thereafter, a plurality of gate dielectric films 130 and a plurality of word lines WL may be respectively formed in the plurality of openings 110H of the mold insulating pattern 110 to sequentially cover the plurality of channel layers 120 in the order described.

[0090] In some embodiments, to form a plurality of gate dielectric films 130 and a plurality of word lines WL, the gate dielectric film 130 may be first formed to conformally cover the exposed surface of each of the interlayer dielectric 106G and the plurality of channel layers 120, and thereafter, the plurality of word lines WL may be formed on the gate dielectric film 130. During the process of forming the plurality of word lines WL, a portion of the gate dielectric film 130 between two word lines WL in the opening 110H may be removed. The upper surface of the channel layer 120 may be exposed between the two word lines WL in the opening 110H.

[0091] Next, a lower insulating liner 142 and an upper insulating partition wall 144 may be sequentially formed on the two word lines WL in the opening 110H in the order of the lower insulating liner 142 and the upper insulating partition wall 144. After the upper insulating partition wall 144 is formed, respective upper surfaces of the channel layer 120, the gate dielectric film 130, the lower insulating liner 142, the upper insulating partition wall 144, and the mold insulating pattern 110 may form one flat surface.

[0092] Reference Fig.16A and Fig. 16B ,exist Fig.15A and Fig. 15BIn the resulting product, each of the plurality of channel layers 120 may be partially removed from the upper surface of each of the plurality of channel layers 120, thereby reducing the height of each of the plurality of channel layers 120, and a plurality of contact spaces CTH may be formed to expose the upper surfaces of the plurality of channel layers 120, respectively. During the formation of the plurality of contact spaces CTH, a portion of the gate dielectric film 130 and a portion of the mold insulating pattern 110 exposed when the channel layer 120 is removed may also be removed together with the channel layer 120. As a result, the width of each of the plurality of contact spaces CTH in the second horizontal direction (Y direction) may be greater than the width of the channel layer 120, and the word line WL adjacent to the channel layer 120 may be exposed through the contact space CTH. During the formation of the plurality of contact spaces CTH, in order to remove a portion of each of the plurality of channel layers 120 from the upper surface of each of the plurality of channel layers 120 and form the plurality of contact spaces CTH, a process including a wet process, a dry process, or a combination thereof may be used. For example, in order to remove a portion of each of the plurality of channel layers 120 from an upper surface of each of the plurality of channel layers 120 and form a plurality of contact spaces CTH, a wet process may be used.

[0093] Reference Fig.17A and Fig. 17B , you can Fig.16A and Fig. 16B An insulating spacer layer 148L is formed on the resulting product to conformally cover Fig.16A and Fig. 16B The exposed surface of the resulting product. The insulating spacer layer 148L may include silicon oxide, silicon nitride, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, or a combination thereof. To form the insulating spacer layer 148L, an ALD process may be used.

[0094] Reference Fig.18A and Fig.18B ,exist Fig.17A and Fig. 17B In the resulting product, the insulating spacer layer 148L may be anisotropically etched, thereby exposing the upper surface of each of the plurality of channel layers 120 in the plurality of contact spaces CTH, and a plurality of insulating spacers 148 may be formed by the insulating spacer layer 148L to respectively cover the inner sidewalls of the plurality of contact spaces CTH. After forming the plurality of insulating spacers 148, the word line WL in each of the plurality of contact spaces CTH may be covered by the insulating spacer 148 so that the word line WL is not exposed by the contact space CTH.

[0095] Reference Fig.19A and Fig.19B, a plurality of conductive contact patterns 150 may be formed to fill the plurality of contact spaces CTH respectively. In order to form the plurality of conductive contact patterns 150, a plurality of conductive contact patterns 150 may be formed to fill the plurality of contact spaces CTH respectively. Fig.18A and Fig.18B A conductive layer is formed on the resulting product, and portions of the conductive layer outside the plurality of contact spaces CTH may be removed.

[0096] The conductive layer may include Ti, TiN, Ta, TaN, Mo, Ru, W, WN, TiSiN, WSiN, Ni, Ru, or a combination thereof. For example, the conductive layer may have a stacked structure of a conductive barrier film including TiN and a conductive film including W.

[0097] Next, if Figures 1 to 4 As shown, an isolation insulating film 160 and a plurality of conductive landing pads LP may be formed on the resultant product having the plurality of conductive contact patterns 150 formed thereon, each of the plurality of conductive landing pads LP passing through the isolation insulating film 160 in the vertical direction (Z direction). Figure 2 and Figure 3 As shown, an etch stop film 162 and an interlayer dielectric 170 may be formed on or over the resulting product having the plurality of conductive landing pads LP formed thereon, and then a plurality of capacitor structures CAP may be formed to be connected to the plurality of conductive contact patterns 150 through the etch stop film 162 and the interlayer dielectric 170, respectively, thereby manufacturing Figures 1 to 4 The semiconductor device 100 shown in FIG.

[0098] FIG. 20A to FIG. 24B are diagrams respectively illustrating the process sequence of a method for manufacturing a semiconductor device according to some embodiments. More specifically, Fig. 20A , Fig.21A , Fig.22A , Fig.23A and Fig.24A are each showing a semiconductor device according to a process sequence and along Figure 1 A cross-sectional view of a portion corresponding to a cross-sectional view taken along line AA', and Fig. 20B , Fig.21B , Fig. 22B , Fig. 23B and Fig. 24B They are Fig. 20A , Fig.21A , Fig.22A , Fig.23A and Fig.24A An enlarged cross-sectional view of the region EX2. FIG. 20A to FIG. 24B Describes the manufacturing Figure 5 and Figure 6 The method of the semiconductor device 200 shown in FIG. Figures 20A to 24B In, with Figures 1 to 19BThe same reference numerals in the drawings respectively denote the same components, and repeated descriptions thereof are omitted here for the sake of brevity.

[0099] Reference Fig. 20A and Fig. 20B , you can execute the reference FIG. 11A to FIG. 16B Next, you can Fig.16A and Fig. 16B A first mask pattern MP21 is formed on the resultant product. The first mask pattern MP21 may be formed to fill a plurality of contact spaces CTH (see Fig.16A and Fig. 16B ) adjacent to the word line WL of each of the lower insulating liner 142, the upper insulating partition wall 144, and the mold insulating pattern 110, and covers the upper surface of each of the lower insulating liner 142, the upper insulating partition wall 144, and the mold insulating pattern 110. The first mask pattern MP21 may have a plurality of openings H21 respectively connected to the plurality of contact spaces CTH. The first mask pattern MP21 may include a plurality of hard mask patterns each including a silicon oxide film, a silicon nitride film, or a combination thereof.

[0100] Next, portions of the mold insulating pattern 110 exposed by the plurality of openings H21 and the plurality of contact spaces CTH in the first mask pattern MP21 may be removed by an anisotropic dry etching process using the first mask pattern MP21 as an etching mask, thereby forming a plurality of expanded contact spaces CTH2 from the plurality of contact spaces CTH. Here, in order to form the plurality of expanded contact spaces CTH2, only the second mold insulating pattern 110C of the first mold insulating pattern 110B and the second mold insulating pattern 110C included in the mold insulating pattern 110 may be selectively removed.

[0101] Reference Fig.21A and Fig.21B , can be obtained from Fig. 20A and Fig. 20B The first mask pattern MP21 is removed from the resulting product, and then, the first mask pattern MP21 can be removed from the first mask pattern MP21 by Fig.17A and Fig. 17B The insulating spacer layer 248L is formed on the resultant product obtained after removing the first mask pattern MP21 in a similar manner to the method of forming the insulating spacer layer 148L described above. The constituent material of the insulating spacer layer 248L is the same as that already described with reference to Fig.17A and Fig. 17B The constituent materials of the insulating spacer layer 148L described are substantially the same.

[0102] Reference Fig.22A and Fig. 22B, a second mask pattern MP22 may be formed on the resulting product formed with the insulating spacer layer 248L. The second mask pattern MP22 may be formed on the insulating spacer layer 248L to fill a portion of each of the plurality of expanded contact spaces CTH2 adjacent to the word line WL and cover an upper surface of each of the lower insulating liner 142 and the upper insulating partition wall 144. Portions of the insulating spacer layer 248L located in the plurality of expanded contact spaces CTH2 and portions of the insulating spacer layer 248L covering the upper surface of the mold insulating pattern 110 may be exposed by the second mask pattern MP22.

[0103] Reference Fig.23A and Fig. 23B By using the second mask pattern MP22 as an etching mask, Fig.21A and Fig.21B The exposed portion of the insulating spacer layer 248L is removed from the resulting product. Next, the second mask pattern MP22 may be removed. Fig.23A and Fig. 23B In a resultant product, the word line WL in each of the plurality of expanded contact spaces CTH2 may be covered by the insulating spacer layer 248L so that the word line WL is not exposed by each of the plurality of expanded contact spaces CTH2.

[0104] Reference Fig.24A and Fig. 24B ,exist Fig.23A and Fig. 23B The obtained product is obtained by comparing with the reference Fig.19A and Fig.19B A plurality of conductive contact patterns 250 may be formed to fill the plurality of expanded contact spaces CTH2, respectively, in a similar manner to that described with respect to forming the plurality of conductive contact patterns 250. During the formation of the plurality of conductive contact patterns 250, portions of the insulating spacer layer 248L covering respective upper surfaces of the lower insulating liner 142 and the upper insulating partition wall 144 may be removed, and as a result, a plurality of insulating spacers 248 may be obtained, respectively, from portions of the insulating spacer layer 248L located in the plurality of expanded contact spaces CTH2.

[0105] After forming the plurality of conductive contact patterns 250 , a structure in which the upper surface of the mold insulating pattern 110 is exposed and the insulating spacer 248 is disposed between the conductive contact pattern 250 and the word line WL may be obtained.

[0106] Next, if Figures 5 and 6 As shown in , an isolation insulating film 160 and a plurality of conductive landing pads LP each passing through the isolation insulating film 160 in a vertical direction (Z direction) may be formed on the resultant product having the plurality of conductive contact patterns 250 formed thereon. Figure 5As shown in FIG. 1 , an etch stop film 162 and an interlayer dielectric 170 may be formed on or over the resulting product having the plurality of conductive landing pads LP formed thereon, and then a plurality of capacitor structures CAP may be formed to be connected to the plurality of conductive contact patterns 250 through the etch stop film 162 and the interlayer dielectric 170, respectively, thereby manufacturing Figure 5 and Figure 6 The semiconductor device 200 shown in FIG.

[0107] To manufacture Figure 7 The semiconductor device 200A shown in FIG. 1 can be implemented as described with reference to FIG. FIG. 20A to FIG. 24B However, in reference to Fig. 20A and Fig. 20B In the described process, when the portions of the mold insulating pattern 110 exposed by the plurality of openings H21 and the plurality of contact spaces CTH in the first mask pattern MP21 are removed by the anisotropic dry etching process, the second mold insulating pattern 110C and the first mold insulating pattern 110B of the mold insulating pattern 110 may be partially etched, thereby forming an enlarged contact space having a length greater than that of the enlarged contact space CTH2 in the vertical direction (Z direction). Next, the same method as in reference may be performed. FIG. 21A to FIG. 24B A process similar to the one described.

[0108] Fig.25A and Fig.25B are diagrams respectively illustrating the process sequence of a method for manufacturing a semiconductor device according to some embodiments. More specifically, Fig.25A is a diagram showing the relationship between the semiconductor device and the Figure 1 The cross-section taken along the line AA' corresponds to a cross-sectional view of some processes of the part, and Fig.25B yes Fig.25A An enlarged cross-sectional view of the region EX3. Fig.25A and Fig.25B Describes the manufacturing Figure 8 and Fig. 9 The method of the semiconductor device 300 shown in FIG. Fig.25A and Fig.25B In, with Figures 1 to 24B The same reference numerals in the drawings respectively denote the same components, and here, repeated description thereof is omitted.

[0109] Reference Fig.25A and Fig.25B , in the implementation of the reference FIG. 11A to FIG. 16B After the process described, you can Fig. 20A and Fig. 20B The same method described in Fig.16A and Fig. 16B A first mask pattern MP21 is formed on the resultant product.

[0110] Next, portions of the mold insulating pattern 110 exposed by the plurality of openings H21 and the plurality of contact spaces CTH in the first mask pattern MP21 may be removed by an isotropic wet etching process, thereby forming a plurality of expanded contact spaces CTH3 from the plurality of contact spaces CTH. Here, in order to form the plurality of expanded contact spaces CTH3, only the first mold insulating pattern 110B and the second mold insulating pattern 110C of the mold insulating pattern 110 may be selectively removed.

[0111] Next, you can Fig.25A and Fig.25B The obtained product is executed with reference to FIG. 21A to FIG. 24B Described process, thereby manufacturing Figure 8 and Fig. 9 The semiconductor device 300 shown in FIG.

[0112] To manufacture Fig.10 The semiconductor device 300A shown in FIG. 1 can be implemented as described with reference to FIG. Fig.25A and Fig.25B However, when the portions of the mold insulating pattern 110 exposed by the plurality of openings H21 and the plurality of contact spaces CTH in the first mask pattern MP21 are removed by the isotropic wet etching process, the second mold insulating pattern 110C and the first mold insulating pattern 110B of the mold insulating pattern 110 may be partially etched, thereby forming an enlarged contact space having a length greater than that of the enlarged contact space CTH3 in the vertical direction (Z direction). Next, the same process as in reference may be performed. FIG. 21A to FIG. 24B A process similar to the one described.

[0113] So far, although reference has been made to FIG. 11A to FIG. 25B Describes the manufacturing Figures 1 to 10 The examples of the semiconductor devices 100, 200, 200A, 300 and methods of 300A are shown in the drawings, but without departing from the spirit and scope of the present disclosure and the appended claims, the same may be referred to by reference. FIG. 11A to FIG. 25B Various modifications and changes to the described examples can be made to produce Figures 1 to 10 The semiconductor devices 100 , 200 , 200A, 300 , and 300A shown in the drawings are semiconductor devices of various structures modified and changed.

[0114] Although various embodiments have been particularly shown and described with reference to the accompanying drawings, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device comprising: an upper conductive line extending in a first horizontal direction above the substrate; a channel layer facing the upper conductive line in a second horizontal direction perpendicular to the first horizontal direction; a gate dielectric film disposed between the channel layer and the upper conductive line; a conductive contact pattern including a lower surface and a sidewall, the lower surface being in contact with the upper surface of the channel layer, the sidewall including a first sidewall facing the upper conductive line in the second horizontal direction; as well as An insulating spacer includes a first portion located between the upper conductive line and the conductive contact pattern in the second horizontal direction.

2. The semiconductor device according to claim 1, wherein The sidewall of the conductive contact pattern further includes a second sidewall located on a side opposite to the first sidewall in the second horizontal direction, and The insulating spacer surrounds the sidewall of the conductive contact pattern such that the insulating spacer contacts each of the first sidewall and the second sidewall of the conductive contact pattern.

3. The semiconductor device according to claim 1, wherein The sidewall of the conductive contact pattern further includes a second sidewall located on a side opposite to the first sidewall in the second horizontal direction, and The insulating spacer surrounds only some of the sidewalls of the conductive contact pattern such that the insulating spacer contacts the first sidewall of the conductive contact pattern and does not contact the second sidewall of the conductive contact pattern.

4. The semiconductor device according to claim 1, wherein The insulating spacer also includes a second portion located between the gate dielectric film and the conductive contact pattern.

5. The semiconductor device according to claim 1, wherein The conductive contact pattern also includes a surface in contact with a sidewall of the channel layer.

6. The semiconductor device according to claim 1, further comprising a mold insulation pattern disposed over the substrate and defining a transistor region, in, The channel layer includes a vertical channel portion that contacts the mold insulation pattern and extends in a vertical direction in the transistor region, and The conductive contact pattern is spaced apart from the mold insulating pattern in the second horizontal direction with the insulating spacer therebetween.

7. The semiconductor device according to claim 1, further comprising a mold insulation pattern disposed over the substrate and defining a transistor region, in, The channel layer includes a vertical channel portion that contacts the mold insulation pattern and extends in a vertical direction in the transistor region, and The conductive contact pattern contacts the mold insulation pattern.

8. The semiconductor device according to claim 1, further comprising a mold insulation pattern disposed over the substrate and defining a transistor region, in, A sidewall of the sidewalls of the conductive contact pattern facing the mold insulating pattern includes a curved surface convex toward the mold insulating pattern.

9. The semiconductor device according to claim 1, further comprising a mold insulation pattern disposed over the substrate and defining a transistor region, in, The mold insulating pattern includes a first mold insulating pattern and a second mold insulating pattern which are sequentially stacked in a vertical direction and include materials different from each other, and The conductive contact pattern contacts each of the first mold insulating pattern and the second mold insulating pattern.

10. The semiconductor device according to claim 1, wherein The channel layer includes InGaZnO, Sn-IGZO, InWO, InZnO, ZnSnO, ZnO, yttrium-doped zinc oxide, InGaSiO, InO, SnO, TiO, ZnON, MgZnO, ZrInZnO, HfInZnO, SnInZnO, SiInZnO, GaZnSnO, ZrZnSnO, Si, Ge, SiGe, III-V compound semiconductors, or combinations thereof.

11. The semiconductor device according to claim 1, wherein The insulating spacer includes silicon oxide, silicon nitride, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, or a combination thereof.

12. The semiconductor device according to claim 1, wherein The conductive contact pattern includes Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, Ni, Ru, or a combination thereof.

13. A semiconductor device comprising: a plurality of lower conductive lines arranged parallel to each other above the substrate; a mold insulation pattern disposed on the plurality of lower conductive lines and defining a transistor region extending in a first horizontal direction; a plurality of channel layers arranged in a row along the first horizontal direction in the transistor region, each of the plurality of channel layers including a vertical channel portion facing a sidewall of the mold insulation pattern; a plurality of upper conductive lines, the plurality of upper conductive lines being respectively arranged above the plurality of channel layers, each of the plurality of upper conductive lines having a sidewall facing a vertical channel portion of a corresponding channel layer of the plurality of channel layers; a plurality of gate dielectric films, the plurality of gate dielectric films being respectively located between the plurality of channel layers and the plurality of upper conductive lines; a plurality of conductive contact patterns connected to vertical channel portions of corresponding channel layers among the plurality of channel layers; as well as a plurality of insulating spacers, the plurality of insulating spacers being respectively on the plurality of gate dielectric films, wherein each of the plurality of conductive contact patterns comprises a lower surface and a first side wall, the lower surface contacts an upper surface of the vertical channel portion, the first side wall faces a corresponding upper conductive line of the plurality of upper conductive lines in a second horizontal direction perpendicular to the first horizontal direction, and Each of the plurality of insulating spacers includes a first portion located between a corresponding upper conductive line of the plurality of upper conductive lines and a corresponding conductive contact pattern of the plurality of conductive contact patterns in the second horizontal direction.

14. The semiconductor device according to claim 13, wherein: Each of the plurality of insulating spacers further includes a second portion located between the corresponding conductive contact pattern and the mold insulating pattern in the second horizontal direction.

15. The semiconductor device according to claim 13, wherein: Each of the plurality of insulating spacers is not disposed between the corresponding conductive contact pattern and the mold insulating pattern in the second horizontal direction.

16. The semiconductor device according to claim 13, wherein: Each of the plurality of conductive contact patterns contacts an upper surface and a sidewall of the corresponding channel layer.

17. The semiconductor device according to claim 13, wherein: Each of the plurality of conductive contact patterns includes a first portion contacting a corresponding insulating spacer and a second portion contacting the mold insulating pattern, In each of the plurality of conductive contact patterns, a vertical length of the first portion is smaller than a vertical length of the second portion, and A vertical length of each of the plurality of insulating spacers is smaller than a vertical length of the second portion of each of the plurality of conductive contact patterns.

18. A semiconductor device comprising: a peripheral circuit region arranged on the substrate and including a plurality of peripheral circuits; a lower conductive line disposed on the peripheral circuit region and connected to the plurality of peripheral circuits; a molded insulating pattern disposed on the lower conductive line and having a sidewall defining a transistor region; a channel layer disposed in the transistor region and including an oxide semiconductor layer, the channel layer having a lower surface in contact with an upper surface of the lower conductive line and a vertical channel portion facing a sidewall of the mold insulating pattern; a gate dielectric film covering the channel layer in the transistor region; an upper conductive line disposed on the gate dielectric film in the transistor region and having a sidewall facing the vertical channel portion, the upper conductive line extending in a first horizontal direction; a conductive contact pattern including a lower surface and a first side wall, the lower surface being in contact with an upper surface of the channel layer, the first side wall facing the upper conductive line in a second horizontal direction perpendicular to the first horizontal direction, and An insulating spacer includes a first portion located between the upper conductive line and the conductive contact pattern in the second horizontal direction.

19. The semiconductor device according to claim 18, wherein: The conductive contact pattern further includes a surface in contact with a sidewall of the channel layer, and The channel layer includes InGaZnO, Sn-IGZO, InWO, InZnO, ZnSnO, ZnO, yttrium-doped zinc oxide, InGaSiO, InO, SnO, TiO, ZnON, MgZnO, ZrInZnO, HfInZnO, SnInZnO, Si InZnO, GaZnSnO, ZrZnSnO, Si, Ge, SiGe, III-V compound semiconductors, or combinations thereof.

20. The semiconductor device according to claim 18, wherein The conductive contact pattern further includes a surface in contact with a sidewall of the channel layer, and The insulating spacer includes silicon oxide, silicon nitride, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, or a combination thereof.

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