Chip, chip design method, manufacturing method and device

Abstract

The embodiment of the invention discloses a chip, a chip design method, a chip manufacturing method and a chip device, relates to the field of integrated circuits, and can improve the utilization rate of a chip main body structure on the chip area while ensuring that a test structure of a three-dimensional integrated chip is set. The chip comprises a main body structure and a test structure, the main body structure and the test structure are distributed in a plurality of crystal grains of a to-be-designed chip, the plurality of crystal grains comprise first crystal grains and second crystal grains, and the first crystal grains and the second crystal grains are used for being stacked, mixed and bonded with each other to form a bonded crystal grain group; the test structure comprises at least two key components; the preset position of the bonding crystal grain group is provided with at least one part of elements of the main body structure, and the preset position comprises at least one of the following items: the projection coverage area of at least one key component along the first direction; the distance between the position and the edge of at least one key assembly or the distance between the position and the edge of the projection coverage area of the key assembly in the first direction is smaller than a preset distance threshold value.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular to a chip, a chip design method, a chip manufacturing method and a device. Background Art

[0002] WAT (Wafer Acceptance Test) is a test of the electrical parameters of specific test structures on the wafer after the wafer product is taped out to determine whether the wafer product meets the electrical specification requirements of the process technology platform. The WAT data can be used as a quality certificate for wafer product delivery.

[0003] For traditional two-dimensional integrated chips, the test structure required for WAT is generally made on the cutting paths between the grains. Similarly, for chips that are three-dimensionally integrated by W2W (wafer to wafer) bonding, since the shapes and sizes of the grains (such as the top grain and the bottom grain) in the same chip are the same, the cutting paths of the grains are also completely corresponding, so the test structure of the three-dimensional WAT can also be made on the cutting paths. For chips that are three-dimensionally integrated by C2W (chip to wafer) bonding, since the shapes and sizes of the grains in the same chip are not exactly the same, for example, the top grain is smaller than the bottom grain, there are cutting paths on the bottom wafer, but there are no corresponding cutting paths in the top grain, that is, there is no suitable setting space for the test structure of the three-dimensional WAT on the cutting paths. For this reason, in the related art, part of the area on the chip is often divided for setting the test structure of the three-dimensional WAT, instead of setting the test structure on the cutting path. However, since the chip is mainly used to manufacture its main structure to realize the preset chip function, setting the test structure on the chip will occupy a certain chip area, thereby reducing the utilization rate of the main structure to the chip area. Summary of the invention

[0004] In view of this, the embodiments of the present invention provide a chip, a chip design method, a manufacturing method and an apparatus, which can effectively improve the chip area utilization of the chip main structure while ensuring that the test structure of the three-dimensional integrated chip is effectively set.

[0005] In a first aspect, an embodiment of the present invention provides a chip, comprising: a main structure and a test structure, wherein the main structure and the test structure are distributed in a plurality of grains of the chip to be designed, and there is no electrical connection between the main structure and the test structure, and the plurality of grains include a first grain and a second grain, and the first grain and the second grain are used to stack and hybrid bond with each other to form a bonded grain group; the main structure is used to implement a preset circuit function; the test structure is used to test preset electrical parameters of the bonded grain group, and the preset electrical parameters include electrical parameters related to the interconnection characteristics between the first grain and the second grain; the test structure includes at least two key components; at least a part of the elements of the main structure are arranged at a preset position of the bonded grain group, and the preset position includes at least one of the following: the projection coverage of at least one of the key components along the first direction; the position where the distance from the edge of at least one of the key components or the distance from the edge of the projection coverage of the key component along the first direction is less than a preset distance threshold; wherein the first direction is the stacking direction of the first grain and the second grain.

[0006] In one embodiment, each grain in the bonded grain group includes a plurality of structural layers stacked along the first direction, each of the key components is arranged in one or more of the structural layers, and the preset position includes at least one of the following: at least one of the key components is within the projection coverage range on any of the structural layers; a position in any of the structural layers at a distance from an edge of at least one of the key components being less than a preset distance threshold; a position in any of the structural layers at a distance from an edge of the projection coverage range of at least one of the key components along the first direction being less than a preset distance threshold.

[0007] In one embodiment, the types of the key components include at least one of the following: a test pad, a first metal pattern, a through silicon via, a second metal pattern, a hybrid bonding structure, and a third metal pattern; and the number of the key components of each type is one or more.

[0008] In one embodiment, the test pad is arranged on the first surface of the first crystal grain; the first metal pattern is arranged on the first surface side of the first crystal grain and is located below the first surface; the through silicon via is arranged in the first crystal grain, corresponds to the first metal pattern one by one and is aligned in position, each of the through silicon vias extends from the second surface of the first crystal grain to the corresponding first metal pattern and is electrically connected to the first metal pattern, wherein the first surface is opposite to the second surface; the second metal pattern is arranged on the second surface of the first crystal grain for electrically connecting to the first end of the hybrid bonding structure; the hybrid bonding structure is arranged between the second surface of the first crystal grain and the second crystal grain; the third metal pattern is arranged on the surface of the second crystal grain opposite to the first crystal grain for electrically connecting to the second end of the hybrid bonding structure.

[0009] In one embodiment, the second metal pattern includes at least one target metal pattern, one end of each of the target metal patterns is electrically connected to one of the through silicon vias, and the other end is electrically connected to one of the hybrid bonding structures; the first metal pattern, the through silicon via, the target metal pattern, and the hybrid bonding structure that are electrically connected to each other are aligned with each other in the first direction.

[0010] In one embodiment, each of the test pads is arranged in a preset shape, which corresponds to an arrangement shape of probes in a probe card of a test device, and each of the test pads is used to be electrically connected to each of the probes on the probe card.

[0011] In one embodiment, each of the first metal patterns is electrically connected to one of the test pads, and the first metal patterns and the test pads that are electrically connected to each other are aligned with or not aligned with each other in the first direction.

[0012] In one implementation, the second metal pattern, the hybrid bonding structure, and the third metal pattern that are electrically connected to each other are aligned with each other in the first direction.

[0013] In a second aspect, an embodiment of the present invention further provides a chip design method, comprising: determining a main structure and a test structure of a chip to be designed, wherein the main structure and the test structure are distributed in a plurality of grains of the chip to be designed, and there is no electrical connection between the main structure and the test structure, and the plurality of grains include a first grain and a second grain, and the first grain and the second grain are used to be stacked and mixed-bonded with each other to form a bonded grain group; the main structure is used to realize a preset circuit function; the test structure is used to test preset electrical parameters of the bonded grain group, and the preset electrical parameters include the relationship between the first grain and the second grain. Electrical parameters related to interconnection characteristics; the test structure includes at least two key components; the test structure is designed in a design file corresponding to the bonded grain group, wherein the preset position of the bonded grain group is used to arrange at least a part of the elements of the main structure, and the preset position includes at least one of the following: a projection coverage of at least one of the key components along a first direction; a position where the distance from an edge of at least one of the key components or the distance from an edge of the projection coverage of the key component along the first direction is less than a preset distance threshold; wherein the first direction is a stacking direction of the first grain and the second grain.

[0014] In one embodiment, each grain in the bonded grain group includes a plurality of structural layers stacked along the first direction, each of the key components is arranged in one or more of the structural layers, and the preset position includes at least one of the following: at least one of the key components is within the projection coverage range on any of the structural layers; a position in any of the structural layers at a distance from an edge of at least one of the key components being less than a preset distance threshold; a position in any of the structural layers at a distance from an edge of the projection coverage range of at least one of the key components along the first direction being less than a preset distance threshold.

[0015] In one embodiment, the types of key components include at least one of the following: a test pad, a first metal pattern, a through silicon via, a second metal pattern, a hybrid bonding structure, and a third metal pattern; the number of the key components of each type is one or more; the test pad is arranged on the first surface of the first grain; the first metal pattern is arranged on the first surface side of the first grain and is located below the first surface; the through silicon via is arranged in the first grain, corresponds to the first metal pattern one by one and is aligned in position, each of the through silicon vias extends from the second surface of the first grain to the corresponding first metal pattern and is electrically connected to the first metal pattern, wherein the first surface is opposite to the second surface; the second metal pattern is arranged on the second surface of the first grain for electrically connecting to the first end of the hybrid bonding structure; the hybrid bonding structure is arranged between the second surface of the first grain and the second grain; the third metal pattern is arranged on the surface of the second grain opposite to the first grain for electrically connecting to the second end of the hybrid bonding structure.

[0016] In one embodiment, designing the test structure in the design file corresponding to the bonding grain group includes: designing the test pad, the first metal pattern, the through silicon via, the second metal pattern and the first pad corresponding to the hybrid bonding structure in the first design file, and designing the second pad corresponding to the hybrid bonding structure and the third metal pattern in the second design file; wherein the second metal pattern includes at least one target metal pattern, one end of each target metal pattern is electrically connected to a through silicon via, and the other end is electrically connected to a first pad corresponding to the hybrid bonding structure; the first metal pattern, the through silicon via, the target metal pattern, and the first pad corresponding to the hybrid bonding structure that are electrically connected to each other are aligned with each other in the first direction; the first pad corresponding to the hybrid bonding structure, the second pad corresponding to the hybrid bonding structure, and the third metal pattern are aligned with each other in the first direction.

[0017] In one embodiment, designing the test structure in the design file corresponding to the bonding grain group includes: designing the test pad and the first metal pattern in a third design file, designing the through silicon via, the second metal pattern, and the first pad and the second pad corresponding to the hybrid bonding structure in a fourth design file, and designing the third metal pattern in the fifth design file; wherein the second metal pattern includes at least one target metal pattern, one end of each target metal pattern is electrically connected to a through silicon via, and the other end is electrically connected to a first pad corresponding to the hybrid bonding structure; the first metal pattern, the through silicon via, the target metal pattern, and the first pad of the hybrid bonding structure that are electrically connected to each other are aligned with each other in the first direction; the first pad corresponding to the hybrid bonding structure, the second pad corresponding to the hybrid bonding structure, and the third metal pattern are aligned with each other in the first direction.

[0018] In one embodiment, after the test structure is designed in the design file corresponding to the bonded die group, the method further includes: adding a spare pad for the test structure in the design file corresponding to the bonded die group, and the spare pad is used to connect the first die or the second die to a probe card for testing before integrating the first die and the second die into the bonded die group.

[0019] In one embodiment, each of the test pads is arranged in a preset shape, which corresponds to an arrangement shape of probes in a probe card of a test device, and each of the test pads is used to be electrically connected to each of the probes on the probe card.

[0020] In one embodiment, each of the first metal patterns is electrically connected to one of the test pads, and the first metal patterns and the test pads that are electrically connected to each other are aligned with or not aligned with each other in the first direction.

[0021] In a third aspect, an embodiment of the present invention further provides a chip design device, comprising: a determination unit, for determining a main structure and a test structure of a chip to be designed, wherein the main structure and the test structure are distributed in a plurality of grains of the chip to be designed, and there is no electrical connection between the main structure and the test structure, and the plurality of grains include a first grain and a second grain, and the first grain and the second grain are used to be stacked and mixed-bonded with each other to form a bonded grain group; the main structure is used to implement a preset circuit function; the test structure is used to test preset electrical parameters of the bonded grain group, and the preset electrical parameters include the relationship between the first grain and the second grain. Electrical parameters related to interconnection characteristics; the test structure includes at least two key components; a design unit, used to design the test structure in a design file corresponding to the bonded grain group, wherein the preset position of the bonded grain group is used to arrange at least a part of the elements of the main structure, and the preset position includes at least one of the following: a projection coverage of at least one of the key components along a first direction; a position where the distance from the edge of at least one of the key components or the distance from the edge of the projection coverage of the key component along the first direction is less than a preset distance threshold; wherein the first direction is the stacking direction of the first grain and the second grain.

[0022] In a fourth aspect, an embodiment of the present invention further provides a chip manufacturing method, comprising: manufacturing a main structure and a test structure corresponding to a target chip in a plurality of grains respectively, wherein the main structure and the test structure have no electrical connection, wherein the plurality of grains include a first grain and a second grain, and the first grain and the second grain are used to be stacked and mixed-bonded with each other to form a bonded grain group; the main structure is used to implement a preset circuit function; the test structure is used to test preset electrical parameters of the bonded grain group, and the preset electrical parameters include electrical parameters related to the interconnection characteristics between the first grain and the second grain; the test structure includes to at least two key components; at least a part of the elements of the main structure are arranged at a preset position of the bonded grain group, and the preset position includes at least one of the following: a projection coverage of at least one of the key components along a first direction; a position where the distance to an edge of at least one of the key components or the distance to an edge of the projection coverage of the key component along the first direction is less than a preset distance threshold; wherein the first direction is a stacking direction of the first grain and the second grain; the first grain and the second grain are stacked and mixed-bonded to form the bonded grain group; and the target chip is formed based on the bonded grain group.

[0023] In one embodiment, each grain in the bonded grain group includes a plurality of structural layers stacked along the first direction, each of the key components is arranged in one or more of the structural layers, and the preset position includes at least one of the following: at least one of the key components is within the projection coverage range on any of the structural layers; a position in any of the structural layers at a distance from an edge of at least one of the key components being less than a preset distance threshold; a position in any of the structural layers at a distance from an edge of the projection coverage range of at least one of the key components along the first direction being less than a preset distance threshold.

[0024] In one embodiment, the types of key components include at least one of the following: a test pad, a first metal pattern, a through silicon via, a second metal pattern, a hybrid bonding structure, and a third metal pattern; the number of the key components of each type is one or more; the test pad is arranged on the first surface of the first grain; the first metal pattern is arranged on the first surface side of the first grain and is located below the first surface; the through silicon via is arranged in the first grain, corresponds to the first metal pattern one by one and is aligned in position, each of the through silicon vias extends from the second surface of the first grain to the corresponding first metal pattern and is electrically connected to the first metal pattern, wherein the first surface is opposite to the second surface; the second metal pattern is arranged on the second surface of the first grain for electrically connecting to the first end of the hybrid bonding structure; the hybrid bonding structure is arranged between the second surface of the first grain and the second grain; the third metal pattern is arranged on the surface of the second grain opposite to the first grain for electrically connecting to the second end of the hybrid bonding structure.

[0025] In one embodiment, the manufacturing of the main structure and the test structure corresponding to the target chip in multiple grains respectively includes: manufacturing the test pad, the first metal pattern, the silicon through via, the second metal pattern and the first pad corresponding to the hybrid bonding structure in the first grain, and manufacturing the second pad corresponding to the hybrid bonding structure and the third metal pattern in the second grain; wherein the second metal pattern includes at least one target metal pattern, one end of each target metal pattern is electrically connected to a silicon through via, and the other end is electrically connected to a first pad corresponding to the hybrid bonding structure; the first metal pattern, the silicon through via, the target metal pattern, and the first pad of the hybrid bonding structure that are electrically connected to each other are aligned with each other in the first direction; the first pad corresponding to the hybrid bonding structure, the second pad corresponding to the hybrid bonding structure, and the third metal pattern are aligned with each other in the first direction.

[0026] In one embodiment, stacking and hybrid bonding the first grain and the second grain to form the bonded grain group includes: stacking the first grain and the second grain, and hybrid bonding the first pad corresponding to the hybrid bonding structure in the first grain and the second pad corresponding to the hybrid bonding structure in the second grain to form the bonded grain group.

[0027] In one embodiment, after manufacturing the main structure and the test structure corresponding to the target chip in a plurality of grains respectively, before stacking and hybrid bonding the first grain and the second grain to form the bonded grain group, the method further includes: making spare pads for the test structure in the first grain and the second grain, and covering the test pads with a protective layer; electrically connecting the spare pads to a probe card to test the first grain and the second grain respectively to obtain the first grain and the second grain that pass the test; flattening the spare pads of the first grain and the second grain that pass the test; removing the protective layer of the test pads in the first grain and the second grain that pass the test to expose the test pads; stacking and hybrid bonding the first grain and the second grain to form the bonded grain group includes: stacking and hybrid bonding the first grain and the second grain that expose the test pads to form the bonded grain group.

[0028] In one embodiment, each of the test pads is arranged in a preset shape, which corresponds to an arrangement shape of probes in a probe card of a test device, and each of the test pads is used to be electrically connected to each of the probes on the probe card.

[0029] In one embodiment, each of the first metal patterns is electrically connected to one of the test pads, and the first metal patterns and the test pads that are electrically connected to each other are aligned with or not aligned with each other in the first direction.

[0030] In a fifth aspect, an embodiment of the present invention further provides an electronic device, comprising: a housing, a processor, a memory, a circuit board and a power supply circuit, wherein the circuit board is placed inside the space enclosed by the housing, and the processor and the memory are arranged on the circuit board; a power supply circuit is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, so as to execute the chip design method provided in any embodiment of the present invention.

[0031] In a sixth aspect, an embodiment of the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the chip design method provided by any embodiment of the present invention.

[0032] The embodiments of the present invention provide a chip, a chip design method, a manufacturing method and an apparatus, wherein the chip includes a main structure and a test structure, wherein the main structure and the test structure are distributed in multiple grains of the chip to be designed, wherein there is no electrical connection between the main structure and the test structure, wherein the multiple grains include a first grain and a second grain, wherein the first grain and the second grain are used to be stacked and mixedly bonded with each other to form a bonded grain group, wherein at least a portion of the elements of the main structure are arranged at a preset position of the bonded grain group, and the preset position includes at least one of the following: a projection coverage of at least one key component along a first direction; a position where the distance from an edge of at least one key component or a distance from an edge of the projection coverage of the key component along the first direction is less than a preset distance threshold; wherein the first direction is a stacking direction of the first grain and the second grain. In this way, on the one hand, the test structures are all located on the die rather than in the cutting lanes, thereby avoiding the situation in which there is nowhere to set up the test structures in C2W; on the other hand, at least a part of the elements of the main structure are set at the preset positions of the bonded die group, and these preset positions include at least one of the following: the projection coverage of at least one key component along the first direction; the position where the distance from the edge of at least one key component or the distance from the edge of the projection coverage of the key component along the first direction is less than a preset distance threshold. That is to say, in the chip provided by the embodiment of the present invention, the positions near the key components of the bonded grain group, or the positions within the projection coverage range of the key components in the first direction or near the projection coverage range, can allow for the setting of at least some elements of the main structure. The test structure is not like the prior art, which packages the key components into a whole, occupies a relatively complete space in the grain, and is clearly separated from the distribution area of ​​the main structure. Instead, the key components are separated so that at least some elements of the main structure can be arranged at the positions in the bonded grain group that are not occupied by the key components. In this way, the main structure can be arranged in a wider range, thereby effectively improving the utilization rate of the chip area by the chip main structure while ensuring that the test structure of the three-dimensional integrated chip is effectively set. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0034] Figure 1 A schematic diagram of the structure of a chip provided by an embodiment of the present invention; Figure 2 Another schematic diagram of the structure of a chip provided by an embodiment of the present invention; Figure 3 Another schematic diagram of the structure of a chip provided by an embodiment of the present invention; Figure 4 A schematic diagram of another structure of a chip provided by an embodiment of the present invention; Figure 5 A schematic diagram of the chip area that can be used by the main structure in the chip provided by the embodiment of the present invention; Figure 6 A schematic diagram of the chip area that can be used for the main structure in the prior art; Figure 7 A flow chart of a chip design method provided by an embodiment of the present invention; Figure 8 A schematic diagram of the structure of a chip design device provided by an embodiment of the present invention; Fig. 9 A flow chart of a chip manufacturing method provided by an embodiment of the present invention; Fig.10 A schematic structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0035] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0036] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0037] The embodiment of the present invention provides a chip design method, which can effectively improve the chip area utilization rate of the main structure of the chip while ensuring that the test structure of the three-dimensional integrated chip is effectively arranged.

[0038] like Figure 1 As shown, an embodiment of the present invention provides a chip, including: A main structure 1 and a test structure 2, wherein the main structure 1 and the test structure 2 are distributed in a plurality of crystal grains of the chip to be designed, the main structure 1 and the test structure 2 are not electrically connected, the plurality of crystal grains include a first crystal grain 31 and a second crystal grain 32, the first crystal grain 31 and the second crystal grain 32 are used to be stacked and hybrid-bonded to each other to form a bonded crystal grain group 30; The main structure 1 is used to realize a preset circuit function; the test structure 2 is used to test preset electrical parameters of the bonded die group 30, wherein the preset electrical parameters include electrical parameters related to the interconnection characteristics between the first die 31 and the second die 32; the test structure 2 includes at least two key components 20; The preset position of the bonded grain group 30 is provided with at least a portion of the elements of the main structure 1, and the preset position includes at least one of the following: the projection coverage of at least one key component 20 along the first direction; a position where the distance between the edge of at least one key component 20 or the distance between the edge of the projection coverage 21 of the key component 20 along the first direction is less than a preset distance threshold; wherein the first direction is the stacking direction of the first grain 31 and the second grain 32.

[0039] The chip provided by an embodiment of the present invention includes a main structure 1 and a test structure 2, the main structure 1 and the test structure 2 are distributed in multiple grains of the chip to be designed, there is no electrical connection between the main structure 1 and the test structure 2, the multiple grains include a first grain 31 and a second grain 32, the first grain 31 and the second grain 32 are used to stack and hybrid bond with each other to form a bonded grain group 30, and at least a part of the elements of the main structure 1 are set at a preset position of the bonded grain group 30, and the preset position includes at least one of the following: the projection coverage of at least one key component 20 along the first direction; the distance between the edge of at least one key component 20 or the distance between the edge of the projection coverage 201 of the key component 20 along the first direction is less than a preset distance threshold; wherein the first direction is the stacking direction of the first grain 31 and the second grain 32. In this way, on the one hand, the test structures 2 are all located on the die rather than in the cutting path, thereby avoiding the situation in which there is nowhere to set the test structure 2 in C2W; on the other hand, since at least a part of the elements of the main structure 1 are set at the preset positions of the bonding die group 30, and these preset positions include at least one of the following: the projection coverage of at least one key component 20 along the first direction; the distance between the edge of at least one key component 20 or the distance between the edge of the projection coverage 201 of the key component 20 along the first direction is less than a preset distance threshold. That is to say, in the chip provided by the embodiment of the present invention, the positions near the key components 20 of the bonded grain group 30, or the positions within the projection coverage range of the key components 20 in the first direction or near the projection coverage range, can allow for the setting of at least some elements in the main structure 1. The test structure 2 is not like the prior art, which packages the key components 20 into a whole, occupies a relatively complete space in the grain, and is clearly separated from the distribution area of ​​the main structure 1. Instead, the key components 20 are split apart so that at least some elements of the main structure 1 can be arranged at the positions in the bonded grain group 30 that are not occupied by the key components 20. In this way, the main structure can be arranged in a wider range, thereby effectively improving the utilization rate of the chip area by the chip main structure while ensuring that the test structure of the three-dimensional integrated chip is effectively set.

[0040] In the embodiment of the present invention, the main structure 1 may refer to a structure for realizing the main function of the chip. For example, the main structure 1 in the analog-to-digital conversion chip is a structure for realizing the analog-to-digital conversion function. The test structure 2 is irrelevant to the main function of the chip and is mainly used for testing. Specifically, in the embodiment of the present invention, the test structure 2 may be used to measure electrical parameters related to the interconnection characteristics between the first crystal grain 31 and the second crystal grain 32. For example, it may be used to measure the voltage, resistance, current, etc. between the first crystal grain 31 and the second crystal grain 32.

[0041] In one embodiment of the present invention, the main structure 1 and the test structure 2 can be distributed in multiple grains of the chip. Here, the multiple grains can include all the grains in the chip, that is, each grain of the chip is distributed with the main structure 1 and the test structure 2, or can include a part of the grains in the chip, that is, some grains in the chip are distributed with the main structure 1 and the test structure 2, and other grains may not be distributed with the main structure 1 or the test structure 2. The embodiment of the present invention is not limited to this. The multiple grains may include a first grain 31 and a second grain 32, and the first grain 31 and the second grain 32 can be used to stack and mix bond with each other to form a bonded grain group 30.

[0042] Specifically, in one embodiment of the present invention, each of the grains in the bonded grain group 30 may include a plurality of structural layers stacked along a first direction, such as a first metal layer, a first dielectric layer, etc., and each of the key components may be arranged in one or more of the structural layers. Based on this, the preset position may include one or more of the following: at least one key component 20 is within the projection coverage range on any structural layer; in any structural layer, the distance between the edge of at least one key component 20 is less than a preset distance threshold; in any structural layer, the distance between the edge of the projection coverage range of at least one key component 20 along the first direction is less than a preset distance threshold. In other words, the position of the key component arranged in each structural layer of the bonded grain group can be determined, so that the corresponding preset position can be further determined in each structural layer according to the distance between the edge of the key component. Alternatively, the projection coverage range of the key components on other structural layers on a certain structural layer can also be determined, so that the corresponding preset position can be further determined in the structural layer according to the distance between the edge of the projection coverage range of the key components.

[0043] Optional, such as Figure 2 As shown, in an embodiment of the present invention, the test structure 2 may include a variety of key components 20, and these key components 20 are related to the test of the interconnection characteristics of the first die 31 and the second die 32 in the bonded die group 30. For example, in an embodiment of the present invention, the types of key components 20 may include one or more of the following: test pads 21, first metal patterns 22, through silicon vias 23, second metal patterns 24, hybrid bonding structures 25, and third metal patterns 26; the number of each type of key components 20 may be one or more.

[0044] Specifically, the test pad 21 can be set on the first surface of the first grain 31; the first metal pattern 22 can be set on the first surface side of the first grain 31 and located below the first surface; the through silicon via 23 can be set on the first grain 31, corresponding to the first metal pattern 22 one by one and aligned in position, each through silicon via 23 can extend from the second surface of the first grain 31 to the corresponding first metal pattern 22, and be electrically connected to the first metal pattern 22, wherein the first surface is opposite to the second surface; the second metal pattern 24 is set on the second surface of the first grain 31, for being electrically connected to the first end of the hybrid bonding structure 25; the hybrid bonding structure 25 is set between the second surface of the first grain 31 and the second grain 32; the third metal pattern 26 is set on the surface of the second grain 32 opposite to the first grain 31, for being electrically connected to the second end of the hybrid bonding structure 25.

[0045] As mentioned above, the preset positions of the bonding die group 30 are provided with at least a part of the elements of the main structure 1, and these preset positions include at least one of the following: the projection coverage of at least one key component 20 along the first direction; the position where the distance from the edge of at least one key component 20 or the distance from the edge 22 of the projection coverage 21 of the key component 20 along the first direction is less than the preset distance threshold, and the test pad 21, the first metal pattern 22, the silicon through via 23, the second metal pattern 24, the hybrid bonding structure 25, and the third metal pattern 26 are all key components 20, that is, the test pad 21, the first metal pattern 22, the silicon through via 23, the second metal pattern 24, the hybrid bonding structure 25, the third metal pattern 26 and other key components 20 along the first direction The coverage, or the distance from the edge of at least one key component 20 or the distance from the edge 22 of the projection coverage 21 of the key component 20 along the first direction is less than the preset distance threshold, all allow the layout of at least some elements of the main structure 1. For example, Figure 3 As shown, in an example, the standard cells in the main structure 1 can be deployed within the projection coverage 201 of a first metal pattern 221 in the first direction, the standard cells can be arranged in the blank positions between the through silicon vias 231 and 232, and the metal wires of the main structure 1 can be arranged between the test pads 211 and 212.

[0046] Exemplarily, in one embodiment of the present invention, the first metal pattern 22 may be the top metal of the first crystal grain 31. If, during the manufacturing process of the first crystal grain 31, the through silicon via 23 is formed from the second surface (i.e., the back side) of the first crystal grain 31, the first metal pattern 22 may serve as the landing metal (TSV landing metal) of the through silicon via 23, i.e., the through silicon via 22 extends from the second surface 312 of the first crystal grain 31 to the corresponding first metal pattern 22 and stops, and is electrically connected to the first metal pattern 22.

[0047] The second metal pattern 24 may be the back metal of the first crystal grain 31, and the second metal pattern 24 may be electrically connected to the hybrid bonding structure 25. The hybrid bonding structure 25 is connected between the first crystal grain 31 and the second crystal grain 32, and the first crystal grain 31 and the second crystal grain 32 may be interconnected. In one embodiment of the present invention, a first pad corresponding to the hybrid bonding structure 25 may be provided on the first crystal grain 31, and a second pad corresponding to the hybrid bonding structure 25 may be provided on the second crystal grain 32. The first pad and the second pad may be fused with each other when the first crystal grain 31 and the second crystal grain 32 are hybrid bonded to form the hybrid bonding structure 25.

[0048] like Figure 4 As shown, in one embodiment of the present invention, the second metal pattern 24 may include one or more target metal patterns 240, one end of each target metal pattern 240 is electrically connected to a through silicon via 23, and the other end is electrically connected to a hybrid bonding structure 25; the first metal pattern 22, the through silicon via 23, the target metal pattern 240, and the hybrid bonding structure 25 that are electrically connected to each other are aligned with each other in a first direction, so that the target metal pattern 240 can introduce the electrical signal in the first surface of the first grain 31 into the second surface of the first grain 31 through the through silicon via 23, and further transmit the electrical signal to the second grain 32 through the hybrid bonding structure 25, thereby realizing the interconnection between the first grain 31 and the second grain 32.

[0049] In an embodiment of the present invention, each test pad 21 on the first die 31 can be arranged in a preset shape, and the preset shape can correspond to the arrangement shape of the probes in the probe card of the test device, and each of the test pads is used to be electrically connected to each of the probes on the probe card. For example, in one example, the arrangement shape of the probes in the probe card of the test device is a row, and the preset shape can also be a row. In another example, the arrangement shape of the probes in the probe card of the test device is an array, and the preset shape can also be an array, so that it can be conveniently electrically connected to the probe card of the test device to implement the test.

[0050] In an embodiment of the present invention, the test pad 21 is a key component 20, and the arrangement shape of the test pad 21 can correspond to the arrangement shape of the probe in the probe card. Since the key components 20 in the test structure 2 are relatively independent, and the interconnection relationship between the test pad 21 itself and the grain is not close, the arrangement shape of other key components 20 except the test pad 21 can be relatively freely set, and can be free from the constraints of the distribution position of the test pad 21, so that the test structure can be more flexibly distributed in the chip, so that the layout of the main structure can be effectively avoided, and the utilization rate of the chip area by the main structure is further improved. Specifically, in one embodiment of the present invention, each first metal pattern 22 is electrically connected to a test pad 21, and the first metal pattern 22 and the test pad 21 electrically connected to each other can be aligned with each other or not aligned with each other in the first direction. Based on this, in one example, in one or more structural layers of the bonding grain group 30, the test pad 211 may not have any elements of the test structure 2 within the projection coverage range of the first direction, and accordingly, some elements of the main structure 1 can be arranged within the projection range.

[0051] For example, the chip area available for the main structure 1 in the chip provided by the embodiment of the present invention can be as follows: Figure 5 As shown. In the prior art, the chip area available for the main structure 1 can be as follows: Figure 6 As shown. Figure 5 and Figure 6 In the figure, the part inside the dotted box is occupied by the test structure 2, and the main structure 1 cannot be used. The part outside the dotted box is not occupied by the test structure 2, and the main structure 1 can be used. Figure 5 and Figure 6 It can be seen that in the chip provided by the embodiment of the present invention, the chip area that can be used by the main structure 1 is greatly increased.

[0052] In an embodiment of the present invention, one end of the first metal pattern 22 can be electrically connected to the test pad 21, and the other end can be electrically connected to the through silicon via 23. The end of the first metal pattern 22 electrically connected to each other can be aligned with the test pad 21 or not, and the first metal pattern 22, through silicon via 23, and target metal pattern 240 electrically connected to each other can be aligned with each other.

[0053] Furthermore, the second metal pattern 22 , the hybrid bonding structure 25 , and the third metal pattern 26 electrically connected to each other may also be aligned with each other in the first direction, so that the first crystal grains 31 and the second crystal grains 32 are mixed and spaced to form a bonded crystal grain group 30 .

[0054] Corresponding to the aforementioned chip, an embodiment of the present invention further provides a chip design method, which can effectively improve the chip area utilization rate of the main structure of the chip while ensuring that the test structure of the three-dimensional integrated chip is effectively set.

[0055] like Figure 7 As shown, the chip design method provided by the embodiment of the present invention may include: S41, determining a main structure and a test structure of a chip to be designed, wherein the main structure and the test structure are distributed in a plurality of crystal grains of the chip to be designed, there is no electrical connection between the main structure and the test structure, the plurality of crystal grains include a first crystal grain and a second crystal grain, the first crystal grain and the second crystal grain are used to be stacked and mixed-bonded with each other to form a bonded crystal grain group; the main structure is used to implement a preset circuit function; the test structure is used to test preset electrical parameters of the bonded crystal grain group, the preset electrical parameters include electrical parameters related to the interconnection characteristics between the first crystal grain and the second crystal grain; the test structure includes at least two key components; S42, designing the test structure in the design file corresponding to the bonded grain group, wherein the preset position of the bonded grain group is used to arrange at least a part of the elements of the main structure, and the preset position includes at least one of the following: a projection coverage of at least one of the key components along the first direction; a position where the distance to the edge of at least one of the key components or the distance to the edge of the projection coverage of the key component along the first direction is less than a preset distance threshold; wherein the first direction is the stacking direction of the first grain and the second grain.

[0056] The chip design method provided by the embodiment of the present invention can determine the main structure and test structure of the chip to be designed, wherein the main structure and the test structure are distributed in multiple grains of the chip to be designed, and there is no electrical connection between the main structure and the test structure, and the multiple grains include a first grain and a second grain, and the first grain and the second grain are used to stack and hybrid bond with each other to form a bonded grain group; the main structure is used to realize a preset circuit function; the test structure is used to test the preset electrical parameters of the bonded grain group, and the preset electrical parameters include electrical parameters related to the interconnection characteristics between the first grain and the second grain; the test structure includes at least two key components; the test structure is designed in a design file corresponding to the bonded grain group, wherein the preset position of the bonded grain group is used to arrange at least a part of the elements of the main structure, and the preset position includes at least one of the following: the projection coverage of at least one of the key components along the first direction; the position where the distance from the edge of at least one of the key components or the distance from the edge of the projection coverage of the key component along the first direction is less than a preset distance threshold; wherein the first direction is the stacking direction of the first grain and the second grain. In this way, on the one hand, the test structures are all located on the die rather than in the cutting lanes, thereby avoiding the situation in which there is nowhere to set up the test structures in C2W; on the other hand, at least a part of the elements of the main structure are set at the preset positions of the bonded die group, and these preset positions include at least one of the following: the projection coverage of at least one key component along the first direction; the position where the distance from the edge of at least one key component or the distance from the edge of the projection coverage of the key component along the first direction is less than a preset distance threshold. That is to say, in the chip design method provided by the embodiment of the present invention, the positions near the key components of the bonded grain group, or the positions within the projection coverage range of the key components in the first direction or near the projection coverage range, can allow for the setting of at least some elements in the main structure. The test structure is not like the prior art, which packages the key components into a whole, occupies a relatively complete space in the grain, and is clearly separated from the distribution area of ​​the main structure. Instead, the key components are split apart so that at least some elements of the main structure can be arranged at positions in the bonded grain group that are not occupied by the key components. In this way, the main structure can be arranged in a wider range, thereby effectively improving the utilization rate of the chip area by the chip main structure while ensuring that the test structure of the three-dimensional integrated chip is effectively set.

[0057] Specifically, first, the main structure and test structure of the chip to be designed can be determined in step S41. In an embodiment of the present invention, the main structure may refer to a structure that implements the main function of the chip. For example, the main structure in an analog-to-digital conversion chip is a structure used to implement the analog-to-digital conversion function. The test structure is irrelevant to the main function of the chip and is mainly used for testing. In an embodiment of the present invention, the test structure can be used to measure electrical parameters related to the interconnection characteristics between the first grain and the second grain. For example, it can be used to measure the voltage, resistance, current, etc. between the first grain and the second grain.

[0058] After determining the main structure and test structure of the chip to be designed, the test structure can be designed in step S42. Specifically, the test structure can be designed in the design file corresponding to the bonded die group. The preset position of the bonded die group is used to arrange at least a part of the elements of the main structure.

[0059] In one embodiment of the present invention, each of the grains in the bonded grain group may include a plurality of structural layers stacked along a first direction, and each key component may be disposed in one or more of the structural layers. Based on this, the preset position may include one or more of the following: at least one key component is within the projection coverage of any structural layer; in any structural layer, the distance between the edge of at least one key component is less than a preset distance threshold; in any structural layer, the distance between the edge of the projection coverage of at least one key component along the first direction is less than a preset distance threshold. In other words, the position of the key component disposed in each structural layer of the bonded grain group may be determined, so that the corresponding preset position may be further determined in each structural layer according to the distance between the edge of the key component. Alternatively, the projection coverage of the key components on other structural layers on a certain structural layer may be determined, so that the corresponding preset position may be further determined in the structural layer according to the distance between the edge of the projection coverage of the key components.

[0060] In one embodiment of the present invention, the types of key components may include at least one of the following: a test pad, a first metal pattern, a through silicon via, a second metal pattern, a hybrid bonding structure, and a third metal pattern; the number of the key components of each type is one or more; the test pad is arranged on the first surface of the first crystal grain; the first metal pattern is arranged on the first surface side of the first crystal grain and is located below the first surface; the through silicon via is arranged in the first crystal grain, one-to-one corresponding to the first metal pattern and aligned in position, each of the through silicon vias extends from the second surface of the first crystal grain to the corresponding first metal pattern and is electrically connected to the first metal pattern, wherein the first surface is opposite to the second surface; the second metal pattern is arranged on the second surface of the first crystal grain for electrically connecting to the first end of the hybrid bonding structure; the hybrid bonding structure is arranged between the second surface of the first crystal grain and the second crystal grain; the third metal pattern is arranged on the surface of the second crystal grain opposite to the first crystal grain for electrically connecting to the second end of the hybrid bonding structure.

[0061] In one embodiment, each of the test pads may be arranged in a preset shape, the preset shape corresponding to the arrangement shape of probes in a probe card of a test device, and each of the test pads is used to be electrically connected to each of the probes on the probe card.

[0062] In one embodiment, each of the first metal patterns may be electrically connected to one test pad, and the first metal pattern and the test pad electrically connected to each other may be aligned with or not aligned with each other in the first direction.

[0063] In one embodiment of the present invention, step S42 of designing the test structure in the design file corresponding to the bonding grain group may specifically include: designing the test pad, the first metal pattern, the through silicon via, the second metal pattern and the first pad corresponding to the hybrid bonding structure in the first design file, and designing the second pad corresponding to the hybrid bonding structure and the third metal pattern in the second design file; wherein the second metal pattern includes at least one target metal pattern, one end of each target metal pattern is electrically connected to one of the through silicon vias, and the other end is electrically connected to a first pad corresponding to the hybrid bonding structure; the first metal pattern, the through silicon via, the target metal pattern, and the first pad corresponding to the hybrid bonding structure that are electrically connected to each other are aligned with each other in the first direction; the first pad corresponding to the hybrid bonding structure, the second pad corresponding to the hybrid bonding structure, and the third metal pattern are aligned with each other in the first direction.

[0064] That is to say, in this embodiment, when designing the chip to be designed, different parts of the test structure can be designed in different design files according to the different crystal grains where the test structure is located. Among them, each key component designed in the first design file is located in the first crystal grain, and each key component designed in the second design file is located in the second crystal grain. The structure in the first design file and the structure in the second design file can be aligned through coordinates or alignment marks. In an embodiment of the present invention, a hybrid bonding structure is a structure formed between the first crystal grain and the second crystal grain after the first crystal grain and the second crystal grain are hybrid bonded. The first pad corresponding to the hybrid bonding structure can refer to a pad to be bonded set on the first crystal grain before the first crystal grain is bonded to the second crystal grain. Similarly, the second pad corresponding to the hybrid bonding structure can refer to a pad to be bonded set on the second crystal grain before the first crystal grain is bonded to the second crystal grain. The first pad and the second pad can form a hybrid bonding structure after hybrid bonding.

[0065] In another embodiment of the present invention, step S42 of designing the test structure in the design file corresponding to the bonding grain group may specifically include: designing the test pad and the first metal pattern in a third design file, designing the through silicon via, the second metal pattern and the first pad and the second pad corresponding to the hybrid bonding structure in a fourth design file, and designing the third metal pattern in the fifth design file; wherein the second metal pattern includes at least one target metal pattern, one end of each target metal pattern is electrically connected to a through silicon via, and the other end is electrically connected to a first pad corresponding to the hybrid bonding structure; the first metal pattern, the through silicon via, the target metal pattern, and the first pad of the hybrid bonding structure that are electrically connected to each other are aligned with each other in the first direction; the first pad corresponding to the hybrid bonding structure, the second pad corresponding to the hybrid bonding structure, and the third metal pattern are aligned with each other in the first direction.

[0066] In this embodiment, when designing the chip to be designed, different parts of the test structure can be designed in different design files according to the different process implementation processes of the test structure. Among them, each key component designed in the third design file belongs to the two-dimensional integration process of the first crystal grain, each key component designed in the fourth design file belongs to the process of three-dimensional integration of the first crystal grain and the second crystal grain, and each key component designed in the fifth design file belongs to the two-dimensional integration process of the second crystal grain. The structure in the third design file, the structure in the fourth design file, and the structure in the fifth design file can be aligned with each other through coordinates or alignment marks.

[0067] Furthermore, after designing the test structure in the design file corresponding to the bonded grain group in step S42, the chip design method provided by the embodiment of the present invention may also include: adding a spare pad to the test structure in the design file corresponding to the bonded grain group, the spare pad being used to connect the first grain or the second grain to a probe card for testing before integrating the first grain and the second grain into the bonded grain group. In this embodiment, not only can the three-dimensional chip integrated with multiple grains be tested, but each grain can also be tested separately before each grain is integrated into a three-dimensional chip, so as to screen out qualified grains for integration. Since a spare pad is added to the test structure, the spare pad can be used when the grain is tested separately, and the probe card contacts the spare pad but not the test pad. In this way, the probe card will not damage the test pad, thereby not affecting the subsequent testing of the three-dimensional chip.

[0068] Corresponding to the aforementioned chip design method, an embodiment of the present invention further provides a chip design device, which can effectively improve the chip area utilization rate of the chip's main structure while ensuring that the test structure of the three-dimensional integrated chip is effectively set.

[0069] like Figure 8 As shown, the chip design device provided by the embodiment of the present invention may include: A determination unit 71 is used to determine a main structure and a test structure of a chip to be designed, wherein the main structure and the test structure are distributed in a plurality of crystal grains of the chip to be designed, there is no electrical connection between the main structure and the test structure, the plurality of crystal grains include a first crystal grain and a second crystal grain, the first crystal grain and the second crystal grain are used to be stacked and mixed-bonded with each other to form a bonded crystal grain group; the main structure is used to implement a preset circuit function; the test structure is used to test preset electrical parameters of the bonded crystal grain group, the preset electrical parameters include electrical parameters related to the interconnection characteristics between the first crystal grain and the second crystal grain; the test structure includes at least two key components; A design unit 72 is used to design the test structure in a design file corresponding to the bonded grain group, wherein a preset position of the bonded grain group is used to arrange at least a part of the elements of the main structure, and the preset position includes at least one of the following: a projection coverage of at least one of the key components along a first direction; a position where the distance from an edge of at least one of the key components or the distance from an edge of the projection coverage of the key component along the first direction is less than a preset distance threshold; wherein the first direction is a stacking direction of the first grain and the second grain.

[0070] The chip design device provided by the embodiment of the present invention can determine the main structure and test structure of the chip to be designed, wherein the main structure and the test structure are distributed in multiple grains of the chip to be designed, there is no electrical connection between the main structure and the test structure, the multiple grains include a first grain and a second grain, the first grain and the second grain are used to stack and hybrid bond with each other to form a bonded grain group; the main structure is used to realize a preset circuit function; the test structure is used to test the preset electrical parameters of the bonded grain group, the preset electrical parameters include electrical parameters related to the interconnection characteristics between the first grain and the second grain; the test structure includes at least two key components; the test structure is designed in a design file corresponding to the bonded grain group, wherein the preset position of the bonded grain group is used to arrange at least a part of the elements of the main structure, and the preset position includes at least one of the following: the projection coverage of at least one of the key components along the first direction; the position where the distance from the edge of at least one of the key components or the distance from the edge of the projection coverage of the key component along the first direction is less than a preset distance threshold; wherein the first direction is the stacking direction of the first grain and the second grain. In this way, on the one hand, the test structures are all located on the die rather than in the cutting lanes, thereby avoiding the situation in which there is nowhere to set up the test structures in C2W; on the other hand, at least a part of the elements of the main structure are set at the preset positions of the bonded die group, and these preset positions include at least one of the following: the projection coverage of at least one key component along the first direction; the position where the distance from the edge of at least one key component or the distance from the edge of the projection coverage of the key component along the first direction is less than a preset distance threshold. That is to say, in the chip design method provided by the embodiment of the present invention, the positions near the key components of the bonded grain group, or the positions within the projection coverage range of the key components in the first direction or near the projection coverage range, can allow for the setting of at least some elements in the main structure. The test structure is not like the prior art, which packages the key components into a whole, occupies a relatively complete space in the grain, and is clearly separated from the distribution area of ​​the main structure. Instead, the key components are split apart so that at least some elements of the main structure can be arranged at positions in the bonded grain group that are not occupied by the key components. In this way, the main structure can be arranged in a wider range, thereby effectively improving the utilization rate of the chip area by the chip main structure while ensuring that the test structure of the three-dimensional integrated chip is effectively set.

[0071] Corresponding to the aforementioned chip, an embodiment of the present invention further provides a chip manufacturing method, which can effectively improve the chip area utilization rate of the main structure of the chip while ensuring that the test structure of the three-dimensional integrated chip is effectively set.

[0072] like Fig. 9 As shown, the chip manufacturing method provided by the embodiment of the present invention may include: S51, respectively manufacturing a main structure and a test structure corresponding to a target chip in a plurality of grains, wherein there is no electrical connection between the main structure and the test structure, wherein the plurality of grains include a first grain and a second grain, and the first grain and the second grain are used to be stacked and mixed-bonded with each other to form a bonded grain group; the main structure is used to realize a preset circuit function; the test structure is used to test preset electrical parameters of the bonded grain group, and the preset electrical parameters include electrical parameters related to the interconnection characteristics between the first grain and the second grain; the test structure includes at least two key components; at least a part of the elements of the main structure are arranged at a preset position of the bonded grain group, and the preset position includes at least one of the following: the projection coverage of at least one of the key components along the first direction; the position where the distance from the edge of at least one of the key components or the distance from the edge of the projection coverage of the key component along the first direction is less than a preset distance threshold; wherein the first direction is the stacking direction of the first grain and the second grain.

[0073] S52, stacking and hybrid bonding the first crystal grains and the second crystal grains to form the bonded crystal grain group; S53, forming the target chip based on the bonded die group.

[0074] The chip manufacturing method provided by the embodiment of the present invention can manufacture the main structure and the test structure corresponding to the target chip in multiple grains respectively, the main structure and the test structure are not electrically connected, the first grain and the second grain are stacked and mixed bonded to form the bonded grain group, and the target chip is formed based on the bonded grain group. Wherein, the multiple grains include a first grain and a second grain, the first grain and the second grain are used to stack and mix bond with each other to form a bonded grain group; the main structure is used to realize a preset circuit function; the test structure is used to test the preset electrical parameters of the bonded grain group, and the preset electrical parameters include electrical parameters related to the interconnection characteristics between the first grain and the second grain; the test structure includes at least two key components; at least a part of the elements of the main structure are set at a preset position of the bonded grain group, and the preset position includes at least one of the following: the projection coverage of at least one of the key components along the first direction; the distance between the edge of at least one of the key components or the distance between the edge of the projection coverage of the key component along the first direction is less than the preset distance threshold; wherein, the first direction is the stacking direction of the first grain and the second grain. In this way, on the one hand, the test structures are all located on the die rather than in the cutting lanes, thereby avoiding the situation in which there is nowhere to set up the test structures in C2W; on the other hand, at least a part of the elements of the main structure are set at the preset positions of the bonded die group, and these preset positions include at least one of the following: the projection coverage of at least one key component along the first direction; the position where the distance from the edge of at least one key component or the distance from the edge of the projection coverage of the key component along the first direction is less than a preset distance threshold. That is to say, in the chip design method provided by the embodiment of the present invention, the positions near the key components of the bonded grain group, or the positions within the projection coverage range of the key components in the first direction or near the projection coverage range, can allow for the setting of at least some elements in the main structure. The test structure is not like the prior art, which packages the key components into a whole, occupies a relatively complete space in the grain, and is clearly separated from the distribution area of ​​the main structure. Instead, the key components are split apart so that at least some elements of the main structure can be arranged at positions in the bonded grain group that are not occupied by the key components. In this way, the main structure can be arranged in a wider range, thereby effectively improving the utilization rate of the chip area by the chip main structure while ensuring that the test structure of the three-dimensional integrated chip is effectively set.

[0075] In one embodiment of the present invention, each of the grains in the bonded grain group may include a plurality of structural layers stacked along a first direction, and each key component may be disposed in one or more of the structural layers. Based on this, the preset position may include one or more of the following: at least one key component is within the projection coverage of any structural layer; in any structural layer, the distance between the edge of at least one key component is less than a preset distance threshold; in any structural layer, the distance between the edge of the projection coverage of at least one key component along the first direction is less than a preset distance threshold. In other words, the position of the key component disposed in each structural layer of the bonded grain group may be determined, so that the corresponding preset position may be further determined in each structural layer according to the distance between the edge of the key component. Alternatively, the projection coverage of the key components on other structural layers on a certain structural layer may be determined, so that the corresponding preset position may be further determined in the structural layer according to the distance between the edge of the projection coverage of the key components.

[0076] In one embodiment of the present invention, the types of key components may include at least one of the following: a test pad, a first metal pattern, a through silicon via, a second metal pattern, a hybrid bonding structure, and a third metal pattern; the number of the key components of each type is one or more; the test pad is arranged on the first surface of the first crystal grain; the first metal pattern is arranged on the first surface side of the first crystal grain and is located below the first surface; the through silicon via is arranged in the first crystal grain, one-to-one corresponding to the first metal pattern and aligned in position, each of the through silicon vias extends from the second surface of the first crystal grain to the corresponding first metal pattern and is electrically connected to the first metal pattern, wherein the first surface is opposite to the second surface; the second metal pattern is arranged on the second surface of the first crystal grain for electrically connecting to the first end of the hybrid bonding structure; the hybrid bonding structure is arranged between the second surface of the first crystal grain and the second crystal grain; the third metal pattern is arranged on the surface of the second crystal grain opposite to the first crystal grain for electrically connecting to the second end of the hybrid bonding structure.

[0077] In one embodiment, each of the test pads may be arranged in a preset shape, the preset shape corresponding to the arrangement shape of probes in a probe card of a test device, and each of the test pads is used to be electrically connected to each of the probes on the probe card.

[0078] In one embodiment, each of the first metal patterns may be electrically connected to one test pad, and the first metal pattern and the test pad electrically connected to each other may be aligned with or not aligned with each other in the first direction.

[0079] In one embodiment of the present invention, step S51 of manufacturing the main structure and test structure corresponding to the target chip in multiple crystal grains respectively may specifically include: manufacturing the test pad, the first metal pattern, the through silicon via, the second metal pattern and the first pad corresponding to the hybrid bonding structure in the first crystal grain, and manufacturing the second pad corresponding to the hybrid bonding structure and the third metal pattern in the second crystal grain; wherein the second metal pattern includes at least one target metal pattern, one end of each target metal pattern is electrically connected to a through silicon via, and the other end is electrically connected to a first pad corresponding to the hybrid bonding structure; the first metal pattern, the through silicon via, the target metal pattern, and the first pad of the hybrid bonding structure electrically connected to each other are aligned with each other in the first direction; the first pad corresponding to the hybrid bonding structure, the second pad corresponding to the hybrid bonding structure, and the third metal pattern are aligned with each other in the first direction. In this way, the target metal pattern can introduce the electrical signal in the first surface of the first crystal grain into the second surface of the first crystal grain through the through silicon via, and further transmit the electrical signal to the second crystal grain through the hybrid bonding structure, thereby realizing the interconnection between the first crystal grain and the second crystal grain.

[0080] That is to say, in this embodiment, when manufacturing the target chip, different parts of the test structure can be manufactured in corresponding dies according to the different dies where the test structure is located.

[0081] In an embodiment of the present invention, the hybrid bonding structure is a structure formed between the first crystal grain and the second crystal grain after the first crystal grain and the second crystal grain are hybrid bonded. The first pad corresponding to the hybrid bonding structure may refer to a pad to be bonded that is arranged on the first crystal grain before the first crystal grain and the second crystal grain are bonded. Similarly, the second pad corresponding to the hybrid bonding structure may refer to a pad to be bonded that is arranged on the second crystal grain before the first crystal grain and the second crystal grain are bonded. The first pad and the second pad may form a hybrid bonding structure after hybrid bonding.

[0082] After obtaining the first grain and the second grain, the first grain and the second grain can be stacked and mixed bonded to each other in step S52 to form the bonded grain group. Specifically, stacking the first grain and the second grain to each other and mixed bonding to form the bonded grain group can include: stacking the first grain and the second grain, and mixed bonding the first pad corresponding to the mixed bonding structure in the first grain with the second pad corresponding to the mixed bonding structure in the second grain to form the bonded grain group.

[0083] Further, after manufacturing the main structure and test structure corresponding to the target chip in multiple grains respectively in step S51, before stacking and hybrid bonding the first grain and the second grain to form the bonded grain group in step S52, the chip manufacturing method provided by the embodiment of the present invention may also include: making spare pads for the test structure in the first grain and the second grain, and covering the test pads with a protective layer; electrically connecting the spare pads to a probe card to test the first grain and the second grain respectively to obtain the first grain and the second grain that pass the test; flattening the spare pads of the first grain and the second grain that pass the test; removing the protective layer of the test pads in the first grain and the second grain that pass the test to expose the test pads. Based on this, step S52 stacking and hybrid bonding the first grain and the second grain to form the bonded grain group may specifically include: stacking and hybrid bonding the first grain and the second grain that expose the test pads to form the bonded grain group.

[0084] In this embodiment, not only can the three-dimensional chip integrated with multiple crystals be tested, but each crystal can also be tested separately before each crystal is integrated into the three-dimensional chip, so as to screen out qualified crystals for integration. Since spare pads are made for the test structure, the spare pads can be used when the crystal is tested separately, and the probe card contacts the spare pads instead of the test pads. In this way, the probe card will not damage the test pads, thereby not affecting the subsequent test of the three-dimensional chip.

[0085] In one embodiment of the present invention, a protective layer can be prepared for the test pad in advance. The protective layer can be, for example, a thin film such as silicon dioxide. When the crystal grain is tested, the test pad is covered by the protective layer, and only the spare pad is used to connect the probe card. After the crystal grain is tested, the spare pad can be flattened. For example, the spare pad can be removed by wet etching or dry etching, so as to avoid the probe card damaging the spare pad and causing the metal of the spare pad to bulge and make the flatness of the crystal grain not meet the subsequent processing requirements. When etching the spare pad, since the test pad is covered with a protective layer, the test pad will not be etched. After the spare pad is etched, the protective layer can be removed to expose the test pad, so that after the crystal grains are three-dimensionally integrated to form a target chip, the target chip can be tested using the test pad.

[0086] After obtaining the bonded grain group in step S52, a target chip can be formed based on the bonded grain group in step S53. For example, if the target chip is composed of a bonded grain group formed by a first grain and a second grain, the bonded grain group can be used as the target chip. For another example, if the target chip includes other grains in addition to the bonded grain group, it can be further integrated with the other grains. The specific integration method is similar to the integration method of the first grain and the second grain, which has been described in detail in the previous article and will not be repeated here.

[0087] Accordingly, an embodiment of the present invention further provides an electronic device that can effectively improve the chip area utilization rate of the main structure of the chip while ensuring that the test structure of the three-dimensional integrated chip is effectively arranged.

[0088] like Fig.10 As shown, the electronic device provided by an embodiment of the present invention may include: a shell 61, a processor 62, a memory 63, a circuit board 64 and a power supply circuit 65, wherein the circuit board 64 is arranged inside the space enclosed by the shell 61, and the processor 62 and the memory 63 are arranged on the circuit board 64; the power supply circuit 65 is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory 63 is used to store executable program codes; the processor 62 runs a program corresponding to the executable program code by reading the executable program code stored in the memory 63, so as to execute the chip design method provided by any of the aforementioned embodiments.

[0089] The specific execution process of the above steps by the processor 62 and the steps further executed by the processor 62 by running the executable program code can be found in the description of the previous embodiment, which will not be repeated here.

[0090] Correspondingly, an embodiment of the present invention also provides a computer-readable storage medium, which stores one or more programs. The one or more programs can be executed by one or more processors to implement any chip design method provided in the aforementioned embodiments, thereby also achieving the corresponding technical effects, which have been described in detail above and will not be repeated here.

[0091] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0092] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0093] In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0094] For the convenience of description, the above device is described by dividing the functions into various units / modules. Of course, when implementing the present invention, the functions of each unit / module can be implemented in the same or multiple software and / or hardware.

[0095] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0096] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A chip, characterized in that: include: A main structure and a test structure, wherein the main structure and the test structure are distributed in a plurality of crystal grains of the chip to be designed, the main structure and the test structure are not electrically connected, the plurality of crystal grains include a first crystal grain and a second crystal grain, the first crystal grain and the second crystal grain are used to be stacked and mixed-bonded with each other to form a bonded crystal grain group; The main structure is used to implement a preset circuit function; the test structure is used to test preset electrical parameters of the bonded die group, wherein the preset electrical parameters include electrical parameters related to the interconnection characteristics between the first die and the second die; the test structure includes at least two key components; The preset position of the bonded grain group is provided with at least a part of the elements of the main structure, and the preset position includes at least one of the following: the projection coverage of at least one of the key components along the first direction; the position where the distance from the edge of at least one of the key components or the distance from the edge of the projection coverage of the key component along the first direction is less than a preset distance threshold; wherein the first direction is the stacking direction of the first grain and the second grain.

2. The chip according to claim 1, characterized in that: Each grain in the bonded grain group includes a plurality of structural layers stacked along the first direction, each of the key components is arranged in one or more of the structural layers, and the preset position includes at least one of the following: at least one of the key components is within the projection coverage range on any of the structural layers; a position in any of the structural layers, where the distance from the edge of at least one of the key components is less than a preset distance threshold; a position in any of the structural layers, where the distance from the edge of the projection coverage range of at least one of the key components along the first direction is less than a preset distance threshold.

3. The chip according to claim 1, characterized in that: The types of the key components include at least one of the following: a test pad, a first metal pattern, a through silicon via, a second metal pattern, a hybrid bonding structure, and a third metal pattern; the number of the key components of each type is one or more.

4. The chip according to claim 3, characterized in that: The test pad is disposed on the first surface of the first die; The first metal pattern is disposed on the first surface side of the first crystal grain and is located below the first surface; The through silicon vias are arranged in the first crystal grain, corresponding to the first metal pattern one by one and aligned in position, each of the through silicon vias extends from the second surface of the first crystal grain to the corresponding first metal pattern, and is electrically connected to the first metal pattern, wherein the first surface is opposite to the second surface; The second metal pattern is disposed on the second surface of the first crystal grain and is used to be electrically connected to the first end of the hybrid bonding structure; The hybrid bonding structure is disposed between the second surface of the first die and the second die; The third metal pattern is disposed on a surface of the second crystal grain opposite to the first crystal grain, and is used for being electrically connected to the second end of the hybrid bonding structure.

5. The chip according to claim 4, characterized in that: The second metal pattern includes at least one target metal pattern, one end of each target metal pattern is electrically connected to one of the through silicon vias, and the other end is electrically connected to one of the hybrid bonding structures; the first metal pattern, the through silicon via, the target metal pattern, and the hybrid bonding structure that are electrically connected to each other are aligned with each other in the first direction.

6. The chip according to claim 3, characterized in that: Each of the test pads is arranged in a preset shape, which corresponds to the arrangement shape of the probes in the probe card of the test equipment, and each of the test pads is used to be electrically connected to each of the probes on the probe card.

7. The chip according to claim 3, characterized in that: Each of the first metal patterns is electrically connected to one of the test pads, and the first metal patterns and the test pads that are electrically connected to each other are aligned with or not aligned with each other in the first direction.

8. The chip according to claim 3, characterized in that: The second metal pattern, the hybrid bonding structure, and the third metal pattern that are electrically connected to each other are aligned with each other in the first direction.

9. A chip design method, characterized in that: include: Determine a main structure and a test structure of a chip to be designed, wherein the main structure and the test structure are distributed in a plurality of crystal grains of the chip to be designed, there is no electrical connection between the main structure and the test structure, the plurality of crystal grains include a first crystal grain and a second crystal grain, the first crystal grain and the second crystal grain are used to stack and hybrid bond with each other to form a bonded crystal grain group; the main structure is used to implement a preset circuit function; the test structure is used to test preset electrical parameters of the bonded crystal grain group, the preset electrical parameters include electrical parameters related to the interconnection characteristics between the first crystal grain and the second crystal grain; the test structure includes at least two key components; The test structure is designed in a design file corresponding to the bonded die group, wherein a preset position of the bonded die group is used to arrange at least a portion of the elements of the main structure, and the preset position includes at least one of the following: a projection coverage of at least one of the key components along a first direction; a position where the distance to an edge of at least one of the key components or the distance to an edge of the projection coverage of the key component along the first direction is less than a preset distance threshold; wherein the first direction is a stacking direction of the first die and the second die.

10. The method according to claim 9, characterized in that Each grain in the bonded grain group includes a plurality of structural layers stacked along the first direction, each of the key components is arranged in one or more of the structural layers, and the preset position includes at least one of the following: at least one of the key components is within the projection coverage range on any of the structural layers; a position in any of the structural layers, where the distance from the edge of at least one of the key components is less than a preset distance threshold; a position in any of the structural layers, where the distance from the edge of the projection coverage range of at least one of the key components along the first direction is less than a preset distance threshold.

11. The method according to claim 9, characterized in that The types of the key components include at least one of the following: a test pad, a first metal pattern, a through silicon via, a second metal pattern, a hybrid bonding structure, and a third metal pattern; the number of the key components of each type is one or more; The test pad is disposed on the first surface of the first die; The first metal pattern is disposed on the first surface side of the first crystal grain and is located below the first surface; The through silicon vias are arranged in the first crystal grain, corresponding to the first metal pattern one by one and aligned in position, each of the through silicon vias extends from the second surface of the first crystal grain to the corresponding first metal pattern, and is electrically connected to the first metal pattern, wherein the first surface is opposite to the second surface; The second metal pattern is disposed on the second surface of the first crystal grain and is used to be electrically connected to the first end of the hybrid bonding structure; The hybrid bonding structure is disposed between the second surface of the first die and the second die; The third metal pattern is disposed on a surface of the second crystal grain opposite to the first crystal grain, and is used for being electrically connected to the second end of the hybrid bonding structure.

12. The method according to claim 11, characterized in that The designing of the test structure in the design file corresponding to the bonded die group includes: Designing the test pad, the first metal pattern, the through silicon via, the second metal pattern, and the first pad corresponding to the hybrid bonding structure in the first design file, and designing the second pad corresponding to the hybrid bonding structure and the third metal pattern in the second design file; Among them, the second metal pattern includes at least one target metal pattern, one end of each of the target metal patterns is electrically connected to a through silicon via, and the other end is electrically connected to a first pad corresponding to the hybrid bonding structure; the first metal pattern, the through silicon via, the target metal pattern, and the first pad corresponding to the hybrid bonding structure that are electrically connected to each other are aligned with each other in the first direction; the first pad corresponding to the hybrid bonding structure, the second pad corresponding to the hybrid bonding structure, and the third metal pattern are aligned with each other in the first direction.

13. The method according to claim 11, characterized in that The designing of the test structure in the design file corresponding to the bonded die group includes: The test pad and the first metal pattern are designed in a third design file, the through silicon via, the second metal pattern, and the first pad and the second pad corresponding to the hybrid bonding structure are designed in a fourth design file, and the third metal pattern is designed in the fifth design file; Among them, the second metal pattern includes at least one target metal pattern, one end of each of the target metal patterns is electrically connected to a through silicon via, and the other end is electrically connected to a first pad corresponding to the hybrid bonding structure; the first metal pattern, the through silicon via, the target metal pattern, and the first pad of the hybrid bonding structure that are electrically connected to each other are aligned with each other in the first direction; the first pad corresponding to the hybrid bonding structure, the second pad corresponding to the hybrid bonding structure, and the third metal pattern are aligned with each other in the first direction.

14. The method according to claim 11, characterized in that After designing the test structure in the design file corresponding to the bonded die group, the method further includes: A spare pad is added for the test structure in the design file corresponding to the bonded die group, and the spare pad is used to connect the first die or the second die to a probe card for testing before integrating the first die and the second die into the bonded die group.

15. The method according to claim 11, characterized in that Each of the test pads is arranged in a preset shape, which corresponds to the arrangement shape of the probes in the probe card of the test equipment, and each of the test pads is used to be electrically connected to each of the probes on the probe card.

16. The method according to claim 11, characterized in that Each of the first metal patterns is electrically connected to one of the test pads, and the first metal patterns and the test pads that are electrically connected to each other are aligned with or not aligned with each other in the first direction.

17. A chip design device, characterized in that: include: A determination unit, configured to determine a main structure and a test structure of a chip to be designed, wherein the main structure and the test structure are distributed in a plurality of crystal grains of the chip to be designed, and there is no electrical connection between the main structure and the test structure, and the plurality of crystal grains include a first crystal grain and a second crystal grain, and the first crystal grain and the second crystal grain are used to be stacked and mixed-bonded with each other to form a bonded crystal grain group; the main structure is used to implement a preset circuit function; the test structure is used to test preset electrical parameters of the bonded crystal grain group, and the preset electrical parameters include electrical parameters related to the interconnection characteristics between the first crystal grain and the second crystal grain; and the test structure includes at least two key components; A design unit is used to design the test structure in a design file corresponding to the bonded grain group, wherein the preset position of the bonded grain group is used to arrange at least a part of the elements of the main structure, and the preset position includes at least one of the following: a projection coverage of at least one of the key components along a first direction; a position where the distance from an edge of at least one of the key components or the distance from an edge of the projection coverage of the key component along the first direction is less than a preset distance threshold; wherein the first direction is a stacking direction of the first grain and the second grain.

18. A chip manufacturing method, characterized in that: include: A main structure and a test structure corresponding to a target chip are manufactured in a plurality of grains respectively, and there is no electrical connection between the main structure and the test structure, wherein the plurality of grains include a first grain and a second grain, and the first grain and the second grain are used to be stacked and mixed-bonded with each other to form a bonded grain group; the main structure is used to realize a preset circuit function; the test structure is used to test preset electrical parameters of the bonded grain group, and the preset electrical parameters include electrical parameters related to the interconnection characteristics between the first grain and the second grain; the test structure includes at least two key components; at least a part of the elements of the main structure are arranged at a preset position of the bonded grain group, and the preset position includes at least one of the following: a projection coverage of at least one of the key components along a first direction; a position where the distance from the edge of at least one of the key components or the distance from the edge of the projection coverage of the key component along the first direction is less than a preset distance threshold; wherein the first direction is the stacking direction of the first grain and the second grain; Stacking and hybrid bonding the first crystal grains and the second crystal grains to form the bonded crystal grain group; The target chip is formed based on the bonded die group.

19. The method according to claim 18, characterized in that Each grain in the bonded grain group includes a plurality of structural layers stacked along the first direction, each of the key components is arranged in one or more of the structural layers, and the preset position includes at least one of the following: at least one of the key components is within the projection coverage range on any of the structural layers; a position in any of the structural layers, where the distance from the edge of at least one of the key components is less than a preset distance threshold; a position in any of the structural layers, where the distance from the edge of the projection coverage range of at least one of the key components along the first direction is less than a preset distance threshold.

20. The method according to claim 18, characterized in that The types of the key components include at least one of the following: a test pad, a first metal pattern, a through silicon via, a second metal pattern, a hybrid bonding structure, and a third metal pattern; the number of the key components of each type is one or more; The test pad is disposed on the first surface of the first die; The first metal pattern is disposed on the first surface side of the first crystal grain and is located below the first surface; The through silicon vias are arranged in the first crystal grain, corresponding to the first metal pattern one by one and aligned in position, each of the through silicon vias extends from the second surface of the first crystal grain to the corresponding first metal pattern, and is electrically connected to the first metal pattern, wherein the first surface is opposite to the second surface; The second metal pattern is disposed on the second surface of the first crystal grain and is used to be electrically connected to the first end of the hybrid bonding structure; The hybrid bonding structure is disposed between the second surface of the first die and the second die; The third metal pattern is disposed on a surface of the second crystal grain opposite to the first crystal grain, and is used for being electrically connected to the second end of the hybrid bonding structure.

21. The method according to claim 20, characterized in that The manufacturing of the main structure and the test structure corresponding to the target chip in the plurality of crystal grains respectively comprises: Manufacturing the test pad, the first metal pattern, the through silicon via, the second metal pattern, and the first pad corresponding to the hybrid bonding structure in the first die, and manufacturing the second pad corresponding to the hybrid bonding structure and the third metal pattern in the second die; Among them, the second metal pattern includes at least one target metal pattern, one end of each of the target metal patterns is electrically connected to a through silicon via, and the other end is electrically connected to a first pad corresponding to the hybrid bonding structure; the first metal pattern, the through silicon via, the target metal pattern, and the first pad of the hybrid bonding structure that are electrically connected to each other are aligned with each other in the first direction; the first pad corresponding to the hybrid bonding structure, the second pad corresponding to the hybrid bonding structure, and the third metal pattern are aligned with each other in the first direction.

22. The method according to claim 21, characterized in that The stacking and hybrid bonding of the first crystal grain and the second crystal grain to form the bonded crystal grain group comprises: The first die and the second die are stacked, and the first pad corresponding to the hybrid bonding structure in the first die is hybrid-bonded with the second pad corresponding to the hybrid bonding structure in the second die to form the bonded die group.

23. The method according to claim 21, characterized in that After manufacturing the main structure and the test structure corresponding to the target chip in the plurality of crystal grains respectively, and before stacking and hybrid bonding the first crystal grain and the second crystal grain to form the bonded crystal grain group, the method further includes: Making spare pads for the test structure in the first die and the second die, and covering the test pads with a protective layer; The spare pad is electrically connected to a probe card to test the first die and the second die respectively to obtain the first die and the second die that pass the test; performing a planarization process on the spare pads of the first die and the second die that have passed the test; Removing the protective layer of the test pad in the first die and the second die that have passed the test to expose the test pad; The stacking and hybrid bonding of the first crystal grain and the second crystal grain to form the bonded crystal grain group comprises: The first die and the second die with the test pad exposed are stacked and hybrid-bonded to form the bonded die group.

24. The method according to claim 20, characterized in that Each of the test pads is arranged in a preset shape, which corresponds to the arrangement shape of the probes in the probe card of the test equipment, and each of the test pads is used to be electrically connected to each of the probes on the probe card.

25. The method according to claim 20, characterized in that Each of the first metal patterns is electrically connected to one of the test pads, and the first metal patterns and the test pads that are electrically connected to each other are aligned with or not aligned with each other in the first direction.

26. An electronic device, characterized in that: The electronic device comprises: a housing, a processor, a memory, a circuit board and a power supply circuit, wherein the circuit board is placed inside the space enclosed by the housing, and the processor and the memory are arranged on the circuit board; the power supply circuit is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, so as to execute the chip design method described in any one of claims 9 to 16.

27. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the chip design method according to any one of claims 9 to 16.

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