Back power supply packaging structure and preparation method thereof, and electronic device

Abstract

The invention relates to the technical field of semiconductors, in particular to a back power supply packaging structure, a preparation method thereof and an electronic device, and the back power supply packaging structure comprises a packaging substrate, a chip, a first substrate layer, a first device layer and a first wiring layer. The first device layer is formed on the front side of the first substrate layer and is electrically connected with the first wiring layer; the back power supply structure is formed on the back side of the first substrate layer and electrically connected with the first device layer and the first wiring layer; the active intermediate layer is positioned between the packaging substrate and the chip and is jointed on one side of the first device layer, and a second wiring layer electrically connected with the first wiring layer and a first interconnection structure electrically connected with the second wiring layer are formed in the active intermediate layer; one end, facing the packaging substrate, of the first interconnection structure penetrates through the active interposer and is electrically connected with the packaging substrate. On the basis of the technical scheme, the chip packaging mechanical strength can be remarkably improved, and the power supply IR voltage drop and the power loss are reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a back-side power supply packaging structure and a preparation method thereof, and an electronic device. Background Art

[0002] Traditional chips use pads on the front side of the chip to connect to the power supply network. However, as the demand for structural miniaturization increases, the front side power supply solution faces many challenges, such as the resource crowding out between the signal network and the power supply network, and because the front side routing needs to pass through 15 to 20 layers of stacked back-end processes, the closer to the device layer, the narrower the line width and through-hole, resulting in IR voltage drop during the downward transmission of electrons, causing power loss. In view of this, backside power supply packaging becomes a possible solution to the above problems. The existing technology "Power Delivery Network PDN Modeling for Backside-PDN Configurations With Buried Power Rails and μTSVs (IEEE Transactions On Electron Devices, Vol. 67, No. 1, January 2020)" provides a backside power supply modeling scheme, which simulates the formation of a backside power supply structure on the back side of a chip with transistors to improve the power transmission performance of the chip power supply. However, this scheme simulates the back-end process in the same wafer. The upper and lower ends of the transistors in the formed wafer structure are both metal layers with a very thin thickness. The mechanical strength of the chip is extremely poor, and subsequent processes such as transportation and packaging cannot be realized, and thus productization and mass production cannot be achieved. Summary of the invention

[0003] In view of the above problems in the prior art, the present application provides a back-side power supply packaging structure and a preparation method thereof, and an electronic device. The specific technical solutions are as follows:

[0004] On the one hand, the present application provides a back-side power supply packaging structure, including:

[0005] Package substrate,

[0006] A chip, comprising a first substrate layer, a first device layer and a first wiring layer, wherein the first device layer is formed on the front side of the first substrate layer and is electrically connected to the first wiring layer;

[0007] a back power supply structure, formed on the back side of the first substrate layer and electrically connected to the first device layer and the first wiring layer respectively;

[0008] An active interposer is located between the packaging substrate and the chip and is bonded to one side of the first device layer. A second wiring layer electrically connected to the first wiring layer and a first interconnect structure electrically connected to the second wiring layer are formed in the active interposer. The first interconnect structure passes through the active interposer toward one end of the packaging substrate and is electrically connected to the packaging substrate.

[0009] On the other hand, the present application provides a method for preparing a back-side power supply packaging structure, the preparation method comprising:

[0010] A packaging substrate, a first wafer formed with a chip, and a second wafer formed with an active interposer are provided; the first wafer has a first surface and a second surface opposite to each other; the chip comprises a first initial substrate, a first device layer, and a first wiring layer, the first device layer is formed on the front side of the first initial substrate and is electrically connected to the first wiring layer; the active interposer is formed with an electrically connected second wiring layer and a first interconnection structure, the first interconnection structure penetrates the active interposer toward one end of the packaging substrate;

[0011] Bonding the first surface of the first wafer to the second wafer so that the active interposer is bonded to one side of the first device layer and the second wiring layer is electrically connected to the first wiring layer;

[0012] Thinning the first wafer from the second surface of the first wafer to thin the first initial substrate into a first substrate layer;

[0013] forming a back side power supply structure electrically connected to the first device layer and the first wiring layer respectively on the back side of the first substrate layer;

[0014] The first interconnect structure is electrically connected to the packaging substrate to form the back-side power supply packaging structure.

[0015] On the other hand, the present application provides an electronic device, which is manufactured using the above-mentioned back-side power supply packaging structure or the preparation method of the above-mentioned back-side power supply packaging structure.

[0016] On the other hand, the present application provides an electronic device, including an electronic component, wherein the electronic component is manufactured using the above-mentioned back-side power supply packaging structure or the preparation method of the above-mentioned back-side power supply packaging structure.

[0017] Based on the above technical solution, this application has the following beneficial effects:

[0018] The back-side power supply packaging structure of the present application includes a bonded chip and an active interposer. The back-side power supply structure is formed on the back side of the first substrate layer and is electrically connected to the first device layer and the first wiring layer in the chip, respectively, and is electrically connected to the first wiring layer in the chip through a second wiring layer formed in the active interposer, so as to electrically connect the back-side power supply structure, the chip, and the active interposer to the packaging substrate based on the first interconnect structure to achieve back-side power supply and signal network communication. The packaging structure transmits signals and power through the active interposer while bonding the chip to provide structural support, significantly improving the mechanical strength of the chip formed by thinning, facilitating chip transportation and substrate packaging processes, and realizing mass production of products. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solution of the present application, the following is a brief introduction to the drawings required for use in the embodiments or prior art descriptions. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0020] Figure 1 : A cross-sectional view of a back-side power supply packaging structure provided in an embodiment of the present application;

[0021] Figure 2 : A cross-sectional view of another back-side power supply packaging structure provided in an embodiment of the present application;

[0022] Figure 3 : A cross-sectional view of another back-side power supply packaging structure provided in an embodiment of the present application;

[0023] Figure 4 : A cross-sectional view of another back-side power supply packaging structure provided in an embodiment of the present application;

[0024] Figure 5 : A schematic diagram of a process for preparing a back-side power supply packaging structure provided in an embodiment of the present application;

[0025] Figure 6 : A cross-sectional view of a first wafer provided in an embodiment of the present application;

[0026] Figure 7 : A cross-sectional view of a second wafer provided in an embodiment of the present application;

[0027] Figure 8-15 :The embodiment of the present application provides a method based on Figure 6-7 Structural cross-section of the wafer during the preparation of the power supply packaging structure;

[0028] Figure 16-22 :Another method based on Figure 6-7Structural cross-section of the wafer during the preparation of the power supply packaging structure;

[0029] Fig.23 : A cross-sectional view of another first wafer provided in an embodiment of the present application;

[0030] Figure 24-31 :The embodiment of the present application provides a method based on Figure 7 and Fig.23 Structural cross-section of the wafer during the preparation of the power supply packaging structure;

[0031] Figure 32-38 :Another method based on Figure 7 and Fig.23 Structural cross-section of the wafer during the preparation of the power supply packaging structure;

[0032] Reference numerals: 100 - chip, 101 - first substrate layer, 102 - first device layer, 102a - first device, 103 - first wiring layer, 103a - first metal layer, 103b - third metal layer, 103c - fourth metal layer, 104 - power rail, 105 - first interlayer dielectric, 106 - fourth interconnect structure, 200 - active interposer, 201 - second substrate layer, 202 - second device layer, 202a - second device, 203 - second wiring layer, 203a - second metal layer, 203b - fifth metal layer, 203c - Sixth metal layer, 204-first interconnection structure, 205-second interlayer dielectric, 300-back power supply structure, 301-back metal layer, 302-second interconnection structure, 303-third interconnection structure, 304-third interlayer dielectric, 400-packaging substrate, 401-first bump structure, 402-filling structure, 403-second bump structure, 500-packaging layer, 600-first wafer, 601-first initial substrate 601, 700-second wafer, 701-second initial substrate 701, 800-carrier, 801-adhesive layer. DETAILED DESCRIPTION

[0033] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0034] It should be noted that in the description of the present application, for the following defined terms, unless a different definition is given in the claims or elsewhere in this specification, these definitions should be applied. All numerical values, whether or not explicitly indicated, are defined herein as being modified by the term "about". The term "about" generally refers to a numerical range that a person of ordinary skill in the art would consider to be equivalent to the stated value to produce substantially the same properties, functions, results, etc. A numerical range indicated by a low value and a high value is defined to include all numerical values ​​included in the numerical range and all subranges included in the numerical range.

[0035] It should be noted that, in the description of the present application, the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0036] It should be noted that, in the description of the present application, the meaning of the terms "on", "above", "above", and "above" should be interpreted in the broadest sense, meaning that the description containing these terms is interpreted as "the component can be set on another component in direct contact, or there can be an intermediate component or layer between the components". In addition, for the convenience of description, the present application may also use spatial relative terms such as "under", "below", "under", "on", "above", "above", "lower", "upper", etc. to describe the relationship between an element or component and another element or component shown in the drawings. In addition to the orientations described in the figures, the spatially relative terms are also intended to cover different orientations of the device in use or operation. The device can be oriented in other ways (rotated 90° or in other orientations), and the spatially relative descriptors used in the present application can be interpreted accordingly.

[0037] The term "layer" as used in this application refers to a portion of a material including an area with a certain thickness. A layer may extend over the entire underlying or superstructure, or may extend over a localized area of ​​the underlying or superstructure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes therebetween. A layer may extend horizontally, vertically and / or along a tapered surface. A layer may include multiple layers. For example, a wiring layer may include one or more doped or undoped semiconductor layers or metal layers, and may have the same or different materials.

[0038] It should be understood that the "surface" used in this application, such as "first surface", "second surface", etc., refers to the XY plane of the chip, active interposer, wafer or packaging substrate, etc., corresponding to the XY plane of the back-powered packaging structure, and the "thickness direction" refers to the Z direction relative to the XY plane.

[0039] The following combination Figure 1-4 The back-side power supply packaging structure of the present application is introduced. It can be understood that the back-side power supply packaging structure in the drawings is only a technical solution of an exemplary embodiment of the present application. The back-side power supply packaging structure of the present application may include fewer or more structural features and is not limited to the device structure described in the drawings. Figure 1-4 , which is a cross-sectional view of a back-side power supply packaging structure provided in an embodiment of the present application.

[0040] like Figure 1-4 As shown, the back-side power supply packaging structure of the embodiment of the present application includes a packaging substrate 400, which is used to integrate the chip 100 and the active interposer 200, realize electrical signal transmission and processing, and provide protection, support and heat dissipation for the chip 100 and the active interposer 200. In one example, the packaging substrate 400 is a PCB (Printed Circuit Board).

[0041] The backside power supply package structure further includes a chip 100 , which includes a first substrate layer 101 , a first device layer 102 and a first wiring layer 103 . The first device layer 102 is formed on the front side of the first substrate layer 101 and is electrically connected to the first wiring layer 103 .

[0042] Specifically, the front side of the first substrate layer 101 corresponds to the front side of the chip 100 (eg Figure 1 The back side of the first substrate layer 101 corresponds to the back side of the chip 100 (eg, Figure 1 The first device layer 102 and the first wiring layer 103 are formed on the front side of the chip 100, and a connection is formed between the first substrate layer 101 and the first device layer 102. Exemplarily, the constituent material of the first substrate layer 101 may include, but is not limited to, at least one of the following materials: silicon or doped silicon, silicon-containing semiconductor materials (such as SiGe, SiC, GaAsP, AlInAs, etc.), compound semiconductors (such as III V group compound semiconductor materials (such as GaAs, etc.)), silicon on insulator (Silicon On Insulator, SOI), or other semiconductor materials that can be device substrates.

[0043] In some embodiments, the first substrate layer 101 is a partial wafer area in a thinned first wafer, that is, the first substrate layer 101 is formed by thinning the back side of the first wafer 600. The first substrate layer is formed by thinning for forming and connecting the back power supply structure, thereby reducing the difficulty of penetrating the back power supply structure and the back power supply spacing, thereby reducing the power supply IR voltage drop and power loss, and optimizing the chip power supply efficiency, power supply performance and heat dissipation performance.

[0044] Specifically, the first wafer 600 formed by the chip preparation process has a first initial substrate 601. The thickness of the first initial substrate 601 is relatively thick to facilitate transportation and process processing. The back side is thinned to a preset thickness to obtain a first substrate layer 101, thereby reducing the difficulty of the preparation process of the back power supply structure 300, avoiding wiring blockage problems in the back-end process, and reducing the IR voltage drop and voltage loss of the back power, thereby improving the power supply efficiency, power supply performance and heat dissipation performance.

[0045] In some embodiments, the thickness of the first substrate layer 101 is 100nm-1000nm; it can be understood that the thickness of the first substrate layer 101 can be any point value within the above range, such as the upper limit of the thickness can be 1000nm, 950nm, 900nm, 850nm, 800nm, 750nm, 700nm, etc., the lower limit of the thickness can be 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, etc., and can also be 500nm, 550nm and other intermediate values. In one example, the thickness of the first substrate is preferably 100nm-700nm. The lateral size of the first substrate layer 101 can be selected based on the chip size requirements and is not limited here. By forming the first substrate layer 101 of the above thickness, the mechanical strength requirements of the package are met, while the packaging density is improved and the difficulty of the back-electrical formation process is reduced.

[0046] Specifically, a power rail (BPR) 104 is formed in the first substrate layer 101, which is used to be electrically connected to the back power supply structure 300 and the first device layer 102 to supply power to the devices in the chip 100, including a power rail (such as VDD) connected to the power supply voltage and a ground power rail (such as VSS). The power rail 104 can be prepared before the formation process of the first device layer 102. In an example, the first device 102a includes a transistor, and the power rail 104 can be connected to the source and drain of the transistor through an interconnection structure for power supply connection.

[0047] In some embodiments, reference Figure 1 and 3, one end of the power rail 104 facing the back power supply structure 300 is buried in the first substrate layer 101, that is, the end of the power rail 104 facing the back side of the chip does not expose the back side of the first substrate layer 101. Accordingly, the power rail 104 and the back power supply structure 300 are electrically connected through the interconnection structure. The buried power rail 104 reduces the amount of substrate thinning, ensures the mechanical strength of the chip package and reduces the power rail thickness requirement. In an example, the buried depth of the power rail 104 in the first substrate layer 101 is 50-200nm, preferably 50nm-100nm. Based on the buried depth setting, the depth of the interconnection structure and the corresponding opening between the power rail 104 and the back power supply structure 300 is reduced, thereby reducing the difficulty of preparation and the power supply distance.

[0048] In some other embodiments, reference Figure 2 and 4 The power rail 104 penetrates the first substrate layer 101 and is connected to the back metal layer 301 in the back power supply structure 300, that is, one end of the power rail 104 facing the back side of the chip is exposed to the back side of the first substrate layer 101, and accordingly, the back power supply structure 300 can be directly formed on the power rail 104. The power rail 104 that penetrates the substrate layer reduces the complexity and difficulty of the interconnection process with the back power supply structure 300, further reduces the power supply distance and power supply resistance, and effectively improves the power supply efficiency.

[0049] Optionally, the material constituting the power rail 104 may include, but is not limited to, at least one of the following materials: Ta, Ti, Al, Mo, Cu, Co, W, TiN, TaN, or other suitable conductive materials.

[0050] Specifically, the first device layer includes a first device 102a, and the first device 102a can be an active device, such as a transistor, a diode, etc., or a capacitor, a resistor, etc. In one example, referring to Figure 1-4 , the first device 102a includes a transistor.

[0051] Specifically, the first wiring layer 103 can be used to form electrical connections between the first devices 102a and / or components in the first device layer 102, the electrical connections between the first device layer 102 and the active interposer 200, and the electrical connections with the back power supply structure 300, so that each device and / or component can be operated as needed, perform signal transmission, and realize back-side power supply; wherein the component can be, for example, a gate structure, a source or a drain, etc. A plurality of metal layers stacked in sequence can be formed in the first wiring layer 103, each metal layer includes one or more wires, and some metal layers are arranged horizontally along the xy plane, such as Figure 1-4As shown in FIG. 1 , the first metal layer 103a exposed on the surface of the chip 100 and the third metal layer 103b buried in the chip 100, part of the metal layers are arranged vertically along the z direction to form electrical connections between different metal layers, such as Figure 1-4 The fourth metal layer 103c shown in FIG. 1 , the vertically arranged metal layer can be prepared by metal filling in the formed interconnection line through hole. It can be understood that Figure 1-4 Only a simplified structure of the first wiring layer 103 is shown, which may include more metal layers to achieve electrical connection and signal transmission wiring within the chip 100.

[0052] Optionally, the constituent material of the first wiring layer 103 may include but is not limited to at least one of the following materials: Ta, Ti, Al, Mo, Cu, Co, W, TiN, TaN, or other suitable conductive materials.

[0053] Specifically, the chip 100 may further include a first interlayer dielectric 105 covering the first device 102a, the metal layer and the power rail 104, etc., and is used for isolating different devices, different metal layers and different power rails 104, and one side of the first metal layer 103a is exposed to the surface of the first interlayer dielectric 105.

[0054] Specifically, the first interlayer dielectric 105 is formed of a dielectric material that provides good isolation for the first device 102a, the metal layer or the power rail 104. Optionally, the constituent material of the first interlayer dielectric 105 may include, but is not limited to, at least one of the following materials: silicon oxide, silicon nitride, silicon oxynitride, oxide formed by TEOS, PSG, BPSG, low-k dielectric material, or other suitable dielectric materials, and may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD) or a combination thereof.

[0055] The back-side power supply packaging structure also includes an active interposer 200, which is located between the packaging substrate 400 and the chip 100 and is bonded to one side of the first device layer 102. The active interposer 200 is formed by a second wafer 700 including an interposer chip 100. The functional components of the packaging structure are formed by bonding the chip 100. Compared with the prior art in which the back-end process is directly performed on the same chip wafer to form a back-side power supply structure, the packaging structure of the present application uses an interposer to bond with the chip 100 and further forms a back-side power supply structure 300, thereby improving the mechanical strength and packaging feasibility of the overall functional components, and avoiding cutting damage, packaging damage or fracture caused by a single wafer being too thin after the back-end process. Specifically, the above-mentioned bonding is bump-free bonding, preferably bonding.

[0056] A second wiring layer 203 electrically connected to the first wiring layer 103 and a first interconnect structure 204 electrically connected to the second wiring layer 203 are formed in the active interposer 200. One end of the first interconnect structure 204 facing the packaging substrate 400 passes through the active interposer 200 and is electrically connected to the packaging substrate 400. An electrical connection is formed among the chip 100, the active interposer 200 and the packaging substrate 400 through the first wiring layer 103, the second wiring layer 203 and the first interconnect structure 204, thereby realizing power supply, signal transmission and system operation.

[0057] Specifically, the active interposer 200 further includes a second substrate layer 201 and a second device layer 202. The second device layer 202 is formed on the front side of the second substrate layer 201 and is electrically connected to the second wiring layer 203. The front side of the second substrate layer 201 corresponds to the front side of the active interposer 200 (eg, Figure 1 The back side of the second substrate layer 201 corresponds to the back side of the active interposer 200 (eg, Figure 1 The second device layer 202 and the second wiring layer 203 are formed on the front side of the active interposer 200, and a connection is formed between the second substrate layer 201 and the second device layer 202. Exemplarily, the constituent material of the second substrate layer 201 may include but is not limited to at least one of the following materials: silicon or doped silicon, silicon-containing semiconductor materials (such as SiGe, SiC, GaAsP, AlInAs, etc.), compound semiconductors (such as III V compound semiconductor materials (such as GaAs, etc.)), silicon on insulator (SOI), or other semiconductor materials that can be device substrates. The chip 100 is bonded to the active interposer 200 with the second substrate layer 201 to achieve packaging, thereby improving the reliability and yield of the packaging process, and facilitating the realization of back-side power supply packaging.

[0058] In some embodiments, the thickness of the second substrate layer 201 is 75-150 μm; it is understandable that the thickness of the second substrate layer 201 can be any point value within the above range, such as the upper limit of the thickness can be 150 μm, 140 μm, 130 μm, 120 μm, etc., the lower limit of the thickness can be 75 μm, 80 μm, 85 μm, 90 μm, etc., and can also be 110 μm, 100 μm and other intermediate values. In one example, the thickness of the second substrate is preferably 75-120 μm. The lateral size of the second substrate layer 201 can be selected based on the chip size requirements and is not limited here. By forming the second substrate layer 201 of the above thickness, the packaging mechanical strength requirements are met while the packaging density is improved and the transmission distance is reduced.

[0059] Specifically, a second device 202a is formed in the second device layer 202. The second device 202a may be an active device, such as a transistor, a diode, etc., or a capacitor, a resistor, etc. In one example, referring to Figure 1-4 , the second device 202a includes a transistor.

[0060] Specifically, the second wiring layer 203 can be used to form electrical connections between the second devices 202a and / or components in the second device layer 202, the electrical connections between the second device layer 202 and the chip 100, and the electrical connections with the back power supply structure 300, so that each device and / or component can be operated as needed, perform signal transmission and realize back-side power supply; wherein the component can be, for example, a gate structure, a source or a drain. Similar to the first wiring layer 103, a plurality of metal layers stacked in sequence can be formed in the second wiring layer 203, each metal layer includes one or more wires, and some metal layers are arranged horizontally along the xy plane, such as Figure 1-4 As shown in the second metal layer 203a exposed on the surface of the active interposer 200 and the fifth metal layer 203b buried in the active interposer 200, some metal layers are arranged vertically along the z direction to form electrical connections between different metal layers, such as Figure 1-4 The sixth metal layer 203c shown in FIG. 1 , the vertically arranged metal layer can be prepared by performing metal filling in the formed interconnection line through hole. It can be understood that Figure 1-4 Only a simplified structure of the second wiring layer 203 is shown, which may include more metal layers to achieve electrical connection and signal transmission wiring within the active interposer 200 .

[0061] Specifically, the first metal layer 103a in the first wiring layer 103 is exposed to the front side surface of the chip 100, the second metal layer 203a is exposed to the front side surface of the active interposer 200, and the second metal layer 203a is bonded to the first metal layer 103a, and the electrical connection between the first wiring layer 103 and the second wiring layer 203 is formed by bonding, thereby realizing the electrical connection between the chip 100 and the active interposer 200, the back power supply structure 300 and the active interposer 200, and the chip 100 and the package substrate 400. The above bonding is bumpless bonding, preferably bonding.

[0062] Optionally, the constituent material of the second wiring layer 203 may include but is not limited to at least one of the following materials: Ta, Ti, Al, Mo, Cu, Co, W, Ag, Au, TiN, TaN, or other suitable conductive materials.

[0063] Specifically, the chip 100 may also include a second interlayer dielectric 205 covering the second device 202a, the metal layer and the first interconnect structure 204, etc., for isolating different devices, different metal layers and different first interconnect structures 204, and one side of the second metal layer 203a is exposed to the surface of the second interlayer dielectric 205.

[0064] Specifically, the second interlayer dielectric 205 is formed of a dielectric material that provides good isolation for the second device 202a, the metal layer or the first interconnect structure 204. Optionally, the constituent material of the second interlayer dielectric 205 may include, but is not limited to, at least one of the following materials: silicon oxide, silicon nitride, silicon oxynitride, oxide formed by TEOS, PSG, BPSG, low-k dielectric material, or other suitable dielectric materials, which may be formed by CVD, ALD, or a combination thereof.

[0065] Specifically, the first interconnect structure 204 pre-buried in the active interposer 200 is used to electrically connect the package substrate 400 and the second wiring layer 203, and it passes through the second device layer 202 and penetrates the second substrate layer 201. In some embodiments, the first interconnect structure 204 includes a first deep conductive via extending in the z direction and a first conductive structure filled in the first deep conductive via, the first deep conductive via passes through the second device layer 202 and the second substrate layer 201, and is pre-buried in the second wafer 700 for providing the active interposer 200; in one example, the first deep conductive via is a through silicon via (TSV). One end of the first conductive structure is buried in the second interlayer dielectric 205 and extends to the second wiring layer 203, and the other end passes through the second substrate layer 201 and is electrically connected to the package substrate 400, so as to form an electrical connection between the second wiring layer 203 and the package substrate 400, and its constituent material may include but is not limited to at least one of the following materials: Ta, Ti, Al, Mo, Cu, Co, W, Ag, Au, or other suitable conductive materials. In some embodiments, the first interconnect structure 204 also includes a first barrier layer formed on the sidewall of the first deep conductive via to isolate the first conductive structure from the sidewall of the first deep conductive via; the constituent material of the first barrier layer may be an insulating material, such as silicon oxide, silicon oxynitride, etc., and the formation of the first barrier layer can repair edge surface damage formed when etching the second substrate layer 201 and the second interlayer dielectric 205 to form the first deep conductive via, and form electrical isolation.

[0066] The back-side power supply packaging structure also includes a plurality of first bump structures 401 formed between the first interconnect structure 204 and the packaging substrate 400 and arranged at intervals in the xy plane, which are used to connect the packaging substrate 400 and the active interposer 200 and realize electrical connection. The interposer integration and connection are realized based on the first bump structure 401, which can reduce the size of the packaging structure and effectively increase the number of I / O ports.

[0067] Optionally, the material of the first bump structure 401 may include but is not limited to copper, nickel, aluminum, palladium, gold, silver, tin, etc. or a combination of multiple thereof, or other alternative conductive materials. Preferably, the material of the first bump structure 401 includes tin.

[0068] Optionally, the first bump structure 401 may be, but is not limited to, a ball grid array (BGA), a solder ball, a controlled collapse chip connection (C4) or a micro bump (Chip Connection, C2), etc., preferably a micro bump.

[0069] The backside power supply packaging structure also includes a filling structure 402 formed between the packaging substrate 400 and the active interposer 200, and the filling structure 402 is used to fill the gap between the packaging substrate 400 and the active interposer 200. Specifically, the filling structure 402 covers the first bump structure 401. The filling structure 402 strengthens the connection between the active interposer 200, the packaging substrate 400, and the first bump structure 401, alleviates the stress concentration problem introduced by the mismatch of the thermal expansion coefficient, and improves the temperature, humidity and impact resistance, improves the packaging reliability and reduces vibration noise.

[0070] Optionally, the constituent material of the filling structure 402 may include an adhesive, which may specifically include but is not limited to at least one of the following materials: epoxy resin, modified epoxy resin, polyimide resin, or other alternative adhesive materials. The constituent material of the filling structure 402 may also include auxiliary components such as fillers, hardeners, adhesion promoters, flame retardants, and dispersants.

[0071] The back-side power supply package structure also includes a plurality of second bump structures 403, which are arranged at intervals on the side of the package substrate 400 away from the active interposer 200, for electrical interconnection between the package substrate 400 and other devices. The material of the second bump structure 403 may include but is not limited to copper, nickel, aluminum, palladium, gold, silver, tin, etc. or a combination of multiple thereof, or other alternative conductive materials. Preferably, the material of the second bump structure 403 includes tin. Optionally, the second bump structure 403 may be but is not limited to a ball array, a solder ball or a controlled collapse chip 100 connection, etc.

[0072] The back-side power supply packaging structure further includes a back-side power supply structure 300, which is formed on the back side of the first substrate layer 101 and is electrically connected to the first device layer 102 and the first wiring layer 103. The back-side power supply structure 300 is formed in the back-end process of the packaging structure to supply power to the chip 100, and supplies power to the active interposer 200 through the connection between the first wiring layer 103 and the second wiring layer 203.

[0073] Specifically, the back power supply structure 300 may also include a third interlayer dielectric 304, which at least covers the sidewalls of the back metal layer 301 and its related interconnection structure, etc., and is used for isolation between different back metal layers 301 and different interconnection structures. The third interlayer dielectric 304 is formed of a dielectric material that provides good isolation for the back metal layer 301 or the interconnection structure. Optionally, the constituent material of the third interlayer dielectric 304 may include, but is not limited to, at least one of the following materials: silicon oxide, silicon nitride, silicon oxynitride, oxide formed by TEOS, PSG, BPSG, low-k dielectric material, or other suitable dielectric materials, which may be formed by CVD, ALD, or a combination thereof.

[0074] In some embodiments, reference Figure 3 and Figure 4 The back power supply structure 300 includes a back metal layer 301, and the back metal layer 301 is electrically connected to the first device layer 102 and the first wiring layer 103 through the power rail 104. The power rail 104 serves as a connecting intermediate between the back power supply structure 300 and the first wiring layer 103, and the back power supply structure 300 and the first wiring layer 103 are not directly connected. The power rail 104 is connected between the first device layer 102 and the back power supply structure 300, and between the first wiring layer 103 and the back power supply structure 300. The power rail 104 is electrically connected to the first device 102a, and is electrically connected to the first wiring layer 103 through a fourth interconnect structure 106 pre-formed between the power rail 104 and the first wiring layer 103 and extending in the z direction. The power rail 104 is formed through the front-end process to perform the subsequent back electrical connection between the first device layer 102 and the first wiring layer 103, avoiding the deep conductive via process that penetrates the first substrate layer 101, and reducing the process complexity of the back-end process.

[0075] In one example, refer to Figure 3 , one end of the power rail 104 facing the back power supply structure 300 is buried in the first substrate layer 101, and the back power supply structure 300 also includes a third interconnect structure 303 extending from the back metal layer 301 and extending into the first substrate layer 101 and connected to the power rail 104, which is used to electrically connect the back metal layer 301 and the power rail 104. The third interconnect structure 303 can be formed by at least opening a hole from the back side of the first substrate layer 101 to form a recessed structure, etching a barrier layer to expose the power rail 104 from the back side of the first substrate layer 101, and filling with a conductive material. The third interconnect structure 303 is exposed to the back side of the first substrate layer 101, and a back metal layer 301 is formed thereon to achieve electrical connection. By burying the protection power rail 104, the transport conditions are reduced and the oxidation of the power rail and other problems are avoided. Combined with the setting of the burying depth, the opening depth requirement of the third interconnect structure and the filling cost of the conductive material are reduced, and the reliability and preparation cost of the back power supply are synergistically improved.

[0076] In another example, refer to Figure 4 The power rail 104 passes through the first substrate layer 101 and is connected to the back metal layer 301. The back metal layer 301 is directly formed on the back side of the first substrate layer 101 to connect to the power rail 104 exposed on the back side of the first substrate layer 101 and realize power supply, thereby eliminating the formation process of the third interconnect structure 303, reducing the difficulty and complexity of back power preparation, and reducing the electrical connection distance.

[0077] In some other embodiments, reference Figure 1 and Figure 2 The back power supply structure 300 includes a back metal layer 301 and a second interconnect structure 302 extending from the back metal layer 301 and penetrating through the first substrate layer 101 and connected to the first wiring layer 103; the back metal layer 301 is electrically connected to the first device layer 102 through the power rail 104, and is electrically connected to the first wiring layer 103 through the second interconnect structure 302. A power rail 104 electrically connected to the first device 102a is connected between the first device layer 102 and the back power supply structure 300 to realize power supply connection to the first device layer 102, and the second interconnect structure 302 extending in the z direction formed in the back-end process is electrically connected to the first wiring layer 103. The second interconnect structure 302 is formed in the back-end process to realize the back electrical connection of the first wiring layer 103, thereby reducing the network design requirements and occupied volume of the power rail 104 in the front-end process.

[0078] Specifically, the diameter of the second interconnect structure 302 can be 10-200nm. It can be understood that the diameter of the second interconnect structure 302 can be any point value within the above range, such as the upper limit of the diameter can be 200nm, 180nm, 160nm, 140nm, 120nm, 100nm, 80nm, etc., the lower limit of the diameter can be 10nm, 20nm, 30nm, 40nm, etc., and can also be 50μm, 60μm and other intermediate values. In one example, the thickness of the second substrate is preferably 30-80nm. Based on the thinning formation method of the first substrate layer, the opening depth required for the second interconnect structure is reduced, so that its diameter can be miniaturized to the above range, and the opening aperture requirements and metal filling amount are reduced under the premise of ensuring the power supply voltage, thereby improving the preparation efficiency.

[0079] Specifically, the second interconnect structure 302 is formed in the back-end process, which is buried in the third interlayer dielectric 304 and extends to the first substrate layer 101 until it penetrates the first substrate layer 101 and then extends into the first interlayer dielectric 105. In some embodiments, the second interconnect structure 302 includes a second deep conductive via extending in the z direction and a second conductive structure filled in the second deep conductive via, the second deep conductive via passes through the first device layer 102 and the first substrate layer 101 and then extends to the first wiring layer 103, and is formed in the first wafer 600 providing the chip 100; in one example, the second deep conductive via is a through silicon via. One end of the second conductive structure is electrically connected to the back metal layer 301, and the other end passes through the first substrate layer 101 and extends to the first wiring layer 103, which is used to form an electrical connection between the first wiring layer 103 and the back power supply structure 300, and its constituent material may include but is not limited to at least one of the following materials: Ta, Ti, Al, Mo, Cu, Co, W, TiN, TaN, or other suitable conductive materials. In some embodiments, the second interconnect structure 302 further includes a second barrier layer formed on the sidewall of the second deep conductive via, isolating the second conductive structure from the sidewall of the second deep conductive via; the constituent material of the second barrier layer may be an insulating material, such as silicon oxide, silicon oxynitride, etc., and the formation of the second barrier layer can repair the edge surface damage formed when etching the third interlayer dielectric 304, the first substrate layer and the first interlayer dielectric 105 to form the second deep conductive via, and form electrical isolation. It can be understood that the first substrate layer 101 is formed by thinning the back side of the wafer, and the thinner substrate layer thickness significantly reduces the process difficulty of penetrating the first substrate layer 101 when opening the second deep conductive via, and reduces the radial size and depth requirements of the opening, thereby reducing the amount of second conductive material filling, while avoiding the wiring blockage problem caused by the via being too deep, and improving the reliability of back power supply.

[0080] In one example, refer to Figure 1 , one end of the power rail 104 facing the back power supply structure 300 is buried in the first substrate layer 101, and the power rail 104 is electrically connected to the back metal layer 301 through the third interconnect structure 303 formed in the back-end process. Figure 2 The power rail 104 penetrates the first substrate layer 101 and is connected to the back metal layer 301. The back metal layer 301 is directly formed on the back side of the first substrate layer 101 to connect to the power rail 104 exposed to the back side of the first substrate layer 101 and realize power supply.

[0081] The back power supply packaging structure also includes a packaging layer 500 formed on the side of the back power supply structure 300 away from the first substrate layer 101 to achieve the interconnection strength between the back power supply structure and the second substrate layer, and facilitate the transportation and subsequent processes of the intermediate structure during the preparation process.

[0082] The following combination Figure 1-38The following describes a method for preparing a back-side power supply packaging structure provided in an embodiment of the present application. Figure 5 It is a flow chart of the preparation method of the back-side power supply packaging structure. This specification provides method operation steps such as the embodiments or flow charts, but more or fewer operation steps may be included based on conventional or non-creative labor. The order of steps listed in the embodiments is only one way of executing the order of many steps and does not represent the only execution order. When the actual preparation method is executed, it can be executed in the order of the methods shown in the embodiments or the drawings or in parallel. The preparation method of the back-side power supply packaging structure may include S11-S15:

[0083] S11 : providing a package substrate 400 , a first wafer 600 on which a chip 100 is formed, and a second wafer 700 on which an active interposer 200 is formed.

[0084] refer to Figure 6 and 23 The first wafer 600 can be a logic wafer (such as a central processing unit (CPU), a graphics processing unit (GPU), a system on chip (SoC), an application processor (AP), a microcontroller, an ASIC, an FPGA, etc.), a memory die (such as a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, a non-volatile memory (NVM), etc.), a radio frequency (RF) wafer, a sensor wafer, a microelectromechanical system (MEMS) wafer, a signal processing wafer (such as a digital signal processing (DSP) wafer, etc.), a front-end wafer (such as an analog front-end (AFE) wafer), etc., or a combination thereof.

[0085] The first wafer 600 may include a plurality of chips 100 that can be cut and formed in subsequent steps, each chip 100 includes a first initial substrate 601, a first device layer 102, and a first wiring layer 103, the first device layer 102 is formed on the front side of the first initial substrate 601 and is electrically connected to the first wiring layer 103; the first initial substrate 601, the first device layer 102, and the first wiring layer 103 of each chip 100 are formed in the first wafer 600 in sequence based on their own processes. It can be understood that in order to ensure that the wafer has the mechanical strength to meet the requirements of the transportation process, it is necessary to ensure that the first initial substrate 601 has a large thickness to avoid problems such as transportation or bonding damage and breakage.

[0086] Specifically, the first wafer 600 has a first surface and a second surface opposite to each other, the first surface corresponds to the front side of the first wafer 600 , and the second surface corresponds to the back side of the first wafer 600 .

[0087] refer to Figure 7The second wafer 700 is an interposer wafer, and is formed with an active interposer 200 for bonding with the front side of the chip 100. The active interposer 200 is formed with an electrically connected second wiring layer 203 and a first interconnect structure 204, and the first interconnect structure 204 penetrates the active interposer 200 toward one end of the package substrate 400, as well as a second device layer 202 including active devices and a second initial substrate 701 for being thinned to form a second substrate layer 201.

[0088] The first interconnect structure 204 including the first deep conductive via, the first conductive structure and the first barrier layer is pre-formed in the second wafer 700, extending from the second wiring layer 203 and passing through the second device layer 202 and then extending into the second initial substrate 701, and is not exposed to the back side of the second initial substrate 701, and is used for subsequent back side thinning and exposure to electrically connect to the packaging substrate 400. In one example, the first deep conductive via can be formed in the second initial substrate 701 by, for example, etching, grinding, laser technology or a combination thereof; then, a dielectric material can be formed in the first deep conductive via by, for example, oxidation technology, and then, a conductive material can be deposited in the first deep conductive via to form a first barrier layer by, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation or a combination thereof, so as to cover the sidewalls and bottom wall of the first deep conductive via; then, a conductive material can be deposited on the first barrier layer by electrochemical plating process, CVD, PVD or a combination thereof to fill the first deep conductive via and form a first conductive structure electrically connected to the second wiring layer 203. Specifically, during the formation process, excess conductive material and the barrier layer may be removed by a process such as chemical mechanical polishing (CMP).

[0089] Optionally, the constituent material of the first barrier layer may include at least one of the following materials: titanium nitride, titanium oxynitride, tantalum nitride, tantalum oxynitride, tungsten nitride, nitride, oxynitride, or other alternative materials.

[0090] Specifically, the second wafer 700 has a third surface and a fourth surface that are opposite to each other. The third surface corresponds to the front side of the second wafer 700 , and the fourth surface corresponds to the back side of the second wafer 700 .

[0091] S12 : bonding the first surface of the first wafer 600 to the second wafer 700 , so that the active interposer 200 is bonded to one side of the first device layer 102 , and the second wiring layer 203 is electrically connected to the first wiring layer 103 .

[0092] The first surface of the front side of the first wafer 600 and the third surface of the front side of the second wafer 700 are connected without bumps, and preferably can be bonded. Figure 8 and 24, the first wafer 600 is bonded to the second wafer 700 by hybrid bonding, the first metal layer 103a exposed on the first surface is bonded to the second metal layer 203a exposed on the third surface, so as to electrically connect the first wiring layer 103 and the second wiring layer 203, and the first interlayer dielectric 105 and the second interlayer dielectric 205 are bonded; the bonding process may include at least pre-bonding and annealing, etc. Specifically, at low temperature, a certain pressure is applied to press the first wafer 600 and the second wafer 700 against each other, so that the first metal layer 103a and the second metal layer 203a form a preliminary bond and the first interlayer dielectric 105 and the second interlayer dielectric 205 form a preliminary bond, and then annealing is performed to improve the bonding strength.

[0093] S13: Thinning the first wafer 600 from the second surface thereof to thin the first initial substrate 601 to the first substrate layer 101. The first wafer 600 may be thinned from the back side thereof to approach or expose the power rail 104 by at least grinding or lapping processes to form the first substrate layer 101 of the chip 100. The thickness of the back side of the first wafer 600 is reduced by thinning, thereby reducing the difficulty and complexity of the electrical connection process between the back power supply structure and the power rail 104 and the first wiring layer 103, and improving the back power transmission and thermal management performance.

[0094] In one example, refer to Fig.16 and 32 The power rail 104 penetrates the first substrate layer 101 and is used to connect with the back metal layer 301 . Accordingly, S13 includes: thinning the second surface of the first wafer 600 to expose the power rail 104 to form the first substrate layer 101 .

[0095] In another example, refer to Fig. 9 and Fig.25 One end of the power rail 104 is buried in the first substrate layer 101 . Accordingly, S13 includes: thinning the second surface of the first wafer 600 to near the power rail 104 to form the first substrate layer 101 .

[0096] S14: forming a back side power supply structure 300 electrically connected to the first device layer 102 and the first wiring layer 103 on the back side of the first substrate layer 101 .

[0097] After the back side of the first wafer 600 is thinned, Fig.10 , 17, 26 and 33, a third interlayer dielectric 304 and a back side power supply structure 300 including a back side metal layer 301 are formed on the surface exposed after thinning, and the back side power supply structure 300 is electrically connected to the first device 102a and the first wiring layer 103, and is coupled to the active interposer 200 and the packaging substrate 400 through the first wiring layer 103 and the second wiring layer 203 to realize back side power supply.

[0098] A power rail 104 is formed in the first substrate layer 101 . In combination with different arrangements of the power rail 104 , the components and the forming process of the back side power supply structure 300 are different.

[0099] In some embodiments, reference Figure 6-22 The first device layer 102 and the first wiring layer 103 are electrically connected to the power rail 104 respectively. The power rail 104 is used as a connecting intermediate between the back power supply structure 300 and the first wiring layer 103 and the back power supply structure 300 and the first device layer 102. The power rail 104 is connected between the first device layer 102 and the back power supply structure 300 and between the first wiring layer 103 and the back power supply structure 300.

[0100] Accordingly, in one example, one end of the power rail 104 is buried in the first substrate layer 101, referring to Figure 6-15 , the back power supply structure 300 can be formed in the following manner:

[0101] S21: forming a recessed structure extending into the first substrate layer 101 and extending to the power rail 104 from the back side of the first substrate layer 101, and filling the recessed structure with a conductive material to form a third interconnection structure 303 connected to the power rail 104, for electrically connecting the back metal layer 301 and the power rail 104;

[0102] S22 : forming a back metal layer 301 electrically connected to the power rail 104 on the back side of the first substrate layer 101 , and the back metal layer 301 is electrically connected to the first device layer 102 and the first wiring layer 103 through the power rail 104 .

[0103] The first substrate layer 101 can be patterned and etched at least by a photolithography process to form a recessed structure, and then a third interconnect structure 303 can be formed by at least filling the recessed structure with a conductive material, and then a back metal layer 301 bonded to the third interconnect structure 303 is formed by dielectric layer deposition, patterning and etching, metal deposition and other techniques; a back metal layer connection is formed based on the embedded power rail 104 and the third interconnect structure 303, thereby reducing the pre-embedded depth requirement of the power rail 104 and the thinning amount of the first wafer 600, and avoiding problems such as exposure contamination and oxidation of the power rail.

[0104] In another example, the power rail 104 runs through the first substrate layer 101, and one end thereof facing the back side of the first substrate layer 101 is exposed outside the back side of the first substrate layer 101, referring to Figure 6 and 16-22, the back power supply structure 300 can be formed in the following manner: a back metal layer 301 electrically connected to the power rail 104 is formed on the back side of the first substrate layer 101, the back metal layer 301 is electrically connected to the first device layer 102 and the first wiring layer 103 respectively through the power rail 104, and the back metal layer 301 connected to the power rail 104 is directly formed on the back side of the first substrate, without the need to open a substrate layer or form an electrical connection intermediate component, thereby reducing the process complexity and the back power supply transmission distance, further reducing IR voltage drop, voltage loss and power consumption.

[0105] In some other embodiments, reference Figure 23-38 The first device layer 102 is electrically connected to the power rail 104 to achieve power supply connection to the first device layer 102 , and the first wiring layer 103 is electrically connected to the back power supply structure 300 through the second interconnect structure 302 .

[0106] Accordingly, in one example, one end of the power rail 104 is buried in the first substrate layer 101, referring to Figure 23-31 , the back power supply structure 300 can be formed in the following manner:

[0107] S41: forming a recessed structure extending into the first substrate layer 101 and extending to the power rail 104 from the back side of the first substrate layer 101, and filling the recessed structure with a conductive material to form a third interconnection structure 303 connected to the power rail 104, for electrically connecting the back metal layer 301 and the power rail 104;

[0108] S42: forming a through hole penetrating the first substrate layer 101 and extending to the first wiring layer 103 from the back side of the first substrate layer 101, and filling the through hole with metal to form a second interconnect structure 302 connected to the first wiring layer 103;

[0109] S43: A back metal layer 301 electrically connected to the power rail 104 and the second interconnect structure 302 is formed on the back side of the first substrate layer 101. The back metal layer 301 is electrically connected to the first device layer 102 through the power rail 104 and to the first wiring layer 103 through the second interconnect structure 302.

[0110] A third interconnect structure 303 extending into the first substrate layer 101 and a second interconnect structure 302 penetrating the first substrate layer 101 and extending to the first wiring layer 103 are formed on the back side of the first substrate layer 101 to improve the electrical connection reliability between the back metal layer 301 and the power rail 104 and the first wiring layer 103.

[0111] In another example, the power rail 104 runs through the first substrate layer 101. Fig.23 , 24 and 32-38, the back power supply structure 300 can be formed in the following manner:

[0112] S31: forming a through hole penetrating the first substrate layer 101 and extending to the first wiring layer 103 from the back side of the first substrate layer 101, and filling the through hole with metal to form a second interconnect structure 302 connected to the first wiring layer 103;

[0113] S32: A back metal layer 301 electrically connected to the power rail 104 and the second interconnect structure 302 is formed on the back side of the first substrate layer 101. The back metal layer 301 is electrically connected to the first device layer 102 through the power rail 104 and to the first wiring layer 103 through the second interconnect structure 302.

[0114] The first substrate layer 101 can be patterned and etched at least by photolithography process to form a through hole, and then the second interconnect structure 302 can be formed by at least filling the through hole with a conductive material, and then the back metal layer 301 connected to the second interconnect structure 302 and the power rail 104 can be formed by dielectric layer deposition, patterning and etching, metal deposition and other technologies; based on the through-type power rail 104 and the second interconnect structure 302, the back metal layer 301, the first device layer 102, and the first wiring layer 103 are electrically connected, the layout requirements and volume occupancy of the power rail 104 are reduced, and at the same time, the electrical connection nodes between the first wiring layer 103 and the back metal layer 301 are reduced, thereby improving the power transmission performance.

[0115] Furthermore, before S15, the preparation method also includes forming a packaging layer 500 on the side of the back power supply structure 300 away from the first substrate layer 101, and the packaging layer 500 is stacked on the side of the back power supply structure 300 away from the first substrate layer 101, for realizing structural plastic sealing, strengthening the interconnection between the back power supply structure 300 and the first substrate layer 101, improving the reliability of the back power supply packaging structure, and enhancing the heat dissipation and shock resistance of the back power supply packaging structure, and reducing signal noise; and because the second substrate layer is thinner after thinning, the mechanical strength of the overall intermediate structure is reduced, the packaging layer 500 can enhance the mechanical strength of the structure to facilitate subsequent transportation, cutting and packaging substrate connection, etc.

[0116] Specifically, the encapsulation layer 500 can be made of a plastic encapsulation material or a flexible encapsulation substrate 400 material, such as but not limited to epoxy molding compound (EMC), Ajinomoto build up film (ABF), polyimide (PI), etc., or other alternative materials that can be cured into layers can be used.

[0117] S15: electrically connecting the first interconnect structure 204 to the packaging substrate 400 to form the backside power supply packaging structure.

[0118] One end of the first interconnect structure 204 facing the package substrate 400 penetrates the active interposer 200 and is electrically connected to the package substrate 400 to achieve electrical connection among the backside power supply structure 300 , the chip 100 , the active interposer 200 and the package substrate 400 .

[0119] In some embodiments, S15 may include the following steps S151-S153:

[0120] S151: forming a substrate attachment structure electrically connected to the first interconnect structure 204 on one side of the second wafer 700 where the first interconnect structure 204 is formed, to obtain a wafer-level packaging structure;

[0121] S152: cutting the wafer-level packaging structure to obtain an initial packaging structure;

[0122] S153: Connecting the initial packaging structure to the packaging substrate 400 through a substrate attachment structure to form a back-side power supply packaging structure.

[0123] refer to Fig.12 , 19, 28 and 35, after forming the back power supply structure 300 and / or the packaging layer 500, the formed packaging structure is turned over to bond one side of the back power supply structure 300 to the carrier 800 and process the back side of the second wafer 700 to form a substrate attachment structure to obtain a wafer-level packaging structure (such as Fig.14 , 21, 30 and 37). The carrier 800 is used to provide packaging support, chip 100 protection, etc., and can be but not limited to a glass carrier, a ceramic carrier, a metal carrier, etc. An adhesive layer can be formed on the carrier 800 to facilitate the attachment of the first wafer 600.

[0124] In some embodiments, forming a substrate attachment structure electrically connected to the first interconnect structure 204 on a side of the second wafer 700 on which the first interconnect structure 204 is formed may specifically include: thinning the side of the second wafer 700 on which the first interconnect structure 204 is formed until the first interconnect structure 204 is exposed; and forming a substrate attachment structure at the exposed end of the first interconnect structure 204.

[0125] refer to Figure 13-15 , 20-22, 29-31 and 36-38, thinning the second initial substrate 701 from the back side of the second wafer 700 to expose the first interconnect structure 204 and forming a dielectric layer thereon, and then forming a substrate attachment structure bonded to the dielectric layer on the dielectric layer, the substrate attachment structure may include a first bump structure 401 to facilitate connection to the package substrate 400; then peeling off the carrier 800 and cutting the wafer-level packaging structure (such as the first wafer 600 and the second wafer 700) formed based on the needs and the chip 100 arrangement Fig.15, 22, 31 and 38), to obtain an initial packaging structure that can be transported and combined with the packaging substrate 400, and further connected to the packaging substrate 400 to form the back-side power supply packaging structure as described above (reference Figure 1-4 ).

[0126] After attaching the packaging substrate 400 , a filling structure 402 covering the substrate attachment structure and connected to the second substrate layer 201 may be formed on the packaging substrate 400 to enhance the connection and alleviate problems such as thermal mismatch.

[0127] It can be understood that the above-mentioned back side power supply packaging structure embodiment and the embodiment of the method for preparing the back side power supply packaging structure are based on the same application concept, and the back side power supply packaging structure can be prepared by using the above-mentioned method for preparing the back side power supply packaging structure.

[0128] Correspondingly, the present application also provides an electronic device, which is manufactured using the above-mentioned back-side power supply packaging structure or the preparation method of the above-mentioned back-side power supply packaging structure.

[0129] Correspondingly, the present application provides an electronic device, including an electronic component, wherein the electronic component is manufactured using the above-mentioned back-side power supply packaging structure or the preparation method of the above-mentioned back-side power supply packaging structure.

[0130] The electronic device of the embodiment of the present application can be selected from any electronic product or equipment such as a mobile phone, a personal digital assistant (PDA), a tablet computer (pad), a laptop computer, a game console, a television, a video compact disc (VCD), a digital video disc (DVD), a navigator, a camera, a camcorder, a voice recorder, an MP3, an MP4, a handheld game console (PlayStation Portable, PSP), etc., and can also be any intermediate product of an electronic device made of the above-mentioned back-side power supply packaging structure.

[0131] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0132] The above description has fully disclosed the specific implementation methods of the present application. It should be pointed out that any changes made by technicians familiar with the field to the specific implementation methods of the present application do not deviate from the scope of the claims of the present application. Accordingly, the scope of the claims of the present application is not limited to the above specific implementation methods.

Claims

1. A back-side power supply packaging structure, characterized in that: include: Package substrate, A chip, comprising a first substrate layer, a first device layer and a first wiring layer, wherein the first device layer is formed on the front side of the first substrate layer and is electrically connected to the first wiring layer; a back power supply structure, formed on the back side of the first substrate layer and electrically connected to the first device layer and the first wiring layer respectively; An active interposer is located between the packaging substrate and the chip and is bonded to one side of the first device layer. A second wiring layer electrically connected to the first wiring layer and a first interconnect structure electrically connected to the second wiring layer are formed in the active interposer. The first interconnect structure passes through the active interposer toward one end of the packaging substrate and is electrically connected to the packaging substrate.

2. The back side power supply packaging structure according to claim 1, characterized in that: A power rail is formed in the first substrate layer, and the back power supply structure includes a back metal layer. The back metal layer is electrically connected to the first device layer and the first wiring layer respectively through the power rail.

3. The back side power supply packaging structure according to claim 1, characterized in that: A power rail is formed in the first substrate layer, and the back power supply structure includes a back metal layer and a second interconnect structure extending from the back metal layer and penetrating through the first substrate layer and then connected to the first wiring layer; The back metal layer is electrically connected to the first device layer through the power rail, and is electrically connected to the first wiring layer through the second interconnect structure.

4. The back side power supply packaging structure according to claim 2 or 3, characterized in that: One end of the power rail facing the back power supply structure is buried in the first substrate layer; The back power supply structure further includes a third interconnect structure extending from the back metal layer and extending into the first substrate layer and connected to the power rail, for electrically connecting the back metal layer and the power rail.

5. The back side power supply packaging structure according to claim 4, characterized in that: The power rail is buried in the first substrate layer to a depth of 50-200 nm.

6. The back side power supply packaging structure according to claim 2 or 3, characterized in that: The power rail passes through the first substrate layer and is connected to the back metal layer.

7. The back side power supply packaging structure according to any one of claims 1 to 3, characterized in that: The thickness of the first substrate layer is 100nm-1000nm.

8. The back side power supply packaging structure according to any one of claims 1 to 3, characterized in that: The first device layer includes transistors.

9. The back side power supply packaging structure according to any one of claims 1 to 3, characterized in that: The active interposer further includes a second substrate layer and a second device layer, wherein the second device layer is formed on the front side of the second substrate layer and is electrically connected to the second wiring layer.

10. The back side power supply packaging structure according to claim 9, characterized in that: The thickness of the second substrate layer is 75-150 μm.

11. The back side power supply packaging structure according to any one of claims 1 to 3, characterized in that: The first wiring layer includes a first metal layer exposed on the surface of the chip, and the second wiring layer includes a second metal layer exposed on the surface of the active interposer and bonded to the first metal layer.

12. The back side power supply packaging structure according to any one of claims 1 to 3, characterized in that: The invention also includes a packaging layer formed on a side of the back power supply structure facing away from the first substrate layer.

13. A method for preparing a back-side power supply packaging structure, characterized in that: The preparation method comprises: A packaging substrate, a first wafer formed with a chip, and a second wafer formed with an active interposer are provided; the first wafer has a first surface and a second surface opposite to each other; the chip comprises a first initial substrate, a first device layer, and a first wiring layer, the first device layer is formed on the front side of the first initial substrate and is electrically connected to the first wiring layer; the active interposer is formed with an electrically connected second wiring layer and a first interconnection structure, the first interconnection structure penetrates the active interposer toward one end of the packaging substrate; Bonding the first surface of the first wafer to the second wafer so that the active interposer is bonded to one side of the first device layer and the second wiring layer is electrically connected to the first wiring layer; Thinning the first wafer from the second surface of the first wafer to thin the first initial substrate into a first substrate layer; forming a back side power supply structure electrically connected to the first device layer and the first wiring layer respectively on the back side of the first substrate layer; The first interconnect structure is electrically connected to the packaging substrate to form the back-side power supply packaging structure.

14. The preparation method according to claim 13, characterized in that: A power rail is formed in the first substrate layer, and the first device layer and the first wiring layer are electrically connected to the power rail respectively; The back side power supply structure formed on the back side of the first substrate layer and electrically connected to the first device layer and the first wiring layer respectively comprises: A back metal layer electrically connected to the power rail is formed on the back side of the first substrate layer, and the back metal layer is electrically connected to the first device layer and the first wiring layer respectively through the power rail.

15. The preparation method according to claim 13, characterized in that: A power rail is formed in the first substrate layer, and the first device layer is electrically connected to the power rail; The back side power supply structure formed on the back side of the first substrate layer and electrically connected to the first device layer and the first wiring layer respectively comprises: forming a through hole from the back side of the first substrate layer that penetrates the first substrate layer and extends to the first wiring layer, and filling the through hole with metal to form a second interconnect structure connected to the first wiring layer; A back metal layer electrically connected to the power rail and the second interconnect structure is formed on the back side of the first substrate layer. The back metal layer is electrically connected to the first device layer through the power rail and to the first wiring layer through the second interconnect structure.

16. The preparation method according to claim 14 or 15, characterized in that: The thinning the first wafer from the second surface of the first wafer to thin the first initial substrate into a first substrate layer comprises: Thinning the second surface of the first wafer to a point close to the power rail to form the first substrate layer, wherein one end of the power rail is buried in the first substrate layer; Before forming the back metal layer, the preparation method further comprises: A recessed structure extending into the first substrate layer and to the power rail is formed from the back side of the first substrate layer, and a conductive material is filled in the recessed structure to form a third interconnection structure connected to the power rail for electrically connecting the back metal layer and the power rail.

17. The preparation method according to claim 14 or 15, characterized in that: The thinning the first wafer from the second surface of the first wafer to thin the first initial substrate into a first substrate layer comprises: The first substrate layer is formed by thinning the second surface of the first wafer until the power rail is exposed. The power rail penetrates the first substrate layer and is used to connect with the back metal layer.

18. The preparation method according to any one of claims 13 to 15, characterized in that: The step of electrically connecting the first interconnect structure to the packaging substrate to form the back-side power supply packaging structure includes: forming a substrate attachment structure electrically connected to the first interconnect structure on a side of the second wafer where the first interconnect structure is formed, to obtain a wafer-level packaging structure; Cutting the wafer-level packaging structure to obtain an initial packaging structure; The initial packaging structure is connected to a packaging substrate through the substrate attachment structure to form the backside power supply packaging structure.

19. The preparation method according to any one of claims 13 to 15, characterized in that: Before electrically connecting the first interconnect structure to the packaging substrate to form the back-side power supply packaging structure, the preparation method further includes: A packaging layer is formed on a surface of the back power supply structure away from the first substrate layer.

20. An electronic device, characterized in that: The invention comprises an electronic device, wherein the electronic device is manufactured by adopting the preparation method of the back side power supply packaging structure according to any one of claims 1 to 12 or the back side power supply packaging structure according to any one of claims 13 to 19.

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